Blame - drivers/scsi/qla2xxx/qla_dbg.c - kernel/msm-4.9

blob: 493a3ea81e7933b78433dc76079bc350a861aa9b [file] [log] [blame]

Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1	/*
Andrew Vasquez	fa90c54	2005-10-27 11:10:08 -0700	[diff] [blame]	2	* QLogic Fibre Channel HBA Driver
Armen Baloyan	bd21eaf	2014-04-11 16:54:24 -0400	[diff] [blame]	3	* Copyright (c) 2003-2014 QLogic Corporation
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	4	*
Andrew Vasquez	fa90c54	2005-10-27 11:10:08 -0700	[diff] [blame]	5	* See LICENSE.qla2xxx for copyright and licensing details.
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	6	*/
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	7
				8	/*
				9	* Table for showing the current message id in use for particular level
				10	* Change this table for addition of log/debug messages.
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	11	* ----------------------------------------------------------------------
				12	* \| Level \| Last Value Used \| Holes \|
				13	* ----------------------------------------------------------------------
Sawan Chandak	4243c11	2016-01-27 12:03:31 -0500	[diff] [blame^]	14	* \| Module Init and Probe \| 0x018f \| 0x0146 \|
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	15	* \| \| \| 0x015b-0x0160 \|
Himanshu Madhani	d14e72f	2015-04-09 15:00:03 -0400	[diff] [blame]	16	* \| \| \| 0x016e-0x0170 \|
Himanshu Madhani	2f56a7f	2015-12-17 14:56:57 -0500	[diff] [blame]	17	* \| Mailbox commands \| 0x1192 \| \|
				18	* \| \| \| \|
Himanshu Madhani	df57cab	2014-09-25 05:16:46 -0400	[diff] [blame]	19	* \| Device Discovery \| 0x2016 \| 0x2020-0x2022, \|
Bart Van Assche	6593d5b	2013-06-25 11:27:24 -0400	[diff] [blame]	20	* \| \| \| 0x2011-0x2012, \|
Himanshu Madhani	df57cab	2014-09-25 05:16:46 -0400	[diff] [blame]	21	* \| \| \| 0x2099-0x20a4 \|
Himanshu Madhani	6eb5471	2015-12-17 14:57:00 -0500	[diff] [blame]	22	* \| Queue Command and IO tracing \| 0x3074 \| 0x300b \|
Arun Easi	9e522cd	2012-08-22 14:21:31 -0400	[diff] [blame]	23	* \| \| \| 0x3027-0x3028 \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	24	* \| \| \| 0x303d-0x3041 \|
				25	* \| \| \| 0x302d,0x3033 \|
				26	* \| \| \| 0x3036,0x3038 \|
				27	* \| \| \| 0x303a \|
Armen Baloyan	e8f5e95	2013-10-30 03:38:17 -0400	[diff] [blame]	28	* \| DPC Thread \| 0x4023 \| 0x4002,0x4013 \|
Alexei Potashnik	b7bd104	2015-12-17 14:57:02 -0500	[diff] [blame]	29	* \| Async Events \| 0x5089 \| 0x502b-0x502f \|
Chad Dupuis	0a583e4	2016-01-27 12:03:28 -0500	[diff] [blame]	30	* \| \| \| 0x505e \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	31	* \| \| \| 0x5084,0x5075 \|
Chad Dupuis	a78951b	2013-08-27 01:37:34 -0400	[diff] [blame]	32	* \| \| \| 0x503d,0x5044 \|
Chad Dupuis	8e5a948	2014-08-08 07:38:09 -0400	[diff] [blame]	33	* \| \| \| 0x507b,0x505f \|
Armen Baloyan	71e5600	2013-08-27 01:37:38 -0400	[diff] [blame]	34	* \| Timer Routines \| 0x6012 \| \|
Himanshu Madhani	6eb5471	2015-12-17 14:57:00 -0500	[diff] [blame]	35	* \| User Space Interactions \| 0x70e65 \| 0x7018,0x702e \|
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	36	* \| \| \| 0x7020,0x7024 \|
				37	* \| \| \| 0x7039,0x7045 \|
				38	* \| \| \| 0x7073-0x7075 \|
				39	* \| \| \| 0x70a5-0x70a6 \|
				40	* \| \| \| 0x70a8,0x70ab \|
				41	* \| \| \| 0x70ad-0x70ae \|
				42	* \| \| \| 0x70d7-0x70db \|
				43	* \| \| \| 0x70de-0x70df \|
Chad Dupuis	7108b76	2014-04-11 16:54:45 -0400	[diff] [blame]	44	* \| Task Management \| 0x803d \| 0x8000,0x800b \|
Chad Dupuis	63ee707	2014-04-11 16:54:46 -0400	[diff] [blame]	45	* \| \| \| 0x8019 \|
Chad Dupuis	7108b76	2014-04-11 16:54:45 -0400	[diff] [blame]	46	* \| \| \| 0x8025,0x8026 \|
				47	* \| \| \| 0x8031,0x8032 \|
				48	* \| \| \| 0x8039,0x803c \|
Saurav Kashyap	5f28d2d	2012-05-15 14:34:15 -0400	[diff] [blame]	49	* \| AER/EEH \| 0x9011 \| \|
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	50	* \| Virtual Port \| 0xa007 \| \|
Atul Deshmukh	27f4b72	2014-04-11 16:54:26 -0400	[diff] [blame]	51	* \| ISP82XX Specific \| 0xb157 \| 0xb002,0xb024 \|
Atul Deshmukh	7ec0eff	2013-08-27 01:37:28 -0400	[diff] [blame]	52	* \| \| \| 0xb09e,0xb0ae \|
Hiral Patel	a018d8f	2014-04-11 16:54:34 -0400	[diff] [blame]	53	* \| \| \| 0xb0c3,0xb0c6 \|
Atul Deshmukh	7ec0eff	2013-08-27 01:37:28 -0400	[diff] [blame]	54	* \| \| \| 0xb0e0-0xb0ef \|
				55	* \| \| \| 0xb085,0xb0dc \|
				56	* \| \| \| 0xb107,0xb108 \|
				57	* \| \| \| 0xb111,0xb11e \|
				58	* \| \| \| 0xb12c,0xb12d \|
				59	* \| \| \| 0xb13a,0xb142 \|
				60	* \| \| \| 0xb13c-0xb140 \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	61	* \| \| \| 0xb149 \|
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	62	* \| MultiQ \| 0xc00c \| \|
Himanshu Madhani	ce1025c	2015-12-17 14:56:58 -0500	[diff] [blame]	63	* \| Misc \| 0xd301 \| 0xd031-0xd0ff \|
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	64	* \| \| \| 0xd101-0xd1fe \|
Joe Carnuccio	2ac224b	2014-09-25 05:16:36 -0400	[diff] [blame]	65	* \| \| \| 0xd214-0xd2fe \|
Alexei Potashnik	a6ca887	2015-07-14 16:00:44 -0400	[diff] [blame]	66	* \| Target Mode \| 0xe080 \| \|
Alexei Potashnik	b7bd104	2015-12-17 14:57:02 -0500	[diff] [blame]	67	* \| Target Mode Management \| 0xf09b \| 0xf002 \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	68	* \| \| \| 0xf046-0xf049 \|
Alexei Potashnik	a6ca887	2015-07-14 16:00:44 -0400	[diff] [blame]	69	* \| Target Mode Task Management \| 0x1000d \| \|
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	70	* ----------------------------------------------------------------------
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	71	*/
				72
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	73	#include "qla_def.h"
				74
				75	#include <linux/delay.h>
				76
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	77	static uint32_t ql_dbg_offset = 0x800;
				78
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	79	static inline void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	80	qla2xxx_prep_dump(struct qla_hw_data ha, struct qla2xxx_fw_dump fw_dump)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	81	{
				82	fw_dump->fw_major_version = htonl(ha->fw_major_version);
				83	fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
				84	fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
				85	fw_dump->fw_attributes = htonl(ha->fw_attributes);
				86
				87	fw_dump->vendor = htonl(ha->pdev->vendor);
				88	fw_dump->device = htonl(ha->pdev->device);
				89	fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
				90	fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
				91	}
				92
				93	static inline void *
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	94	qla2xxx_copy_queues(struct qla_hw_data ha, void ptr)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	95	{
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	96	struct req_que *req = ha->req_q_map[0];
				97	struct rsp_que *rsp = ha->rsp_q_map[0];
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	98	/* Request queue. */
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	99	memcpy(ptr, req->ring, req->length *
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	100	sizeof(request_t));
				101
				102	/* Response queue. */
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	103	ptr += req->length * sizeof(request_t);
				104	memcpy(ptr, rsp->ring, rsp->length *
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	105	sizeof(response_t));
				106
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	107	return ptr + (rsp->length * sizeof(response_t));
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	108	}
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	109
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	110	int
				111	qla27xx_dump_mpi_ram(struct qla_hw_data ha, uint32_t addr, uint32_t ram,
				112	uint32_t ram_dwords, void **nxt)
				113	{
				114	int rval;
				115	uint32_t cnt, stat, timer, dwords, idx;
Bart Van Assche	52c8282	2015-07-09 07:23:26 -0700	[diff] [blame]	116	uint16_t mb0;
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	117	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				118	dma_addr_t dump_dma = ha->gid_list_dma;
				119	uint32_t dump = (uint32_t )ha->gid_list;
				120
				121	rval = QLA_SUCCESS;
				122	mb0 = 0;
				123
				124	WRT_REG_WORD(&reg->mailbox0, MBC_LOAD_DUMP_MPI_RAM);
				125	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				126
				127	dwords = qla2x00_gid_list_size(ha) / 4;
				128	for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
				129	cnt += dwords, addr += dwords) {
				130	if (cnt + dwords > ram_dwords)
				131	dwords = ram_dwords - cnt;
				132
				133	WRT_REG_WORD(&reg->mailbox1, LSW(addr));
				134	WRT_REG_WORD(&reg->mailbox8, MSW(addr));
				135
				136	WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
				137	WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
				138	WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
				139	WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
				140
				141	WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
				142	WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
				143
				144	WRT_REG_WORD(&reg->mailbox9, 0);
				145	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
				146
				147	ha->flags.mbox_int = 0;
				148	for (timer = 6000000; timer; timer--) {
				149	/* Check for pending interrupts. */
				150	stat = RD_REG_DWORD(&reg->host_status);
				151	if (stat & HSRX_RISC_INT) {
				152	stat &= 0xff;
				153
				154	if (stat == 0x1 \|\| stat == 0x2 \|\|
				155	stat == 0x10 \|\| stat == 0x11) {
				156	set_bit(MBX_INTERRUPT,
				157	&ha->mbx_cmd_flags);
				158
				159	mb0 = RD_REG_WORD(&reg->mailbox0);
Bart Van Assche	52c8282	2015-07-09 07:23:26 -0700	[diff] [blame]	160	RD_REG_WORD(&reg->mailbox1);
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	161
				162	WRT_REG_DWORD(&reg->hccr,
				163	HCCRX_CLR_RISC_INT);
				164	RD_REG_DWORD(&reg->hccr);
				165	break;
				166	}
				167
				168	/* Clear this intr; it wasn't a mailbox intr */
				169	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
				170	RD_REG_DWORD(&reg->hccr);
				171	}
				172	udelay(5);
				173	}
				174	ha->flags.mbox_int = 1;
				175
				176	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				177	rval = mb0 & MBS_MASK;
				178	for (idx = 0; idx < dwords; idx++)
				179	ram[cnt + idx] = IS_QLA27XX(ha) ?
				180	le32_to_cpu(dump[idx]) : swab32(dump[idx]);
				181	} else {
				182	rval = QLA_FUNCTION_FAILED;
				183	}
				184	}
				185
				186	*nxt = rval == QLA_SUCCESS ? &ram[cnt] : NULL;
				187	return rval;
				188	}
				189
				190	int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	191	qla24xx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint32_t ram,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	192	uint32_t ram_dwords, void **nxt)
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	193	{
				194	int rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	195	uint32_t cnt, stat, timer, dwords, idx;
				196	uint16_t mb0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	197	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	198	dma_addr_t dump_dma = ha->gid_list_dma;
				199	uint32_t dump = (uint32_t )ha->gid_list;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	200
				201	rval = QLA_SUCCESS;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	202	mb0 = 0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	203
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	204	WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	205	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				206
Chad Dupuis	642ef98	2012-02-09 11:15:57 -0800	[diff] [blame]	207	dwords = qla2x00_gid_list_size(ha) / 4;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	208	for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
				209	cnt += dwords, addr += dwords) {
				210	if (cnt + dwords > ram_dwords)
				211	dwords = ram_dwords - cnt;
				212
				213	WRT_REG_WORD(&reg->mailbox1, LSW(addr));
				214	WRT_REG_WORD(&reg->mailbox8, MSW(addr));
				215
				216	WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
				217	WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
				218	WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
				219	WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
				220
				221	WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
				222	WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	223	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
				224
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	225	ha->flags.mbox_int = 0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	226	for (timer = 6000000; timer; timer--) {
				227	/* Check for pending interrupts. */
				228	stat = RD_REG_DWORD(&reg->host_status);
				229	if (stat & HSRX_RISC_INT) {
				230	stat &= 0xff;
				231
				232	if (stat == 0x1 \|\| stat == 0x2 \|\|
				233	stat == 0x10 \|\| stat == 0x11) {
				234	set_bit(MBX_INTERRUPT,
				235	&ha->mbx_cmd_flags);
				236
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	237	mb0 = RD_REG_WORD(&reg->mailbox0);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	238
				239	WRT_REG_DWORD(&reg->hccr,
				240	HCCRX_CLR_RISC_INT);
				241	RD_REG_DWORD(&reg->hccr);
				242	break;
				243	}
				244
				245	/* Clear this intr; it wasn't a mailbox intr */
				246	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
				247	RD_REG_DWORD(&reg->hccr);
				248	}
				249	udelay(5);
				250	}
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	251	ha->flags.mbox_int = 1;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	252
				253	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	254	rval = mb0 & MBS_MASK;
				255	for (idx = 0; idx < dwords; idx++)
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	256	ram[cnt + idx] = IS_QLA27XX(ha) ?
				257	le32_to_cpu(dump[idx]) : swab32(dump[idx]);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	258	} else {
				259	rval = QLA_FUNCTION_FAILED;
				260	}
				261	}
				262
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	263	*nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	264	return rval;
				265	}
				266
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	267	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	268	qla24xx_dump_memory(struct qla_hw_data ha, uint32_t code_ram,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	269	uint32_t cram_size, void **nxt)
				270	{
				271	int rval;
				272
				273	/* Code RAM. */
				274	rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
				275	if (rval != QLA_SUCCESS)
				276	return rval;
				277
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	278	set_bit(RISC_SRAM_DUMP_CMPL, &ha->fw_dump_cap_flags);
				279
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	280	/* External Memory. */
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	281	rval = qla24xx_dump_ram(ha, 0x100000, *nxt,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	282	ha->fw_memory_size - 0x100000 + 1, nxt);
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	283	if (rval == QLA_SUCCESS)
				284	set_bit(RISC_EXT_MEM_DUMP_CMPL, &ha->fw_dump_cap_flags);
				285
				286	return rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	287	}
				288
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	289	static uint32_t *
				290	qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
				291	uint32_t count, uint32_t *buf)
				292	{
				293	uint32_t __iomem *dmp_reg;
				294
				295	WRT_REG_DWORD(&reg->iobase_addr, iobase);
				296	dmp_reg = &reg->iobase_window;
				297	while (count--)
				298	*buf++ = htonl(RD_REG_DWORD(dmp_reg++));
				299
				300	return buf;
				301	}
				302
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	303	void
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	304	qla24xx_pause_risc(struct device_reg_24xx __iomem reg, struct qla_hw_data ha)
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	305	{
Andrew Vasquez	c3b058a	2007-09-20 14:07:38 -0700	[diff] [blame]	306	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	307
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	308	/* 100 usec delay is sufficient enough for hardware to pause RISC */
				309	udelay(100);
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	310	if (RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED)
				311	set_bit(RISC_PAUSE_CMPL, &ha->fw_dump_cap_flags);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	312	}
				313
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	314	int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	315	qla24xx_soft_reset(struct qla_hw_data *ha)
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	316	{
				317	int rval = QLA_SUCCESS;
				318	uint32_t cnt;
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	319	uint16_t wd;
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	320	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				321
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	322	/*
				323	* Reset RISC. The delay is dependent on system architecture.
				324	* Driver can proceed with the reset sequence after waiting
				325	* for a timeout period.
				326	*/
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	327	WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
				328	for (cnt = 0; cnt < 30000; cnt++) {
				329	if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
				330	break;
				331
				332	udelay(10);
				333	}
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	334	if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
				335	set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	336
				337	WRT_REG_DWORD(&reg->ctrl_status,
				338	CSRX_ISP_SOFT_RESET\|CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
				339	pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
				340
				341	udelay(100);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	342
				343	/* Wait for soft-reset to complete. */
				344	for (cnt = 0; cnt < 30000; cnt++) {
				345	if ((RD_REG_DWORD(&reg->ctrl_status) &
				346	CSRX_ISP_SOFT_RESET) == 0)
				347	break;
				348
				349	udelay(10);
				350	}
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	351	if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
				352	set_bit(ISP_RESET_CMPL, &ha->fw_dump_cap_flags);
				353
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	354	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
				355	RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
				356
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	357	for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	358	rval == QLA_SUCCESS; cnt--) {
				359	if (cnt)
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	360	udelay(10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	361	else
				362	rval = QLA_FUNCTION_TIMEOUT;
				363	}
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	364	if (rval == QLA_SUCCESS)
				365	set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	366
				367	return rval;
				368	}
				369
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	370	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	371	qla2xxx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint16_t ram,
Andrew Vasquez	e18e963	2009-06-17 10:30:31 -0700	[diff] [blame]	372	uint32_t ram_words, void **nxt)
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	373	{
				374	int rval;
				375	uint32_t cnt, stat, timer, words, idx;
				376	uint16_t mb0;
				377	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
				378	dma_addr_t dump_dma = ha->gid_list_dma;
				379	uint16_t dump = (uint16_t )ha->gid_list;
				380
				381	rval = QLA_SUCCESS;
				382	mb0 = 0;
				383
				384	WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
				385	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				386
Chad Dupuis	642ef98	2012-02-09 11:15:57 -0800	[diff] [blame]	387	words = qla2x00_gid_list_size(ha) / 2;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	388	for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
				389	cnt += words, addr += words) {
				390	if (cnt + words > ram_words)
				391	words = ram_words - cnt;
				392
				393	WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
				394	WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
				395
				396	WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
				397	WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
				398	WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
				399	WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
				400
				401	WRT_MAILBOX_REG(ha, reg, 4, words);
				402	WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
				403
				404	for (timer = 6000000; timer; timer--) {
				405	/* Check for pending interrupts. */
				406	stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
				407	if (stat & HSR_RISC_INT) {
				408	stat &= 0xff;
				409
				410	if (stat == 0x1 \|\| stat == 0x2) {
				411	set_bit(MBX_INTERRUPT,
				412	&ha->mbx_cmd_flags);
				413
				414	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				415
				416	/* Release mailbox registers. */
				417	WRT_REG_WORD(&reg->semaphore, 0);
				418	WRT_REG_WORD(&reg->hccr,
				419	HCCR_CLR_RISC_INT);
				420	RD_REG_WORD(&reg->hccr);
				421	break;
				422	} else if (stat == 0x10 \|\| stat == 0x11) {
				423	set_bit(MBX_INTERRUPT,
				424	&ha->mbx_cmd_flags);
				425
				426	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				427
				428	WRT_REG_WORD(&reg->hccr,
				429	HCCR_CLR_RISC_INT);
				430	RD_REG_WORD(&reg->hccr);
				431	break;
				432	}
				433
				434	/* clear this intr; it wasn't a mailbox intr */
				435	WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
				436	RD_REG_WORD(&reg->hccr);
				437	}
				438	udelay(5);
				439	}
				440
				441	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				442	rval = mb0 & MBS_MASK;
				443	for (idx = 0; idx < words; idx++)
				444	ram[cnt + idx] = swab16(dump[idx]);
				445	} else {
				446	rval = QLA_FUNCTION_FAILED;
				447	}
				448	}
				449
				450	*nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
				451	return rval;
				452	}
				453
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	454	static inline void
				455	qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
				456	uint16_t *buf)
				457	{
				458	uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
				459
				460	while (count--)
				461	*buf++ = htons(RD_REG_WORD(dmp_reg++));
				462	}
				463
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	464	static inline void *
				465	qla24xx_copy_eft(struct qla_hw_data ha, void ptr)
				466	{
				467	if (!ha->eft)
				468	return ptr;
				469
				470	memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
				471	return ptr + ntohl(ha->fw_dump->eft_size);
				472	}
				473
				474	static inline void *
				475	qla25xx_copy_fce(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				476	{
				477	uint32_t cnt;
				478	uint32_t *iter_reg;
				479	struct qla2xxx_fce_chain *fcec = ptr;
				480
				481	if (!ha->fce)
				482	return ptr;
				483
				484	*last_chain = &fcec->type;
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	485	fcec->type = htonl(DUMP_CHAIN_FCE);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	486	fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
				487	fce_calc_size(ha->fce_bufs));
				488	fcec->size = htonl(fce_calc_size(ha->fce_bufs));
				489	fcec->addr_l = htonl(LSD(ha->fce_dma));
				490	fcec->addr_h = htonl(MSD(ha->fce_dma));
				491
				492	iter_reg = fcec->eregs;
				493	for (cnt = 0; cnt < 8; cnt++)
				494	*iter_reg++ = htonl(ha->fce_mb[cnt]);
				495
				496	memcpy(iter_reg, ha->fce, ntohl(fcec->size));
				497
Giridhar Malavali	3cb0a67	2011-11-18 09:03:11 -0800	[diff] [blame]	498	return (char *)iter_reg + ntohl(fcec->size);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	499	}
				500
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	501	static inline void *
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	502	qla2xxx_copy_atioqueues(struct qla_hw_data ha, void ptr,
				503	uint32_t **last_chain)
				504	{
				505	struct qla2xxx_mqueue_chain *q;
				506	struct qla2xxx_mqueue_header *qh;
				507	uint32_t num_queues;
				508	int que;
				509	struct {
				510	int length;
				511	void *ring;
				512	} aq, *aqp;
				513
Arun Easi	00876ae	2013-03-25 02:21:37 -0400	[diff] [blame]	514	if (!ha->tgt.atio_ring)
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	515	return ptr;
				516
				517	num_queues = 1;
				518	aqp = &aq;
				519	aqp->length = ha->tgt.atio_q_length;
				520	aqp->ring = ha->tgt.atio_ring;
				521
				522	for (que = 0; que < num_queues; que++) {
				523	/* aqp = ha->atio_q_map[que]; */
				524	q = ptr;
				525	*last_chain = &q->type;
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	526	q->type = htonl(DUMP_CHAIN_QUEUE);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	527	q->chain_size = htonl(
				528	sizeof(struct qla2xxx_mqueue_chain) +
				529	sizeof(struct qla2xxx_mqueue_header) +
				530	(aqp->length * sizeof(request_t)));
				531	ptr += sizeof(struct qla2xxx_mqueue_chain);
				532
				533	/* Add header. */
				534	qh = ptr;
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	535	qh->queue = htonl(TYPE_ATIO_QUEUE);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	536	qh->number = htonl(que);
				537	qh->size = htonl(aqp->length * sizeof(request_t));
				538	ptr += sizeof(struct qla2xxx_mqueue_header);
				539
				540	/* Add data. */
				541	memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t));
				542
				543	ptr += aqp->length * sizeof(request_t);
				544	}
				545
				546	return ptr;
				547	}
				548
				549	static inline void *
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	550	qla25xx_copy_mqueues(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				551	{
				552	struct qla2xxx_mqueue_chain *q;
				553	struct qla2xxx_mqueue_header *qh;
				554	struct req_que *req;
				555	struct rsp_que *rsp;
				556	int que;
				557
				558	if (!ha->mqenable)
				559	return ptr;
				560
				561	/* Request queues */
				562	for (que = 1; que < ha->max_req_queues; que++) {
				563	req = ha->req_q_map[que];
				564	if (!req)
				565	break;
				566
				567	/* Add chain. */
				568	q = ptr;
				569	*last_chain = &q->type;
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	570	q->type = htonl(DUMP_CHAIN_QUEUE);
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	571	q->chain_size = htonl(
				572	sizeof(struct qla2xxx_mqueue_chain) +
				573	sizeof(struct qla2xxx_mqueue_header) +
				574	(req->length * sizeof(request_t)));
				575	ptr += sizeof(struct qla2xxx_mqueue_chain);
				576
				577	/* Add header. */
				578	qh = ptr;
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	579	qh->queue = htonl(TYPE_REQUEST_QUEUE);
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	580	qh->number = htonl(que);
				581	qh->size = htonl(req->length * sizeof(request_t));
				582	ptr += sizeof(struct qla2xxx_mqueue_header);
				583
				584	/* Add data. */
				585	memcpy(ptr, req->ring, req->length * sizeof(request_t));
				586	ptr += req->length * sizeof(request_t);
				587	}
				588
				589	/* Response queues */
				590	for (que = 1; que < ha->max_rsp_queues; que++) {
				591	rsp = ha->rsp_q_map[que];
				592	if (!rsp)
				593	break;
				594
				595	/* Add chain. */
				596	q = ptr;
				597	*last_chain = &q->type;
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	598	q->type = htonl(DUMP_CHAIN_QUEUE);
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	599	q->chain_size = htonl(
				600	sizeof(struct qla2xxx_mqueue_chain) +
				601	sizeof(struct qla2xxx_mqueue_header) +
				602	(rsp->length * sizeof(response_t)));
				603	ptr += sizeof(struct qla2xxx_mqueue_chain);
				604
				605	/* Add header. */
				606	qh = ptr;
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	607	qh->queue = htonl(TYPE_RESPONSE_QUEUE);
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	608	qh->number = htonl(que);
				609	qh->size = htonl(rsp->length * sizeof(response_t));
				610	ptr += sizeof(struct qla2xxx_mqueue_header);
				611
				612	/* Add data. */
				613	memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t));
				614	ptr += rsp->length * sizeof(response_t);
				615	}
				616
				617	return ptr;
				618	}
				619
				620	static inline void *
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	621	qla25xx_copy_mq(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				622	{
				623	uint32_t cnt, que_idx;
Anirban Chakraborty	2afa19a	2009-04-06 22:33:40 -0700	[diff] [blame]	624	uint8_t que_cnt;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	625	struct qla2xxx_mq_chain *mq = ptr;
Bart Van Assche	118e2ef	2015-07-09 07:24:27 -0700	[diff] [blame]	626	device_reg_t *reg;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	627
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	628	if (!ha->mqenable \|\| IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	629	return ptr;
				630
				631	mq = ptr;
				632	*last_chain = &mq->type;
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	633	mq->type = htonl(DUMP_CHAIN_MQ);
				634	mq->chain_size = htonl(sizeof(struct qla2xxx_mq_chain));
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	635
Anirban Chakraborty	2afa19a	2009-04-06 22:33:40 -0700	[diff] [blame]	636	que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
				637	ha->max_req_queues : ha->max_rsp_queues;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	638	mq->count = htonl(que_cnt);
				639	for (cnt = 0; cnt < que_cnt; cnt++) {
Andrew Vasquez	da9b1d5	2013-08-27 01:37:30 -0400	[diff] [blame]	640	reg = ISP_QUE_REG(ha, cnt);
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	641	que_idx = cnt * 4;
Andrew Vasquez	da9b1d5	2013-08-27 01:37:30 -0400	[diff] [blame]	642	mq->qregs[que_idx] =
				643	htonl(RD_REG_DWORD(&reg->isp25mq.req_q_in));
				644	mq->qregs[que_idx+1] =
				645	htonl(RD_REG_DWORD(&reg->isp25mq.req_q_out));
				646	mq->qregs[que_idx+2] =
				647	htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_in));
				648	mq->qregs[que_idx+3] =
				649	htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_out));
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	650	}
				651
				652	return ptr + sizeof(struct qla2xxx_mq_chain);
				653	}
				654
Giridhar Malavali	08de284	2011-08-16 11:31:44 -0700	[diff] [blame]	655	void
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	656	qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
				657	{
				658	struct qla_hw_data *ha = vha->hw;
				659
				660	if (rval != QLA_SUCCESS) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	661	ql_log(ql_log_warn, vha, 0xd000,
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	662	"Failed to dump firmware (%x), dump status flags (0x%lx).\n",
				663	rval, ha->fw_dump_cap_flags);
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	664	ha->fw_dumped = 0;
				665	} else {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	666	ql_log(ql_log_info, vha, 0xd001,
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	667	"Firmware dump saved to temp buffer (%ld/%p), dump status flags (0x%lx).\n",
				668	vha->host_no, ha->fw_dump, ha->fw_dump_cap_flags);
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	669	ha->fw_dumped = 1;
				670	qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
				671	}
				672	}
				673
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	674	/**
				675	* qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
				676	* @ha: HA context
				677	* @hardware_locked: Called with the hardware_lock
				678	*/
				679	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	680	qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	681	{
				682	int rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	683	uint32_t cnt;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	684	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	3d71644	2005-07-06 10:30:26 -0700	[diff] [blame]	685	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	686	uint16_t __iomem *dmp_reg;
				687	unsigned long flags;
				688	struct qla2300_fw_dump *fw;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	689	void *nxt;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	690	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	691
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	692	flags = 0;
				693
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	694	#ifndef __CHECKER__
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	695	if (!hardware_locked)
				696	spin_lock_irqsave(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	697	#endif
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	698
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	699	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	700	ql_log(ql_log_warn, vha, 0xd002,
				701	"No buffer available for dump.\n");
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	702	goto qla2300_fw_dump_failed;
				703	}
				704
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	705	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	706	ql_log(ql_log_warn, vha, 0xd003,
				707	"Firmware has been previously dumped (%p) "
				708	"-- ignoring request.\n",
				709	ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	710	goto qla2300_fw_dump_failed;
				711	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	712	fw = &ha->fw_dump->isp.isp23;
				713	qla2xxx_prep_dump(ha, ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	714
				715	rval = QLA_SUCCESS;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	716	fw->hccr = htons(RD_REG_WORD(&reg->hccr));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	717
				718	/* Pause RISC. */
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	719	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	720	if (IS_QLA2300(ha)) {
				721	for (cnt = 30000;
				722	(RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				723	rval == QLA_SUCCESS; cnt--) {
				724	if (cnt)
				725	udelay(100);
				726	else
				727	rval = QLA_FUNCTION_TIMEOUT;
				728	}
				729	} else {
				730	RD_REG_WORD(&reg->hccr); /* PCI Posting. */
				731	udelay(10);
				732	}
				733
				734	if (rval == QLA_SUCCESS) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	735	dmp_reg = &reg->flash_address;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	736	for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	737	fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	738
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	739	dmp_reg = &reg->u.isp2300.req_q_in;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	740	for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	741	fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	742
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	743	dmp_reg = &reg->u.isp2300.mailbox0;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	744	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	745	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	746
				747	WRT_REG_WORD(&reg->ctrl_status, 0x40);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	748	qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	749
				750	WRT_REG_WORD(&reg->ctrl_status, 0x50);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	751	qla2xxx_read_window(reg, 48, fw->dma_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	752
				753	WRT_REG_WORD(&reg->ctrl_status, 0x00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	754	dmp_reg = &reg->risc_hw;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	755	for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	756	fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	757
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	758	WRT_REG_WORD(&reg->pcr, 0x2000);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	759	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	760
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	761	WRT_REG_WORD(&reg->pcr, 0x2200);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	762	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	763
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	764	WRT_REG_WORD(&reg->pcr, 0x2400);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	765	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	766
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	767	WRT_REG_WORD(&reg->pcr, 0x2600);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	768	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	769
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	770	WRT_REG_WORD(&reg->pcr, 0x2800);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	771	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	772
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	773	WRT_REG_WORD(&reg->pcr, 0x2A00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	774	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	775
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	776	WRT_REG_WORD(&reg->pcr, 0x2C00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	777	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	778
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	779	WRT_REG_WORD(&reg->pcr, 0x2E00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	780	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	781
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	782	WRT_REG_WORD(&reg->ctrl_status, 0x10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	783	qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	784
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	785	WRT_REG_WORD(&reg->ctrl_status, 0x20);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	786	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	787
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	788	WRT_REG_WORD(&reg->ctrl_status, 0x30);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	789	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	790
				791	/* Reset RISC. */
				792	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
				793	for (cnt = 0; cnt < 30000; cnt++) {
				794	if ((RD_REG_WORD(&reg->ctrl_status) &
				795	CSR_ISP_SOFT_RESET) == 0)
				796	break;
				797
				798	udelay(10);
				799	}
				800	}
				801
				802	if (!IS_QLA2300(ha)) {
				803	for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
				804	rval == QLA_SUCCESS; cnt--) {
				805	if (cnt)
				806	udelay(100);
				807	else
				808	rval = QLA_FUNCTION_TIMEOUT;
				809	}
				810	}
				811
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	812	/* Get RISC SRAM. */
				813	if (rval == QLA_SUCCESS)
				814	rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
				815	sizeof(fw->risc_ram) / 2, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	816
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	817	/* Get stack SRAM. */
				818	if (rval == QLA_SUCCESS)
				819	rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
				820	sizeof(fw->stack_ram) / 2, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	821
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	822	/* Get data SRAM. */
				823	if (rval == QLA_SUCCESS)
				824	rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
				825	ha->fw_memory_size - 0x11000 + 1, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	826
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	827	if (rval == QLA_SUCCESS)
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	828	qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	829
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	830	qla2xxx_dump_post_process(base_vha, rval);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	831
				832	qla2300_fw_dump_failed:
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	833	#ifndef __CHECKER__
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	834	if (!hardware_locked)
				835	spin_unlock_irqrestore(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	836	#else
				837	;
				838	#endif
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	839	}
				840
				841	/**
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	842	* qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
				843	* @ha: HA context
				844	* @hardware_locked: Called with the hardware_lock
				845	*/
				846	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	847	qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	848	{
				849	int rval;
				850	uint32_t cnt, timer;
				851	uint16_t risc_address;
				852	uint16_t mb0, mb2;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	853	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	3d71644	2005-07-06 10:30:26 -0700	[diff] [blame]	854	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	855	uint16_t __iomem *dmp_reg;
				856	unsigned long flags;
				857	struct qla2100_fw_dump *fw;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	858	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	859
				860	risc_address = 0;
				861	mb0 = mb2 = 0;
				862	flags = 0;
				863
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	864	#ifndef __CHECKER__
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	865	if (!hardware_locked)
				866	spin_lock_irqsave(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	867	#endif
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	868
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	869	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	870	ql_log(ql_log_warn, vha, 0xd004,
				871	"No buffer available for dump.\n");
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	872	goto qla2100_fw_dump_failed;
				873	}
				874
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	875	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	876	ql_log(ql_log_warn, vha, 0xd005,
				877	"Firmware has been previously dumped (%p) "
				878	"-- ignoring request.\n",
				879	ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	880	goto qla2100_fw_dump_failed;
				881	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	882	fw = &ha->fw_dump->isp.isp21;
				883	qla2xxx_prep_dump(ha, ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	884
				885	rval = QLA_SUCCESS;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	886	fw->hccr = htons(RD_REG_WORD(&reg->hccr));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	887
				888	/* Pause RISC. */
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	889	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	890	for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				891	rval == QLA_SUCCESS; cnt--) {
				892	if (cnt)
				893	udelay(100);
				894	else
				895	rval = QLA_FUNCTION_TIMEOUT;
				896	}
				897	if (rval == QLA_SUCCESS) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	898	dmp_reg = &reg->flash_address;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	899	for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	900	fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	901
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	902	dmp_reg = &reg->u.isp2100.mailbox0;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	903	for (cnt = 0; cnt < ha->mbx_count; cnt++) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	904	if (cnt == 8)
				905	dmp_reg = &reg->u_end.isp2200.mailbox8;
				906
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	907	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	908	}
				909
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	910	dmp_reg = &reg->u.isp2100.unused_2[0];
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	911	for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	912	fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	913
				914	WRT_REG_WORD(&reg->ctrl_status, 0x00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	915	dmp_reg = &reg->risc_hw;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	916	for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	917	fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	918
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	919	WRT_REG_WORD(&reg->pcr, 0x2000);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	920	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	921
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	922	WRT_REG_WORD(&reg->pcr, 0x2100);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	923	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	924
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	925	WRT_REG_WORD(&reg->pcr, 0x2200);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	926	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	927
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	928	WRT_REG_WORD(&reg->pcr, 0x2300);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	929	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	930
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	931	WRT_REG_WORD(&reg->pcr, 0x2400);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	932	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	933
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	934	WRT_REG_WORD(&reg->pcr, 0x2500);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	935	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	936
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	937	WRT_REG_WORD(&reg->pcr, 0x2600);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	938	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	939
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	940	WRT_REG_WORD(&reg->pcr, 0x2700);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	941	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	942
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	943	WRT_REG_WORD(&reg->ctrl_status, 0x10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	944	qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	945
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	946	WRT_REG_WORD(&reg->ctrl_status, 0x20);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	947	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	948
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	949	WRT_REG_WORD(&reg->ctrl_status, 0x30);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	950	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	951
				952	/* Reset the ISP. */
				953	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
				954	}
				955
				956	for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
				957	rval == QLA_SUCCESS; cnt--) {
				958	if (cnt)
				959	udelay(100);
				960	else
				961	rval = QLA_FUNCTION_TIMEOUT;
				962	}
				963
				964	/* Pause RISC. */
				965	if (rval == QLA_SUCCESS && (IS_QLA2200(ha) \|\| (IS_QLA2100(ha) &&
				966	(RD_REG_WORD(&reg->mctr) & (BIT_1 \| BIT_0)) != 0))) {
				967
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	968	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	969	for (cnt = 30000;
				970	(RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				971	rval == QLA_SUCCESS; cnt--) {
				972	if (cnt)
				973	udelay(100);
				974	else
				975	rval = QLA_FUNCTION_TIMEOUT;
				976	}
				977	if (rval == QLA_SUCCESS) {
				978	/* Set memory configuration and timing. */
				979	if (IS_QLA2100(ha))
				980	WRT_REG_WORD(&reg->mctr, 0xf1);
				981	else
				982	WRT_REG_WORD(&reg->mctr, 0xf2);
				983	RD_REG_WORD(&reg->mctr); /* PCI Posting. */
				984
				985	/* Release RISC. */
				986	WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
				987	}
				988	}
				989
				990	if (rval == QLA_SUCCESS) {
				991	/* Get RISC SRAM. */
				992	risc_address = 0x1000;
				993	WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
				994	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				995	}
				996	for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
				997	cnt++, risc_address++) {
				998	WRT_MAILBOX_REG(ha, reg, 1, risc_address);
				999	WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
				1000
				1001	for (timer = 6000000; timer != 0; timer--) {
				1002	/* Check for pending interrupts. */
				1003	if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
				1004	if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
				1005	set_bit(MBX_INTERRUPT,
				1006	&ha->mbx_cmd_flags);
				1007
				1008	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				1009	mb2 = RD_MAILBOX_REG(ha, reg, 2);
				1010
				1011	WRT_REG_WORD(&reg->semaphore, 0);
				1012	WRT_REG_WORD(&reg->hccr,
				1013	HCCR_CLR_RISC_INT);
				1014	RD_REG_WORD(&reg->hccr);
				1015	break;
				1016	}
				1017	WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
				1018	RD_REG_WORD(&reg->hccr);
				1019	}
				1020	udelay(5);
				1021	}
				1022
				1023	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				1024	rval = mb0 & MBS_MASK;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1025	fw->risc_ram[cnt] = htons(mb2);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1026	} else {
				1027	rval = QLA_FUNCTION_FAILED;
				1028	}
				1029	}
				1030
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1031	if (rval == QLA_SUCCESS)
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1032	qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1033
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1034	qla2xxx_dump_post_process(base_vha, rval);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1035
				1036	qla2100_fw_dump_failed:
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1037	#ifndef __CHECKER__
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1038	if (!hardware_locked)
				1039	spin_unlock_irqrestore(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1040	#else
				1041	;
				1042	#endif
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1043	}
				1044
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1045	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1046	qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1047	{
				1048	int rval;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1049	uint32_t cnt;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1050	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1051	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1052	uint32_t __iomem *dmp_reg;
				1053	uint32_t *iter_reg;
				1054	uint16_t __iomem *mbx_reg;
				1055	unsigned long flags;
				1056	struct qla24xx_fw_dump *fw;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1057	void *nxt;
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1058	void *nxt_chain;
				1059	uint32_t *last_chain = NULL;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1060	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1061
Atul Deshmukh	7ec0eff	2013-08-27 01:37:28 -0400	[diff] [blame]	1062	if (IS_P3P_TYPE(ha))
Giridhar Malavali	a908301	2010-04-12 17:59:55 -0700	[diff] [blame]	1063	return;
				1064
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1065	flags = 0;
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1066	ha->fw_dump_cap_flags = 0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1067
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1068	#ifndef __CHECKER__
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1069	if (!hardware_locked)
				1070	spin_lock_irqsave(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1071	#endif
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1072
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	1073	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1074	ql_log(ql_log_warn, vha, 0xd006,
				1075	"No buffer available for dump.\n");
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1076	goto qla24xx_fw_dump_failed;
				1077	}
				1078
				1079	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1080	ql_log(ql_log_warn, vha, 0xd007,
				1081	"Firmware has been previously dumped (%p) "
				1082	"-- ignoring request.\n",
				1083	ha->fw_dump);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1084	goto qla24xx_fw_dump_failed;
				1085	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1086	fw = &ha->fw_dump->isp.isp24;
				1087	qla2xxx_prep_dump(ha, ha->fw_dump);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1088
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1089	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1090
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	1091	/*
				1092	* Pause RISC. No need to track timeout, as resetting the chip
				1093	* is the right approach incase of pause timeout
				1094	*/
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1095	qla24xx_pause_risc(reg, ha);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1096
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1097	/* Host interface registers. */
				1098	dmp_reg = &reg->flash_addr;
				1099	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1100	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1101
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1102	/* Disable interrupts. */
				1103	WRT_REG_DWORD(&reg->ictrl, 0);
				1104	RD_REG_DWORD(&reg->ictrl);
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1105
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1106	/* Shadow registers. */
				1107	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1108	RD_REG_DWORD(&reg->iobase_addr);
				1109	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1110	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1111
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1112	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1113	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1114
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1115	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1116	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1117
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1118	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1119	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1120
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1121	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1122	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1123
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1124	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1125	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1126
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1127	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1128	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1129
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1130	/* Mailbox registers. */
				1131	mbx_reg = &reg->mailbox0;
				1132	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1133	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1134
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1135	/* Transfer sequence registers. */
				1136	iter_reg = fw->xseq_gp_reg;
				1137	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1138	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1139	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1140	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1141	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1142	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1143	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1144	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1145
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1146	qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
				1147	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1148
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1149	/* Receive sequence registers. */
				1150	iter_reg = fw->rseq_gp_reg;
				1151	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1152	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1153	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1154	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1155	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1156	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1157	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1158	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1159
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1160	qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
				1161	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1162	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1163
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1164	/* Command DMA registers. */
				1165	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1166
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1167	/* Queues. */
				1168	iter_reg = fw->req0_dma_reg;
				1169	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1170	dmp_reg = &reg->iobase_q;
				1171	for (cnt = 0; cnt < 7; cnt++)
				1172	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1173
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1174	iter_reg = fw->resp0_dma_reg;
				1175	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1176	dmp_reg = &reg->iobase_q;
				1177	for (cnt = 0; cnt < 7; cnt++)
				1178	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1179
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1180	iter_reg = fw->req1_dma_reg;
				1181	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1182	dmp_reg = &reg->iobase_q;
				1183	for (cnt = 0; cnt < 7; cnt++)
				1184	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1185
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1186	/* Transmit DMA registers. */
				1187	iter_reg = fw->xmt0_dma_reg;
				1188	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1189	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1190
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1191	iter_reg = fw->xmt1_dma_reg;
				1192	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1193	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1194
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1195	iter_reg = fw->xmt2_dma_reg;
				1196	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1197	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1198
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1199	iter_reg = fw->xmt3_dma_reg;
				1200	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1201	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1202
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1203	iter_reg = fw->xmt4_dma_reg;
				1204	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1205	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1206
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1207	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1208
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1209	/* Receive DMA registers. */
				1210	iter_reg = fw->rcvt0_data_dma_reg;
				1211	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1212	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1213
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1214	iter_reg = fw->rcvt1_data_dma_reg;
				1215	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1216	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1217
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1218	/* RISC registers. */
				1219	iter_reg = fw->risc_gp_reg;
				1220	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1221	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1222	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1223	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1224	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1225	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1226	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1227	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1228
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1229	/* Local memory controller registers. */
				1230	iter_reg = fw->lmc_reg;
				1231	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1232	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1233	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1234	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1235	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1236	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1237	qla24xx_read_window(reg, 0x3060, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1238
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1239	/* Fibre Protocol Module registers. */
				1240	iter_reg = fw->fpm_hdw_reg;
				1241	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1242	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1243	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1244	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1245	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1246	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1247	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1248	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1249	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1250	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1251	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1252	qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1253
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1254	/* Frame Buffer registers. */
				1255	iter_reg = fw->fb_hdw_reg;
				1256	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1257	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1258	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1259	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1260	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1261	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1262	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1263	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1264	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1265	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1266	qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1267
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1268	rval = qla24xx_soft_reset(ha);
				1269	if (rval != QLA_SUCCESS)
				1270	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1271
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1272	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	1273	&nxt);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1274	if (rval != QLA_SUCCESS)
				1275	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1276
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1277	nxt = qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1278
				1279	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1280
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1281	nxt_chain = (void *)ha->fw_dump + ha->chain_offset;
				1282	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
				1283	if (last_chain) {
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	1284	ha->fw_dump->version \|= htonl(DUMP_CHAIN_VARIANT);
				1285	*last_chain \|= htonl(DUMP_CHAIN_LAST);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1286	}
				1287
				1288	/* Adjust valid length. */
				1289	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1290
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1291	qla24xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1292	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1293
				1294	qla24xx_fw_dump_failed:
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1295	#ifndef __CHECKER__
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1296	if (!hardware_locked)
				1297	spin_unlock_irqrestore(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1298	#else
				1299	;
				1300	#endif
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1301	}
				1302
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1303	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1304	qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1305	{
				1306	int rval;
				1307	uint32_t cnt;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1308	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1309	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1310	uint32_t __iomem *dmp_reg;
				1311	uint32_t *iter_reg;
				1312	uint16_t __iomem *mbx_reg;
				1313	unsigned long flags;
				1314	struct qla25xx_fw_dump *fw;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1315	void nxt, nxt_chain;
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1316	uint32_t *last_chain = NULL;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1317	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1318
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1319	flags = 0;
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1320	ha->fw_dump_cap_flags = 0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1321
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1322	#ifndef __CHECKER__
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1323	if (!hardware_locked)
				1324	spin_lock_irqsave(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1325	#endif
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1326
				1327	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1328	ql_log(ql_log_warn, vha, 0xd008,
				1329	"No buffer available for dump.\n");
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1330	goto qla25xx_fw_dump_failed;
				1331	}
				1332
				1333	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1334	ql_log(ql_log_warn, vha, 0xd009,
				1335	"Firmware has been previously dumped (%p) "
				1336	"-- ignoring request.\n",
				1337	ha->fw_dump);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1338	goto qla25xx_fw_dump_failed;
				1339	}
				1340	fw = &ha->fw_dump->isp.isp25;
				1341	qla2xxx_prep_dump(ha, ha->fw_dump);
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	1342	ha->fw_dump->version = htonl(2);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1343
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1344	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1345
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	1346	/*
				1347	* Pause RISC. No need to track timeout, as resetting the chip
				1348	* is the right approach incase of pause timeout
				1349	*/
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1350	qla24xx_pause_risc(reg, ha);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1351
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1352	/* Host/Risc registers. */
				1353	iter_reg = fw->host_risc_reg;
				1354	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1355	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1356
				1357	/* PCIe registers. */
				1358	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1359	RD_REG_DWORD(&reg->iobase_addr);
				1360	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1361	dmp_reg = &reg->iobase_c4;
				1362	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				1363	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				1364	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1365	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1366
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1367	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1368	RD_REG_DWORD(&reg->iobase_window);
				1369
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1370	/* Host interface registers. */
				1371	dmp_reg = &reg->flash_addr;
				1372	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1373	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1374
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1375	/* Disable interrupts. */
				1376	WRT_REG_DWORD(&reg->ictrl, 0);
				1377	RD_REG_DWORD(&reg->ictrl);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1378
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1379	/* Shadow registers. */
				1380	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1381	RD_REG_DWORD(&reg->iobase_addr);
				1382	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1383	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1384
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1385	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1386	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1387
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1388	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1389	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1390
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1391	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1392	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1393
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1394	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1395	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1396
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1397	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1398	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1399
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1400	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1401	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1402
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1403	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1404	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1405
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1406	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1407	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1408
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1409	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1410	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1411
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1412	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1413	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1414
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1415	/* RISC I/O register. */
				1416	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1417	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1418
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1419	/* Mailbox registers. */
				1420	mbx_reg = &reg->mailbox0;
				1421	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1422	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1423
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1424	/* Transfer sequence registers. */
				1425	iter_reg = fw->xseq_gp_reg;
				1426	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1427	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1428	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1429	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1430	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1431	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1432	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1433	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1434
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1435	iter_reg = fw->xseq_0_reg;
				1436	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1437	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1438	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1439
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1440	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1441
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1442	/* Receive sequence registers. */
				1443	iter_reg = fw->rseq_gp_reg;
				1444	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1445	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1446	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1447	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1448	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1449	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1450	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1451	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1452
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1453	iter_reg = fw->rseq_0_reg;
				1454	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				1455	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1456
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1457	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1458	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1459
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1460	/* Auxiliary sequence registers. */
				1461	iter_reg = fw->aseq_gp_reg;
				1462	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				1463	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				1464	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				1465	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				1466	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				1467	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				1468	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				1469	qla24xx_read_window(reg, 0xB070, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1470
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1471	iter_reg = fw->aseq_0_reg;
				1472	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				1473	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1474
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1475	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				1476	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1477
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1478	/* Command DMA registers. */
				1479	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1480
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1481	/* Queues. */
				1482	iter_reg = fw->req0_dma_reg;
				1483	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1484	dmp_reg = &reg->iobase_q;
				1485	for (cnt = 0; cnt < 7; cnt++)
				1486	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1487
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1488	iter_reg = fw->resp0_dma_reg;
				1489	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1490	dmp_reg = &reg->iobase_q;
				1491	for (cnt = 0; cnt < 7; cnt++)
				1492	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1493
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1494	iter_reg = fw->req1_dma_reg;
				1495	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1496	dmp_reg = &reg->iobase_q;
				1497	for (cnt = 0; cnt < 7; cnt++)
				1498	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1499
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1500	/* Transmit DMA registers. */
				1501	iter_reg = fw->xmt0_dma_reg;
				1502	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1503	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1504
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1505	iter_reg = fw->xmt1_dma_reg;
				1506	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1507	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1508
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1509	iter_reg = fw->xmt2_dma_reg;
				1510	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1511	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1512
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1513	iter_reg = fw->xmt3_dma_reg;
				1514	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1515	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1516
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1517	iter_reg = fw->xmt4_dma_reg;
				1518	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1519	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1520
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1521	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1522
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1523	/* Receive DMA registers. */
				1524	iter_reg = fw->rcvt0_data_dma_reg;
				1525	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1526	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1527
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1528	iter_reg = fw->rcvt1_data_dma_reg;
				1529	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1530	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1531
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1532	/* RISC registers. */
				1533	iter_reg = fw->risc_gp_reg;
				1534	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1535	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1536	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1537	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1538	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1539	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1540	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1541	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1542
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1543	/* Local memory controller registers. */
				1544	iter_reg = fw->lmc_reg;
				1545	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1546	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1547	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1548	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1549	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1550	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1551	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				1552	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1553
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1554	/* Fibre Protocol Module registers. */
				1555	iter_reg = fw->fpm_hdw_reg;
				1556	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1557	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1558	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1559	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1560	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1561	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1562	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1563	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1564	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1565	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1566	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1567	qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1568
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1569	/* Frame Buffer registers. */
				1570	iter_reg = fw->fb_hdw_reg;
				1571	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1572	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1573	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1574	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1575	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1576	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1577	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1578	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1579	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1580	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1581	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				1582	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1583
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1584	/* Multi queue registers */
				1585	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				1586	&last_chain);
				1587
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1588	rval = qla24xx_soft_reset(ha);
				1589	if (rval != QLA_SUCCESS)
				1590	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1591
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1592	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	1593	&nxt);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1594	if (rval != QLA_SUCCESS)
				1595	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1596
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1597	nxt = qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1598
Bart Van Assche	7f544d0	2013-06-25 11:27:27 -0400	[diff] [blame]	1599	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	df613b9	2008-01-17 09:02:17 -0800	[diff] [blame]	1600
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1601	/* Chain entries -- started with MQ. */
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1602	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				1603	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1604	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1605	if (last_chain) {
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	1606	ha->fw_dump->version \|= htonl(DUMP_CHAIN_VARIANT);
				1607	*last_chain \|= htonl(DUMP_CHAIN_LAST);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1608	}
Andrew Vasquez	df613b9	2008-01-17 09:02:17 -0800	[diff] [blame]	1609
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1610	/* Adjust valid length. */
				1611	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1612
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1613	qla25xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1614	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1615
				1616	qla25xx_fw_dump_failed:
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1617	#ifndef __CHECKER__
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1618	if (!hardware_locked)
				1619	spin_unlock_irqrestore(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1620	#else
				1621	;
				1622	#endif
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1623	}
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1624
				1625	void
				1626	qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
				1627	{
				1628	int rval;
				1629	uint32_t cnt;
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1630	struct qla_hw_data *ha = vha->hw;
				1631	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1632	uint32_t __iomem *dmp_reg;
				1633	uint32_t *iter_reg;
				1634	uint16_t __iomem *mbx_reg;
				1635	unsigned long flags;
				1636	struct qla81xx_fw_dump *fw;
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1637	void nxt, nxt_chain;
				1638	uint32_t *last_chain = NULL;
				1639	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
				1640
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1641	flags = 0;
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1642	ha->fw_dump_cap_flags = 0;
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1643
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1644	#ifndef __CHECKER__
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1645	if (!hardware_locked)
				1646	spin_lock_irqsave(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1647	#endif
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1648
				1649	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1650	ql_log(ql_log_warn, vha, 0xd00a,
				1651	"No buffer available for dump.\n");
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1652	goto qla81xx_fw_dump_failed;
				1653	}
				1654
				1655	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1656	ql_log(ql_log_warn, vha, 0xd00b,
				1657	"Firmware has been previously dumped (%p) "
				1658	"-- ignoring request.\n",
				1659	ha->fw_dump);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1660	goto qla81xx_fw_dump_failed;
				1661	}
				1662	fw = &ha->fw_dump->isp.isp81;
				1663	qla2xxx_prep_dump(ha, ha->fw_dump);
				1664
				1665	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1666
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	1667	/*
				1668	* Pause RISC. No need to track timeout, as resetting the chip
				1669	* is the right approach incase of pause timeout
				1670	*/
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1671	qla24xx_pause_risc(reg, ha);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1672
				1673	/* Host/Risc registers. */
				1674	iter_reg = fw->host_risc_reg;
				1675	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1676	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1677
				1678	/* PCIe registers. */
				1679	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1680	RD_REG_DWORD(&reg->iobase_addr);
				1681	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1682	dmp_reg = &reg->iobase_c4;
				1683	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				1684	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				1685	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1686	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
				1687
				1688	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1689	RD_REG_DWORD(&reg->iobase_window);
				1690
				1691	/* Host interface registers. */
				1692	dmp_reg = &reg->flash_addr;
				1693	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1694	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
				1695
				1696	/* Disable interrupts. */
				1697	WRT_REG_DWORD(&reg->ictrl, 0);
				1698	RD_REG_DWORD(&reg->ictrl);
				1699
				1700	/* Shadow registers. */
				1701	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1702	RD_REG_DWORD(&reg->iobase_addr);
				1703	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1704	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1705
				1706	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1707	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1708
				1709	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1710	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1711
				1712	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1713	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1714
				1715	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1716	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1717
				1718	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1719	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1720
				1721	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1722	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1723
				1724	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1725	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1726
				1727	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1728	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1729
				1730	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1731	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1732
				1733	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1734	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1735
				1736	/* RISC I/O register. */
				1737	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1738	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
				1739
				1740	/* Mailbox registers. */
				1741	mbx_reg = &reg->mailbox0;
				1742	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1743	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
				1744
				1745	/* Transfer sequence registers. */
				1746	iter_reg = fw->xseq_gp_reg;
				1747	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1748	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1749	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1750	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1751	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1752	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1753	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1754	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
				1755
				1756	iter_reg = fw->xseq_0_reg;
				1757	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1758	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1759	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
				1760
				1761	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
				1762
				1763	/* Receive sequence registers. */
				1764	iter_reg = fw->rseq_gp_reg;
				1765	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1766	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1767	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1768	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1769	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1770	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1771	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1772	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
				1773
				1774	iter_reg = fw->rseq_0_reg;
				1775	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				1776	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
				1777
				1778	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1779	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
				1780
				1781	/* Auxiliary sequence registers. */
				1782	iter_reg = fw->aseq_gp_reg;
				1783	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				1784	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				1785	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				1786	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				1787	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				1788	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				1789	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				1790	qla24xx_read_window(reg, 0xB070, 16, iter_reg);
				1791
				1792	iter_reg = fw->aseq_0_reg;
				1793	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				1794	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
				1795
				1796	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				1797	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
				1798
				1799	/* Command DMA registers. */
				1800	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
				1801
				1802	/* Queues. */
				1803	iter_reg = fw->req0_dma_reg;
				1804	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1805	dmp_reg = &reg->iobase_q;
				1806	for (cnt = 0; cnt < 7; cnt++)
				1807	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1808
				1809	iter_reg = fw->resp0_dma_reg;
				1810	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1811	dmp_reg = &reg->iobase_q;
				1812	for (cnt = 0; cnt < 7; cnt++)
				1813	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1814
				1815	iter_reg = fw->req1_dma_reg;
				1816	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1817	dmp_reg = &reg->iobase_q;
				1818	for (cnt = 0; cnt < 7; cnt++)
				1819	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1820
				1821	/* Transmit DMA registers. */
				1822	iter_reg = fw->xmt0_dma_reg;
				1823	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1824	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
				1825
				1826	iter_reg = fw->xmt1_dma_reg;
				1827	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1828	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
				1829
				1830	iter_reg = fw->xmt2_dma_reg;
				1831	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1832	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
				1833
				1834	iter_reg = fw->xmt3_dma_reg;
				1835	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1836	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
				1837
				1838	iter_reg = fw->xmt4_dma_reg;
				1839	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1840	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
				1841
				1842	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
				1843
				1844	/* Receive DMA registers. */
				1845	iter_reg = fw->rcvt0_data_dma_reg;
				1846	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1847	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
				1848
				1849	iter_reg = fw->rcvt1_data_dma_reg;
				1850	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1851	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
				1852
				1853	/* RISC registers. */
				1854	iter_reg = fw->risc_gp_reg;
				1855	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1856	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1857	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1858	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1859	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1860	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1861	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1862	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
				1863
				1864	/* Local memory controller registers. */
				1865	iter_reg = fw->lmc_reg;
				1866	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1867	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1868	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1869	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1870	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1871	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1872	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				1873	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
				1874
				1875	/* Fibre Protocol Module registers. */
				1876	iter_reg = fw->fpm_hdw_reg;
				1877	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1878	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1879	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1880	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1881	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1882	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1883	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1884	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1885	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1886	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1887	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1888	iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
				1889	iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
				1890	qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
				1891
				1892	/* Frame Buffer registers. */
				1893	iter_reg = fw->fb_hdw_reg;
				1894	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1895	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1896	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1897	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1898	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1899	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1900	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1901	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1902	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1903	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1904	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				1905	iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
				1906	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
				1907
				1908	/* Multi queue registers */
				1909	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				1910	&last_chain);
				1911
				1912	rval = qla24xx_soft_reset(ha);
				1913	if (rval != QLA_SUCCESS)
				1914	goto qla81xx_fw_dump_failed_0;
				1915
				1916	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
				1917	&nxt);
				1918	if (rval != QLA_SUCCESS)
				1919	goto qla81xx_fw_dump_failed_0;
				1920
				1921	nxt = qla2xxx_copy_queues(ha, nxt);
				1922
Bart Van Assche	7f544d0	2013-06-25 11:27:27 -0400	[diff] [blame]	1923	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1924
				1925	/* Chain entries -- started with MQ. */
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1926	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				1927	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1928	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1929	if (last_chain) {
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	1930	ha->fw_dump->version \|= htonl(DUMP_CHAIN_VARIANT);
				1931	*last_chain \|= htonl(DUMP_CHAIN_LAST);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1932	}
				1933
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1934	/* Adjust valid length. */
				1935	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1936
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1937	qla81xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1938	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1939
				1940	qla81xx_fw_dump_failed:
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1941	#ifndef __CHECKER__
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1942	if (!hardware_locked)
				1943	spin_unlock_irqrestore(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1944	#else
				1945	;
				1946	#endif
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1947	}
				1948
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1949	void
				1950	qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
				1951	{
				1952	int rval;
Bart Van Assche	52c8282	2015-07-09 07:23:26 -0700	[diff] [blame]	1953	uint32_t cnt;
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1954	struct qla_hw_data *ha = vha->hw;
				1955	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1956	uint32_t __iomem *dmp_reg;
				1957	uint32_t *iter_reg;
				1958	uint16_t __iomem *mbx_reg;
				1959	unsigned long flags;
				1960	struct qla83xx_fw_dump *fw;
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1961	void nxt, nxt_chain;
				1962	uint32_t *last_chain = NULL;
				1963	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
				1964
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1965	flags = 0;
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1966	ha->fw_dump_cap_flags = 0;
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1967
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1968	#ifndef __CHECKER__
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1969	if (!hardware_locked)
				1970	spin_lock_irqsave(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1971	#endif
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1972
				1973	if (!ha->fw_dump) {
				1974	ql_log(ql_log_warn, vha, 0xd00c,
				1975	"No buffer available for dump!!!\n");
				1976	goto qla83xx_fw_dump_failed;
				1977	}
				1978
				1979	if (ha->fw_dumped) {
				1980	ql_log(ql_log_warn, vha, 0xd00d,
				1981	"Firmware has been previously dumped (%p) -- ignoring "
				1982	"request...\n", ha->fw_dump);
				1983	goto qla83xx_fw_dump_failed;
				1984	}
				1985	fw = &ha->fw_dump->isp.isp83;
				1986	qla2xxx_prep_dump(ha, ha->fw_dump);
				1987
				1988	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1989
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	1990	/*
				1991	* Pause RISC. No need to track timeout, as resetting the chip
				1992	* is the right approach incase of pause timeout
				1993	*/
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1994	qla24xx_pause_risc(reg, ha);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1995
				1996	WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
				1997	dmp_reg = &reg->iobase_window;
Bart Van Assche	52c8282	2015-07-09 07:23:26 -0700	[diff] [blame]	1998	RD_REG_DWORD(dmp_reg);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1999	WRT_REG_DWORD(dmp_reg, 0);
				2000
				2001	dmp_reg = &reg->unused_4_1[0];
Bart Van Assche	52c8282	2015-07-09 07:23:26 -0700	[diff] [blame]	2002	RD_REG_DWORD(dmp_reg);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2003	WRT_REG_DWORD(dmp_reg, 0);
				2004
				2005	WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
				2006	dmp_reg = &reg->unused_4_1[2];
Bart Van Assche	52c8282	2015-07-09 07:23:26 -0700	[diff] [blame]	2007	RD_REG_DWORD(dmp_reg);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2008	WRT_REG_DWORD(dmp_reg, 0);
				2009
				2010	/* select PCR and disable ecc checking and correction */
				2011	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				2012	RD_REG_DWORD(&reg->iobase_addr);
				2013	WRT_REG_DWORD(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
				2014
				2015	/* Host/Risc registers. */
				2016	iter_reg = fw->host_risc_reg;
				2017	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				2018	iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				2019	qla24xx_read_window(reg, 0x7040, 16, iter_reg);
				2020
				2021	/* PCIe registers. */
				2022	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				2023	RD_REG_DWORD(&reg->iobase_addr);
				2024	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				2025	dmp_reg = &reg->iobase_c4;
				2026	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				2027	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				2028	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				2029	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
				2030
				2031	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				2032	RD_REG_DWORD(&reg->iobase_window);
				2033
				2034	/* Host interface registers. */
				2035	dmp_reg = &reg->flash_addr;
				2036	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				2037	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
				2038
				2039	/* Disable interrupts. */
				2040	WRT_REG_DWORD(&reg->ictrl, 0);
				2041	RD_REG_DWORD(&reg->ictrl);
				2042
				2043	/* Shadow registers. */
				2044	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				2045	RD_REG_DWORD(&reg->iobase_addr);
				2046	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				2047	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2048
				2049	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				2050	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2051
				2052	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				2053	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2054
				2055	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				2056	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2057
				2058	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				2059	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2060
				2061	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				2062	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2063
				2064	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				2065	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2066
				2067	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				2068	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2069
				2070	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				2071	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2072
				2073	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				2074	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2075
				2076	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				2077	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2078
				2079	/* RISC I/O register. */
				2080	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				2081	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
				2082
				2083	/* Mailbox registers. */
				2084	mbx_reg = &reg->mailbox0;
				2085	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				2086	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
				2087
				2088	/* Transfer sequence registers. */
				2089	iter_reg = fw->xseq_gp_reg;
				2090	iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg);
				2091	iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg);
				2092	iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg);
				2093	iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg);
				2094	iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg);
				2095	iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg);
				2096	iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg);
				2097	iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg);
				2098	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				2099	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				2100	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				2101	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				2102	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				2103	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				2104	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				2105	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
				2106
				2107	iter_reg = fw->xseq_0_reg;
				2108	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				2109	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				2110	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
				2111
				2112	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
				2113
				2114	qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg);
				2115
				2116	/* Receive sequence registers. */
				2117	iter_reg = fw->rseq_gp_reg;
				2118	iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg);
				2119	iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg);
				2120	iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg);
				2121	iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg);
				2122	iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg);
				2123	iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg);
				2124	iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg);
				2125	iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg);
				2126	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				2127	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				2128	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				2129	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				2130	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				2131	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				2132	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				2133	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
				2134
				2135	iter_reg = fw->rseq_0_reg;
				2136	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				2137	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
				2138
				2139	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				2140	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
				2141	qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg);
				2142
				2143	/* Auxiliary sequence registers. */
				2144	iter_reg = fw->aseq_gp_reg;
				2145	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				2146	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				2147	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				2148	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				2149	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				2150	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				2151	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				2152	iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg);
				2153	iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg);
				2154	iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg);
				2155	iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg);
				2156	iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg);
				2157	iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg);
				2158	iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg);
				2159	iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg);
				2160	qla24xx_read_window(reg, 0xB170, 16, iter_reg);
				2161
				2162	iter_reg = fw->aseq_0_reg;
				2163	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				2164	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
				2165
				2166	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				2167	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
				2168	qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg);
				2169
				2170	/* Command DMA registers. */
				2171	iter_reg = fw->cmd_dma_reg;
				2172	iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg);
				2173	iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg);
				2174	iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg);
				2175	qla24xx_read_window(reg, 0x71F0, 16, iter_reg);
				2176
				2177	/* Queues. */
				2178	iter_reg = fw->req0_dma_reg;
				2179	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				2180	dmp_reg = &reg->iobase_q;
				2181	for (cnt = 0; cnt < 7; cnt++)
				2182	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2183
				2184	iter_reg = fw->resp0_dma_reg;
				2185	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				2186	dmp_reg = &reg->iobase_q;
				2187	for (cnt = 0; cnt < 7; cnt++)
				2188	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2189
				2190	iter_reg = fw->req1_dma_reg;
				2191	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				2192	dmp_reg = &reg->iobase_q;
				2193	for (cnt = 0; cnt < 7; cnt++)
				2194	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2195
				2196	/* Transmit DMA registers. */
				2197	iter_reg = fw->xmt0_dma_reg;
				2198	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				2199	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
				2200
				2201	iter_reg = fw->xmt1_dma_reg;
				2202	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				2203	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
				2204
				2205	iter_reg = fw->xmt2_dma_reg;
				2206	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				2207	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
				2208
				2209	iter_reg = fw->xmt3_dma_reg;
				2210	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				2211	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
				2212
				2213	iter_reg = fw->xmt4_dma_reg;
				2214	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				2215	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
				2216
				2217	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
				2218
				2219	/* Receive DMA registers. */
				2220	iter_reg = fw->rcvt0_data_dma_reg;
				2221	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				2222	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
				2223
				2224	iter_reg = fw->rcvt1_data_dma_reg;
				2225	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				2226	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
				2227
				2228	/* RISC registers. */
				2229	iter_reg = fw->risc_gp_reg;
				2230	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				2231	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				2232	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				2233	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				2234	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				2235	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				2236	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				2237	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
				2238
				2239	/* Local memory controller registers. */
				2240	iter_reg = fw->lmc_reg;
				2241	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				2242	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				2243	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				2244	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				2245	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				2246	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				2247	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				2248	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
				2249
				2250	/* Fibre Protocol Module registers. */
				2251	iter_reg = fw->fpm_hdw_reg;
				2252	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				2253	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				2254	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				2255	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				2256	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				2257	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				2258	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				2259	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				2260	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				2261	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				2262	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				2263	iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
				2264	iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
				2265	iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
				2266	iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg);
				2267	qla24xx_read_window(reg, 0x40F0, 16, iter_reg);
				2268
				2269	/* RQ0 Array registers. */
				2270	iter_reg = fw->rq0_array_reg;
				2271	iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg);
				2272	iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg);
				2273	iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg);
				2274	iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg);
				2275	iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg);
				2276	iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg);
				2277	iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg);
				2278	iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg);
				2279	iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg);
				2280	iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg);
				2281	iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg);
				2282	iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg);
				2283	iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg);
				2284	iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg);
				2285	iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg);
				2286	qla24xx_read_window(reg, 0x5CF0, 16, iter_reg);
				2287
				2288	/* RQ1 Array registers. */
				2289	iter_reg = fw->rq1_array_reg;
				2290	iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg);
				2291	iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg);
				2292	iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg);
				2293	iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg);
				2294	iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg);
				2295	iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg);
				2296	iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg);
				2297	iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg);
				2298	iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg);
				2299	iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg);
				2300	iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg);
				2301	iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg);
				2302	iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg);
				2303	iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg);
				2304	iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg);
				2305	qla24xx_read_window(reg, 0x5DF0, 16, iter_reg);
				2306
				2307	/* RP0 Array registers. */
				2308	iter_reg = fw->rp0_array_reg;
				2309	iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg);
				2310	iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg);
				2311	iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg);
				2312	iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg);
				2313	iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg);
				2314	iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg);
				2315	iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg);
				2316	iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg);
				2317	iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg);
				2318	iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg);
				2319	iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg);
				2320	iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg);
				2321	iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg);
				2322	iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg);
				2323	iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg);
				2324	qla24xx_read_window(reg, 0x5EF0, 16, iter_reg);
				2325
				2326	/* RP1 Array registers. */
				2327	iter_reg = fw->rp1_array_reg;
				2328	iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg);
				2329	iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg);
				2330	iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg);
				2331	iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg);
				2332	iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg);
				2333	iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg);
				2334	iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg);
				2335	iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg);
				2336	iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg);
				2337	iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg);
				2338	iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg);
				2339	iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg);
				2340	iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg);
				2341	iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg);
				2342	iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg);
				2343	qla24xx_read_window(reg, 0x5FF0, 16, iter_reg);
				2344
				2345	iter_reg = fw->at0_array_reg;
				2346	iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg);
				2347	iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg);
				2348	iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg);
				2349	iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg);
				2350	iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg);
				2351	iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg);
				2352	iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg);
				2353	qla24xx_read_window(reg, 0x70F0, 16, iter_reg);
				2354
				2355	/* I/O Queue Control registers. */
				2356	qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg);
				2357
				2358	/* Frame Buffer registers. */
				2359	iter_reg = fw->fb_hdw_reg;
				2360	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				2361	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				2362	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				2363	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				2364	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				2365	iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg);
				2366	iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg);
				2367	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				2368	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				2369	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				2370	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				2371	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				2372	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				2373	iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
				2374	iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg);
				2375	iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg);
				2376	iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg);
				2377	iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg);
				2378	iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg);
				2379	iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg);
				2380	iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg);
				2381	iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg);
				2382	iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg);
				2383	iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg);
				2384	iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg);
				2385	iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg);
				2386	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
				2387
				2388	/* Multi queue registers */
				2389	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				2390	&last_chain);
				2391
				2392	rval = qla24xx_soft_reset(ha);
				2393	if (rval != QLA_SUCCESS) {
				2394	ql_log(ql_log_warn, vha, 0xd00e,
				2395	"SOFT RESET FAILED, forcing continuation of dump!!!\n");
				2396	rval = QLA_SUCCESS;
				2397
				2398	ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
				2399
				2400	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
				2401	RD_REG_DWORD(&reg->hccr);
				2402
				2403	WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
				2404	RD_REG_DWORD(&reg->hccr);
				2405
				2406	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
				2407	RD_REG_DWORD(&reg->hccr);
				2408
				2409	for (cnt = 30000; cnt && (RD_REG_WORD(&reg->mailbox0)); cnt--)
				2410	udelay(5);
				2411
				2412	if (!cnt) {
				2413	nxt = fw->code_ram;
Saurav Kashyap	8c0bc70	2012-11-21 02:40:35 -0500	[diff] [blame]	2414	nxt += sizeof(fw->code_ram);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2415	nxt += (ha->fw_memory_size - 0x100000 + 1);
				2416	goto copy_queue;
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	2417	} else {
				2418	set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2419	ql_log(ql_log_warn, vha, 0xd010,
				2420	"bigger hammer success?\n");
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	2421	}
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2422	}
				2423
				2424	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
				2425	&nxt);
				2426	if (rval != QLA_SUCCESS)
				2427	goto qla83xx_fw_dump_failed_0;
				2428
				2429	copy_queue:
				2430	nxt = qla2xxx_copy_queues(ha, nxt);
				2431
Bart Van Assche	7f544d0	2013-06-25 11:27:27 -0400	[diff] [blame]	2432	qla24xx_copy_eft(ha, nxt);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2433
				2434	/* Chain entries -- started with MQ. */
				2435	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				2436	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	2437	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2438	if (last_chain) {
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	2439	ha->fw_dump->version \|= htonl(DUMP_CHAIN_VARIANT);
				2440	*last_chain \|= htonl(DUMP_CHAIN_LAST);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2441	}
				2442
				2443	/* Adjust valid length. */
				2444	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				2445
				2446	qla83xx_fw_dump_failed_0:
				2447	qla2xxx_dump_post_process(base_vha, rval);
				2448
				2449	qla83xx_fw_dump_failed:
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	2450	#ifndef __CHECKER__
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2451	if (!hardware_locked)
				2452	spin_unlock_irqrestore(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	2453	#else
				2454	;
				2455	#endif
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2456	}
				2457
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	2458	/****************************************************************************/
				2459	/* Driver Debug Functions. */
				2460	/****************************************************************************/
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2461
				2462	static inline int
				2463	ql_mask_match(uint32_t level)
				2464	{
				2465	if (ql2xextended_error_logging == 1)
				2466	ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
				2467	return (level & ql2xextended_error_logging) == level;
				2468	}
				2469
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2470	/*
				2471	* This function is for formatting and logging debug information.
				2472	* It is to be used when vha is available. It formats the message
				2473	* and logs it to the messages file.
				2474	* parameters:
				2475	* level: The level of the debug messages to be printed.
				2476	* If ql2xextended_error_logging value is correctly set,
				2477	* this message will appear in the messages file.
				2478	* vha: Pointer to the scsi_qla_host_t.
				2479	* id: This is a unique identifier for the level. It identifies the
				2480	* part of the code from where the message originated.
				2481	* msg: The message to be displayed.
				2482	*/
				2483	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2484	ql_dbg(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
				2485	{
				2486	va_list va;
				2487	struct va_format vaf;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2488
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2489	if (!ql_mask_match(level))
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2490	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2491
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2492	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2493
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2494	vaf.fmt = fmt;
				2495	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2496
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2497	if (vha != NULL) {
				2498	const struct pci_dev *pdev = vha->hw->pdev;
				2499	/* <module-name> <pci-name> <msg-id>:<host> Message */
				2500	pr_warn("%s [%s]-%04x:%ld: %pV",
				2501	QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
				2502	vha->host_no, &vaf);
				2503	} else {
				2504	pr_warn("%s [%s]-%04x: : %pV",
				2505	QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2506	}
				2507
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2508	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2509
				2510	}
				2511
				2512	/*
				2513	* This function is for formatting and logging debug information.
Masanari Iida	d6a0358	2012-08-22 14:20:58 -0400	[diff] [blame]	2514	* It is to be used when vha is not available and pci is available,
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2515	* i.e., before host allocation. It formats the message and logs it
				2516	* to the messages file.
				2517	* parameters:
				2518	* level: The level of the debug messages to be printed.
				2519	* If ql2xextended_error_logging value is correctly set,
				2520	* this message will appear in the messages file.
				2521	* pdev: Pointer to the struct pci_dev.
				2522	* id: This is a unique id for the level. It identifies the part
				2523	* of the code from where the message originated.
				2524	* msg: The message to be displayed.
				2525	*/
				2526	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2527	ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
				2528	const char *fmt, ...)
				2529	{
				2530	va_list va;
				2531	struct va_format vaf;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2532
				2533	if (pdev == NULL)
				2534	return;
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2535	if (!ql_mask_match(level))
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2536	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2537
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2538	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2539
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2540	vaf.fmt = fmt;
				2541	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2542
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2543	/* <module-name> <dev-name>:<msg-id> Message */
				2544	pr_warn("%s [%s]-%04x: : %pV",
				2545	QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2546
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2547	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2548	}
				2549
				2550	/*
				2551	* This function is for formatting and logging log messages.
				2552	* It is to be used when vha is available. It formats the message
				2553	* and logs it to the messages file. All the messages will be logged
				2554	* irrespective of value of ql2xextended_error_logging.
				2555	* parameters:
				2556	* level: The level of the log messages to be printed in the
				2557	* messages file.
				2558	* vha: Pointer to the scsi_qla_host_t
				2559	* id: This is a unique id for the level. It identifies the
				2560	* part of the code from where the message originated.
				2561	* msg: The message to be displayed.
				2562	*/
				2563	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2564	ql_log(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
				2565	{
				2566	va_list va;
				2567	struct va_format vaf;
				2568	char pbuf[128];
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2569
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2570	if (level > ql_errlev)
				2571	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2572
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2573	if (vha != NULL) {
				2574	const struct pci_dev *pdev = vha->hw->pdev;
				2575	/* <module-name> <msg-id>:<host> Message */
				2576	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
				2577	QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
				2578	} else {
				2579	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
				2580	QL_MSGHDR, "0000:00:00.0", id);
				2581	}
				2582	pbuf[sizeof(pbuf) - 1] = 0;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2583
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2584	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2585
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2586	vaf.fmt = fmt;
				2587	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2588
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2589	switch (level) {
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2590	case ql_log_fatal: /* FATAL LOG */
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2591	pr_crit("%s%pV", pbuf, &vaf);
				2592	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2593	case ql_log_warn:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2594	pr_err("%s%pV", pbuf, &vaf);
				2595	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2596	case ql_log_info:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2597	pr_warn("%s%pV", pbuf, &vaf);
				2598	break;
				2599	default:
				2600	pr_info("%s%pV", pbuf, &vaf);
				2601	break;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2602	}
				2603
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2604	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2605	}
				2606
				2607	/*
				2608	* This function is for formatting and logging log messages.
Masanari Iida	d6a0358	2012-08-22 14:20:58 -0400	[diff] [blame]	2609	* It is to be used when vha is not available and pci is available,
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2610	* i.e., before host allocation. It formats the message and logs
				2611	* it to the messages file. All the messages are logged irrespective
				2612	* of the value of ql2xextended_error_logging.
				2613	* parameters:
				2614	* level: The level of the log messages to be printed in the
				2615	* messages file.
				2616	* pdev: Pointer to the struct pci_dev.
				2617	* id: This is a unique id for the level. It identifies the
				2618	* part of the code from where the message originated.
				2619	* msg: The message to be displayed.
				2620	*/
				2621	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2622	ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
				2623	const char *fmt, ...)
				2624	{
				2625	va_list va;
				2626	struct va_format vaf;
				2627	char pbuf[128];
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2628
				2629	if (pdev == NULL)
				2630	return;
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2631	if (level > ql_errlev)
				2632	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2633
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2634	/* <module-name> <dev-name>:<msg-id> Message */
				2635	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
				2636	QL_MSGHDR, dev_name(&(pdev->dev)), id);
				2637	pbuf[sizeof(pbuf) - 1] = 0;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2638
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2639	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2640
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2641	vaf.fmt = fmt;
				2642	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2643
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2644	switch (level) {
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2645	case ql_log_fatal: /* FATAL LOG */
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2646	pr_crit("%s%pV", pbuf, &vaf);
				2647	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2648	case ql_log_warn:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2649	pr_err("%s%pV", pbuf, &vaf);
				2650	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2651	case ql_log_info:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2652	pr_warn("%s%pV", pbuf, &vaf);
				2653	break;
				2654	default:
				2655	pr_info("%s%pV", pbuf, &vaf);
				2656	break;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2657	}
				2658
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2659	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2660	}
				2661
				2662	void
				2663	ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
				2664	{
				2665	int i;
				2666	struct qla_hw_data *ha = vha->hw;
				2667	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
				2668	struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
				2669	struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
				2670	uint16_t __iomem *mbx_reg;
				2671
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2672	if (!ql_mask_match(level))
				2673	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2674
Atul Deshmukh	7ec0eff	2013-08-27 01:37:28 -0400	[diff] [blame]	2675	if (IS_P3P_TYPE(ha))
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2676	mbx_reg = &reg82->mailbox_in[0];
				2677	else if (IS_FWI2_CAPABLE(ha))
				2678	mbx_reg = &reg24->mailbox0;
				2679	else
				2680	mbx_reg = MAILBOX_REG(ha, reg, 0);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2681
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2682	ql_dbg(level, vha, id, "Mailbox registers:\n");
				2683	for (i = 0; i < 6; i++)
				2684	ql_dbg(level, vha, id,
				2685	"mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2686	}
				2687
				2688
				2689	void
				2690	ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
				2691	uint8_t *b, uint32_t size)
				2692	{
				2693	uint32_t cnt;
				2694	uint8_t c;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2695
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2696	if (!ql_mask_match(level))
				2697	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2698
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2699	ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
				2700	"9 Ah Bh Ch Dh Eh Fh\n");
				2701	ql_dbg(level, vha, id, "----------------------------------"
				2702	"----------------------------\n");
				2703
				2704	ql_dbg(level, vha, id, " ");
				2705	for (cnt = 0; cnt < size;) {
				2706	c = *b++;
				2707	printk("%02x", (uint32_t) c);
				2708	cnt++;
				2709	if (!(cnt % 16))
				2710	printk("\n");
				2711	else
				2712	printk(" ");
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2713	}
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2714	if (cnt % 16)
				2715	ql_dbg(level, vha, id, "\n");
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2716	}