Blame - drivers/scsi/qla2xxx/qla_dbg.c - kernel/msm-4.9

blob: b063c3928f88ab952c1e98c8d3824e7298f38e51 [file] [log] [blame]

Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1	/*
Andrew Vasquez	fa90c54	2005-10-27 11:10:08 -0700	[diff] [blame]	2	* QLogic Fibre Channel HBA Driver
Saurav Kashyap	1e63395	2013-02-08 01:57:54 -0500	[diff] [blame]	3	* Copyright (c) 2003-2013 QLogic Corporation
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	4	*
Andrew Vasquez	fa90c54	2005-10-27 11:10:08 -0700	[diff] [blame]	5	* See LICENSE.qla2xxx for copyright and licensing details.
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	6	*/
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	7
				8	/*
				9	* Table for showing the current message id in use for particular level
				10	* Change this table for addition of log/debug messages.
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	11	* ----------------------------------------------------------------------
				12	* \| Level \| Last Value Used \| Holes \|
				13	* ----------------------------------------------------------------------
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	14	* \| Module Init and Probe \| 0x017d \| 0x004b,0x0141 \|
				15	* \| \| \| 0x0144,0x0146 \|
				16	* \| \| \| 0x015b-0x0160 \|
				17	* \| \| \| 0x016e-0x0170 \|
Joe Carnuccio	e8887c5	2014-04-11 16:54:17 -0400	[diff] [blame]	18	* \| Mailbox commands \| 0x118d \| 0x1018-0x1019 \|
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	19	* \| \| \| 0x10ca \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	20	* \| \| \| 0x1115-0x1116 \|
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	21	* \| \| \| 0x111a-0x111b \|
				22	* \| \| \| 0x1155-0x1158 \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	23	* \| Device Discovery \| 0x2095 \| 0x2020-0x2022, \|
Bart Van Assche	6593d5b	2013-06-25 11:27:24 -0400	[diff] [blame]	24	* \| \| \| 0x2011-0x2012, \|
Saurav Kashyap	2a8593f	2012-08-22 14:21:27 -0400	[diff] [blame]	25	* \| \| \| 0x2016 \|
Chad Dupuis	36008cf	2013-10-03 03:21:13 -0400	[diff] [blame]	26	* \| Queue Command and IO tracing \| 0x3059 \| 0x3006-0x300b \|
Arun Easi	9e522cd	2012-08-22 14:21:31 -0400	[diff] [blame]	27	* \| \| \| 0x3027-0x3028 \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	28	* \| \| \| 0x303d-0x3041 \|
				29	* \| \| \| 0x302d,0x3033 \|
				30	* \| \| \| 0x3036,0x3038 \|
				31	* \| \| \| 0x303a \|
Armen Baloyan	e8f5e95	2013-10-30 03:38:17 -0400	[diff] [blame]	32	* \| DPC Thread \| 0x4023 \| 0x4002,0x4013 \|
Santosh Vernekar	454073c	2013-08-27 01:37:48 -0400	[diff] [blame]	33	* \| Async Events \| 0x5087 \| 0x502b-0x502f \|
Giridhar Malavali	9ba56b9	2012-02-09 11:15:36 -0800	[diff] [blame]	34	* \| \| \| 0x5047,0x5052 \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	35	* \| \| \| 0x5084,0x5075 \|
Chad Dupuis	a78951b	2013-08-27 01:37:34 -0400	[diff] [blame]	36	* \| \| \| 0x503d,0x5044 \|
Armen Baloyan	faef62d	2014-02-26 04:15:17 -0500	[diff] [blame]	37	* \| \| \| 0x507b \|
Armen Baloyan	71e5600	2013-08-27 01:37:38 -0400	[diff] [blame]	38	* \| Timer Routines \| 0x6012 \| \|
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	39	* \| User Space Interactions \| 0x70e2 \| 0x7018,0x702e \|
				40	* \| \| \| 0x7020,0x7024 \|
				41	* \| \| \| 0x7039,0x7045 \|
				42	* \| \| \| 0x7073-0x7075 \|
				43	* \| \| \| 0x70a5-0x70a6 \|
				44	* \| \| \| 0x70a8,0x70ab \|
				45	* \| \| \| 0x70ad-0x70ae \|
				46	* \| \| \| 0x70d7-0x70db \|
				47	* \| \| \| 0x70de-0x70df \|
Armen Baloyan	5854771	2013-08-27 01:37:33 -0400	[diff] [blame]	48	* \| Task Management \| 0x803d \| 0x8025-0x8026 \|
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	49	* \| \| \| 0x800b,0x8039 \|
Saurav Kashyap	5f28d2d	2012-05-15 14:34:15 -0400	[diff] [blame]	50	* \| AER/EEH \| 0x9011 \| \|
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	51	* \| Virtual Port \| 0xa007 \| \|
Pratik Mohanty	804df80	2014-04-11 16:54:15 -0400	[diff] [blame]	52	* \| ISP82XX Specific \| 0xb155 \| 0xb002,0xb024 \|
Atul Deshmukh	7ec0eff	2013-08-27 01:37:28 -0400	[diff] [blame]	53	* \| \| \| 0xb09e,0xb0ae \|
				54	* \| \| \| 0xb0e0-0xb0ef \|
				55	* \| \| \| 0xb085,0xb0dc \|
				56	* \| \| \| 0xb107,0xb108 \|
				57	* \| \| \| 0xb111,0xb11e \|
				58	* \| \| \| 0xb12c,0xb12d \|
				59	* \| \| \| 0xb13a,0xb142 \|
				60	* \| \| \| 0xb13c-0xb140 \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	61	* \| \| \| 0xb149 \|
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	62	* \| MultiQ \| 0xc00c \| \|
Joe Carnuccio	0d90c34	2014-04-11 16:54:08 -0400	[diff] [blame]	63	* \| Misc \| 0xd300 \| 0xd017-0xd019 \|
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	64	* \| \| \| 0xd020 \|
				65	* \| \| \| 0xd02e-0xd0ff \|
				66	* \| \| \| 0xd101-0xd1fe \|
				67	* \| \| \| 0xd212-0xd2fe \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	68	* \| Target Mode \| 0xe070 \| 0xe021 \|
				69	* \| Target Mode Management \| 0xf072 \| 0xf002-0xf003 \|
				70	* \| \| \| 0xf046-0xf049 \|
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	71	* \| Target Mode Task Management \| 0x1000b \| \|
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	72	* ----------------------------------------------------------------------
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	73	*/
				74
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	75	#include "qla_def.h"
				76
				77	#include <linux/delay.h>
				78
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	79	static uint32_t ql_dbg_offset = 0x800;
				80
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	81	static inline void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	82	qla2xxx_prep_dump(struct qla_hw_data ha, struct qla2xxx_fw_dump fw_dump)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	83	{
				84	fw_dump->fw_major_version = htonl(ha->fw_major_version);
				85	fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
				86	fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
				87	fw_dump->fw_attributes = htonl(ha->fw_attributes);
				88
				89	fw_dump->vendor = htonl(ha->pdev->vendor);
				90	fw_dump->device = htonl(ha->pdev->device);
				91	fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
				92	fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
				93	}
				94
				95	static inline void *
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	96	qla2xxx_copy_queues(struct qla_hw_data ha, void ptr)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	97	{
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	98	struct req_que *req = ha->req_q_map[0];
				99	struct rsp_que *rsp = ha->rsp_q_map[0];
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	100	/* Request queue. */
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	101	memcpy(ptr, req->ring, req->length *
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	102	sizeof(request_t));
				103
				104	/* Response queue. */
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	105	ptr += req->length * sizeof(request_t);
				106	memcpy(ptr, rsp->ring, rsp->length *
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	107	sizeof(response_t));
				108
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	109	return ptr + (rsp->length * sizeof(response_t));
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	110	}
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	111
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	112	int
				113	qla27xx_dump_mpi_ram(struct qla_hw_data ha, uint32_t addr, uint32_t ram,
				114	uint32_t ram_dwords, void **nxt)
				115	{
				116	int rval;
				117	uint32_t cnt, stat, timer, dwords, idx;
				118	uint16_t mb0, mb1;
				119	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				120	dma_addr_t dump_dma = ha->gid_list_dma;
				121	uint32_t dump = (uint32_t )ha->gid_list;
				122
				123	rval = QLA_SUCCESS;
				124	mb0 = 0;
				125
				126	WRT_REG_WORD(&reg->mailbox0, MBC_LOAD_DUMP_MPI_RAM);
				127	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				128
				129	dwords = qla2x00_gid_list_size(ha) / 4;
				130	for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
				131	cnt += dwords, addr += dwords) {
				132	if (cnt + dwords > ram_dwords)
				133	dwords = ram_dwords - cnt;
				134
				135	WRT_REG_WORD(&reg->mailbox1, LSW(addr));
				136	WRT_REG_WORD(&reg->mailbox8, MSW(addr));
				137
				138	WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
				139	WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
				140	WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
				141	WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
				142
				143	WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
				144	WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
				145
				146	WRT_REG_WORD(&reg->mailbox9, 0);
				147	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
				148
				149	ha->flags.mbox_int = 0;
				150	for (timer = 6000000; timer; timer--) {
				151	/* Check for pending interrupts. */
				152	stat = RD_REG_DWORD(&reg->host_status);
				153	if (stat & HSRX_RISC_INT) {
				154	stat &= 0xff;
				155
				156	if (stat == 0x1 \|\| stat == 0x2 \|\|
				157	stat == 0x10 \|\| stat == 0x11) {
				158	set_bit(MBX_INTERRUPT,
				159	&ha->mbx_cmd_flags);
				160
				161	mb0 = RD_REG_WORD(&reg->mailbox0);
				162	mb1 = RD_REG_WORD(&reg->mailbox1);
				163
				164	WRT_REG_DWORD(&reg->hccr,
				165	HCCRX_CLR_RISC_INT);
				166	RD_REG_DWORD(&reg->hccr);
				167	break;
				168	}
				169
				170	/* Clear this intr; it wasn't a mailbox intr */
				171	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
				172	RD_REG_DWORD(&reg->hccr);
				173	}
				174	udelay(5);
				175	}
				176	ha->flags.mbox_int = 1;
				177
				178	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				179	rval = mb0 & MBS_MASK;
				180	for (idx = 0; idx < dwords; idx++)
				181	ram[cnt + idx] = IS_QLA27XX(ha) ?
				182	le32_to_cpu(dump[idx]) : swab32(dump[idx]);
				183	} else {
				184	rval = QLA_FUNCTION_FAILED;
				185	}
				186	}
				187
				188	*nxt = rval == QLA_SUCCESS ? &ram[cnt] : NULL;
				189	return rval;
				190	}
				191
				192	int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	193	qla24xx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint32_t ram,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	194	uint32_t ram_dwords, void **nxt)
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	195	{
				196	int rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	197	uint32_t cnt, stat, timer, dwords, idx;
				198	uint16_t mb0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	199	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	200	dma_addr_t dump_dma = ha->gid_list_dma;
				201	uint32_t dump = (uint32_t )ha->gid_list;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	202
				203	rval = QLA_SUCCESS;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	204	mb0 = 0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	205
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	206	WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	207	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				208
Chad Dupuis	642ef98	2012-02-09 11:15:57 -0800	[diff] [blame]	209	dwords = qla2x00_gid_list_size(ha) / 4;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	210	for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
				211	cnt += dwords, addr += dwords) {
				212	if (cnt + dwords > ram_dwords)
				213	dwords = ram_dwords - cnt;
				214
				215	WRT_REG_WORD(&reg->mailbox1, LSW(addr));
				216	WRT_REG_WORD(&reg->mailbox8, MSW(addr));
				217
				218	WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
				219	WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
				220	WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
				221	WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
				222
				223	WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
				224	WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	225	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
				226
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	227	ha->flags.mbox_int = 0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	228	for (timer = 6000000; timer; timer--) {
				229	/* Check for pending interrupts. */
				230	stat = RD_REG_DWORD(&reg->host_status);
				231	if (stat & HSRX_RISC_INT) {
				232	stat &= 0xff;
				233
				234	if (stat == 0x1 \|\| stat == 0x2 \|\|
				235	stat == 0x10 \|\| stat == 0x11) {
				236	set_bit(MBX_INTERRUPT,
				237	&ha->mbx_cmd_flags);
				238
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	239	mb0 = RD_REG_WORD(&reg->mailbox0);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	240
				241	WRT_REG_DWORD(&reg->hccr,
				242	HCCRX_CLR_RISC_INT);
				243	RD_REG_DWORD(&reg->hccr);
				244	break;
				245	}
				246
				247	/* Clear this intr; it wasn't a mailbox intr */
				248	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
				249	RD_REG_DWORD(&reg->hccr);
				250	}
				251	udelay(5);
				252	}
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	253	ha->flags.mbox_int = 1;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	254
				255	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	256	rval = mb0 & MBS_MASK;
				257	for (idx = 0; idx < dwords; idx++)
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	258	ram[cnt + idx] = IS_QLA27XX(ha) ?
				259	le32_to_cpu(dump[idx]) : swab32(dump[idx]);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	260	} else {
				261	rval = QLA_FUNCTION_FAILED;
				262	}
				263	}
				264
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	265	*nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	266	return rval;
				267	}
				268
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	269	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	270	qla24xx_dump_memory(struct qla_hw_data ha, uint32_t code_ram,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	271	uint32_t cram_size, void **nxt)
				272	{
				273	int rval;
				274
				275	/* Code RAM. */
				276	rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
				277	if (rval != QLA_SUCCESS)
				278	return rval;
				279
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame^]	280	set_bit(RISC_SRAM_DUMP_CMPL, &ha->fw_dump_cap_flags);
				281
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	282	/* External Memory. */
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame^]	283	rval = qla24xx_dump_ram(ha, 0x100000, *nxt,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	284	ha->fw_memory_size - 0x100000 + 1, nxt);
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame^]	285	if (rval == QLA_SUCCESS)
				286	set_bit(RISC_EXT_MEM_DUMP_CMPL, &ha->fw_dump_cap_flags);
				287
				288	return rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	289	}
				290
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	291	static uint32_t *
				292	qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
				293	uint32_t count, uint32_t *buf)
				294	{
				295	uint32_t __iomem *dmp_reg;
				296
				297	WRT_REG_DWORD(&reg->iobase_addr, iobase);
				298	dmp_reg = &reg->iobase_window;
				299	while (count--)
				300	*buf++ = htonl(RD_REG_DWORD(dmp_reg++));
				301
				302	return buf;
				303	}
				304
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	305	void
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame^]	306	qla24xx_pause_risc(struct device_reg_24xx __iomem reg, struct qla_hw_data ha)
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	307	{
Andrew Vasquez	c3b058a	2007-09-20 14:07:38 -0700	[diff] [blame]	308	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	309
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	310	/* 100 usec delay is sufficient enough for hardware to pause RISC */
				311	udelay(100);
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame^]	312	if (RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED)
				313	set_bit(RISC_PAUSE_CMPL, &ha->fw_dump_cap_flags);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	314	}
				315
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	316	int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	317	qla24xx_soft_reset(struct qla_hw_data *ha)
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	318	{
				319	int rval = QLA_SUCCESS;
				320	uint32_t cnt;
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	321	uint16_t wd;
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	322	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				323
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	324	/*
				325	* Reset RISC. The delay is dependent on system architecture.
				326	* Driver can proceed with the reset sequence after waiting
				327	* for a timeout period.
				328	*/
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	329	WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
				330	for (cnt = 0; cnt < 30000; cnt++) {
				331	if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
				332	break;
				333
				334	udelay(10);
				335	}
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame^]	336	if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
				337	set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	338
				339	WRT_REG_DWORD(&reg->ctrl_status,
				340	CSRX_ISP_SOFT_RESET\|CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
				341	pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
				342
				343	udelay(100);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	344
				345	/* Wait for soft-reset to complete. */
				346	for (cnt = 0; cnt < 30000; cnt++) {
				347	if ((RD_REG_DWORD(&reg->ctrl_status) &
				348	CSRX_ISP_SOFT_RESET) == 0)
				349	break;
				350
				351	udelay(10);
				352	}
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame^]	353	if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
				354	set_bit(ISP_RESET_CMPL, &ha->fw_dump_cap_flags);
				355
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	356	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
				357	RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
				358
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	359	for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	360	rval == QLA_SUCCESS; cnt--) {
				361	if (cnt)
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	362	udelay(10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	363	else
				364	rval = QLA_FUNCTION_TIMEOUT;
				365	}
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame^]	366	if (rval == QLA_SUCCESS)
				367	set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	368
				369	return rval;
				370	}
				371
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	372	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	373	qla2xxx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint16_t ram,
Andrew Vasquez	e18e963	2009-06-17 10:30:31 -0700	[diff] [blame]	374	uint32_t ram_words, void **nxt)
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	375	{
				376	int rval;
				377	uint32_t cnt, stat, timer, words, idx;
				378	uint16_t mb0;
				379	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
				380	dma_addr_t dump_dma = ha->gid_list_dma;
				381	uint16_t dump = (uint16_t )ha->gid_list;
				382
				383	rval = QLA_SUCCESS;
				384	mb0 = 0;
				385
				386	WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
				387	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				388
Chad Dupuis	642ef98	2012-02-09 11:15:57 -0800	[diff] [blame]	389	words = qla2x00_gid_list_size(ha) / 2;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	390	for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
				391	cnt += words, addr += words) {
				392	if (cnt + words > ram_words)
				393	words = ram_words - cnt;
				394
				395	WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
				396	WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
				397
				398	WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
				399	WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
				400	WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
				401	WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
				402
				403	WRT_MAILBOX_REG(ha, reg, 4, words);
				404	WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
				405
				406	for (timer = 6000000; timer; timer--) {
				407	/* Check for pending interrupts. */
				408	stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
				409	if (stat & HSR_RISC_INT) {
				410	stat &= 0xff;
				411
				412	if (stat == 0x1 \|\| stat == 0x2) {
				413	set_bit(MBX_INTERRUPT,
				414	&ha->mbx_cmd_flags);
				415
				416	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				417
				418	/* Release mailbox registers. */
				419	WRT_REG_WORD(&reg->semaphore, 0);
				420	WRT_REG_WORD(&reg->hccr,
				421	HCCR_CLR_RISC_INT);
				422	RD_REG_WORD(&reg->hccr);
				423	break;
				424	} else if (stat == 0x10 \|\| stat == 0x11) {
				425	set_bit(MBX_INTERRUPT,
				426	&ha->mbx_cmd_flags);
				427
				428	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				429
				430	WRT_REG_WORD(&reg->hccr,
				431	HCCR_CLR_RISC_INT);
				432	RD_REG_WORD(&reg->hccr);
				433	break;
				434	}
				435
				436	/* clear this intr; it wasn't a mailbox intr */
				437	WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
				438	RD_REG_WORD(&reg->hccr);
				439	}
				440	udelay(5);
				441	}
				442
				443	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				444	rval = mb0 & MBS_MASK;
				445	for (idx = 0; idx < words; idx++)
				446	ram[cnt + idx] = swab16(dump[idx]);
				447	} else {
				448	rval = QLA_FUNCTION_FAILED;
				449	}
				450	}
				451
				452	*nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
				453	return rval;
				454	}
				455
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	456	static inline void
				457	qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
				458	uint16_t *buf)
				459	{
				460	uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
				461
				462	while (count--)
				463	*buf++ = htons(RD_REG_WORD(dmp_reg++));
				464	}
				465
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	466	static inline void *
				467	qla24xx_copy_eft(struct qla_hw_data ha, void ptr)
				468	{
				469	if (!ha->eft)
				470	return ptr;
				471
				472	memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
				473	return ptr + ntohl(ha->fw_dump->eft_size);
				474	}
				475
				476	static inline void *
				477	qla25xx_copy_fce(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				478	{
				479	uint32_t cnt;
				480	uint32_t *iter_reg;
				481	struct qla2xxx_fce_chain *fcec = ptr;
				482
				483	if (!ha->fce)
				484	return ptr;
				485
				486	*last_chain = &fcec->type;
				487	fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
				488	fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
				489	fce_calc_size(ha->fce_bufs));
				490	fcec->size = htonl(fce_calc_size(ha->fce_bufs));
				491	fcec->addr_l = htonl(LSD(ha->fce_dma));
				492	fcec->addr_h = htonl(MSD(ha->fce_dma));
				493
				494	iter_reg = fcec->eregs;
				495	for (cnt = 0; cnt < 8; cnt++)
				496	*iter_reg++ = htonl(ha->fce_mb[cnt]);
				497
				498	memcpy(iter_reg, ha->fce, ntohl(fcec->size));
				499
Giridhar Malavali	3cb0a67	2011-11-18 09:03:11 -0800	[diff] [blame]	500	return (char *)iter_reg + ntohl(fcec->size);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	501	}
				502
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	503	static inline void *
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	504	qla2xxx_copy_atioqueues(struct qla_hw_data ha, void ptr,
				505	uint32_t **last_chain)
				506	{
				507	struct qla2xxx_mqueue_chain *q;
				508	struct qla2xxx_mqueue_header *qh;
				509	uint32_t num_queues;
				510	int que;
				511	struct {
				512	int length;
				513	void *ring;
				514	} aq, *aqp;
				515
Arun Easi	00876ae	2013-03-25 02:21:37 -0400	[diff] [blame]	516	if (!ha->tgt.atio_ring)
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	517	return ptr;
				518
				519	num_queues = 1;
				520	aqp = &aq;
				521	aqp->length = ha->tgt.atio_q_length;
				522	aqp->ring = ha->tgt.atio_ring;
				523
				524	for (que = 0; que < num_queues; que++) {
				525	/* aqp = ha->atio_q_map[que]; */
				526	q = ptr;
				527	*last_chain = &q->type;
				528	q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
				529	q->chain_size = htonl(
				530	sizeof(struct qla2xxx_mqueue_chain) +
				531	sizeof(struct qla2xxx_mqueue_header) +
				532	(aqp->length * sizeof(request_t)));
				533	ptr += sizeof(struct qla2xxx_mqueue_chain);
				534
				535	/* Add header. */
				536	qh = ptr;
				537	qh->queue = __constant_htonl(TYPE_ATIO_QUEUE);
				538	qh->number = htonl(que);
				539	qh->size = htonl(aqp->length * sizeof(request_t));
				540	ptr += sizeof(struct qla2xxx_mqueue_header);
				541
				542	/* Add data. */
				543	memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t));
				544
				545	ptr += aqp->length * sizeof(request_t);
				546	}
				547
				548	return ptr;
				549	}
				550
				551	static inline void *
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	552	qla25xx_copy_mqueues(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				553	{
				554	struct qla2xxx_mqueue_chain *q;
				555	struct qla2xxx_mqueue_header *qh;
				556	struct req_que *req;
				557	struct rsp_que *rsp;
				558	int que;
				559
				560	if (!ha->mqenable)
				561	return ptr;
				562
				563	/* Request queues */
				564	for (que = 1; que < ha->max_req_queues; que++) {
				565	req = ha->req_q_map[que];
				566	if (!req)
				567	break;
				568
				569	/* Add chain. */
				570	q = ptr;
				571	*last_chain = &q->type;
				572	q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
				573	q->chain_size = htonl(
				574	sizeof(struct qla2xxx_mqueue_chain) +
				575	sizeof(struct qla2xxx_mqueue_header) +
				576	(req->length * sizeof(request_t)));
				577	ptr += sizeof(struct qla2xxx_mqueue_chain);
				578
				579	/* Add header. */
				580	qh = ptr;
				581	qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE);
				582	qh->number = htonl(que);
				583	qh->size = htonl(req->length * sizeof(request_t));
				584	ptr += sizeof(struct qla2xxx_mqueue_header);
				585
				586	/* Add data. */
				587	memcpy(ptr, req->ring, req->length * sizeof(request_t));
				588	ptr += req->length * sizeof(request_t);
				589	}
				590
				591	/* Response queues */
				592	for (que = 1; que < ha->max_rsp_queues; que++) {
				593	rsp = ha->rsp_q_map[que];
				594	if (!rsp)
				595	break;
				596
				597	/* Add chain. */
				598	q = ptr;
				599	*last_chain = &q->type;
				600	q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
				601	q->chain_size = htonl(
				602	sizeof(struct qla2xxx_mqueue_chain) +
				603	sizeof(struct qla2xxx_mqueue_header) +
				604	(rsp->length * sizeof(response_t)));
				605	ptr += sizeof(struct qla2xxx_mqueue_chain);
				606
				607	/* Add header. */
				608	qh = ptr;
				609	qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE);
				610	qh->number = htonl(que);
				611	qh->size = htonl(rsp->length * sizeof(response_t));
				612	ptr += sizeof(struct qla2xxx_mqueue_header);
				613
				614	/* Add data. */
				615	memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t));
				616	ptr += rsp->length * sizeof(response_t);
				617	}
				618
				619	return ptr;
				620	}
				621
				622	static inline void *
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	623	qla25xx_copy_mq(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				624	{
				625	uint32_t cnt, que_idx;
Anirban Chakraborty	2afa19a	2009-04-06 22:33:40 -0700	[diff] [blame]	626	uint8_t que_cnt;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	627	struct qla2xxx_mq_chain *mq = ptr;
Andrew Vasquez	da9b1d5	2013-08-27 01:37:30 -0400	[diff] [blame]	628	device_reg_t __iomem *reg;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	629
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	630	if (!ha->mqenable \|\| IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	631	return ptr;
				632
				633	mq = ptr;
				634	*last_chain = &mq->type;
				635	mq->type = __constant_htonl(DUMP_CHAIN_MQ);
				636	mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
				637
Anirban Chakraborty	2afa19a	2009-04-06 22:33:40 -0700	[diff] [blame]	638	que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
				639	ha->max_req_queues : ha->max_rsp_queues;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	640	mq->count = htonl(que_cnt);
				641	for (cnt = 0; cnt < que_cnt; cnt++) {
Andrew Vasquez	da9b1d5	2013-08-27 01:37:30 -0400	[diff] [blame]	642	reg = ISP_QUE_REG(ha, cnt);
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	643	que_idx = cnt * 4;
Andrew Vasquez	da9b1d5	2013-08-27 01:37:30 -0400	[diff] [blame]	644	mq->qregs[que_idx] =
				645	htonl(RD_REG_DWORD(&reg->isp25mq.req_q_in));
				646	mq->qregs[que_idx+1] =
				647	htonl(RD_REG_DWORD(&reg->isp25mq.req_q_out));
				648	mq->qregs[que_idx+2] =
				649	htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_in));
				650	mq->qregs[que_idx+3] =
				651	htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_out));
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	652	}
				653
				654	return ptr + sizeof(struct qla2xxx_mq_chain);
				655	}
				656
Giridhar Malavali	08de284	2011-08-16 11:31:44 -0700	[diff] [blame]	657	void
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	658	qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
				659	{
				660	struct qla_hw_data *ha = vha->hw;
				661
				662	if (rval != QLA_SUCCESS) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	663	ql_log(ql_log_warn, vha, 0xd000,
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame^]	664	"Failed to dump firmware (%x), dump status flags (0x%lx).\n",
				665	rval, ha->fw_dump_cap_flags);
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	666	ha->fw_dumped = 0;
				667	} else {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	668	ql_log(ql_log_info, vha, 0xd001,
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame^]	669	"Firmware dump saved to temp buffer (%ld/%p), dump status flags (0x%lx).\n",
				670	vha->host_no, ha->fw_dump, ha->fw_dump_cap_flags);
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	671	ha->fw_dumped = 1;
				672	qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
				673	}
				674	}
				675
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	676	/**
				677	* qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
				678	* @ha: HA context
				679	* @hardware_locked: Called with the hardware_lock
				680	*/
				681	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	682	qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	683	{
				684	int rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	685	uint32_t cnt;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	686	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	3d71644	2005-07-06 10:30:26 -0700	[diff] [blame]	687	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	688	uint16_t __iomem *dmp_reg;
				689	unsigned long flags;
				690	struct qla2300_fw_dump *fw;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	691	void *nxt;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	692	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	693
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	694	flags = 0;
				695
				696	if (!hardware_locked)
				697	spin_lock_irqsave(&ha->hardware_lock, flags);
				698
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	699	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	700	ql_log(ql_log_warn, vha, 0xd002,
				701	"No buffer available for dump.\n");
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	702	goto qla2300_fw_dump_failed;
				703	}
				704
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	705	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	706	ql_log(ql_log_warn, vha, 0xd003,
				707	"Firmware has been previously dumped (%p) "
				708	"-- ignoring request.\n",
				709	ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	710	goto qla2300_fw_dump_failed;
				711	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	712	fw = &ha->fw_dump->isp.isp23;
				713	qla2xxx_prep_dump(ha, ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	714
				715	rval = QLA_SUCCESS;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	716	fw->hccr = htons(RD_REG_WORD(&reg->hccr));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	717
				718	/* Pause RISC. */
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	719	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	720	if (IS_QLA2300(ha)) {
				721	for (cnt = 30000;
				722	(RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				723	rval == QLA_SUCCESS; cnt--) {
				724	if (cnt)
				725	udelay(100);
				726	else
				727	rval = QLA_FUNCTION_TIMEOUT;
				728	}
				729	} else {
				730	RD_REG_WORD(&reg->hccr); /* PCI Posting. */
				731	udelay(10);
				732	}
				733
				734	if (rval == QLA_SUCCESS) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	735	dmp_reg = &reg->flash_address;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	736	for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	737	fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	738
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	739	dmp_reg = &reg->u.isp2300.req_q_in;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	740	for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	741	fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	742
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	743	dmp_reg = &reg->u.isp2300.mailbox0;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	744	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	745	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	746
				747	WRT_REG_WORD(&reg->ctrl_status, 0x40);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	748	qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	749
				750	WRT_REG_WORD(&reg->ctrl_status, 0x50);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	751	qla2xxx_read_window(reg, 48, fw->dma_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	752
				753	WRT_REG_WORD(&reg->ctrl_status, 0x00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	754	dmp_reg = &reg->risc_hw;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	755	for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	756	fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	757
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	758	WRT_REG_WORD(&reg->pcr, 0x2000);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	759	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	760
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	761	WRT_REG_WORD(&reg->pcr, 0x2200);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	762	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	763
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	764	WRT_REG_WORD(&reg->pcr, 0x2400);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	765	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	766
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	767	WRT_REG_WORD(&reg->pcr, 0x2600);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	768	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	769
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	770	WRT_REG_WORD(&reg->pcr, 0x2800);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	771	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	772
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	773	WRT_REG_WORD(&reg->pcr, 0x2A00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	774	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	775
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	776	WRT_REG_WORD(&reg->pcr, 0x2C00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	777	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	778
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	779	WRT_REG_WORD(&reg->pcr, 0x2E00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	780	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	781
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	782	WRT_REG_WORD(&reg->ctrl_status, 0x10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	783	qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	784
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	785	WRT_REG_WORD(&reg->ctrl_status, 0x20);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	786	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	787
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	788	WRT_REG_WORD(&reg->ctrl_status, 0x30);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	789	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	790
				791	/* Reset RISC. */
				792	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
				793	for (cnt = 0; cnt < 30000; cnt++) {
				794	if ((RD_REG_WORD(&reg->ctrl_status) &
				795	CSR_ISP_SOFT_RESET) == 0)
				796	break;
				797
				798	udelay(10);
				799	}
				800	}
				801
				802	if (!IS_QLA2300(ha)) {
				803	for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
				804	rval == QLA_SUCCESS; cnt--) {
				805	if (cnt)
				806	udelay(100);
				807	else
				808	rval = QLA_FUNCTION_TIMEOUT;
				809	}
				810	}
				811
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	812	/* Get RISC SRAM. */
				813	if (rval == QLA_SUCCESS)
				814	rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
				815	sizeof(fw->risc_ram) / 2, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	816
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	817	/* Get stack SRAM. */
				818	if (rval == QLA_SUCCESS)
				819	rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
				820	sizeof(fw->stack_ram) / 2, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	821
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	822	/* Get data SRAM. */
				823	if (rval == QLA_SUCCESS)
				824	rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
				825	ha->fw_memory_size - 0x11000 + 1, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	826
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	827	if (rval == QLA_SUCCESS)
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	828	qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	829
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	830	qla2xxx_dump_post_process(base_vha, rval);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	831
				832	qla2300_fw_dump_failed:
				833	if (!hardware_locked)
				834	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				835	}
				836
				837	/**
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	838	* qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
				839	* @ha: HA context
				840	* @hardware_locked: Called with the hardware_lock
				841	*/
				842	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	843	qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	844	{
				845	int rval;
				846	uint32_t cnt, timer;
				847	uint16_t risc_address;
				848	uint16_t mb0, mb2;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	849	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	3d71644	2005-07-06 10:30:26 -0700	[diff] [blame]	850	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	851	uint16_t __iomem *dmp_reg;
				852	unsigned long flags;
				853	struct qla2100_fw_dump *fw;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	854	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	855
				856	risc_address = 0;
				857	mb0 = mb2 = 0;
				858	flags = 0;
				859
				860	if (!hardware_locked)
				861	spin_lock_irqsave(&ha->hardware_lock, flags);
				862
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	863	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	864	ql_log(ql_log_warn, vha, 0xd004,
				865	"No buffer available for dump.\n");
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	866	goto qla2100_fw_dump_failed;
				867	}
				868
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	869	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	870	ql_log(ql_log_warn, vha, 0xd005,
				871	"Firmware has been previously dumped (%p) "
				872	"-- ignoring request.\n",
				873	ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	874	goto qla2100_fw_dump_failed;
				875	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	876	fw = &ha->fw_dump->isp.isp21;
				877	qla2xxx_prep_dump(ha, ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	878
				879	rval = QLA_SUCCESS;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	880	fw->hccr = htons(RD_REG_WORD(&reg->hccr));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	881
				882	/* Pause RISC. */
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	883	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	884	for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				885	rval == QLA_SUCCESS; cnt--) {
				886	if (cnt)
				887	udelay(100);
				888	else
				889	rval = QLA_FUNCTION_TIMEOUT;
				890	}
				891	if (rval == QLA_SUCCESS) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	892	dmp_reg = &reg->flash_address;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	893	for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	894	fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	895
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	896	dmp_reg = &reg->u.isp2100.mailbox0;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	897	for (cnt = 0; cnt < ha->mbx_count; cnt++) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	898	if (cnt == 8)
				899	dmp_reg = &reg->u_end.isp2200.mailbox8;
				900
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	901	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	902	}
				903
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	904	dmp_reg = &reg->u.isp2100.unused_2[0];
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	905	for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	906	fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	907
				908	WRT_REG_WORD(&reg->ctrl_status, 0x00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	909	dmp_reg = &reg->risc_hw;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	910	for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	911	fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	912
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	913	WRT_REG_WORD(&reg->pcr, 0x2000);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	914	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	915
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	916	WRT_REG_WORD(&reg->pcr, 0x2100);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	917	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	918
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	919	WRT_REG_WORD(&reg->pcr, 0x2200);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	920	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	921
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	922	WRT_REG_WORD(&reg->pcr, 0x2300);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	923	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	924
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	925	WRT_REG_WORD(&reg->pcr, 0x2400);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	926	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	927
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	928	WRT_REG_WORD(&reg->pcr, 0x2500);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	929	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	930
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	931	WRT_REG_WORD(&reg->pcr, 0x2600);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	932	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	933
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	934	WRT_REG_WORD(&reg->pcr, 0x2700);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	935	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	936
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	937	WRT_REG_WORD(&reg->ctrl_status, 0x10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	938	qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	939
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	940	WRT_REG_WORD(&reg->ctrl_status, 0x20);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	941	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	942
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	943	WRT_REG_WORD(&reg->ctrl_status, 0x30);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	944	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	945
				946	/* Reset the ISP. */
				947	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
				948	}
				949
				950	for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
				951	rval == QLA_SUCCESS; cnt--) {
				952	if (cnt)
				953	udelay(100);
				954	else
				955	rval = QLA_FUNCTION_TIMEOUT;
				956	}
				957
				958	/* Pause RISC. */
				959	if (rval == QLA_SUCCESS && (IS_QLA2200(ha) \|\| (IS_QLA2100(ha) &&
				960	(RD_REG_WORD(&reg->mctr) & (BIT_1 \| BIT_0)) != 0))) {
				961
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	962	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	963	for (cnt = 30000;
				964	(RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				965	rval == QLA_SUCCESS; cnt--) {
				966	if (cnt)
				967	udelay(100);
				968	else
				969	rval = QLA_FUNCTION_TIMEOUT;
				970	}
				971	if (rval == QLA_SUCCESS) {
				972	/* Set memory configuration and timing. */
				973	if (IS_QLA2100(ha))
				974	WRT_REG_WORD(&reg->mctr, 0xf1);
				975	else
				976	WRT_REG_WORD(&reg->mctr, 0xf2);
				977	RD_REG_WORD(&reg->mctr); /* PCI Posting. */
				978
				979	/* Release RISC. */
				980	WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
				981	}
				982	}
				983
				984	if (rval == QLA_SUCCESS) {
				985	/* Get RISC SRAM. */
				986	risc_address = 0x1000;
				987	WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
				988	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				989	}
				990	for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
				991	cnt++, risc_address++) {
				992	WRT_MAILBOX_REG(ha, reg, 1, risc_address);
				993	WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
				994
				995	for (timer = 6000000; timer != 0; timer--) {
				996	/* Check for pending interrupts. */
				997	if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
				998	if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
				999	set_bit(MBX_INTERRUPT,
				1000	&ha->mbx_cmd_flags);
				1001
				1002	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				1003	mb2 = RD_MAILBOX_REG(ha, reg, 2);
				1004
				1005	WRT_REG_WORD(&reg->semaphore, 0);
				1006	WRT_REG_WORD(&reg->hccr,
				1007	HCCR_CLR_RISC_INT);
				1008	RD_REG_WORD(&reg->hccr);
				1009	break;
				1010	}
				1011	WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
				1012	RD_REG_WORD(&reg->hccr);
				1013	}
				1014	udelay(5);
				1015	}
				1016
				1017	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				1018	rval = mb0 & MBS_MASK;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1019	fw->risc_ram[cnt] = htons(mb2);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1020	} else {
				1021	rval = QLA_FUNCTION_FAILED;
				1022	}
				1023	}
				1024
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1025	if (rval == QLA_SUCCESS)
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1026	qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1027
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1028	qla2xxx_dump_post_process(base_vha, rval);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1029
				1030	qla2100_fw_dump_failed:
				1031	if (!hardware_locked)
				1032	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1033	}
				1034
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1035	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1036	qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1037	{
				1038	int rval;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1039	uint32_t cnt;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1040	uint32_t risc_address;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1041	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1042	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1043	uint32_t __iomem *dmp_reg;
				1044	uint32_t *iter_reg;
				1045	uint16_t __iomem *mbx_reg;
				1046	unsigned long flags;
				1047	struct qla24xx_fw_dump *fw;
				1048	uint32_t ext_mem_cnt;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1049	void *nxt;
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1050	void *nxt_chain;
				1051	uint32_t *last_chain = NULL;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1052	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1053
Atul Deshmukh	7ec0eff	2013-08-27 01:37:28 -0400	[diff] [blame]	1054	if (IS_P3P_TYPE(ha))
Giridhar Malavali	a908301	2010-04-12 17:59:55 -0700	[diff] [blame]	1055	return;
				1056
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1057	risc_address = ext_mem_cnt = 0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1058	flags = 0;
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame^]	1059	ha->fw_dump_cap_flags = 0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1060
				1061	if (!hardware_locked)
				1062	spin_lock_irqsave(&ha->hardware_lock, flags);
				1063
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	1064	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1065	ql_log(ql_log_warn, vha, 0xd006,
				1066	"No buffer available for dump.\n");
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1067	goto qla24xx_fw_dump_failed;
				1068	}
				1069
				1070	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1071	ql_log(ql_log_warn, vha, 0xd007,
				1072	"Firmware has been previously dumped (%p) "
				1073	"-- ignoring request.\n",
				1074	ha->fw_dump);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1075	goto qla24xx_fw_dump_failed;
				1076	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1077	fw = &ha->fw_dump->isp.isp24;
				1078	qla2xxx_prep_dump(ha, ha->fw_dump);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1079
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1080	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1081
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	1082	/*
				1083	* Pause RISC. No need to track timeout, as resetting the chip
				1084	* is the right approach incase of pause timeout
				1085	*/
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame^]	1086	qla24xx_pause_risc(reg, ha);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1087
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1088	/* Host interface registers. */
				1089	dmp_reg = &reg->flash_addr;
				1090	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1091	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1092
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1093	/* Disable interrupts. */
				1094	WRT_REG_DWORD(&reg->ictrl, 0);
				1095	RD_REG_DWORD(&reg->ictrl);
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1096
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1097	/* Shadow registers. */
				1098	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1099	RD_REG_DWORD(&reg->iobase_addr);
				1100	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1101	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1102
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1103	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1104	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1105
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1106	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1107	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1108
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1109	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1110	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1111
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1112	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1113	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1114
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1115	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1116	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1117
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1118	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1119	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1120
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1121	/* Mailbox registers. */
				1122	mbx_reg = &reg->mailbox0;
				1123	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1124	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1125
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1126	/* Transfer sequence registers. */
				1127	iter_reg = fw->xseq_gp_reg;
				1128	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1129	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1130	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1131	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1132	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1133	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1134	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1135	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1136
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1137	qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
				1138	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1139
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1140	/* Receive sequence registers. */
				1141	iter_reg = fw->rseq_gp_reg;
				1142	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1143	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1144	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1145	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1146	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1147	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1148	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1149	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1150
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1151	qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
				1152	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1153	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1154
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1155	/* Command DMA registers. */
				1156	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1157
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1158	/* Queues. */
				1159	iter_reg = fw->req0_dma_reg;
				1160	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1161	dmp_reg = &reg->iobase_q;
				1162	for (cnt = 0; cnt < 7; cnt++)
				1163	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1164
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1165	iter_reg = fw->resp0_dma_reg;
				1166	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1167	dmp_reg = &reg->iobase_q;
				1168	for (cnt = 0; cnt < 7; cnt++)
				1169	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1170
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1171	iter_reg = fw->req1_dma_reg;
				1172	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1173	dmp_reg = &reg->iobase_q;
				1174	for (cnt = 0; cnt < 7; cnt++)
				1175	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1176
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1177	/* Transmit DMA registers. */
				1178	iter_reg = fw->xmt0_dma_reg;
				1179	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1180	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1181
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1182	iter_reg = fw->xmt1_dma_reg;
				1183	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1184	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1185
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1186	iter_reg = fw->xmt2_dma_reg;
				1187	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1188	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1189
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1190	iter_reg = fw->xmt3_dma_reg;
				1191	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1192	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1193
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1194	iter_reg = fw->xmt4_dma_reg;
				1195	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1196	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1197
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1198	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1199
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1200	/* Receive DMA registers. */
				1201	iter_reg = fw->rcvt0_data_dma_reg;
				1202	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1203	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1204
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1205	iter_reg = fw->rcvt1_data_dma_reg;
				1206	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1207	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1208
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1209	/* RISC registers. */
				1210	iter_reg = fw->risc_gp_reg;
				1211	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1212	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1213	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1214	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1215	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1216	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1217	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1218	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1219
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1220	/* Local memory controller registers. */
				1221	iter_reg = fw->lmc_reg;
				1222	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1223	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1224	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1225	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1226	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1227	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1228	qla24xx_read_window(reg, 0x3060, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1229
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1230	/* Fibre Protocol Module registers. */
				1231	iter_reg = fw->fpm_hdw_reg;
				1232	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1233	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1234	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1235	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1236	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1237	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1238	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1239	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1240	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1241	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1242	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1243	qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1244
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1245	/* Frame Buffer registers. */
				1246	iter_reg = fw->fb_hdw_reg;
				1247	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1248	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1249	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1250	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1251	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1252	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1253	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1254	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1255	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1256	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1257	qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1258
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1259	rval = qla24xx_soft_reset(ha);
				1260	if (rval != QLA_SUCCESS)
				1261	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1262
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1263	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	1264	&nxt);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1265	if (rval != QLA_SUCCESS)
				1266	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1267
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1268	nxt = qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1269
				1270	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1271
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1272	nxt_chain = (void *)ha->fw_dump + ha->chain_offset;
				1273	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
				1274	if (last_chain) {
				1275	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				1276	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				1277	}
				1278
				1279	/* Adjust valid length. */
				1280	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1281
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1282	qla24xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1283	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1284
				1285	qla24xx_fw_dump_failed:
				1286	if (!hardware_locked)
				1287	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1288	}
				1289
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1290	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1291	qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1292	{
				1293	int rval;
				1294	uint32_t cnt;
				1295	uint32_t risc_address;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1296	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1297	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1298	uint32_t __iomem *dmp_reg;
				1299	uint32_t *iter_reg;
				1300	uint16_t __iomem *mbx_reg;
				1301	unsigned long flags;
				1302	struct qla25xx_fw_dump *fw;
				1303	uint32_t ext_mem_cnt;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1304	void nxt, nxt_chain;
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1305	uint32_t *last_chain = NULL;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1306	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1307
				1308	risc_address = ext_mem_cnt = 0;
				1309	flags = 0;
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame^]	1310	ha->fw_dump_cap_flags = 0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1311
				1312	if (!hardware_locked)
				1313	spin_lock_irqsave(&ha->hardware_lock, flags);
				1314
				1315	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1316	ql_log(ql_log_warn, vha, 0xd008,
				1317	"No buffer available for dump.\n");
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1318	goto qla25xx_fw_dump_failed;
				1319	}
				1320
				1321	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1322	ql_log(ql_log_warn, vha, 0xd009,
				1323	"Firmware has been previously dumped (%p) "
				1324	"-- ignoring request.\n",
				1325	ha->fw_dump);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1326	goto qla25xx_fw_dump_failed;
				1327	}
				1328	fw = &ha->fw_dump->isp.isp25;
				1329	qla2xxx_prep_dump(ha, ha->fw_dump);
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1330	ha->fw_dump->version = __constant_htonl(2);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1331
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1332	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1333
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	1334	/*
				1335	* Pause RISC. No need to track timeout, as resetting the chip
				1336	* is the right approach incase of pause timeout
				1337	*/
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame^]	1338	qla24xx_pause_risc(reg, ha);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1339
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1340	/* Host/Risc registers. */
				1341	iter_reg = fw->host_risc_reg;
				1342	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1343	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1344
				1345	/* PCIe registers. */
				1346	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1347	RD_REG_DWORD(&reg->iobase_addr);
				1348	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1349	dmp_reg = &reg->iobase_c4;
				1350	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				1351	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				1352	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1353	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1354
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1355	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1356	RD_REG_DWORD(&reg->iobase_window);
				1357
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1358	/* Host interface registers. */
				1359	dmp_reg = &reg->flash_addr;
				1360	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1361	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1362
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1363	/* Disable interrupts. */
				1364	WRT_REG_DWORD(&reg->ictrl, 0);
				1365	RD_REG_DWORD(&reg->ictrl);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1366
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1367	/* Shadow registers. */
				1368	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1369	RD_REG_DWORD(&reg->iobase_addr);
				1370	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1371	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1372
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1373	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1374	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1375
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1376	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1377	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1378
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1379	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1380	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1381
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1382	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1383	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1384
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1385	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1386	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1387
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1388	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1389	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1390
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1391	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1392	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1393
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1394	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1395	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1396
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1397	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1398	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1399
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1400	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1401	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1402
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1403	/* RISC I/O register. */
				1404	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1405	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1406
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1407	/* Mailbox registers. */
				1408	mbx_reg = &reg->mailbox0;
				1409	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1410	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1411
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1412	/* Transfer sequence registers. */
				1413	iter_reg = fw->xseq_gp_reg;
				1414	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1415	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1416	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1417	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1418	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1419	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1420	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1421	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1422
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1423	iter_reg = fw->xseq_0_reg;
				1424	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1425	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1426	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1427
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1428	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1429
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1430	/* Receive sequence registers. */
				1431	iter_reg = fw->rseq_gp_reg;
				1432	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1433	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1434	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1435	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1436	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1437	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1438	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1439	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1440
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1441	iter_reg = fw->rseq_0_reg;
				1442	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				1443	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1444
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1445	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1446	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1447
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1448	/* Auxiliary sequence registers. */
				1449	iter_reg = fw->aseq_gp_reg;
				1450	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				1451	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				1452	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				1453	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				1454	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				1455	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				1456	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				1457	qla24xx_read_window(reg, 0xB070, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1458
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1459	iter_reg = fw->aseq_0_reg;
				1460	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				1461	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1462
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1463	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				1464	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1465
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1466	/* Command DMA registers. */
				1467	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1468
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1469	/* Queues. */
				1470	iter_reg = fw->req0_dma_reg;
				1471	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1472	dmp_reg = &reg->iobase_q;
				1473	for (cnt = 0; cnt < 7; cnt++)
				1474	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1475
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1476	iter_reg = fw->resp0_dma_reg;
				1477	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1478	dmp_reg = &reg->iobase_q;
				1479	for (cnt = 0; cnt < 7; cnt++)
				1480	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1481
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1482	iter_reg = fw->req1_dma_reg;
				1483	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1484	dmp_reg = &reg->iobase_q;
				1485	for (cnt = 0; cnt < 7; cnt++)
				1486	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1487
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1488	/* Transmit DMA registers. */
				1489	iter_reg = fw->xmt0_dma_reg;
				1490	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1491	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1492
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1493	iter_reg = fw->xmt1_dma_reg;
				1494	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1495	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1496
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1497	iter_reg = fw->xmt2_dma_reg;
				1498	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1499	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1500
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1501	iter_reg = fw->xmt3_dma_reg;
				1502	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1503	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1504
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1505	iter_reg = fw->xmt4_dma_reg;
				1506	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1507	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1508
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1509	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1510
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1511	/* Receive DMA registers. */
				1512	iter_reg = fw->rcvt0_data_dma_reg;
				1513	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1514	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1515
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1516	iter_reg = fw->rcvt1_data_dma_reg;
				1517	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1518	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1519
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1520	/* RISC registers. */
				1521	iter_reg = fw->risc_gp_reg;
				1522	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1523	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1524	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1525	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1526	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1527	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1528	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1529	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1530
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1531	/* Local memory controller registers. */
				1532	iter_reg = fw->lmc_reg;
				1533	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1534	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1535	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1536	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1537	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1538	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1539	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				1540	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1541
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1542	/* Fibre Protocol Module registers. */
				1543	iter_reg = fw->fpm_hdw_reg;
				1544	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1545	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1546	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1547	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1548	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1549	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1550	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1551	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1552	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1553	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1554	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1555	qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1556
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1557	/* Frame Buffer registers. */
				1558	iter_reg = fw->fb_hdw_reg;
				1559	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1560	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1561	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1562	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1563	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1564	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1565	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1566	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1567	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1568	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1569	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				1570	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1571
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1572	/* Multi queue registers */
				1573	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				1574	&last_chain);
				1575
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1576	rval = qla24xx_soft_reset(ha);
				1577	if (rval != QLA_SUCCESS)
				1578	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1579
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1580	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	1581	&nxt);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1582	if (rval != QLA_SUCCESS)
				1583	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1584
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1585	nxt = qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1586
Bart Van Assche	7f544d0	2013-06-25 11:27:27 -0400	[diff] [blame]	1587	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	df613b9	2008-01-17 09:02:17 -0800	[diff] [blame]	1588
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1589	/* Chain entries -- started with MQ. */
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1590	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				1591	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1592	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1593	if (last_chain) {
				1594	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				1595	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				1596	}
Andrew Vasquez	df613b9	2008-01-17 09:02:17 -0800	[diff] [blame]	1597
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1598	/* Adjust valid length. */
				1599	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1600
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1601	qla25xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1602	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1603
				1604	qla25xx_fw_dump_failed:
				1605	if (!hardware_locked)
				1606	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1607	}
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1608
				1609	void
				1610	qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
				1611	{
				1612	int rval;
				1613	uint32_t cnt;
				1614	uint32_t risc_address;
				1615	struct qla_hw_data *ha = vha->hw;
				1616	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1617	uint32_t __iomem *dmp_reg;
				1618	uint32_t *iter_reg;
				1619	uint16_t __iomem *mbx_reg;
				1620	unsigned long flags;
				1621	struct qla81xx_fw_dump *fw;
				1622	uint32_t ext_mem_cnt;
				1623	void nxt, nxt_chain;
				1624	uint32_t *last_chain = NULL;
				1625	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
				1626
				1627	risc_address = ext_mem_cnt = 0;
				1628	flags = 0;
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame^]	1629	ha->fw_dump_cap_flags = 0;
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1630
				1631	if (!hardware_locked)
				1632	spin_lock_irqsave(&ha->hardware_lock, flags);
				1633
				1634	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1635	ql_log(ql_log_warn, vha, 0xd00a,
				1636	"No buffer available for dump.\n");
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1637	goto qla81xx_fw_dump_failed;
				1638	}
				1639
				1640	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1641	ql_log(ql_log_warn, vha, 0xd00b,
				1642	"Firmware has been previously dumped (%p) "
				1643	"-- ignoring request.\n",
				1644	ha->fw_dump);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1645	goto qla81xx_fw_dump_failed;
				1646	}
				1647	fw = &ha->fw_dump->isp.isp81;
				1648	qla2xxx_prep_dump(ha, ha->fw_dump);
				1649
				1650	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1651
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	1652	/*
				1653	* Pause RISC. No need to track timeout, as resetting the chip
				1654	* is the right approach incase of pause timeout
				1655	*/
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame^]	1656	qla24xx_pause_risc(reg, ha);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1657
				1658	/* Host/Risc registers. */
				1659	iter_reg = fw->host_risc_reg;
				1660	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1661	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1662
				1663	/* PCIe registers. */
				1664	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1665	RD_REG_DWORD(&reg->iobase_addr);
				1666	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1667	dmp_reg = &reg->iobase_c4;
				1668	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				1669	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				1670	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1671	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
				1672
				1673	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1674	RD_REG_DWORD(&reg->iobase_window);
				1675
				1676	/* Host interface registers. */
				1677	dmp_reg = &reg->flash_addr;
				1678	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1679	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
				1680
				1681	/* Disable interrupts. */
				1682	WRT_REG_DWORD(&reg->ictrl, 0);
				1683	RD_REG_DWORD(&reg->ictrl);
				1684
				1685	/* Shadow registers. */
				1686	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1687	RD_REG_DWORD(&reg->iobase_addr);
				1688	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1689	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1690
				1691	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1692	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1693
				1694	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1695	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1696
				1697	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1698	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1699
				1700	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1701	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1702
				1703	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1704	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1705
				1706	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1707	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1708
				1709	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1710	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1711
				1712	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1713	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1714
				1715	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1716	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1717
				1718	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1719	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1720
				1721	/* RISC I/O register. */
				1722	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1723	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
				1724
				1725	/* Mailbox registers. */
				1726	mbx_reg = &reg->mailbox0;
				1727	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1728	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
				1729
				1730	/* Transfer sequence registers. */
				1731	iter_reg = fw->xseq_gp_reg;
				1732	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1733	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1734	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1735	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1736	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1737	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1738	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1739	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
				1740
				1741	iter_reg = fw->xseq_0_reg;
				1742	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1743	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1744	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
				1745
				1746	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
				1747
				1748	/* Receive sequence registers. */
				1749	iter_reg = fw->rseq_gp_reg;
				1750	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1751	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1752	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1753	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1754	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1755	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1756	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1757	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
				1758
				1759	iter_reg = fw->rseq_0_reg;
				1760	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				1761	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
				1762
				1763	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1764	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
				1765
				1766	/* Auxiliary sequence registers. */
				1767	iter_reg = fw->aseq_gp_reg;
				1768	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				1769	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				1770	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				1771	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				1772	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				1773	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				1774	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				1775	qla24xx_read_window(reg, 0xB070, 16, iter_reg);
				1776
				1777	iter_reg = fw->aseq_0_reg;
				1778	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				1779	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
				1780
				1781	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				1782	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
				1783
				1784	/* Command DMA registers. */
				1785	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
				1786
				1787	/* Queues. */
				1788	iter_reg = fw->req0_dma_reg;
				1789	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1790	dmp_reg = &reg->iobase_q;
				1791	for (cnt = 0; cnt < 7; cnt++)
				1792	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1793
				1794	iter_reg = fw->resp0_dma_reg;
				1795	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1796	dmp_reg = &reg->iobase_q;
				1797	for (cnt = 0; cnt < 7; cnt++)
				1798	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1799
				1800	iter_reg = fw->req1_dma_reg;
				1801	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1802	dmp_reg = &reg->iobase_q;
				1803	for (cnt = 0; cnt < 7; cnt++)
				1804	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1805
				1806	/* Transmit DMA registers. */
				1807	iter_reg = fw->xmt0_dma_reg;
				1808	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1809	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
				1810
				1811	iter_reg = fw->xmt1_dma_reg;
				1812	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1813	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
				1814
				1815	iter_reg = fw->xmt2_dma_reg;
				1816	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1817	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
				1818
				1819	iter_reg = fw->xmt3_dma_reg;
				1820	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1821	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
				1822
				1823	iter_reg = fw->xmt4_dma_reg;
				1824	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1825	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
				1826
				1827	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
				1828
				1829	/* Receive DMA registers. */
				1830	iter_reg = fw->rcvt0_data_dma_reg;
				1831	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1832	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
				1833
				1834	iter_reg = fw->rcvt1_data_dma_reg;
				1835	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1836	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
				1837
				1838	/* RISC registers. */
				1839	iter_reg = fw->risc_gp_reg;
				1840	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1841	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1842	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1843	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1844	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1845	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1846	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1847	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
				1848
				1849	/* Local memory controller registers. */
				1850	iter_reg = fw->lmc_reg;
				1851	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1852	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1853	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1854	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1855	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1856	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1857	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				1858	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
				1859
				1860	/* Fibre Protocol Module registers. */
				1861	iter_reg = fw->fpm_hdw_reg;
				1862	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1863	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1864	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1865	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1866	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1867	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1868	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1869	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1870	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1871	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1872	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1873	iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
				1874	iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
				1875	qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
				1876
				1877	/* Frame Buffer registers. */
				1878	iter_reg = fw->fb_hdw_reg;
				1879	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1880	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1881	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1882	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1883	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1884	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1885	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1886	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1887	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1888	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1889	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				1890	iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
				1891	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
				1892
				1893	/* Multi queue registers */
				1894	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				1895	&last_chain);
				1896
				1897	rval = qla24xx_soft_reset(ha);
				1898	if (rval != QLA_SUCCESS)
				1899	goto qla81xx_fw_dump_failed_0;
				1900
				1901	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
				1902	&nxt);
				1903	if (rval != QLA_SUCCESS)
				1904	goto qla81xx_fw_dump_failed_0;
				1905
				1906	nxt = qla2xxx_copy_queues(ha, nxt);
				1907
Bart Van Assche	7f544d0	2013-06-25 11:27:27 -0400	[diff] [blame]	1908	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1909
				1910	/* Chain entries -- started with MQ. */
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1911	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				1912	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1913	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1914	if (last_chain) {
				1915	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				1916	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				1917	}
				1918
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1919	/* Adjust valid length. */
				1920	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1921
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1922	qla81xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1923	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1924
				1925	qla81xx_fw_dump_failed:
				1926	if (!hardware_locked)
				1927	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1928	}
				1929
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1930	void
				1931	qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
				1932	{
				1933	int rval;
				1934	uint32_t cnt, reg_data;
				1935	uint32_t risc_address;
				1936	struct qla_hw_data *ha = vha->hw;
				1937	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1938	uint32_t __iomem *dmp_reg;
				1939	uint32_t *iter_reg;
				1940	uint16_t __iomem *mbx_reg;
				1941	unsigned long flags;
				1942	struct qla83xx_fw_dump *fw;
				1943	uint32_t ext_mem_cnt;
				1944	void nxt, nxt_chain;
				1945	uint32_t *last_chain = NULL;
				1946	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
				1947
				1948	risc_address = ext_mem_cnt = 0;
				1949	flags = 0;
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame^]	1950	ha->fw_dump_cap_flags = 0;
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1951
				1952	if (!hardware_locked)
				1953	spin_lock_irqsave(&ha->hardware_lock, flags);
				1954
				1955	if (!ha->fw_dump) {
				1956	ql_log(ql_log_warn, vha, 0xd00c,
				1957	"No buffer available for dump!!!\n");
				1958	goto qla83xx_fw_dump_failed;
				1959	}
				1960
				1961	if (ha->fw_dumped) {
				1962	ql_log(ql_log_warn, vha, 0xd00d,
				1963	"Firmware has been previously dumped (%p) -- ignoring "
				1964	"request...\n", ha->fw_dump);
				1965	goto qla83xx_fw_dump_failed;
				1966	}
				1967	fw = &ha->fw_dump->isp.isp83;
				1968	qla2xxx_prep_dump(ha, ha->fw_dump);
				1969
				1970	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1971
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	1972	/*
				1973	* Pause RISC. No need to track timeout, as resetting the chip
				1974	* is the right approach incase of pause timeout
				1975	*/
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame^]	1976	qla24xx_pause_risc(reg, ha);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1977
				1978	WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
				1979	dmp_reg = &reg->iobase_window;
				1980	reg_data = RD_REG_DWORD(dmp_reg);
				1981	WRT_REG_DWORD(dmp_reg, 0);
				1982
				1983	dmp_reg = &reg->unused_4_1[0];
				1984	reg_data = RD_REG_DWORD(dmp_reg);
				1985	WRT_REG_DWORD(dmp_reg, 0);
				1986
				1987	WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
				1988	dmp_reg = &reg->unused_4_1[2];
				1989	reg_data = RD_REG_DWORD(dmp_reg);
				1990	WRT_REG_DWORD(dmp_reg, 0);
				1991
				1992	/* select PCR and disable ecc checking and correction */
				1993	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1994	RD_REG_DWORD(&reg->iobase_addr);
				1995	WRT_REG_DWORD(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
				1996
				1997	/* Host/Risc registers. */
				1998	iter_reg = fw->host_risc_reg;
				1999	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				2000	iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				2001	qla24xx_read_window(reg, 0x7040, 16, iter_reg);
				2002
				2003	/* PCIe registers. */
				2004	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				2005	RD_REG_DWORD(&reg->iobase_addr);
				2006	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				2007	dmp_reg = &reg->iobase_c4;
				2008	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				2009	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				2010	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				2011	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
				2012
				2013	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				2014	RD_REG_DWORD(&reg->iobase_window);
				2015
				2016	/* Host interface registers. */
				2017	dmp_reg = &reg->flash_addr;
				2018	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				2019	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
				2020
				2021	/* Disable interrupts. */
				2022	WRT_REG_DWORD(&reg->ictrl, 0);
				2023	RD_REG_DWORD(&reg->ictrl);
				2024
				2025	/* Shadow registers. */
				2026	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				2027	RD_REG_DWORD(&reg->iobase_addr);
				2028	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				2029	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2030
				2031	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				2032	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2033
				2034	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				2035	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2036
				2037	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				2038	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2039
				2040	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				2041	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2042
				2043	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				2044	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2045
				2046	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				2047	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2048
				2049	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				2050	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2051
				2052	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				2053	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2054
				2055	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				2056	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2057
				2058	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				2059	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2060
				2061	/* RISC I/O register. */
				2062	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				2063	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
				2064
				2065	/* Mailbox registers. */
				2066	mbx_reg = &reg->mailbox0;
				2067	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				2068	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
				2069
				2070	/* Transfer sequence registers. */
				2071	iter_reg = fw->xseq_gp_reg;
				2072	iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg);
				2073	iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg);
				2074	iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg);
				2075	iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg);
				2076	iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg);
				2077	iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg);
				2078	iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg);
				2079	iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg);
				2080	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				2081	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				2082	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				2083	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				2084	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				2085	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				2086	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				2087	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
				2088
				2089	iter_reg = fw->xseq_0_reg;
				2090	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				2091	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				2092	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
				2093
				2094	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
				2095
				2096	qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg);
				2097
				2098	/* Receive sequence registers. */
				2099	iter_reg = fw->rseq_gp_reg;
				2100	iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg);
				2101	iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg);
				2102	iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg);
				2103	iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg);
				2104	iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg);
				2105	iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg);
				2106	iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg);
				2107	iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg);
				2108	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				2109	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				2110	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				2111	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				2112	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				2113	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				2114	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				2115	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
				2116
				2117	iter_reg = fw->rseq_0_reg;
				2118	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				2119	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
				2120
				2121	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				2122	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
				2123	qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg);
				2124
				2125	/* Auxiliary sequence registers. */
				2126	iter_reg = fw->aseq_gp_reg;
				2127	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				2128	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				2129	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				2130	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				2131	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				2132	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				2133	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				2134	iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg);
				2135	iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg);
				2136	iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg);
				2137	iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg);
				2138	iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg);
				2139	iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg);
				2140	iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg);
				2141	iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg);
				2142	qla24xx_read_window(reg, 0xB170, 16, iter_reg);
				2143
				2144	iter_reg = fw->aseq_0_reg;
				2145	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				2146	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
				2147
				2148	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				2149	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
				2150	qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg);
				2151
				2152	/* Command DMA registers. */
				2153	iter_reg = fw->cmd_dma_reg;
				2154	iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg);
				2155	iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg);
				2156	iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg);
				2157	qla24xx_read_window(reg, 0x71F0, 16, iter_reg);
				2158
				2159	/* Queues. */
				2160	iter_reg = fw->req0_dma_reg;
				2161	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				2162	dmp_reg = &reg->iobase_q;
				2163	for (cnt = 0; cnt < 7; cnt++)
				2164	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2165
				2166	iter_reg = fw->resp0_dma_reg;
				2167	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				2168	dmp_reg = &reg->iobase_q;
				2169	for (cnt = 0; cnt < 7; cnt++)
				2170	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2171
				2172	iter_reg = fw->req1_dma_reg;
				2173	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				2174	dmp_reg = &reg->iobase_q;
				2175	for (cnt = 0; cnt < 7; cnt++)
				2176	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2177
				2178	/* Transmit DMA registers. */
				2179	iter_reg = fw->xmt0_dma_reg;
				2180	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				2181	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
				2182
				2183	iter_reg = fw->xmt1_dma_reg;
				2184	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				2185	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
				2186
				2187	iter_reg = fw->xmt2_dma_reg;
				2188	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				2189	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
				2190
				2191	iter_reg = fw->xmt3_dma_reg;
				2192	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				2193	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
				2194
				2195	iter_reg = fw->xmt4_dma_reg;
				2196	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				2197	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
				2198
				2199	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
				2200
				2201	/* Receive DMA registers. */
				2202	iter_reg = fw->rcvt0_data_dma_reg;
				2203	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				2204	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
				2205
				2206	iter_reg = fw->rcvt1_data_dma_reg;
				2207	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				2208	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
				2209
				2210	/* RISC registers. */
				2211	iter_reg = fw->risc_gp_reg;
				2212	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				2213	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				2214	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				2215	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				2216	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				2217	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				2218	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				2219	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
				2220
				2221	/* Local memory controller registers. */
				2222	iter_reg = fw->lmc_reg;
				2223	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				2224	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				2225	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				2226	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				2227	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				2228	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				2229	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				2230	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
				2231
				2232	/* Fibre Protocol Module registers. */
				2233	iter_reg = fw->fpm_hdw_reg;
				2234	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				2235	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				2236	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				2237	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				2238	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				2239	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				2240	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				2241	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				2242	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				2243	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				2244	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				2245	iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
				2246	iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
				2247	iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
				2248	iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg);
				2249	qla24xx_read_window(reg, 0x40F0, 16, iter_reg);
				2250
				2251	/* RQ0 Array registers. */
				2252	iter_reg = fw->rq0_array_reg;
				2253	iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg);
				2254	iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg);
				2255	iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg);
				2256	iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg);
				2257	iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg);
				2258	iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg);
				2259	iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg);
				2260	iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg);
				2261	iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg);
				2262	iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg);
				2263	iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg);
				2264	iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg);
				2265	iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg);
				2266	iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg);
				2267	iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg);
				2268	qla24xx_read_window(reg, 0x5CF0, 16, iter_reg);
				2269
				2270	/* RQ1 Array registers. */
				2271	iter_reg = fw->rq1_array_reg;
				2272	iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg);
				2273	iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg);
				2274	iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg);
				2275	iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg);
				2276	iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg);
				2277	iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg);
				2278	iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg);
				2279	iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg);
				2280	iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg);
				2281	iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg);
				2282	iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg);
				2283	iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg);
				2284	iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg);
				2285	iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg);
				2286	iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg);
				2287	qla24xx_read_window(reg, 0x5DF0, 16, iter_reg);
				2288
				2289	/* RP0 Array registers. */
				2290	iter_reg = fw->rp0_array_reg;
				2291	iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg);
				2292	iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg);
				2293	iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg);
				2294	iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg);
				2295	iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg);
				2296	iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg);
				2297	iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg);
				2298	iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg);
				2299	iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg);
				2300	iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg);
				2301	iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg);
				2302	iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg);
				2303	iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg);
				2304	iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg);
				2305	iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg);
				2306	qla24xx_read_window(reg, 0x5EF0, 16, iter_reg);
				2307
				2308	/* RP1 Array registers. */
				2309	iter_reg = fw->rp1_array_reg;
				2310	iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg);
				2311	iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg);
				2312	iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg);
				2313	iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg);
				2314	iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg);
				2315	iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg);
				2316	iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg);
				2317	iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg);
				2318	iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg);
				2319	iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg);
				2320	iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg);
				2321	iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg);
				2322	iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg);
				2323	iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg);
				2324	iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg);
				2325	qla24xx_read_window(reg, 0x5FF0, 16, iter_reg);
				2326
				2327	iter_reg = fw->at0_array_reg;
				2328	iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg);
				2329	iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg);
				2330	iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg);
				2331	iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg);
				2332	iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg);
				2333	iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg);
				2334	iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg);
				2335	qla24xx_read_window(reg, 0x70F0, 16, iter_reg);
				2336
				2337	/* I/O Queue Control registers. */
				2338	qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg);
				2339
				2340	/* Frame Buffer registers. */
				2341	iter_reg = fw->fb_hdw_reg;
				2342	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				2343	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				2344	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				2345	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				2346	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				2347	iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg);
				2348	iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg);
				2349	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				2350	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				2351	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				2352	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				2353	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				2354	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				2355	iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
				2356	iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg);
				2357	iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg);
				2358	iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg);
				2359	iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg);
				2360	iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg);
				2361	iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg);
				2362	iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg);
				2363	iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg);
				2364	iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg);
				2365	iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg);
				2366	iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg);
				2367	iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg);
				2368	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
				2369
				2370	/* Multi queue registers */
				2371	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				2372	&last_chain);
				2373
				2374	rval = qla24xx_soft_reset(ha);
				2375	if (rval != QLA_SUCCESS) {
				2376	ql_log(ql_log_warn, vha, 0xd00e,
				2377	"SOFT RESET FAILED, forcing continuation of dump!!!\n");
				2378	rval = QLA_SUCCESS;
				2379
				2380	ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
				2381
				2382	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
				2383	RD_REG_DWORD(&reg->hccr);
				2384
				2385	WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
				2386	RD_REG_DWORD(&reg->hccr);
				2387
				2388	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
				2389	RD_REG_DWORD(&reg->hccr);
				2390
				2391	for (cnt = 30000; cnt && (RD_REG_WORD(&reg->mailbox0)); cnt--)
				2392	udelay(5);
				2393
				2394	if (!cnt) {
				2395	nxt = fw->code_ram;
Saurav Kashyap	8c0bc70	2012-11-21 02:40:35 -0500	[diff] [blame]	2396	nxt += sizeof(fw->code_ram);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2397	nxt += (ha->fw_memory_size - 0x100000 + 1);
				2398	goto copy_queue;
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame^]	2399	} else {
				2400	set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2401	ql_log(ql_log_warn, vha, 0xd010,
				2402	"bigger hammer success?\n");
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame^]	2403	}
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2404	}
				2405
				2406	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
				2407	&nxt);
				2408	if (rval != QLA_SUCCESS)
				2409	goto qla83xx_fw_dump_failed_0;
				2410
				2411	copy_queue:
				2412	nxt = qla2xxx_copy_queues(ha, nxt);
				2413
Bart Van Assche	7f544d0	2013-06-25 11:27:27 -0400	[diff] [blame]	2414	qla24xx_copy_eft(ha, nxt);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2415
				2416	/* Chain entries -- started with MQ. */
				2417	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				2418	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	2419	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2420	if (last_chain) {
				2421	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				2422	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				2423	}
				2424
				2425	/* Adjust valid length. */
				2426	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				2427
				2428	qla83xx_fw_dump_failed_0:
				2429	qla2xxx_dump_post_process(base_vha, rval);
				2430
				2431	qla83xx_fw_dump_failed:
				2432	if (!hardware_locked)
				2433	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				2434	}
				2435
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	2436	/****************************************************************************/
				2437	/* Driver Debug Functions. */
				2438	/****************************************************************************/
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2439
				2440	static inline int
				2441	ql_mask_match(uint32_t level)
				2442	{
				2443	if (ql2xextended_error_logging == 1)
				2444	ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
				2445	return (level & ql2xextended_error_logging) == level;
				2446	}
				2447
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2448	/*
				2449	* This function is for formatting and logging debug information.
				2450	* It is to be used when vha is available. It formats the message
				2451	* and logs it to the messages file.
				2452	* parameters:
				2453	* level: The level of the debug messages to be printed.
				2454	* If ql2xextended_error_logging value is correctly set,
				2455	* this message will appear in the messages file.
				2456	* vha: Pointer to the scsi_qla_host_t.
				2457	* id: This is a unique identifier for the level. It identifies the
				2458	* part of the code from where the message originated.
				2459	* msg: The message to be displayed.
				2460	*/
				2461	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2462	ql_dbg(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
				2463	{
				2464	va_list va;
				2465	struct va_format vaf;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2466
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2467	if (!ql_mask_match(level))
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2468	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2469
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2470	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2471
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2472	vaf.fmt = fmt;
				2473	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2474
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2475	if (vha != NULL) {
				2476	const struct pci_dev *pdev = vha->hw->pdev;
				2477	/* <module-name> <pci-name> <msg-id>:<host> Message */
				2478	pr_warn("%s [%s]-%04x:%ld: %pV",
				2479	QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
				2480	vha->host_no, &vaf);
				2481	} else {
				2482	pr_warn("%s [%s]-%04x: : %pV",
				2483	QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2484	}
				2485
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2486	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2487
				2488	}
				2489
				2490	/*
				2491	* This function is for formatting and logging debug information.
Masanari Iida	d6a0358	2012-08-22 14:20:58 -0400	[diff] [blame]	2492	* It is to be used when vha is not available and pci is available,
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2493	* i.e., before host allocation. It formats the message and logs it
				2494	* to the messages file.
				2495	* parameters:
				2496	* level: The level of the debug messages to be printed.
				2497	* If ql2xextended_error_logging value is correctly set,
				2498	* this message will appear in the messages file.
				2499	* pdev: Pointer to the struct pci_dev.
				2500	* id: This is a unique id for the level. It identifies the part
				2501	* of the code from where the message originated.
				2502	* msg: The message to be displayed.
				2503	*/
				2504	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2505	ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
				2506	const char *fmt, ...)
				2507	{
				2508	va_list va;
				2509	struct va_format vaf;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2510
				2511	if (pdev == NULL)
				2512	return;
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2513	if (!ql_mask_match(level))
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2514	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2515
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2516	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2517
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2518	vaf.fmt = fmt;
				2519	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2520
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2521	/* <module-name> <dev-name>:<msg-id> Message */
				2522	pr_warn("%s [%s]-%04x: : %pV",
				2523	QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2524
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2525	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2526	}
				2527
				2528	/*
				2529	* This function is for formatting and logging log messages.
				2530	* It is to be used when vha is available. It formats the message
				2531	* and logs it to the messages file. All the messages will be logged
				2532	* irrespective of value of ql2xextended_error_logging.
				2533	* parameters:
				2534	* level: The level of the log messages to be printed in the
				2535	* messages file.
				2536	* vha: Pointer to the scsi_qla_host_t
				2537	* id: This is a unique id for the level. It identifies the
				2538	* part of the code from where the message originated.
				2539	* msg: The message to be displayed.
				2540	*/
				2541	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2542	ql_log(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
				2543	{
				2544	va_list va;
				2545	struct va_format vaf;
				2546	char pbuf[128];
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2547
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2548	if (level > ql_errlev)
				2549	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2550
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2551	if (vha != NULL) {
				2552	const struct pci_dev *pdev = vha->hw->pdev;
				2553	/* <module-name> <msg-id>:<host> Message */
				2554	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
				2555	QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
				2556	} else {
				2557	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
				2558	QL_MSGHDR, "0000:00:00.0", id);
				2559	}
				2560	pbuf[sizeof(pbuf) - 1] = 0;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2561
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2562	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2563
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2564	vaf.fmt = fmt;
				2565	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2566
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2567	switch (level) {
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2568	case ql_log_fatal: /* FATAL LOG */
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2569	pr_crit("%s%pV", pbuf, &vaf);
				2570	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2571	case ql_log_warn:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2572	pr_err("%s%pV", pbuf, &vaf);
				2573	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2574	case ql_log_info:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2575	pr_warn("%s%pV", pbuf, &vaf);
				2576	break;
				2577	default:
				2578	pr_info("%s%pV", pbuf, &vaf);
				2579	break;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2580	}
				2581
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2582	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2583	}
				2584
				2585	/*
				2586	* This function is for formatting and logging log messages.
Masanari Iida	d6a0358	2012-08-22 14:20:58 -0400	[diff] [blame]	2587	* It is to be used when vha is not available and pci is available,
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2588	* i.e., before host allocation. It formats the message and logs
				2589	* it to the messages file. All the messages are logged irrespective
				2590	* of the value of ql2xextended_error_logging.
				2591	* parameters:
				2592	* level: The level of the log messages to be printed in the
				2593	* messages file.
				2594	* pdev: Pointer to the struct pci_dev.
				2595	* id: This is a unique id for the level. It identifies the
				2596	* part of the code from where the message originated.
				2597	* msg: The message to be displayed.
				2598	*/
				2599	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2600	ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
				2601	const char *fmt, ...)
				2602	{
				2603	va_list va;
				2604	struct va_format vaf;
				2605	char pbuf[128];
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2606
				2607	if (pdev == NULL)
				2608	return;
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2609	if (level > ql_errlev)
				2610	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2611
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2612	/* <module-name> <dev-name>:<msg-id> Message */
				2613	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
				2614	QL_MSGHDR, dev_name(&(pdev->dev)), id);
				2615	pbuf[sizeof(pbuf) - 1] = 0;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2616
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2617	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2618
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2619	vaf.fmt = fmt;
				2620	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2621
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2622	switch (level) {
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2623	case ql_log_fatal: /* FATAL LOG */
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2624	pr_crit("%s%pV", pbuf, &vaf);
				2625	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2626	case ql_log_warn:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2627	pr_err("%s%pV", pbuf, &vaf);
				2628	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2629	case ql_log_info:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2630	pr_warn("%s%pV", pbuf, &vaf);
				2631	break;
				2632	default:
				2633	pr_info("%s%pV", pbuf, &vaf);
				2634	break;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2635	}
				2636
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2637	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2638	}
				2639
				2640	void
				2641	ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
				2642	{
				2643	int i;
				2644	struct qla_hw_data *ha = vha->hw;
				2645	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
				2646	struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
				2647	struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
				2648	uint16_t __iomem *mbx_reg;
				2649
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2650	if (!ql_mask_match(level))
				2651	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2652
Atul Deshmukh	7ec0eff	2013-08-27 01:37:28 -0400	[diff] [blame]	2653	if (IS_P3P_TYPE(ha))
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2654	mbx_reg = &reg82->mailbox_in[0];
				2655	else if (IS_FWI2_CAPABLE(ha))
				2656	mbx_reg = &reg24->mailbox0;
				2657	else
				2658	mbx_reg = MAILBOX_REG(ha, reg, 0);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2659
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2660	ql_dbg(level, vha, id, "Mailbox registers:\n");
				2661	for (i = 0; i < 6; i++)
				2662	ql_dbg(level, vha, id,
				2663	"mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2664	}
				2665
				2666
				2667	void
				2668	ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
				2669	uint8_t *b, uint32_t size)
				2670	{
				2671	uint32_t cnt;
				2672	uint8_t c;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2673
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2674	if (!ql_mask_match(level))
				2675	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2676
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2677	ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
				2678	"9 Ah Bh Ch Dh Eh Fh\n");
				2679	ql_dbg(level, vha, id, "----------------------------------"
				2680	"----------------------------\n");
				2681
				2682	ql_dbg(level, vha, id, " ");
				2683	for (cnt = 0; cnt < size;) {
				2684	c = *b++;
				2685	printk("%02x", (uint32_t) c);
				2686	cnt++;
				2687	if (!(cnt % 16))
				2688	printk("\n");
				2689	else
				2690	printk(" ");
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2691	}
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2692	if (cnt % 16)
				2693	ql_dbg(level, vha, id, "\n");
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2694	}