Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support |
| 3 | * |
| 4 | * Copyright (C) 2007 ARM Limited |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 18 | */ |
| 19 | #include <linux/init.h> |
Catalin Marinas | 0762097 | 2007-07-20 11:42:40 +0100 | [diff] [blame] | 20 | #include <linux/spinlock.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 21 | #include <linux/io.h> |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 22 | |
| 23 | #include <asm/cacheflush.h> |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 24 | #include <asm/hardware/cache-l2x0.h> |
| 25 | |
| 26 | #define CACHE_LINE_SIZE 32 |
| 27 | |
| 28 | static void __iomem *l2x0_base; |
Catalin Marinas | 0762097 | 2007-07-20 11:42:40 +0100 | [diff] [blame] | 29 | static DEFINE_SPINLOCK(l2x0_lock); |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 30 | |
Russell King | 3d10743 | 2009-11-19 11:41:09 +0000 | [diff] [blame] | 31 | static inline void cache_wait(void __iomem *reg, unsigned long mask) |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 32 | { |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 33 | /* wait for the operation to complete */ |
Russell King | 3d10743 | 2009-11-19 11:41:09 +0000 | [diff] [blame] | 34 | while (readl(reg) & mask) |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 35 | ; |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 36 | } |
| 37 | |
| 38 | static inline void cache_sync(void) |
| 39 | { |
Russell King | 3d10743 | 2009-11-19 11:41:09 +0000 | [diff] [blame] | 40 | void __iomem *base = l2x0_base; |
| 41 | writel(0, base + L2X0_CACHE_SYNC); |
| 42 | cache_wait(base + L2X0_CACHE_SYNC, 1); |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 43 | } |
| 44 | |
Santosh Shilimkar | 424d6b1 | 2010-02-04 19:35:06 +0100 | [diff] [blame^] | 45 | static inline void l2x0_clean_line(unsigned long addr) |
| 46 | { |
| 47 | void __iomem *base = l2x0_base; |
| 48 | cache_wait(base + L2X0_CLEAN_LINE_PA, 1); |
| 49 | writel(addr, base + L2X0_CLEAN_LINE_PA); |
| 50 | } |
| 51 | |
| 52 | static inline void l2x0_inv_line(unsigned long addr) |
| 53 | { |
| 54 | void __iomem *base = l2x0_base; |
| 55 | cache_wait(base + L2X0_INV_LINE_PA, 1); |
| 56 | writel(addr, base + L2X0_INV_LINE_PA); |
| 57 | } |
| 58 | |
| 59 | static inline void l2x0_flush_line(unsigned long addr) |
| 60 | { |
| 61 | void __iomem *base = l2x0_base; |
| 62 | cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); |
| 63 | writel(addr, base + L2X0_CLEAN_INV_LINE_PA); |
| 64 | } |
| 65 | |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 66 | static inline void l2x0_inv_all(void) |
| 67 | { |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame] | 68 | unsigned long flags; |
| 69 | |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 70 | /* invalidate all ways */ |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame] | 71 | spin_lock_irqsave(&l2x0_lock, flags); |
Russell King | 3d10743 | 2009-11-19 11:41:09 +0000 | [diff] [blame] | 72 | writel(0xff, l2x0_base + L2X0_INV_WAY); |
| 73 | cache_wait(l2x0_base + L2X0_INV_WAY, 0xff); |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 74 | cache_sync(); |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame] | 75 | spin_unlock_irqrestore(&l2x0_lock, flags); |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 76 | } |
| 77 | |
| 78 | static void l2x0_inv_range(unsigned long start, unsigned long end) |
| 79 | { |
Russell King | 3d10743 | 2009-11-19 11:41:09 +0000 | [diff] [blame] | 80 | void __iomem *base = l2x0_base; |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame] | 81 | unsigned long flags; |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 82 | |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame] | 83 | spin_lock_irqsave(&l2x0_lock, flags); |
Rui Sousa | 4f6627a | 2007-09-15 00:56:19 +0100 | [diff] [blame] | 84 | if (start & (CACHE_LINE_SIZE - 1)) { |
| 85 | start &= ~(CACHE_LINE_SIZE - 1); |
Santosh Shilimkar | 424d6b1 | 2010-02-04 19:35:06 +0100 | [diff] [blame^] | 86 | l2x0_flush_line(start); |
Rui Sousa | 4f6627a | 2007-09-15 00:56:19 +0100 | [diff] [blame] | 87 | start += CACHE_LINE_SIZE; |
| 88 | } |
| 89 | |
| 90 | if (end & (CACHE_LINE_SIZE - 1)) { |
| 91 | end &= ~(CACHE_LINE_SIZE - 1); |
Santosh Shilimkar | 424d6b1 | 2010-02-04 19:35:06 +0100 | [diff] [blame^] | 92 | l2x0_flush_line(end); |
Rui Sousa | 4f6627a | 2007-09-15 00:56:19 +0100 | [diff] [blame] | 93 | } |
| 94 | |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame] | 95 | while (start < end) { |
| 96 | unsigned long blk_end = start + min(end - start, 4096UL); |
| 97 | |
| 98 | while (start < blk_end) { |
Santosh Shilimkar | 424d6b1 | 2010-02-04 19:35:06 +0100 | [diff] [blame^] | 99 | l2x0_inv_line(start); |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame] | 100 | start += CACHE_LINE_SIZE; |
| 101 | } |
| 102 | |
| 103 | if (blk_end < end) { |
| 104 | spin_unlock_irqrestore(&l2x0_lock, flags); |
| 105 | spin_lock_irqsave(&l2x0_lock, flags); |
| 106 | } |
| 107 | } |
Russell King | 3d10743 | 2009-11-19 11:41:09 +0000 | [diff] [blame] | 108 | cache_wait(base + L2X0_INV_LINE_PA, 1); |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 109 | cache_sync(); |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame] | 110 | spin_unlock_irqrestore(&l2x0_lock, flags); |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 111 | } |
| 112 | |
| 113 | static void l2x0_clean_range(unsigned long start, unsigned long end) |
| 114 | { |
Russell King | 3d10743 | 2009-11-19 11:41:09 +0000 | [diff] [blame] | 115 | void __iomem *base = l2x0_base; |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame] | 116 | unsigned long flags; |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 117 | |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame] | 118 | spin_lock_irqsave(&l2x0_lock, flags); |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 119 | start &= ~(CACHE_LINE_SIZE - 1); |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame] | 120 | while (start < end) { |
| 121 | unsigned long blk_end = start + min(end - start, 4096UL); |
| 122 | |
| 123 | while (start < blk_end) { |
Santosh Shilimkar | 424d6b1 | 2010-02-04 19:35:06 +0100 | [diff] [blame^] | 124 | l2x0_clean_line(start); |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame] | 125 | start += CACHE_LINE_SIZE; |
| 126 | } |
| 127 | |
| 128 | if (blk_end < end) { |
| 129 | spin_unlock_irqrestore(&l2x0_lock, flags); |
| 130 | spin_lock_irqsave(&l2x0_lock, flags); |
| 131 | } |
| 132 | } |
Russell King | 3d10743 | 2009-11-19 11:41:09 +0000 | [diff] [blame] | 133 | cache_wait(base + L2X0_CLEAN_LINE_PA, 1); |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 134 | cache_sync(); |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame] | 135 | spin_unlock_irqrestore(&l2x0_lock, flags); |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | static void l2x0_flush_range(unsigned long start, unsigned long end) |
| 139 | { |
Russell King | 3d10743 | 2009-11-19 11:41:09 +0000 | [diff] [blame] | 140 | void __iomem *base = l2x0_base; |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame] | 141 | unsigned long flags; |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 142 | |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame] | 143 | spin_lock_irqsave(&l2x0_lock, flags); |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 144 | start &= ~(CACHE_LINE_SIZE - 1); |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame] | 145 | while (start < end) { |
| 146 | unsigned long blk_end = start + min(end - start, 4096UL); |
| 147 | |
| 148 | while (start < blk_end) { |
Santosh Shilimkar | 424d6b1 | 2010-02-04 19:35:06 +0100 | [diff] [blame^] | 149 | l2x0_flush_line(start); |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame] | 150 | start += CACHE_LINE_SIZE; |
| 151 | } |
| 152 | |
| 153 | if (blk_end < end) { |
| 154 | spin_unlock_irqrestore(&l2x0_lock, flags); |
| 155 | spin_lock_irqsave(&l2x0_lock, flags); |
| 156 | } |
| 157 | } |
Russell King | 3d10743 | 2009-11-19 11:41:09 +0000 | [diff] [blame] | 158 | cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 159 | cache_sync(); |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame] | 160 | spin_unlock_irqrestore(&l2x0_lock, flags); |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 161 | } |
| 162 | |
| 163 | void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) |
| 164 | { |
| 165 | __u32 aux; |
| 166 | |
| 167 | l2x0_base = base; |
| 168 | |
Srinidhi Kasagar | 48371cd | 2009-12-02 06:18:03 +0100 | [diff] [blame] | 169 | /* |
| 170 | * Check if l2x0 controller is already enabled. |
| 171 | * If you are booting from non-secure mode |
| 172 | * accessing the below registers will fault. |
| 173 | */ |
| 174 | if (!(readl(l2x0_base + L2X0_CTRL) & 1)) { |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 175 | |
Srinidhi Kasagar | 48371cd | 2009-12-02 06:18:03 +0100 | [diff] [blame] | 176 | /* l2x0 controller is disabled */ |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 177 | |
Srinidhi Kasagar | 48371cd | 2009-12-02 06:18:03 +0100 | [diff] [blame] | 178 | aux = readl(l2x0_base + L2X0_AUX_CTRL); |
| 179 | aux &= aux_mask; |
| 180 | aux |= aux_val; |
| 181 | writel(aux, l2x0_base + L2X0_AUX_CTRL); |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 182 | |
Srinidhi Kasagar | 48371cd | 2009-12-02 06:18:03 +0100 | [diff] [blame] | 183 | l2x0_inv_all(); |
| 184 | |
| 185 | /* enable L2X0 */ |
| 186 | writel(1, l2x0_base + L2X0_CTRL); |
| 187 | } |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 188 | |
| 189 | outer_cache.inv_range = l2x0_inv_range; |
| 190 | outer_cache.clean_range = l2x0_clean_range; |
| 191 | outer_cache.flush_range = l2x0_flush_range; |
| 192 | |
| 193 | printk(KERN_INFO "L2X0 cache controller enabled\n"); |
| 194 | } |