Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1 | /* |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 2 | * Copyright (c) 2008-2010 Atheros Communications Inc. |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | |
| 17 | #ifndef HW_H |
| 18 | #define HW_H |
| 19 | |
| 20 | #include <linux/if_ether.h> |
| 21 | #include <linux/delay.h> |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 22 | #include <linux/io.h> |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 23 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 24 | #include "mac.h" |
| 25 | #include "ani.h" |
| 26 | #include "eeprom.h" |
| 27 | #include "calib.h" |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 28 | #include "reg.h" |
| 29 | #include "phy.h" |
Luis R. Rodriguez | af03abe | 2009-09-09 02:33:11 -0700 | [diff] [blame] | 30 | #include "btcoex.h" |
Luis R. Rodriguez | a085ff7 | 2008-12-23 15:58:51 -0800 | [diff] [blame] | 31 | |
Luis R. Rodriguez | 203c480 | 2009-03-30 22:30:33 -0400 | [diff] [blame] | 32 | #include "../regd.h" |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 33 | #include "../debug.h" |
Bob Copeland | 3a702e4 | 2009-03-30 22:30:29 -0400 | [diff] [blame] | 34 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 35 | #define ATHEROS_VENDOR_ID 0x168c |
Luis R. Rodriguez | 7976b42 | 2009-09-23 23:07:02 -0400 | [diff] [blame] | 36 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 37 | #define AR5416_DEVID_PCI 0x0023 |
| 38 | #define AR5416_DEVID_PCIE 0x0024 |
| 39 | #define AR9160_DEVID_PCI 0x0027 |
| 40 | #define AR9280_DEVID_PCI 0x0029 |
| 41 | #define AR9280_DEVID_PCIE 0x002a |
| 42 | #define AR9285_DEVID_PCIE 0x002b |
Luis R. Rodriguez | 5ffaf8a | 2010-02-02 11:58:33 -0500 | [diff] [blame] | 43 | #define AR2427_DEVID_PCIE 0x002c |
Senthil Balasubramanian | db3cc53 | 2010-04-15 17:38:18 -0400 | [diff] [blame] | 44 | #define AR9287_DEVID_PCI 0x002d |
| 45 | #define AR9287_DEVID_PCIE 0x002e |
| 46 | #define AR9300_DEVID_PCIE 0x0030 |
Luis R. Rodriguez | 7976b42 | 2009-09-23 23:07:02 -0400 | [diff] [blame] | 47 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 48 | #define AR5416_AR9100_DEVID 0x000b |
Luis R. Rodriguez | 7976b42 | 2009-09-23 23:07:02 -0400 | [diff] [blame] | 49 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 50 | #define AR_SUBVENDOR_ID_NOG 0x0e11 |
| 51 | #define AR_SUBVENDOR_ID_NEW_A 0x7065 |
| 52 | #define AR5416_MAGIC 0x19641014 |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 53 | |
Vasanthakumar Thiagarajan | fe12946 | 2009-09-09 15:25:50 +0530 | [diff] [blame] | 54 | #define AR9280_COEX2WIRE_SUBSYSID 0x309b |
| 55 | #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa |
| 56 | #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab |
| 57 | |
Luis R. Rodriguez | e3d01bf | 2009-09-13 23:11:13 -0700 | [diff] [blame] | 58 | #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) |
| 59 | |
Luis R. Rodriguez | cfe8cba | 2009-09-13 23:39:31 -0700 | [diff] [blame] | 60 | #define ATH_DEFAULT_NOISE_FLOOR -95 |
| 61 | |
John W. Linville | 04658fb | 2009-11-13 13:12:59 -0500 | [diff] [blame] | 62 | #define ATH9K_RSSI_BAD -128 |
Luis R. Rodriguez | 990b70a | 2009-09-13 23:55:05 -0700 | [diff] [blame] | 63 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 64 | /* Register read/write primitives */ |
Luis R. Rodriguez | 9e4bffd | 2009-09-10 16:11:21 -0700 | [diff] [blame] | 65 | #define REG_WRITE(_ah, _reg, _val) \ |
| 66 | ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg)) |
| 67 | |
| 68 | #define REG_READ(_ah, _reg) \ |
| 69 | ath9k_hw_common(_ah)->ops->read((_ah), (_reg)) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 70 | |
Sujith | 20b3efd | 2010-04-16 11:53:55 +0530 | [diff] [blame] | 71 | #define ENABLE_REGWRITE_BUFFER(_ah) \ |
| 72 | do { \ |
| 73 | if (AR_SREV_9271(_ah)) \ |
| 74 | ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \ |
| 75 | } while (0) |
| 76 | |
| 77 | #define DISABLE_REGWRITE_BUFFER(_ah) \ |
| 78 | do { \ |
| 79 | if (AR_SREV_9271(_ah)) \ |
| 80 | ath9k_hw_common(_ah)->ops->disable_write_buffer((_ah)); \ |
| 81 | } while (0) |
| 82 | |
| 83 | #define REGWRITE_BUFFER_FLUSH(_ah) \ |
| 84 | do { \ |
| 85 | if (AR_SREV_9271(_ah)) \ |
| 86 | ath9k_hw_common(_ah)->ops->write_flush((_ah)); \ |
| 87 | } while (0) |
| 88 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 89 | #define SM(_v, _f) (((_v) << _f##_S) & _f) |
| 90 | #define MS(_v, _f) (((_v) & _f) >> _f##_S) |
| 91 | #define REG_RMW(_a, _r, _set, _clr) \ |
| 92 | REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set)) |
| 93 | #define REG_RMW_FIELD(_a, _r, _f, _v) \ |
| 94 | REG_WRITE(_a, _r, \ |
| 95 | (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f)) |
Luis R. Rodriguez | 1547da3 | 2010-04-15 17:39:15 -0400 | [diff] [blame] | 96 | #define REG_READ_FIELD(_a, _r, _f) \ |
| 97 | (((REG_READ(_a, _r) & _f) >> _f##_S)) |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 98 | #define REG_SET_BIT(_a, _r, _f) \ |
| 99 | REG_WRITE(_a, _r, REG_READ(_a, _r) | _f) |
| 100 | #define REG_CLR_BIT(_a, _r, _f) \ |
| 101 | REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 102 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 103 | #define DO_DELAY(x) do { \ |
| 104 | if ((++(x) % 64) == 0) \ |
| 105 | udelay(1); \ |
| 106 | } while (0) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 107 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 108 | #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ |
| 109 | int r; \ |
| 110 | for (r = 0; r < ((iniarray)->ia_rows); r++) { \ |
| 111 | REG_WRITE(ah, INI_RA((iniarray), (r), 0), \ |
| 112 | INI_RA((iniarray), r, (column))); \ |
| 113 | DO_DELAY(regWr); \ |
| 114 | } \ |
| 115 | } while (0) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 116 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 117 | #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 |
| 118 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 |
| 119 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 |
| 120 | #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 |
Vasanthakumar Thiagarajan | 1773912 | 2009-08-26 21:08:50 +0530 | [diff] [blame] | 121 | #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 122 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 |
| 123 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 124 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 125 | #define AR_GPIOD_MASK 0x00001FFF |
| 126 | #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 127 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 128 | #define BASE_ACTIVATE_DELAY 100 |
Senthil Balasubramanian | 63a75b9 | 2009-09-18 15:07:03 +0530 | [diff] [blame] | 129 | #define RTC_PLL_SETTLE_DELAY 100 |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 130 | #define COEF_SCALE_S 24 |
| 131 | #define HT40_CHANNEL_CENTER_SHIFT 10 |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 132 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 133 | #define ATH9K_ANTENNA0_CHAINMASK 0x1 |
| 134 | #define ATH9K_ANTENNA1_CHAINMASK 0x2 |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 135 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 136 | #define ATH9K_NUM_DMA_DEBUG_REGS 8 |
| 137 | #define ATH9K_NUM_QUEUES 10 |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 138 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 139 | #define MAX_RATE_POWER 63 |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 140 | #define AH_WAIT_TIMEOUT 100000 /* (us) */ |
Gabor Juhos | f9b604f | 2009-06-21 00:02:15 +0200 | [diff] [blame] | 141 | #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 142 | #define AH_TIME_QUANTUM 10 |
| 143 | #define AR_KEYTABLE_SIZE 128 |
Sujith | d8caa83 | 2009-09-17 09:25:45 +0530 | [diff] [blame] | 144 | #define POWER_UP_TIME 10000 |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 145 | #define SPUR_RSSI_THRESH 40 |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 146 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 147 | #define CAB_TIMEOUT_VAL 10 |
| 148 | #define BEACON_TIMEOUT_VAL 10 |
| 149 | #define MIN_BEACON_TIMEOUT_VAL 1 |
| 150 | #define SLEEP_SLOP 3 |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 151 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 152 | #define INIT_CONFIG_STATUS 0x00000000 |
| 153 | #define INIT_RSSI_THR 0x00000700 |
| 154 | #define INIT_BCON_CNTRL_REG 0x00000000 |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 155 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 156 | #define TU_TO_USEC(_tu) ((_tu) << 10) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 157 | |
Vasanthakumar Thiagarajan | ceb2644 | 2010-04-15 17:38:25 -0400 | [diff] [blame] | 158 | #define ATH9K_HW_RX_HP_QDEPTH 16 |
| 159 | #define ATH9K_HW_RX_LP_QDEPTH 128 |
| 160 | |
Felix Fietkau | 717f6be | 2010-06-12 00:34:00 -0400 | [diff] [blame] | 161 | #define PAPRD_GAIN_TABLE_ENTRIES 32 |
| 162 | #define PAPRD_TABLE_SZ 24 |
| 163 | |
Luis R. Rodriguez | 13ce3e9 | 2010-04-15 17:38:37 -0400 | [diff] [blame] | 164 | enum ath_ini_subsys { |
| 165 | ATH_INI_PRE = 0, |
| 166 | ATH_INI_CORE, |
| 167 | ATH_INI_POST, |
| 168 | ATH_INI_NUM_SPLIT, |
| 169 | }; |
| 170 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 171 | enum wireless_mode { |
| 172 | ATH9K_MODE_11A = 0, |
Luis R. Rodriguez | b9b6e15 | 2009-07-14 20:14:03 -0400 | [diff] [blame] | 173 | ATH9K_MODE_11G, |
| 174 | ATH9K_MODE_11NA_HT20, |
| 175 | ATH9K_MODE_11NG_HT20, |
| 176 | ATH9K_MODE_11NA_HT40PLUS, |
| 177 | ATH9K_MODE_11NA_HT40MINUS, |
| 178 | ATH9K_MODE_11NG_HT40PLUS, |
| 179 | ATH9K_MODE_11NG_HT40MINUS, |
| 180 | ATH9K_MODE_MAX, |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 181 | }; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 182 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 183 | enum ath9k_hw_caps { |
Sujith | bdbdf46 | 2009-03-30 15:28:22 +0530 | [diff] [blame] | 184 | ATH9K_HW_CAP_MIC_AESCCM = BIT(0), |
| 185 | ATH9K_HW_CAP_MIC_CKIP = BIT(1), |
| 186 | ATH9K_HW_CAP_MIC_TKIP = BIT(2), |
| 187 | ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3), |
| 188 | ATH9K_HW_CAP_CIPHER_CKIP = BIT(4), |
| 189 | ATH9K_HW_CAP_CIPHER_TKIP = BIT(5), |
| 190 | ATH9K_HW_CAP_VEOL = BIT(6), |
| 191 | ATH9K_HW_CAP_BSSIDMASK = BIT(7), |
| 192 | ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8), |
| 193 | ATH9K_HW_CAP_HT = BIT(9), |
| 194 | ATH9K_HW_CAP_GTT = BIT(10), |
| 195 | ATH9K_HW_CAP_FASTCC = BIT(11), |
| 196 | ATH9K_HW_CAP_RFSILENT = BIT(12), |
| 197 | ATH9K_HW_CAP_CST = BIT(13), |
| 198 | ATH9K_HW_CAP_ENHANCEDPM = BIT(14), |
| 199 | ATH9K_HW_CAP_AUTOSLEEP = BIT(15), |
| 200 | ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16), |
Vasanthakumar Thiagarajan | 1adf02f | 2010-04-15 17:38:24 -0400 | [diff] [blame] | 201 | ATH9K_HW_CAP_EDMA = BIT(17), |
Vasanthakumar Thiagarajan | 6c84ce0 | 2010-04-15 17:39:16 -0400 | [diff] [blame] | 202 | ATH9K_HW_CAP_RAC_SUPPORTED = BIT(18), |
Luis R. Rodriguez | ce01805 | 2010-04-15 17:39:38 -0400 | [diff] [blame] | 203 | ATH9K_HW_CAP_LDPC = BIT(19), |
Vasanthakumar Thiagarajan | e555372 | 2010-04-26 15:04:33 -0400 | [diff] [blame] | 204 | ATH9K_HW_CAP_FASTCLOCK = BIT(20), |
Vasanthakumar Thiagarajan | 6473d24 | 2010-05-13 18:42:38 -0700 | [diff] [blame] | 205 | ATH9K_HW_CAP_SGI_20 = BIT(21), |
Felix Fietkau | 4935250 | 2010-06-12 00:33:59 -0400 | [diff] [blame] | 206 | ATH9K_HW_CAP_PAPRD = BIT(22), |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 207 | }; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 208 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 209 | struct ath9k_hw_capabilities { |
| 210 | u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ |
| 211 | DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */ |
| 212 | u16 total_queues; |
| 213 | u16 keycache_size; |
| 214 | u16 low_5ghz_chan, high_5ghz_chan; |
| 215 | u16 low_2ghz_chan, high_2ghz_chan; |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 216 | u16 rts_aggr_limit; |
| 217 | u8 tx_chainmask; |
| 218 | u8 rx_chainmask; |
| 219 | u16 tx_triglevel_max; |
| 220 | u16 reg_cap; |
| 221 | u8 num_gpio_pins; |
| 222 | u8 num_antcfg_2ghz; |
| 223 | u8 num_antcfg_5ghz; |
Vasanthakumar Thiagarajan | ceb2644 | 2010-04-15 17:38:25 -0400 | [diff] [blame] | 224 | u8 rx_hp_qdepth; |
| 225 | u8 rx_lp_qdepth; |
| 226 | u8 rx_status_len; |
Vasanthakumar Thiagarajan | 162c3be | 2010-04-15 17:38:41 -0400 | [diff] [blame] | 227 | u8 tx_desc_len; |
Vasanthakumar Thiagarajan | 5088c2f | 2010-04-15 17:39:34 -0400 | [diff] [blame] | 228 | u8 txs_len; |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 229 | }; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 230 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 231 | struct ath9k_ops_config { |
| 232 | int dma_beacon_response_time; |
| 233 | int sw_beacon_response_time; |
| 234 | int additional_swba_backoff; |
| 235 | int ack_6mb; |
Felix Fietkau | 41f3e54 | 2010-06-12 00:33:56 -0400 | [diff] [blame] | 236 | u32 cwm_ignore_extcca; |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 237 | u8 pcie_powersave_enable; |
Luis R. Rodriguez | 6a0ec30 | 2010-06-21 18:38:49 -0400 | [diff] [blame] | 238 | bool pcieSerDesWrite; |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 239 | u8 pcie_clock_req; |
| 240 | u32 pcie_waen; |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 241 | u8 analog_shiftreg; |
| 242 | u8 ht_enable; |
| 243 | u32 ofdm_trig_low; |
| 244 | u32 ofdm_trig_high; |
| 245 | u32 cck_trig_high; |
| 246 | u32 cck_trig_low; |
| 247 | u32 enable_ani; |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 248 | int serialize_regmode; |
Sujith | 0ce024c | 2009-12-14 14:57:00 +0530 | [diff] [blame] | 249 | bool rx_intr_mitigation; |
Vasanthakumar Thiagarajan | 55e82df | 2010-04-15 17:39:06 -0400 | [diff] [blame] | 250 | bool tx_intr_mitigation; |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 251 | #define SPUR_DISABLE 0 |
| 252 | #define SPUR_ENABLE_IOCTL 1 |
| 253 | #define SPUR_ENABLE_EEPROM 2 |
| 254 | #define AR_EEPROM_MODAL_SPURS 5 |
| 255 | #define AR_SPUR_5413_1 1640 |
| 256 | #define AR_SPUR_5413_2 1200 |
| 257 | #define AR_NO_SPUR 0x8000 |
| 258 | #define AR_BASE_FREQ_2GHZ 2300 |
| 259 | #define AR_BASE_FREQ_5GHZ 4900 |
| 260 | #define AR_SPUR_FEEQ_BOUND_HT40 19 |
| 261 | #define AR_SPUR_FEEQ_BOUND_HT20 10 |
| 262 | int spurmode; |
| 263 | u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; |
Luis R. Rodriguez | f4709fd | 2009-11-24 21:37:57 -0500 | [diff] [blame] | 264 | u8 max_txtrig_level; |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 265 | u16 ani_poll_interval; /* ANI poll interval in ms */ |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 266 | }; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 267 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 268 | enum ath9k_int { |
| 269 | ATH9K_INT_RX = 0x00000001, |
| 270 | ATH9K_INT_RXDESC = 0x00000002, |
Felix Fietkau | b5c80475 | 2010-04-15 17:38:48 -0400 | [diff] [blame] | 271 | ATH9K_INT_RXHP = 0x00000001, |
| 272 | ATH9K_INT_RXLP = 0x00000002, |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 273 | ATH9K_INT_RXNOFRM = 0x00000008, |
| 274 | ATH9K_INT_RXEOL = 0x00000010, |
| 275 | ATH9K_INT_RXORN = 0x00000020, |
| 276 | ATH9K_INT_TX = 0x00000040, |
| 277 | ATH9K_INT_TXDESC = 0x00000080, |
| 278 | ATH9K_INT_TIM_TIMER = 0x00000100, |
Luis R. Rodriguez | aea702b | 2010-05-13 13:33:43 -0400 | [diff] [blame] | 279 | ATH9K_INT_BB_WATCHDOG = 0x00000400, |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 280 | ATH9K_INT_TXURN = 0x00000800, |
| 281 | ATH9K_INT_MIB = 0x00001000, |
| 282 | ATH9K_INT_RXPHY = 0x00004000, |
| 283 | ATH9K_INT_RXKCM = 0x00008000, |
| 284 | ATH9K_INT_SWBA = 0x00010000, |
| 285 | ATH9K_INT_BMISS = 0x00040000, |
| 286 | ATH9K_INT_BNR = 0x00100000, |
| 287 | ATH9K_INT_TIM = 0x00200000, |
| 288 | ATH9K_INT_DTIM = 0x00400000, |
| 289 | ATH9K_INT_DTIMSYNC = 0x00800000, |
| 290 | ATH9K_INT_GPIO = 0x01000000, |
| 291 | ATH9K_INT_CABEND = 0x02000000, |
Sujith | 4af9cf4 | 2009-02-12 10:06:47 +0530 | [diff] [blame] | 292 | ATH9K_INT_TSFOOR = 0x04000000, |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 293 | ATH9K_INT_GENTIMER = 0x08000000, |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 294 | ATH9K_INT_CST = 0x10000000, |
| 295 | ATH9K_INT_GTT = 0x20000000, |
| 296 | ATH9K_INT_FATAL = 0x40000000, |
| 297 | ATH9K_INT_GLOBAL = 0x80000000, |
| 298 | ATH9K_INT_BMISC = ATH9K_INT_TIM | |
| 299 | ATH9K_INT_DTIM | |
| 300 | ATH9K_INT_DTIMSYNC | |
Sujith | 4af9cf4 | 2009-02-12 10:06:47 +0530 | [diff] [blame] | 301 | ATH9K_INT_TSFOOR | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 302 | ATH9K_INT_CABEND, |
| 303 | ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | |
| 304 | ATH9K_INT_RXDESC | |
| 305 | ATH9K_INT_RXEOL | |
| 306 | ATH9K_INT_RXORN | |
| 307 | ATH9K_INT_TXURN | |
| 308 | ATH9K_INT_TXDESC | |
| 309 | ATH9K_INT_MIB | |
| 310 | ATH9K_INT_RXPHY | |
| 311 | ATH9K_INT_RXKCM | |
| 312 | ATH9K_INT_SWBA | |
| 313 | ATH9K_INT_BMISS | |
| 314 | ATH9K_INT_GPIO, |
| 315 | ATH9K_INT_NOCARD = 0xffffffff |
| 316 | }; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 317 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 318 | #define CHANNEL_CW_INT 0x00002 |
| 319 | #define CHANNEL_CCK 0x00020 |
| 320 | #define CHANNEL_OFDM 0x00040 |
| 321 | #define CHANNEL_2GHZ 0x00080 |
| 322 | #define CHANNEL_5GHZ 0x00100 |
| 323 | #define CHANNEL_PASSIVE 0x00200 |
| 324 | #define CHANNEL_DYN 0x00400 |
| 325 | #define CHANNEL_HALF 0x04000 |
| 326 | #define CHANNEL_QUARTER 0x08000 |
| 327 | #define CHANNEL_HT20 0x10000 |
| 328 | #define CHANNEL_HT40PLUS 0x20000 |
| 329 | #define CHANNEL_HT40MINUS 0x40000 |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 330 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 331 | #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) |
| 332 | #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) |
| 333 | #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) |
| 334 | #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) |
| 335 | #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) |
| 336 | #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) |
| 337 | #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) |
| 338 | #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) |
| 339 | #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) |
| 340 | #define CHANNEL_ALL \ |
| 341 | (CHANNEL_OFDM| \ |
| 342 | CHANNEL_CCK| \ |
| 343 | CHANNEL_2GHZ | \ |
| 344 | CHANNEL_5GHZ | \ |
| 345 | CHANNEL_HT20 | \ |
| 346 | CHANNEL_HT40PLUS | \ |
| 347 | CHANNEL_HT40MINUS) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 348 | |
Felix Fietkau | 20bd2a0 | 2010-07-31 00:12:00 +0200 | [diff] [blame] | 349 | struct ath9k_hw_cal_data { |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 350 | u16 channel; |
| 351 | u32 channelFlags; |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 352 | int32_t CalValid; |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 353 | int8_t iCoff; |
| 354 | int8_t qCoff; |
| 355 | int16_t rawNoiseFloor; |
Felix Fietkau | 717f6be | 2010-06-12 00:34:00 -0400 | [diff] [blame] | 356 | bool paprd_done; |
Felix Fietkau | 4254bc1 | 2010-07-31 00:12:01 +0200 | [diff] [blame^] | 357 | bool nfcal_pending; |
Felix Fietkau | 717f6be | 2010-06-12 00:34:00 -0400 | [diff] [blame] | 358 | u16 small_signal_gain[AR9300_MAX_CHAINS]; |
| 359 | u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ]; |
Felix Fietkau | 20bd2a0 | 2010-07-31 00:12:00 +0200 | [diff] [blame] | 360 | struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; |
| 361 | }; |
| 362 | |
| 363 | struct ath9k_channel { |
| 364 | struct ieee80211_channel *chan; |
| 365 | u16 channel; |
| 366 | u32 channelFlags; |
| 367 | u32 chanmode; |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 368 | }; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 369 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 370 | #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ |
| 371 | (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ |
| 372 | (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ |
| 373 | (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) |
| 374 | #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) |
| 375 | #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) |
| 376 | #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 377 | #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) |
| 378 | #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) |
Felix Fietkau | 6b42e8d | 2010-04-26 15:04:35 -0400 | [diff] [blame] | 379 | #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \ |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 380 | ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ |
Felix Fietkau | 6b42e8d | 2010-04-26 15:04:35 -0400 | [diff] [blame] | 381 | ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 382 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 383 | /* These macros check chanmode and not channelFlags */ |
| 384 | #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) |
| 385 | #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ |
| 386 | ((_c)->chanmode == CHANNEL_G_HT20)) |
| 387 | #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ |
| 388 | ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ |
| 389 | ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ |
| 390 | ((_c)->chanmode == CHANNEL_G_HT40MINUS)) |
| 391 | #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 392 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 393 | enum ath9k_power_mode { |
| 394 | ATH9K_PM_AWAKE = 0, |
| 395 | ATH9K_PM_FULL_SLEEP, |
| 396 | ATH9K_PM_NETWORK_SLEEP, |
| 397 | ATH9K_PM_UNDEFINED |
| 398 | }; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 399 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 400 | enum ath9k_tp_scale { |
| 401 | ATH9K_TP_SCALE_MAX = 0, |
| 402 | ATH9K_TP_SCALE_50, |
| 403 | ATH9K_TP_SCALE_25, |
| 404 | ATH9K_TP_SCALE_12, |
| 405 | ATH9K_TP_SCALE_MIN |
| 406 | }; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 407 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 408 | enum ser_reg_mode { |
| 409 | SER_REG_MODE_OFF = 0, |
| 410 | SER_REG_MODE_ON = 1, |
| 411 | SER_REG_MODE_AUTO = 2, |
| 412 | }; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 413 | |
Vasanthakumar Thiagarajan | ad7b806 | 2010-04-15 17:38:28 -0400 | [diff] [blame] | 414 | enum ath9k_rx_qtype { |
| 415 | ATH9K_RX_QUEUE_HP, |
| 416 | ATH9K_RX_QUEUE_LP, |
| 417 | ATH9K_RX_QUEUE_MAX, |
| 418 | }; |
| 419 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 420 | struct ath9k_beacon_state { |
| 421 | u32 bs_nexttbtt; |
| 422 | u32 bs_nextdtim; |
| 423 | u32 bs_intval; |
| 424 | #define ATH9K_BEACON_PERIOD 0x0000ffff |
| 425 | #define ATH9K_BEACON_ENA 0x00800000 |
| 426 | #define ATH9K_BEACON_RESET_TSF 0x01000000 |
Sujith | 4af9cf4 | 2009-02-12 10:06:47 +0530 | [diff] [blame] | 427 | #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 428 | u32 bs_dtimperiod; |
| 429 | u16 bs_cfpperiod; |
| 430 | u16 bs_cfpmaxduration; |
| 431 | u32 bs_cfpnext; |
| 432 | u16 bs_timoffset; |
| 433 | u16 bs_bmissthreshold; |
| 434 | u32 bs_sleepduration; |
Sujith | 4af9cf4 | 2009-02-12 10:06:47 +0530 | [diff] [blame] | 435 | u32 bs_tsfoor_threshold; |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 436 | }; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 437 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 438 | struct chan_centers { |
| 439 | u16 synth_center; |
| 440 | u16 ctl_center; |
| 441 | u16 ext_center; |
| 442 | }; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 443 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 444 | enum { |
| 445 | ATH9K_RESET_POWER_ON, |
| 446 | ATH9K_RESET_WARM, |
| 447 | ATH9K_RESET_COLD, |
| 448 | }; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 449 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 450 | struct ath9k_hw_version { |
| 451 | u32 magic; |
| 452 | u16 devid; |
| 453 | u16 subvendorid; |
| 454 | u32 macVersion; |
| 455 | u16 macRev; |
| 456 | u16 phyRev; |
| 457 | u16 analog5GhzRev; |
| 458 | u16 analog2GhzRev; |
Vasanthakumar Thiagarajan | aeac355 | 2009-09-09 15:25:49 +0530 | [diff] [blame] | 459 | u16 subsysid; |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 460 | }; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 461 | |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 462 | /* Generic TSF timer definitions */ |
| 463 | |
| 464 | #define ATH_MAX_GEN_TIMER 16 |
| 465 | |
| 466 | #define AR_GENTMR_BIT(_index) (1 << (_index)) |
| 467 | |
| 468 | /* |
Walter Goldens | 77c2061 | 2010-05-18 04:44:54 -0700 | [diff] [blame] | 469 | * Using de Bruijin sequence to look up 1's index in a 32 bit number |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 470 | * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001 |
| 471 | */ |
Vasanthakumar Thiagarajan | c90017d | 2009-11-13 14:32:39 +0530 | [diff] [blame] | 472 | #define debruijn32 0x077CB531U |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 473 | |
| 474 | struct ath_gen_timer_configuration { |
| 475 | u32 next_addr; |
| 476 | u32 period_addr; |
| 477 | u32 mode_addr; |
| 478 | u32 mode_mask; |
| 479 | }; |
| 480 | |
| 481 | struct ath_gen_timer { |
| 482 | void (*trigger)(void *arg); |
| 483 | void (*overflow)(void *arg); |
| 484 | void *arg; |
| 485 | u8 index; |
| 486 | }; |
| 487 | |
| 488 | struct ath_gen_timer_table { |
| 489 | u32 gen_timer_index[32]; |
| 490 | struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; |
| 491 | union { |
| 492 | unsigned long timer_bits; |
| 493 | u16 val; |
| 494 | } timer_mask; |
| 495 | }; |
| 496 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 497 | /** |
| 498 | * struct ath_hw_private_ops - callbacks used internally by hardware code |
| 499 | * |
| 500 | * This structure contains private callbacks designed to only be used internally |
| 501 | * by the hardware core. |
| 502 | * |
Luis R. Rodriguez | 795f5e2 | 2010-04-15 17:39:00 -0400 | [diff] [blame] | 503 | * @init_cal_settings: setup types of calibrations supported |
| 504 | * @init_cal: starts actual calibration |
| 505 | * |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 506 | * @init_mode_regs: Initializes mode registers |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 507 | * @init_mode_gain_regs: Initialize TX/RX gain registers |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 508 | * @macversion_supported: If this specific mac revision is supported |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 509 | * |
| 510 | * @rf_set_freq: change frequency |
| 511 | * @spur_mitigate_freq: spur mitigation |
| 512 | * @rf_alloc_ext_banks: |
| 513 | * @rf_free_ext_banks: |
| 514 | * @set_rf_regs: |
Luis R. Rodriguez | 6477396 | 2010-04-15 17:38:17 -0400 | [diff] [blame] | 515 | * @compute_pll_control: compute the PLL control value to use for |
| 516 | * AR_RTC_PLL_CONTROL for a given channel |
Luis R. Rodriguez | 795f5e2 | 2010-04-15 17:39:00 -0400 | [diff] [blame] | 517 | * @setup_calibration: set up calibration |
| 518 | * @iscal_supported: used to query if a type of calibration is supported |
Luis R. Rodriguez | ac0bb76 | 2010-06-12 00:33:42 -0400 | [diff] [blame] | 519 | * |
| 520 | * @ani_reset: reset ANI parameters to default values |
| 521 | * @ani_lower_immunity: lower the noise immunity level. The level controls |
| 522 | * the power-based packet detection on hardware. If a power jump is |
| 523 | * detected the adapter takes it as an indication that a packet has |
| 524 | * arrived. The level ranges from 0-5. Each level corresponds to a |
| 525 | * few dB more of noise immunity. If you have a strong time-varying |
| 526 | * interference that is causing false detections (OFDM timing errors or |
| 527 | * CCK timing errors) the level can be increased. |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 528 | * @ani_cache_ini_regs: cache the values for ANI from the initial |
| 529 | * register settings through the register initialization. |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 530 | */ |
| 531 | struct ath_hw_private_ops { |
Luis R. Rodriguez | 795f5e2 | 2010-04-15 17:39:00 -0400 | [diff] [blame] | 532 | /* Calibration ops */ |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 533 | void (*init_cal_settings)(struct ath_hw *ah); |
Luis R. Rodriguez | 795f5e2 | 2010-04-15 17:39:00 -0400 | [diff] [blame] | 534 | bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan); |
| 535 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 536 | void (*init_mode_regs)(struct ath_hw *ah); |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 537 | void (*init_mode_gain_regs)(struct ath_hw *ah); |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 538 | bool (*macversion_supported)(u32 macversion); |
Luis R. Rodriguez | 795f5e2 | 2010-04-15 17:39:00 -0400 | [diff] [blame] | 539 | void (*setup_calibration)(struct ath_hw *ah, |
| 540 | struct ath9k_cal_list *currCal); |
| 541 | bool (*iscal_supported)(struct ath_hw *ah, |
| 542 | enum ath9k_cal_types calType); |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 543 | |
| 544 | /* PHY ops */ |
| 545 | int (*rf_set_freq)(struct ath_hw *ah, |
| 546 | struct ath9k_channel *chan); |
| 547 | void (*spur_mitigate_freq)(struct ath_hw *ah, |
| 548 | struct ath9k_channel *chan); |
| 549 | int (*rf_alloc_ext_banks)(struct ath_hw *ah); |
| 550 | void (*rf_free_ext_banks)(struct ath_hw *ah); |
| 551 | bool (*set_rf_regs)(struct ath_hw *ah, |
| 552 | struct ath9k_channel *chan, |
| 553 | u16 modesIndex); |
| 554 | void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan); |
| 555 | void (*init_bb)(struct ath_hw *ah, |
| 556 | struct ath9k_channel *chan); |
| 557 | int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan); |
| 558 | void (*olc_init)(struct ath_hw *ah); |
| 559 | void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan); |
| 560 | void (*mark_phy_inactive)(struct ath_hw *ah); |
| 561 | void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); |
| 562 | bool (*rfbus_req)(struct ath_hw *ah); |
| 563 | void (*rfbus_done)(struct ath_hw *ah); |
| 564 | void (*enable_rfkill)(struct ath_hw *ah); |
| 565 | void (*restore_chainmask)(struct ath_hw *ah); |
| 566 | void (*set_diversity)(struct ath_hw *ah, bool value); |
Luis R. Rodriguez | 6477396 | 2010-04-15 17:38:17 -0400 | [diff] [blame] | 567 | u32 (*compute_pll_control)(struct ath_hw *ah, |
| 568 | struct ath9k_channel *chan); |
Felix Fietkau | c16fcb4 | 2010-04-15 17:38:39 -0400 | [diff] [blame] | 569 | bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, |
| 570 | int param); |
Felix Fietkau | 641d992 | 2010-04-15 17:38:49 -0400 | [diff] [blame] | 571 | void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); |
Luis R. Rodriguez | ac0bb76 | 2010-06-12 00:33:42 -0400 | [diff] [blame] | 572 | |
| 573 | /* ANI */ |
Luis R. Rodriguez | 40346b6 | 2010-06-12 00:33:44 -0400 | [diff] [blame] | 574 | void (*ani_reset)(struct ath_hw *ah, bool is_scanning); |
Luis R. Rodriguez | ac0bb76 | 2010-06-12 00:33:42 -0400 | [diff] [blame] | 575 | void (*ani_lower_immunity)(struct ath_hw *ah); |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 576 | void (*ani_cache_ini_regs)(struct ath_hw *ah); |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 577 | }; |
| 578 | |
| 579 | /** |
| 580 | * struct ath_hw_ops - callbacks used by hardware code and driver code |
| 581 | * |
| 582 | * This structure contains callbacks designed to to be used internally by |
| 583 | * hardware code and also by the lower level driver. |
| 584 | * |
| 585 | * @config_pci_powersave: |
Luis R. Rodriguez | 795f5e2 | 2010-04-15 17:39:00 -0400 | [diff] [blame] | 586 | * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC |
Luis R. Rodriguez | ac0bb76 | 2010-06-12 00:33:42 -0400 | [diff] [blame] | 587 | * |
| 588 | * @ani_proc_mib_event: process MIB events, this would happen upon specific ANI |
| 589 | * thresholds being reached or having overflowed. |
| 590 | * @ani_monitor: called periodically by the core driver to collect |
| 591 | * MIB stats and adjust ANI if specific thresholds have been reached. |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 592 | */ |
| 593 | struct ath_hw_ops { |
| 594 | void (*config_pci_powersave)(struct ath_hw *ah, |
| 595 | int restore, |
| 596 | int power_off); |
Vasanthakumar Thiagarajan | cee1f62 | 2010-04-15 17:38:26 -0400 | [diff] [blame] | 597 | void (*rx_enable)(struct ath_hw *ah); |
Vasanthakumar Thiagarajan | 87d5efb | 2010-04-15 17:38:43 -0400 | [diff] [blame] | 598 | void (*set_desc_link)(void *ds, u32 link); |
| 599 | void (*get_desc_link)(void *ds, u32 **link); |
Luis R. Rodriguez | 795f5e2 | 2010-04-15 17:39:00 -0400 | [diff] [blame] | 600 | bool (*calibrate)(struct ath_hw *ah, |
| 601 | struct ath9k_channel *chan, |
| 602 | u8 rxchainmask, |
| 603 | bool longcal); |
Vasanthakumar Thiagarajan | 55e82df | 2010-04-15 17:39:06 -0400 | [diff] [blame] | 604 | bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked); |
Vasanthakumar Thiagarajan | cc610ac0 | 2010-04-15 17:39:26 -0400 | [diff] [blame] | 605 | void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen, |
| 606 | bool is_firstseg, bool is_is_lastseg, |
| 607 | const void *ds0, dma_addr_t buf_addr, |
| 608 | unsigned int qcu); |
| 609 | int (*proc_txdesc)(struct ath_hw *ah, void *ds, |
| 610 | struct ath_tx_status *ts); |
| 611 | void (*set11n_txdesc)(struct ath_hw *ah, void *ds, |
| 612 | u32 pktLen, enum ath9k_pkt_type type, |
| 613 | u32 txPower, u32 keyIx, |
| 614 | enum ath9k_key_type keyType, |
| 615 | u32 flags); |
| 616 | void (*set11n_ratescenario)(struct ath_hw *ah, void *ds, |
| 617 | void *lastds, |
| 618 | u32 durUpdateEn, u32 rtsctsRate, |
| 619 | u32 rtsctsDuration, |
| 620 | struct ath9k_11n_rate_series series[], |
| 621 | u32 nseries, u32 flags); |
| 622 | void (*set11n_aggr_first)(struct ath_hw *ah, void *ds, |
| 623 | u32 aggrLen); |
| 624 | void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds, |
| 625 | u32 numDelims); |
| 626 | void (*set11n_aggr_last)(struct ath_hw *ah, void *ds); |
| 627 | void (*clr11n_aggr)(struct ath_hw *ah, void *ds); |
| 628 | void (*set11n_burstduration)(struct ath_hw *ah, void *ds, |
| 629 | u32 burstDuration); |
| 630 | void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds, |
| 631 | u32 vmf); |
Luis R. Rodriguez | ac0bb76 | 2010-06-12 00:33:42 -0400 | [diff] [blame] | 632 | |
| 633 | void (*ani_proc_mib_event)(struct ath_hw *ah); |
| 634 | void (*ani_monitor)(struct ath_hw *ah, struct ath9k_channel *chan); |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 635 | }; |
| 636 | |
Felix Fietkau | f2552e2 | 2010-07-02 00:09:50 +0200 | [diff] [blame] | 637 | struct ath_nf_limits { |
| 638 | s16 max; |
| 639 | s16 min; |
| 640 | s16 nominal; |
| 641 | }; |
| 642 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 643 | struct ath_hw { |
Luis R. Rodriguez | b002a4a | 2009-09-13 00:03:27 -0700 | [diff] [blame] | 644 | struct ieee80211_hw *hw; |
Luis R. Rodriguez | 27c51f1 | 2009-09-10 11:08:14 -0700 | [diff] [blame] | 645 | struct ath_common common; |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 646 | struct ath9k_hw_version hw_version; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 647 | struct ath9k_ops_config config; |
| 648 | struct ath9k_hw_capabilities caps; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 649 | struct ath9k_channel channels[38]; |
| 650 | struct ath9k_channel *curchan; |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 651 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 652 | union { |
| 653 | struct ar5416_eeprom_def def; |
| 654 | struct ar5416_eeprom_4k map4k; |
Luis R. Rodriguez | 475f598 | 2009-08-03 17:31:25 -0400 | [diff] [blame] | 655 | struct ar9287_eeprom map9287; |
Senthil Balasubramanian | 15c9ee7 | 2010-04-15 17:39:14 -0400 | [diff] [blame] | 656 | struct ar9300_eeprom ar9300_eep; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 657 | } eeprom; |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 658 | const struct eeprom_ops *eep_ops; |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 659 | |
| 660 | bool sw_mgmt_crypto; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 661 | bool is_pciexpress; |
Pavel Roskin | 2eb46d9 | 2010-04-07 01:33:33 -0400 | [diff] [blame] | 662 | bool need_an_top2_fixup; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 663 | u16 tx_trig_level; |
Felix Fietkau | f2552e2 | 2010-07-02 00:09:50 +0200 | [diff] [blame] | 664 | |
Felix Fietkau | bbacee1 | 2010-07-11 15:44:42 +0200 | [diff] [blame] | 665 | u32 nf_regs[6]; |
Felix Fietkau | f2552e2 | 2010-07-02 00:09:50 +0200 | [diff] [blame] | 666 | struct ath_nf_limits nf_2g; |
| 667 | struct ath_nf_limits nf_5g; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 668 | u16 rfsilent; |
| 669 | u32 rfkill_gpio; |
| 670 | u32 rfkill_polarity; |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 671 | u32 ah_flags; |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 672 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 673 | bool htc_reset_init; |
| 674 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 675 | enum nl80211_iftype opmode; |
| 676 | enum ath9k_power_mode power_mode; |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 677 | |
Felix Fietkau | 20bd2a0 | 2010-07-31 00:12:00 +0200 | [diff] [blame] | 678 | struct ath9k_hw_cal_data *caldata; |
Sujith | a13883b | 2009-08-26 08:39:40 +0530 | [diff] [blame] | 679 | struct ath9k_pacal_info pacal_info; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 680 | struct ar5416Stats stats; |
| 681 | struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; |
Sujith | 6a2b9e8 | 2008-08-11 14:04:32 +0530 | [diff] [blame] | 682 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 683 | int16_t curchan_rad_index; |
Pavel Roskin | 3069168 | 2010-03-31 18:05:31 -0400 | [diff] [blame] | 684 | enum ath9k_int imask; |
Pavel Roskin | 74bad5c | 2010-02-23 18:15:27 -0500 | [diff] [blame] | 685 | u32 imrs2_reg; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 686 | u32 txok_interrupt_mask; |
| 687 | u32 txerr_interrupt_mask; |
| 688 | u32 txdesc_interrupt_mask; |
| 689 | u32 txeol_interrupt_mask; |
| 690 | u32 txurn_interrupt_mask; |
| 691 | bool chip_fullsleep; |
| 692 | u32 atim_window; |
Sujith | 6a2b9e8 | 2008-08-11 14:04:32 +0530 | [diff] [blame] | 693 | |
| 694 | /* Calibration */ |
Sujith | cbfe946 | 2009-04-13 21:56:56 +0530 | [diff] [blame] | 695 | enum ath9k_cal_types supp_cals; |
| 696 | struct ath9k_cal_list iq_caldata; |
| 697 | struct ath9k_cal_list adcgain_caldata; |
| 698 | struct ath9k_cal_list adcdc_calinitdata; |
| 699 | struct ath9k_cal_list adcdc_caldata; |
Luis R. Rodriguez | df23aca | 2010-04-15 17:39:11 -0400 | [diff] [blame] | 700 | struct ath9k_cal_list tempCompCalData; |
Sujith | cbfe946 | 2009-04-13 21:56:56 +0530 | [diff] [blame] | 701 | struct ath9k_cal_list *cal_list; |
| 702 | struct ath9k_cal_list *cal_list_last; |
| 703 | struct ath9k_cal_list *cal_list_curr; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 704 | #define totalPowerMeasI meas0.unsign |
| 705 | #define totalPowerMeasQ meas1.unsign |
| 706 | #define totalIqCorrMeas meas2.sign |
| 707 | #define totalAdcIOddPhase meas0.unsign |
| 708 | #define totalAdcIEvenPhase meas1.unsign |
| 709 | #define totalAdcQOddPhase meas2.unsign |
| 710 | #define totalAdcQEvenPhase meas3.unsign |
| 711 | #define totalAdcDcOffsetIOddPhase meas0.sign |
| 712 | #define totalAdcDcOffsetIEvenPhase meas1.sign |
| 713 | #define totalAdcDcOffsetQOddPhase meas2.sign |
| 714 | #define totalAdcDcOffsetQEvenPhase meas3.sign |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 715 | union { |
| 716 | u32 unsign[AR5416_MAX_CHAINS]; |
| 717 | int32_t sign[AR5416_MAX_CHAINS]; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 718 | } meas0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 719 | union { |
| 720 | u32 unsign[AR5416_MAX_CHAINS]; |
| 721 | int32_t sign[AR5416_MAX_CHAINS]; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 722 | } meas1; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 723 | union { |
| 724 | u32 unsign[AR5416_MAX_CHAINS]; |
| 725 | int32_t sign[AR5416_MAX_CHAINS]; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 726 | } meas2; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 727 | union { |
| 728 | u32 unsign[AR5416_MAX_CHAINS]; |
| 729 | int32_t sign[AR5416_MAX_CHAINS]; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 730 | } meas3; |
| 731 | u16 cal_samples; |
Sujith | 6a2b9e8 | 2008-08-11 14:04:32 +0530 | [diff] [blame] | 732 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 733 | u32 sta_id1_defaults; |
| 734 | u32 misc_mode; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 735 | enum { |
| 736 | AUTO_32KHZ, |
| 737 | USE_32KHZ, |
| 738 | DONT_USE_32KHZ, |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 739 | } enable_32kHz_clock; |
Sujith | 6a2b9e8 | 2008-08-11 14:04:32 +0530 | [diff] [blame] | 740 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 741 | /* Private to hardware code */ |
| 742 | struct ath_hw_private_ops private_ops; |
| 743 | /* Accessed by the lower level driver */ |
| 744 | struct ath_hw_ops ops; |
| 745 | |
Luis R. Rodriguez | e68a060 | 2009-10-19 02:33:41 -0400 | [diff] [blame] | 746 | /* Used to program the radio on non single-chip devices */ |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 747 | u32 *analogBank0Data; |
| 748 | u32 *analogBank1Data; |
| 749 | u32 *analogBank2Data; |
| 750 | u32 *analogBank3Data; |
| 751 | u32 *analogBank6Data; |
| 752 | u32 *analogBank6TPCData; |
| 753 | u32 *analogBank7Data; |
| 754 | u32 *addac5416_21; |
| 755 | u32 *bank6Temp; |
Sujith | 6a2b9e8 | 2008-08-11 14:04:32 +0530 | [diff] [blame] | 756 | |
Felix Fietkau | 597a94b | 2010-04-26 15:04:37 -0400 | [diff] [blame] | 757 | u8 txpower_limit; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 758 | int16_t txpower_indexoffset; |
Felix Fietkau | e239d85 | 2010-01-15 02:34:58 +0100 | [diff] [blame] | 759 | int coverage_class; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 760 | u32 beacon_interval; |
| 761 | u32 slottime; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 762 | u32 globaltxtimeout; |
Sujith | 6a2b9e8 | 2008-08-11 14:04:32 +0530 | [diff] [blame] | 763 | |
| 764 | /* ANI */ |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 765 | u32 proc_phyerr; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 766 | u32 aniperiod; |
| 767 | struct ar5416AniState *curani; |
| 768 | struct ar5416AniState ani[255]; |
| 769 | int totalSizeDesired[5]; |
| 770 | int coarse_high[5]; |
| 771 | int coarse_low[5]; |
| 772 | int firpwr[5]; |
| 773 | enum ath9k_ani_cmd ani_function; |
Sujith | 6a2b9e8 | 2008-08-11 14:04:32 +0530 | [diff] [blame] | 774 | |
Luis R. Rodriguez | af03abe | 2009-09-09 02:33:11 -0700 | [diff] [blame] | 775 | /* Bluetooth coexistance */ |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 776 | struct ath_btcoex_hw btcoex_hw; |
Luis R. Rodriguez | af03abe | 2009-09-09 02:33:11 -0700 | [diff] [blame] | 777 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 778 | u32 intr_txqs; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 779 | u8 txchainmask; |
| 780 | u8 rxchainmask; |
Sujith | 6a2b9e8 | 2008-08-11 14:04:32 +0530 | [diff] [blame] | 781 | |
Senthil Balasubramanian | 8bd1d07 | 2009-02-12 13:57:03 +0530 | [diff] [blame] | 782 | u32 originalGain[22]; |
| 783 | int initPDADC; |
| 784 | int PDADCdelta; |
Vivek Natarajan | 08fc5c1 | 2009-08-14 11:30:52 +0530 | [diff] [blame] | 785 | u8 led_pin; |
Senthil Balasubramanian | 8bd1d07 | 2009-02-12 13:57:03 +0530 | [diff] [blame] | 786 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 787 | struct ar5416IniArray iniModes; |
| 788 | struct ar5416IniArray iniCommon; |
| 789 | struct ar5416IniArray iniBank0; |
| 790 | struct ar5416IniArray iniBB_RfGain; |
| 791 | struct ar5416IniArray iniBank1; |
| 792 | struct ar5416IniArray iniBank2; |
| 793 | struct ar5416IniArray iniBank3; |
| 794 | struct ar5416IniArray iniBank6; |
| 795 | struct ar5416IniArray iniBank6TPC; |
| 796 | struct ar5416IniArray iniBank7; |
| 797 | struct ar5416IniArray iniAddac; |
| 798 | struct ar5416IniArray iniPcieSerdes; |
Luis R. Rodriguez | 13ce3e9 | 2010-04-15 17:38:37 -0400 | [diff] [blame] | 799 | struct ar5416IniArray iniPcieSerdesLowPower; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 800 | struct ar5416IniArray iniModesAdditional; |
| 801 | struct ar5416IniArray iniModesRxGain; |
| 802 | struct ar5416IniArray iniModesTxGain; |
Luis R. Rodriguez | 8564328 | 2009-10-19 02:33:33 -0400 | [diff] [blame] | 803 | struct ar5416IniArray iniModes_9271_1_0_only; |
Sujith | 193cd45 | 2009-09-18 15:04:07 +0530 | [diff] [blame] | 804 | struct ar5416IniArray iniCckfirNormal; |
| 805 | struct ar5416IniArray iniCckfirJapan2484; |
Sujith | 70807e9 | 2010-03-17 14:25:14 +0530 | [diff] [blame] | 806 | struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271; |
| 807 | struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271; |
| 808 | struct ar5416IniArray iniModes_9271_ANI_reg; |
| 809 | struct ar5416IniArray iniModes_high_power_tx_gain_9271; |
| 810 | struct ar5416IniArray iniModes_normal_power_tx_gain_9271; |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 811 | |
Luis R. Rodriguez | 13ce3e9 | 2010-04-15 17:38:37 -0400 | [diff] [blame] | 812 | struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; |
| 813 | struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; |
| 814 | struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]; |
| 815 | struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]; |
| 816 | |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 817 | u32 intr_gen_timer_trigger; |
| 818 | u32 intr_gen_timer_thresh; |
| 819 | struct ath_gen_timer_table hw_gen_timers; |
Vasanthakumar Thiagarajan | 744d402 | 2010-04-15 17:39:27 -0400 | [diff] [blame] | 820 | |
| 821 | struct ar9003_txs *ts_ring; |
| 822 | void *ts_start; |
| 823 | u32 ts_paddr_start; |
| 824 | u32 ts_paddr_end; |
| 825 | u16 ts_tail; |
| 826 | u8 ts_size; |
Luis R. Rodriguez | aea702b | 2010-05-13 13:33:43 -0400 | [diff] [blame] | 827 | |
| 828 | u32 bb_watchdog_last_status; |
| 829 | u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */ |
Felix Fietkau | 717f6be | 2010-06-12 00:34:00 -0400 | [diff] [blame] | 830 | |
| 831 | u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES]; |
| 832 | u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES]; |
Luis R. Rodriguez | 9a658d2 | 2010-06-21 18:38:47 -0400 | [diff] [blame] | 833 | /* |
| 834 | * Store the permanent value of Reg 0x4004in WARegVal |
| 835 | * so we dont have to R/M/W. We should not be reading |
| 836 | * this register when in sleep states. |
| 837 | */ |
| 838 | u32 WARegVal; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 839 | }; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 840 | |
Luis R. Rodriguez | 9e4bffd | 2009-09-10 16:11:21 -0700 | [diff] [blame] | 841 | static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) |
| 842 | { |
| 843 | return &ah->common; |
| 844 | } |
| 845 | |
| 846 | static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) |
| 847 | { |
| 848 | return &(ath9k_hw_common(ah)->regulatory); |
| 849 | } |
| 850 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 851 | static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) |
| 852 | { |
| 853 | return &ah->private_ops; |
| 854 | } |
| 855 | |
| 856 | static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) |
| 857 | { |
| 858 | return &ah->ops; |
| 859 | } |
| 860 | |
Felix Fietkau | 54bd500 | 2010-07-02 00:09:51 +0200 | [diff] [blame] | 861 | static inline int sign_extend(int val, const int nbits) |
| 862 | { |
| 863 | int order = BIT(nbits-1); |
| 864 | return (val ^ order) - order; |
| 865 | } |
| 866 | |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 867 | /* Initialization, Detach, Reset */ |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 868 | const char *ath9k_hw_probe(u16 vendorid, u16 devid); |
Sujith | 285f2dd | 2010-01-08 10:36:07 +0530 | [diff] [blame] | 869 | void ath9k_hw_deinit(struct ath_hw *ah); |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 870 | int ath9k_hw_init(struct ath_hw *ah); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 871 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
Felix Fietkau | 20bd2a0 | 2010-07-31 00:12:00 +0200 | [diff] [blame] | 872 | struct ath9k_hw_cal_data *caldata, bool bChannelChange); |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 873 | int ath9k_hw_fill_cap_info(struct ath_hw *ah); |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 874 | u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 875 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 876 | /* Key Cache Management */ |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 877 | bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 878 | bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 879 | const struct ath9k_keyval *k, |
Jouni Malinen | e0caf9e | 2009-03-02 18:15:53 +0200 | [diff] [blame] | 880 | const u8 *mac); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 881 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 882 | /* GPIO / RFKILL / Antennae */ |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 883 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); |
| 884 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); |
| 885 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 886 | u32 ah_signal_type); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 887 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 888 | u32 ath9k_hw_getdefantenna(struct ath_hw *ah); |
| 889 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 890 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 891 | /* General Operation */ |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 892 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 893 | u32 ath9k_hw_reverse_bits(u32 val, u32 n); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 894 | bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high); |
Luis R. Rodriguez | 4f0fc7c | 2009-05-06 02:20:00 -0400 | [diff] [blame] | 895 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
Felix Fietkau | 545750d | 2009-11-23 22:21:01 +0100 | [diff] [blame] | 896 | u8 phy, int kbps, |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 897 | u32 frameLen, u16 rateix, bool shortPreamble); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 898 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 899 | struct ath9k_channel *chan, |
| 900 | struct chan_centers *centers); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 901 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah); |
| 902 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); |
| 903 | bool ath9k_hw_phy_disable(struct ath_hw *ah); |
| 904 | bool ath9k_hw_disable(struct ath_hw *ah); |
Vasanthakumar Thiagarajan | 8fbff4b | 2009-05-08 17:54:51 -0700 | [diff] [blame] | 905 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 906 | void ath9k_hw_setopmode(struct ath_hw *ah); |
| 907 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); |
Luis R. Rodriguez | f2b2143 | 2009-09-10 08:50:20 -0700 | [diff] [blame] | 908 | void ath9k_hw_setbssidmask(struct ath_hw *ah); |
| 909 | void ath9k_hw_write_associd(struct ath_hw *ah); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 910 | u64 ath9k_hw_gettsf64(struct ath_hw *ah); |
| 911 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); |
| 912 | void ath9k_hw_reset_tsf(struct ath_hw *ah); |
Sujith | 54e4cec | 2009-08-07 09:45:09 +0530 | [diff] [blame] | 913 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 914 | void ath9k_hw_init_global_settings(struct ath_hw *ah); |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 915 | void ath9k_hw_set11nmac2040(struct ath_hw *ah); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 916 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); |
| 917 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 918 | const struct ath9k_beacon_state *bs); |
Felix Fietkau | c9c99e5 | 2010-04-19 19:57:29 +0200 | [diff] [blame] | 919 | bool ath9k_hw_check_alive(struct ath_hw *ah); |
Luis R. Rodriguez | a91d75a | 2009-09-09 20:29:18 -0700 | [diff] [blame] | 920 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 921 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); |
Luis R. Rodriguez | a91d75a | 2009-09-09 20:29:18 -0700 | [diff] [blame] | 922 | |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 923 | /* Generic hw timer primitives */ |
| 924 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, |
| 925 | void (*trigger)(void *), |
| 926 | void (*overflow)(void *), |
| 927 | void *arg, |
| 928 | u8 timer_index); |
Luis R. Rodriguez | cd9bf68 | 2009-09-13 02:08:34 -0700 | [diff] [blame] | 929 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
| 930 | struct ath_gen_timer *timer, |
| 931 | u32 timer_next, |
| 932 | u32 timer_period); |
| 933 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); |
| 934 | |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 935 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); |
| 936 | void ath_gen_timer_isr(struct ath_hw *hw); |
Vasanthakumar Thiagarajan | 1773912 | 2009-08-26 21:08:50 +0530 | [diff] [blame] | 937 | u32 ath9k_hw_gettsf32(struct ath_hw *ah); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 938 | |
Luis R. Rodriguez | f934c4d | 2009-10-27 12:59:34 -0400 | [diff] [blame] | 939 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 940 | |
Sujith | 05020d2 | 2010-03-17 14:25:23 +0530 | [diff] [blame] | 941 | /* HTC */ |
| 942 | void ath9k_hw_htc_resetinit(struct ath_hw *ah); |
| 943 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 944 | /* PHY */ |
| 945 | void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, |
| 946 | u32 *coef_mantissa, u32 *coef_exponent); |
| 947 | |
Luis R. Rodriguez | ebd5a14 | 2010-04-15 17:39:18 -0400 | [diff] [blame] | 948 | /* |
| 949 | * Code Specific to AR5008, AR9001 or AR9002, |
| 950 | * we stuff these here to avoid callbacks for AR9003. |
| 951 | */ |
Luis R. Rodriguez | d8f492b | 2010-04-15 17:39:04 -0400 | [diff] [blame] | 952 | void ar9002_hw_cck_chan14_spread(struct ath_hw *ah); |
Luis R. Rodriguez | ebd5a14 | 2010-04-15 17:39:18 -0400 | [diff] [blame] | 953 | int ar9002_hw_rf_claim(struct ath_hw *ah); |
Luis R. Rodriguez | 78ec267 | 2010-04-15 17:39:23 -0400 | [diff] [blame] | 954 | void ar9002_hw_enable_async_fifo(struct ath_hw *ah); |
Sujith | e9141f7 | 2010-06-01 15:14:10 +0530 | [diff] [blame] | 955 | void ar9002_hw_update_async_fifo(struct ath_hw *ah); |
Luis R. Rodriguez | 6c94fdc | 2010-04-15 17:39:24 -0400 | [diff] [blame] | 956 | void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah); |
Luis R. Rodriguez | d8f492b | 2010-04-15 17:39:04 -0400 | [diff] [blame] | 957 | |
Felix Fietkau | 641d992 | 2010-04-15 17:38:49 -0400 | [diff] [blame] | 958 | /* |
Luis R. Rodriguez | aea702b | 2010-05-13 13:33:43 -0400 | [diff] [blame] | 959 | * Code specific to AR9003, we stuff these here to avoid callbacks |
Felix Fietkau | 641d992 | 2010-04-15 17:38:49 -0400 | [diff] [blame] | 960 | * for older families |
| 961 | */ |
Luis R. Rodriguez | aea702b | 2010-05-13 13:33:43 -0400 | [diff] [blame] | 962 | void ar9003_hw_bb_watchdog_config(struct ath_hw *ah); |
| 963 | void ar9003_hw_bb_watchdog_read(struct ath_hw *ah); |
| 964 | void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah); |
Felix Fietkau | 717f6be | 2010-06-12 00:34:00 -0400 | [diff] [blame] | 965 | void ar9003_paprd_enable(struct ath_hw *ah, bool val); |
| 966 | void ar9003_paprd_populate_single_table(struct ath_hw *ah, |
Felix Fietkau | 20bd2a0 | 2010-07-31 00:12:00 +0200 | [diff] [blame] | 967 | struct ath9k_hw_cal_data *caldata, |
| 968 | int chain); |
| 969 | int ar9003_paprd_create_curve(struct ath_hw *ah, |
| 970 | struct ath9k_hw_cal_data *caldata, int chain); |
Felix Fietkau | 717f6be | 2010-06-12 00:34:00 -0400 | [diff] [blame] | 971 | int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain); |
| 972 | int ar9003_paprd_init_table(struct ath_hw *ah); |
| 973 | bool ar9003_paprd_is_done(struct ath_hw *ah); |
| 974 | void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains); |
Felix Fietkau | 641d992 | 2010-04-15 17:38:49 -0400 | [diff] [blame] | 975 | |
| 976 | /* Hardware family op attach helpers */ |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 977 | void ar5008_hw_attach_phy_ops(struct ath_hw *ah); |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 978 | void ar9002_hw_attach_phy_ops(struct ath_hw *ah); |
| 979 | void ar9003_hw_attach_phy_ops(struct ath_hw *ah); |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 980 | |
Luis R. Rodriguez | 795f5e2 | 2010-04-15 17:39:00 -0400 | [diff] [blame] | 981 | void ar9002_hw_attach_calib_ops(struct ath_hw *ah); |
| 982 | void ar9003_hw_attach_calib_ops(struct ath_hw *ah); |
| 983 | |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 984 | void ar9002_hw_attach_ops(struct ath_hw *ah); |
| 985 | void ar9003_hw_attach_ops(struct ath_hw *ah); |
| 986 | |
Luis R. Rodriguez | ac0bb76 | 2010-06-12 00:33:42 -0400 | [diff] [blame] | 987 | /* |
| 988 | * ANI work can be shared between all families but a next |
| 989 | * generation implementation of ANI will be used only for AR9003 only |
| 990 | * for now as the other families still need to be tested with the same |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 991 | * next generation ANI. Feel free to start testing it though for the |
| 992 | * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani. |
Luis R. Rodriguez | ac0bb76 | 2010-06-12 00:33:42 -0400 | [diff] [blame] | 993 | */ |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 994 | extern int modparam_force_new_ani; |
Luis R. Rodriguez | ac0bb76 | 2010-06-12 00:33:42 -0400 | [diff] [blame] | 995 | void ath9k_hw_attach_ani_ops_old(struct ath_hw *ah); |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 996 | void ath9k_hw_attach_ani_ops_new(struct ath_hw *ah); |
Luis R. Rodriguez | ac0bb76 | 2010-06-12 00:33:42 -0400 | [diff] [blame] | 997 | |
Vasanthakumar Thiagarajan | 7b6840a | 2009-09-07 17:46:49 +0530 | [diff] [blame] | 998 | #define ATH_PCIE_CAP_LINK_CTRL 0x70 |
| 999 | #define ATH_PCIE_CAP_LINK_L0S 1 |
| 1000 | #define ATH_PCIE_CAP_LINK_L1 2 |
| 1001 | |
Luis R. Rodriguez | 7337725 | 2010-06-12 00:33:39 -0400 | [diff] [blame] | 1002 | #define ATH9K_CLOCK_RATE_CCK 22 |
| 1003 | #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 |
| 1004 | #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 |
| 1005 | #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 |
| 1006 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1007 | #endif |