blob: 99ec96769dda899817bf1ee41fd836a4e2bbbc53 [file] [log] [blame]
Juergen Beisertd0f349f2008-07-05 10:02:50 +02001/*
2 * linux/arch/arm/plat-mxc/time.c
3 *
4 * Copyright (C) 2000-2001 Deep Blue Solutions
5 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
6 * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
7 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
21 * MA 02110-1301, USA.
22 */
23
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/clockchips.h>
27#include <linux/clk.h>
Sebastian Andrzej Siewior1119c842014-01-22 12:35:44 +010028#include <linux/delay.h>
Sascha Hauer821dc4d2012-03-09 09:29:27 +010029#include <linux/err.h>
Stephen Boyd38ff87f2013-06-01 23:39:40 -070030#include <linux/sched_clock.h>
Shawn Guo6dd74782015-05-22 13:53:45 +080031#include <linux/slab.h>
Gilles Chanteperdrix876292d2014-04-05 17:57:45 +020032#include <linux/of.h>
33#include <linux/of_address.h>
34#include <linux/of_irq.h>
Shawn Guo0931aff2015-05-15 11:41:39 +080035#include <soc/imx/timer.h>
Juergen Beisertd0f349f2008-07-05 10:02:50 +020036
Sascha Hauer0f3332c2009-12-04 09:34:51 +010037/*
Shenwei Wang65d0a162015-04-29 16:40:27 -050038 * There are 4 versions of the timer hardware on Freescale MXC hardware.
39 * - MX1/MXL
40 * - MX21, MX27.
41 * - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
42 * - MX6DL, MX6SX, MX6Q(rev1.1+)
Sascha Hauer0f3332c2009-12-04 09:34:51 +010043 */
44
Sascha Hauerec996ba2009-02-18 20:58:40 +010045/* defines common for all i.MX */
46#define MXC_TCTL 0x00
Sascha Hauer0f3332c2009-12-04 09:34:51 +010047#define MXC_TCTL_TEN (1 << 0) /* Enable module */
Sascha Hauerec996ba2009-02-18 20:58:40 +010048#define MXC_TPRER 0x04
49
50/* MX1, MX21, MX27 */
51#define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
52#define MX1_2_TCTL_IRQEN (1 << 4)
53#define MX1_2_TCTL_FRR (1 << 8)
54#define MX1_2_TCMP 0x08
55#define MX1_2_TCN 0x10
56#define MX1_2_TSTAT 0x14
57
58/* MX21, MX27 */
59#define MX2_TSTAT_CAPT (1 << 1)
60#define MX2_TSTAT_COMP (1 << 0)
61
Anson Huangbad3db12014-09-11 11:29:42 +080062/* MX31, MX35, MX25, MX5, MX6 */
Amit Kucheria38a66f52010-04-21 21:34:36 +030063#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
64#define V2_TCTL_CLK_IPG (1 << 6)
Richard Zhao1f152b42012-05-15 15:34:40 +080065#define V2_TCTL_CLK_PER (2 << 6)
Anson Huangbad3db12014-09-11 11:29:42 +080066#define V2_TCTL_CLK_OSC_DIV8 (5 << 6)
Amit Kucheria38a66f52010-04-21 21:34:36 +030067#define V2_TCTL_FRR (1 << 9)
Anson Huangbad3db12014-09-11 11:29:42 +080068#define V2_TCTL_24MEN (1 << 10)
69#define V2_TPRER_PRE24M 12
Amit Kucheria38a66f52010-04-21 21:34:36 +030070#define V2_IR 0x0c
71#define V2_TSTAT 0x08
72#define V2_TSTAT_OF1 (1 << 0)
73#define V2_TCN 0x24
74#define V2_TCMP 0x10
Juergen Beisertd0f349f2008-07-05 10:02:50 +020075
Anson Huangbad3db12014-09-11 11:29:42 +080076#define V2_TIMER_RATE_OSC_DIV8 3000000
77
Shawn Guo6dd74782015-05-22 13:53:45 +080078struct imx_timer {
Shawn Guo0931aff2015-05-15 11:41:39 +080079 enum imx_gpt_type type;
Shawn Guo6dd74782015-05-22 13:53:45 +080080 void __iomem *base;
81 int irq;
82 struct clk *clk_per;
83 struct clk *clk_ipg;
Shawn Guo9c8694b2015-05-15 14:24:41 +080084 const struct imx_gpt_data *gpt;
Shawn Guoe510d202015-05-22 16:38:49 +080085 struct clock_event_device ced;
Shawn Guoe510d202015-05-22 16:38:49 +080086 struct irqaction act;
Shawn Guo9c8694b2015-05-15 14:24:41 +080087};
88
89struct imx_gpt_data {
Shawn Guo24f74ad2015-05-22 21:39:55 +080090 int reg_tstat;
91 int reg_tcn;
92 int reg_tcmp;
Shawn Guo9c8694b2015-05-15 14:24:41 +080093 void (*gpt_setup_tctl)(struct imx_timer *imxtm);
Shawn Guodb2ae4b2015-05-22 22:42:55 +080094 void (*gpt_irq_enable)(struct imx_timer *imxtm);
95 void (*gpt_irq_disable)(struct imx_timer *imxtm);
96 void (*gpt_irq_acknowledge)(struct imx_timer *imxtm);
Shawn Guo5ab04752015-05-22 15:51:41 +080097 int (*set_next_event)(unsigned long evt,
98 struct clock_event_device *ced);
Shawn Guo6dd74782015-05-22 13:53:45 +080099};
100
Shawn Guoe510d202015-05-22 16:38:49 +0800101static inline struct imx_timer *to_imx_timer(struct clock_event_device *ced)
102{
103 return container_of(ced, struct imx_timer, ced);
104}
105
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800106static void imx1_gpt_irq_disable(struct imx_timer *imxtm)
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200107{
Sascha Hauerec996ba2009-02-18 20:58:40 +0100108 unsigned int tmp;
109
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800110 tmp = readl_relaxed(imxtm->base + MXC_TCTL);
111 writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
112}
113#define imx21_gpt_irq_disable imx1_gpt_irq_disable
114
115static void imx31_gpt_irq_disable(struct imx_timer *imxtm)
116{
117 writel_relaxed(0, imxtm->base + V2_IR);
118}
119#define imx6dl_gpt_irq_disable imx31_gpt_irq_disable
120
121static void imx1_gpt_irq_enable(struct imx_timer *imxtm)
122{
123 unsigned int tmp;
124
125 tmp = readl_relaxed(imxtm->base + MXC_TCTL);
126 writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
127}
128#define imx21_gpt_irq_enable imx1_gpt_irq_enable
129
130static void imx31_gpt_irq_enable(struct imx_timer *imxtm)
131{
132 writel_relaxed(1<<0, imxtm->base + V2_IR);
133}
134#define imx6dl_gpt_irq_enable imx31_gpt_irq_enable
135
136static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm)
137{
138 writel_relaxed(0, imxtm->base + MX1_2_TSTAT);
Sascha Hauerec996ba2009-02-18 20:58:40 +0100139}
140
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800141static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm)
Sascha Hauerec996ba2009-02-18 20:58:40 +0100142{
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800143 writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
Shawn Guo89955522015-05-22 22:23:28 +0800144 imxtm->base + MX1_2_TSTAT);
Sascha Hauerec996ba2009-02-18 20:58:40 +0100145}
146
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800147static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm)
148{
149 writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT);
150}
151#define imx6dl_gpt_irq_acknowledge imx31_gpt_irq_acknowledge
152
Russell King234b6ced2011-05-08 14:09:47 +0100153static void __iomem *sched_clock_reg;
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200154
Stephen Boydb93767e2013-11-15 15:26:12 -0800155static u64 notrace mxc_read_sched_clock(void)
Jan Weitzelc124bef2011-03-17 13:44:30 +0100156{
Shawn Guoc7770bb2015-05-19 18:47:47 +0800157 return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0;
Jan Weitzelc124bef2011-03-17 13:44:30 +0100158}
159
Sebastian Andrzej Siewior1119c842014-01-22 12:35:44 +0100160static struct delay_timer imx_delay_timer;
161
162static unsigned long imx_read_current_timer(void)
163{
Shawn Guoc7770bb2015-05-19 18:47:47 +0800164 return readl_relaxed(sched_clock_reg);
Sebastian Andrzej Siewior1119c842014-01-22 12:35:44 +0100165}
166
Shawn Guo6dd74782015-05-22 13:53:45 +0800167static int __init mxc_clocksource_init(struct imx_timer *imxtm)
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200168{
Shawn Guo6dd74782015-05-22 13:53:45 +0800169 unsigned int c = clk_get_rate(imxtm->clk_per);
Shawn Guo24f74ad2015-05-22 21:39:55 +0800170 void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn;
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200171
Sebastian Andrzej Siewior1119c842014-01-22 12:35:44 +0100172 imx_delay_timer.read_current_timer = &imx_read_current_timer;
173 imx_delay_timer.freq = c;
174 register_current_timer_delay(&imx_delay_timer);
175
Russell King234b6ced2011-05-08 14:09:47 +0100176 sched_clock_reg = reg;
Sascha Hauerec996ba2009-02-18 20:58:40 +0100177
Stephen Boydb93767e2013-11-15 15:26:12 -0800178 sched_clock_register(mxc_read_sched_clock, 32, c);
Russell King234b6ced2011-05-08 14:09:47 +0100179 return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
180 clocksource_mmio_readl_up);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200181}
182
183/* clock event */
184
Sascha Hauerec996ba2009-02-18 20:58:40 +0100185static int mx1_2_set_next_event(unsigned long evt,
Shawn Guo89955522015-05-22 22:23:28 +0800186 struct clock_event_device *ced)
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200187{
Shawn Guo89955522015-05-22 22:23:28 +0800188 struct imx_timer *imxtm = to_imx_timer(ced);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200189 unsigned long tcmp;
190
Shawn Guo89955522015-05-22 22:23:28 +0800191 tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt;
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200192
Shawn Guo89955522015-05-22 22:23:28 +0800193 writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP);
Sascha Hauerec996ba2009-02-18 20:58:40 +0100194
Shawn Guo89955522015-05-22 22:23:28 +0800195 return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ?
Sascha Hauerec996ba2009-02-18 20:58:40 +0100196 -ETIME : 0;
197}
198
Amit Kucheria38a66f52010-04-21 21:34:36 +0300199static int v2_set_next_event(unsigned long evt,
Shawn Guo89955522015-05-22 22:23:28 +0800200 struct clock_event_device *ced)
Sascha Hauerec996ba2009-02-18 20:58:40 +0100201{
Shawn Guo89955522015-05-22 22:23:28 +0800202 struct imx_timer *imxtm = to_imx_timer(ced);
Sascha Hauerec996ba2009-02-18 20:58:40 +0100203 unsigned long tcmp;
204
Shawn Guo89955522015-05-22 22:23:28 +0800205 tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt;
Sascha Hauerec996ba2009-02-18 20:58:40 +0100206
Shawn Guo89955522015-05-22 22:23:28 +0800207 writel_relaxed(tcmp, imxtm->base + V2_TCMP);
Sascha Hauerec996ba2009-02-18 20:58:40 +0100208
Shawn Guoeea8e322012-12-06 22:54:41 +0800209 return evt < 0x7fffffff &&
Shawn Guo89955522015-05-22 22:23:28 +0800210 (int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ?
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200211 -ETIME : 0;
212}
213
Viresh Kumar26b91f02015-07-06 15:39:18 +0530214static int mxc_shutdown(struct clock_event_device *ced)
215{
216 struct imx_timer *imxtm = to_imx_timer(ced);
217 unsigned long flags;
218 u32 tcn;
219
220 /*
221 * The timer interrupt generation is disabled at least
222 * for enough time to call mxc_set_next_event()
223 */
224 local_irq_save(flags);
225
226 /* Disable interrupt in GPT module */
227 imxtm->gpt->gpt_irq_disable(imxtm);
228
229 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
230 /* Set event time into far-far future */
231 writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);
232
233 /* Clear pending interrupt */
234 imxtm->gpt->gpt_irq_acknowledge(imxtm);
235
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200236#ifdef DEBUG
Viresh Kumar26b91f02015-07-06 15:39:18 +0530237 printk(KERN_INFO "%s: changing mode\n", __func__);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200238#endif /* DEBUG */
239
Viresh Kumar26b91f02015-07-06 15:39:18 +0530240 local_irq_restore(flags);
241
242 return 0;
243}
244
245static int mxc_set_oneshot(struct clock_event_device *ced)
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200246{
Shawn Guoe510d202015-05-22 16:38:49 +0800247 struct imx_timer *imxtm = to_imx_timer(ced);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200248 unsigned long flags;
249
250 /*
251 * The timer interrupt generation is disabled at least
252 * for enough time to call mxc_set_next_event()
253 */
254 local_irq_save(flags);
255
256 /* Disable interrupt in GPT module */
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800257 imxtm->gpt->gpt_irq_disable(imxtm);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200258
Viresh Kumar26b91f02015-07-06 15:39:18 +0530259 if (!clockevent_state_oneshot(ced)) {
Shawn Guo24f74ad2015-05-22 21:39:55 +0800260 u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200261 /* Set event time into far-far future */
Shawn Guo24f74ad2015-05-22 21:39:55 +0800262 writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);
Sascha Hauerec996ba2009-02-18 20:58:40 +0100263
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200264 /* Clear pending interrupt */
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800265 imxtm->gpt->gpt_irq_acknowledge(imxtm);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200266 }
267
268#ifdef DEBUG
Viresh Kumar26b91f02015-07-06 15:39:18 +0530269 printk(KERN_INFO "%s: changing mode\n", __func__);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200270#endif /* DEBUG */
271
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200272 /*
273 * Do not put overhead of interrupt enable/disable into
274 * mxc_set_next_event(), the core has about 4 minutes
275 * to call mxc_set_next_event() or shutdown clock after
276 * mode switching
277 */
Viresh Kumar26b91f02015-07-06 15:39:18 +0530278 imxtm->gpt->gpt_irq_enable(imxtm);
279 local_irq_restore(flags);
280
281 return 0;
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200282}
283
284/*
285 * IRQ handler for the timer
286 */
287static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
288{
Shawn Guoe510d202015-05-22 16:38:49 +0800289 struct clock_event_device *ced = dev_id;
Shawn Guo24f74ad2015-05-22 21:39:55 +0800290 struct imx_timer *imxtm = to_imx_timer(ced);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200291 uint32_t tstat;
292
Shawn Guo24f74ad2015-05-22 21:39:55 +0800293 tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200294
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800295 imxtm->gpt->gpt_irq_acknowledge(imxtm);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200296
Shawn Guoe510d202015-05-22 16:38:49 +0800297 ced->event_handler(ced);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200298
299 return IRQ_HANDLED;
300}
301
Shawn Guo6dd74782015-05-22 13:53:45 +0800302static int __init mxc_clockevent_init(struct imx_timer *imxtm)
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200303{
Shawn Guoe510d202015-05-22 16:38:49 +0800304 struct clock_event_device *ced = &imxtm->ced;
305 struct irqaction *act = &imxtm->act;
306
Shawn Guoe510d202015-05-22 16:38:49 +0800307 ced->name = "mxc_timer1";
Lucas Stachf1c08c92015-10-14 11:24:17 +0200308 ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
Viresh Kumar26b91f02015-07-06 15:39:18 +0530309 ced->set_state_shutdown = mxc_shutdown;
310 ced->set_state_oneshot = mxc_set_oneshot;
311 ced->tick_resume = mxc_shutdown;
Shawn Guoe510d202015-05-22 16:38:49 +0800312 ced->set_next_event = imxtm->gpt->set_next_event;
313 ced->rating = 200;
314 ced->cpumask = cpumask_of(0);
Lucas Stachf1c08c92015-10-14 11:24:17 +0200315 ced->irq = imxtm->irq;
Shawn Guoe510d202015-05-22 16:38:49 +0800316 clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per),
Shawn Guo838a2ae2013-01-12 11:50:05 +0000317 0xff, 0xfffffffe);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200318
Shawn Guoe510d202015-05-22 16:38:49 +0800319 act->name = "i.MX Timer Tick";
320 act->flags = IRQF_TIMER | IRQF_IRQPOLL;
321 act->handler = mxc_timer_interrupt;
322 act->dev_id = ced;
323
324 return setup_irq(imxtm->irq, act);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200325}
326
Shawn Guo9c8694b2015-05-15 14:24:41 +0800327static void imx1_gpt_setup_tctl(struct imx_timer *imxtm)
328{
329 u32 tctl_val;
330
331 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
332 writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
333}
334#define imx21_gpt_setup_tctl imx1_gpt_setup_tctl
335
336static void imx31_gpt_setup_tctl(struct imx_timer *imxtm)
337{
338 u32 tctl_val;
339
340 tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
341 if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8)
342 tctl_val |= V2_TCTL_CLK_OSC_DIV8;
343 else
344 tctl_val |= V2_TCTL_CLK_PER;
345
346 writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
347}
348
349static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm)
350{
351 u32 tctl_val;
352
353 tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
354 if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) {
355 tctl_val |= V2_TCTL_CLK_OSC_DIV8;
356 /* 24 / 8 = 3 MHz */
357 writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER);
358 tctl_val |= V2_TCTL_24MEN;
359 } else {
360 tctl_val |= V2_TCTL_CLK_PER;
361 }
362
363 writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
364}
365
366static const struct imx_gpt_data imx1_gpt_data = {
Shawn Guo24f74ad2015-05-22 21:39:55 +0800367 .reg_tstat = MX1_2_TSTAT,
368 .reg_tcn = MX1_2_TCN,
369 .reg_tcmp = MX1_2_TCMP,
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800370 .gpt_irq_enable = imx1_gpt_irq_enable,
371 .gpt_irq_disable = imx1_gpt_irq_disable,
372 .gpt_irq_acknowledge = imx1_gpt_irq_acknowledge,
Shawn Guo9c8694b2015-05-15 14:24:41 +0800373 .gpt_setup_tctl = imx1_gpt_setup_tctl,
Shawn Guo5ab04752015-05-22 15:51:41 +0800374 .set_next_event = mx1_2_set_next_event,
Shawn Guo9c8694b2015-05-15 14:24:41 +0800375};
376
377static const struct imx_gpt_data imx21_gpt_data = {
Shawn Guo24f74ad2015-05-22 21:39:55 +0800378 .reg_tstat = MX1_2_TSTAT,
379 .reg_tcn = MX1_2_TCN,
380 .reg_tcmp = MX1_2_TCMP,
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800381 .gpt_irq_enable = imx21_gpt_irq_enable,
382 .gpt_irq_disable = imx21_gpt_irq_disable,
383 .gpt_irq_acknowledge = imx21_gpt_irq_acknowledge,
Shawn Guo9c8694b2015-05-15 14:24:41 +0800384 .gpt_setup_tctl = imx21_gpt_setup_tctl,
Shawn Guo5ab04752015-05-22 15:51:41 +0800385 .set_next_event = mx1_2_set_next_event,
Shawn Guo9c8694b2015-05-15 14:24:41 +0800386};
387
388static const struct imx_gpt_data imx31_gpt_data = {
Shawn Guo24f74ad2015-05-22 21:39:55 +0800389 .reg_tstat = V2_TSTAT,
390 .reg_tcn = V2_TCN,
391 .reg_tcmp = V2_TCMP,
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800392 .gpt_irq_enable = imx31_gpt_irq_enable,
393 .gpt_irq_disable = imx31_gpt_irq_disable,
394 .gpt_irq_acknowledge = imx31_gpt_irq_acknowledge,
Shawn Guo9c8694b2015-05-15 14:24:41 +0800395 .gpt_setup_tctl = imx31_gpt_setup_tctl,
Shawn Guo5ab04752015-05-22 15:51:41 +0800396 .set_next_event = v2_set_next_event,
Shawn Guo9c8694b2015-05-15 14:24:41 +0800397};
398
399static const struct imx_gpt_data imx6dl_gpt_data = {
Shawn Guo24f74ad2015-05-22 21:39:55 +0800400 .reg_tstat = V2_TSTAT,
401 .reg_tcn = V2_TCN,
402 .reg_tcmp = V2_TCMP,
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800403 .gpt_irq_enable = imx6dl_gpt_irq_enable,
404 .gpt_irq_disable = imx6dl_gpt_irq_disable,
405 .gpt_irq_acknowledge = imx6dl_gpt_irq_acknowledge,
Shawn Guo9c8694b2015-05-15 14:24:41 +0800406 .gpt_setup_tctl = imx6dl_gpt_setup_tctl,
Shawn Guo5ab04752015-05-22 15:51:41 +0800407 .set_next_event = v2_set_next_event,
Shawn Guo9c8694b2015-05-15 14:24:41 +0800408};
409
Shawn Guo6dd74782015-05-22 13:53:45 +0800410static void __init _mxc_timer_init(struct imx_timer *imxtm)
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200411{
Shawn Guo9c8694b2015-05-15 14:24:41 +0800412 switch (imxtm->type) {
413 case GPT_TYPE_IMX1:
414 imxtm->gpt = &imx1_gpt_data;
415 break;
416 case GPT_TYPE_IMX21:
417 imxtm->gpt = &imx21_gpt_data;
418 break;
419 case GPT_TYPE_IMX31:
420 imxtm->gpt = &imx31_gpt_data;
421 break;
422 case GPT_TYPE_IMX6DL:
423 imxtm->gpt = &imx6dl_gpt_data;
424 break;
425 default:
426 BUG();
427 }
428
Shawn Guo6dd74782015-05-22 13:53:45 +0800429 if (IS_ERR(imxtm->clk_per)) {
Sascha Hauer2cfb4512012-05-16 12:29:53 +0200430 pr_err("i.MX timer: unable to get clk\n");
431 return;
Sascha Hauer821dc4d2012-03-09 09:29:27 +0100432 }
Sascha Hauerec996ba2009-02-18 20:58:40 +0100433
Shawn Guo6dd74782015-05-22 13:53:45 +0800434 if (!IS_ERR(imxtm->clk_ipg))
435 clk_prepare_enable(imxtm->clk_ipg);
Sascha Hauer2cfb4512012-05-16 12:29:53 +0200436
Shawn Guo6dd74782015-05-22 13:53:45 +0800437 clk_prepare_enable(imxtm->clk_per);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200438
439 /*
440 * Initialise to a known state (all timers off, and timing reset)
441 */
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200442
Shawn Guo6dd74782015-05-22 13:53:45 +0800443 writel_relaxed(0, imxtm->base + MXC_TCTL);
444 writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */
Sascha Hauerec996ba2009-02-18 20:58:40 +0100445
Shawn Guo9c8694b2015-05-15 14:24:41 +0800446 imxtm->gpt->gpt_setup_tctl(imxtm);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200447
448 /* init and register the timer to the framework */
Shawn Guo6dd74782015-05-22 13:53:45 +0800449 mxc_clocksource_init(imxtm);
450 mxc_clockevent_init(imxtm);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200451}
Gilles Chanteperdrix876292d2014-04-05 17:57:45 +0200452
Shawn Guo0931aff2015-05-15 11:41:39 +0800453void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type)
Alexander Shiyanf4696752014-05-27 13:04:46 +0400454{
Shawn Guo6dd74782015-05-22 13:53:45 +0800455 struct imx_timer *imxtm;
Alexander Shiyanf4696752014-05-27 13:04:46 +0400456
Shawn Guo6dd74782015-05-22 13:53:45 +0800457 imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
458 BUG_ON(!imxtm);
Alexander Shiyand7f98912014-05-27 13:04:47 +0400459
Shawn Guo6dd74782015-05-22 13:53:45 +0800460 imxtm->clk_per = clk_get_sys("imx-gpt.0", "per");
461 imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg");
462
463 imxtm->base = ioremap(pbase, SZ_4K);
464 BUG_ON(!imxtm->base);
465
Shawn Guo0931aff2015-05-15 11:41:39 +0800466 imxtm->type = type;
Guenter Roeckbe3b0f92015-08-20 03:27:21 -0700467 imxtm->irq = irq;
Shawn Guo0931aff2015-05-15 11:41:39 +0800468
Shawn Guo6dd74782015-05-22 13:53:45 +0800469 _mxc_timer_init(imxtm);
Alexander Shiyanf4696752014-05-27 13:04:46 +0400470}
471
Shawn Guobef11c82015-05-15 13:38:20 +0800472static void __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type type)
Gilles Chanteperdrix876292d2014-04-05 17:57:45 +0200473{
Shawn Guo6dd74782015-05-22 13:53:45 +0800474 struct imx_timer *imxtm;
475 static int initialized;
Gilles Chanteperdrix876292d2014-04-05 17:57:45 +0200476
Shawn Guo6dd74782015-05-22 13:53:45 +0800477 /* Support one instance only */
478 if (initialized)
Alexander Shiyanfd4959d2014-07-13 09:34:00 +0400479 return;
480
Shawn Guo6dd74782015-05-22 13:53:45 +0800481 imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
482 BUG_ON(!imxtm);
Gilles Chanteperdrix876292d2014-04-05 17:57:45 +0200483
Shawn Guo6dd74782015-05-22 13:53:45 +0800484 imxtm->base = of_iomap(np, 0);
485 WARN_ON(!imxtm->base);
486 imxtm->irq = irq_of_parse_and_map(np, 0);
487
488 imxtm->clk_ipg = of_clk_get_by_name(np, "ipg");
Alexander Shiyanf4696752014-05-27 13:04:46 +0400489
Anson Huangbad3db12014-09-11 11:29:42 +0800490 /* Try osc_per first, and fall back to per otherwise */
Shawn Guo6dd74782015-05-22 13:53:45 +0800491 imxtm->clk_per = of_clk_get_by_name(np, "osc_per");
492 if (IS_ERR(imxtm->clk_per))
493 imxtm->clk_per = of_clk_get_by_name(np, "per");
Anson Huangbad3db12014-09-11 11:29:42 +0800494
Shawn Guobef11c82015-05-15 13:38:20 +0800495 imxtm->type = type;
496
Shawn Guo6dd74782015-05-22 13:53:45 +0800497 _mxc_timer_init(imxtm);
498
499 initialized = 1;
Gilles Chanteperdrix876292d2014-04-05 17:57:45 +0200500}
Shawn Guobef11c82015-05-15 13:38:20 +0800501
502static void __init imx1_timer_init_dt(struct device_node *np)
503{
504 mxc_timer_init_dt(np, GPT_TYPE_IMX1);
505}
506
507static void __init imx21_timer_init_dt(struct device_node *np)
508{
509 mxc_timer_init_dt(np, GPT_TYPE_IMX21);
510}
511
512static void __init imx31_timer_init_dt(struct device_node *np)
513{
514 enum imx_gpt_type type = GPT_TYPE_IMX31;
515
516 /*
517 * We were using the same compatible string for i.MX6Q/D and i.MX6DL/S
518 * GPT device, while they actually have different programming model.
519 * This is a workaround to keep the existing i.MX6DL/S DTBs continue
520 * working with the new kernel.
521 */
522 if (of_machine_is_compatible("fsl,imx6dl"))
523 type = GPT_TYPE_IMX6DL;
524
525 mxc_timer_init_dt(np, type);
526}
527
528static void __init imx6dl_timer_init_dt(struct device_node *np)
529{
530 mxc_timer_init_dt(np, GPT_TYPE_IMX6DL);
531}
532
533CLOCKSOURCE_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
534CLOCKSOURCE_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
Philippe Reynes747d34e2015-06-27 23:11:44 +0200535CLOCKSOURCE_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt);
Shawn Guobef11c82015-05-15 13:38:20 +0800536CLOCKSOURCE_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
537CLOCKSOURCE_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
538CLOCKSOURCE_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
539CLOCKSOURCE_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
540CLOCKSOURCE_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
541CLOCKSOURCE_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
542CLOCKSOURCE_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
543CLOCKSOURCE_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
544CLOCKSOURCE_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);