Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 1 | /* |
Paul Walmsley | 98fa3d8 | 2010-01-26 20:13:13 -0700 | [diff] [blame] | 2 | * OMAP3 powerdomain definitions |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
Paul Walmsley | 98fa3d8 | 2010-01-26 20:13:13 -0700 | [diff] [blame] | 5 | * Copyright (C) 2007-2010 Nokia Corporation |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 6 | * |
| 7 | * Written by Paul Walmsley |
| 8 | * Debugging and integration fixes by Jouni Högander |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
| 14 | |
| 15 | #ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX |
| 16 | #define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX |
| 17 | |
| 18 | /* |
| 19 | * N.B. If powerdomains are added or removed from this file, update |
| 20 | * the array in mach-omap2/powerdomains.h. |
| 21 | */ |
| 22 | |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 23 | #include <plat/powerdomain.h> |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 24 | |
| 25 | #include "prcm-common.h" |
| 26 | #include "prm.h" |
| 27 | #include "prm-regbits-34xx.h" |
| 28 | #include "cm.h" |
| 29 | #include "cm-regbits-34xx.h" |
| 30 | |
| 31 | /* |
| 32 | * 34XX-specific powerdomains, dependencies |
| 33 | */ |
| 34 | |
Paul Walmsley | 98fa3d8 | 2010-01-26 20:13:13 -0700 | [diff] [blame] | 35 | #ifdef CONFIG_ARCH_OMAP3 |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 36 | |
| 37 | /* |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 38 | * Powerdomains |
| 39 | */ |
| 40 | |
| 41 | static struct powerdomain iva2_pwrdm = { |
| 42 | .name = "iva2_pwrdm", |
| 43 | .prcm_offs = OMAP3430_IVA2_MOD, |
| 44 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 45 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 46 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| 47 | .banks = 4, |
| 48 | .pwrsts_mem_ret = { |
| 49 | [0] = PWRSTS_OFF_RET, |
| 50 | [1] = PWRSTS_OFF_RET, |
| 51 | [2] = PWRSTS_OFF_RET, |
| 52 | [3] = PWRSTS_OFF_RET, |
| 53 | }, |
| 54 | .pwrsts_mem_on = { |
| 55 | [0] = PWRDM_POWER_ON, |
| 56 | [1] = PWRDM_POWER_ON, |
| 57 | [2] = PWRSTS_OFF_ON, |
| 58 | [3] = PWRDM_POWER_ON, |
| 59 | }, |
| 60 | }; |
| 61 | |
Paul Walmsley | 98fa3d8 | 2010-01-26 20:13:13 -0700 | [diff] [blame] | 62 | static struct powerdomain mpu_3xxx_pwrdm = { |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 63 | .name = "mpu_pwrdm", |
| 64 | .prcm_offs = MPU_MOD, |
| 65 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 66 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 67 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
Thara Gopinath | 3863c74 | 2009-12-08 16:33:15 -0700 | [diff] [blame] | 68 | .flags = PWRDM_HAS_MPU_QUIRK, |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 69 | .banks = 1, |
| 70 | .pwrsts_mem_ret = { |
| 71 | [0] = PWRSTS_OFF_RET, |
| 72 | }, |
| 73 | .pwrsts_mem_on = { |
| 74 | [0] = PWRSTS_OFF_ON, |
| 75 | }, |
| 76 | }; |
| 77 | |
Anand Gadiyar | 58dcfb3 | 2010-07-14 13:38:49 +0000 | [diff] [blame] | 78 | /* |
| 79 | * The USBTLL Save-and-Restore mechanism is broken on |
| 80 | * 3430s upto ES3.0 and 3630ES1.0. Hence this feature |
| 81 | * needs to be disabled on these chips. |
| 82 | * Refer: 3430 errata ID i459 and 3630 errata ID i579 |
Jean Pihet | 447b8da | 2010-11-17 17:52:11 +0000 | [diff] [blame^] | 83 | * |
| 84 | * Note: setting the SAR flag could help for errata ID i478 |
| 85 | * which applies to 3430 <= ES3.1, but since the SAR feature |
| 86 | * is broken, do not use it. |
Anand Gadiyar | 58dcfb3 | 2010-07-14 13:38:49 +0000 | [diff] [blame] | 87 | */ |
Paul Walmsley | 98fa3d8 | 2010-01-26 20:13:13 -0700 | [diff] [blame] | 88 | static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 89 | .name = "core_pwrdm", |
| 90 | .prcm_offs = CORE_MOD, |
Paul Walmsley | 7eb1afc | 2009-02-05 20:45:28 -0700 | [diff] [blame] | 91 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | |
| 92 | CHIP_IS_OMAP3430ES2 | |
Anand Gadiyar | 58dcfb3 | 2010-07-14 13:38:49 +0000 | [diff] [blame] | 93 | CHIP_IS_OMAP3430ES3_0 | |
| 94 | CHIP_IS_OMAP3630ES1), |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 95 | .pwrsts = PWRSTS_OFF_RET_ON, |
Thara Gopinath | 4133a44 | 2010-02-24 12:05:50 -0700 | [diff] [blame] | 96 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 97 | .banks = 2, |
| 98 | .pwrsts_mem_ret = { |
| 99 | [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ |
| 100 | [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */ |
| 101 | }, |
| 102 | .pwrsts_mem_on = { |
| 103 | [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ |
| 104 | [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ |
| 105 | }, |
| 106 | }; |
| 107 | |
Paul Walmsley | 98fa3d8 | 2010-01-26 20:13:13 -0700 | [diff] [blame] | 108 | static struct powerdomain core_3xxx_es3_1_pwrdm = { |
Paul Walmsley | 7eb1afc | 2009-02-05 20:45:28 -0700 | [diff] [blame] | 109 | .name = "core_pwrdm", |
| 110 | .prcm_offs = CORE_MOD, |
Anand Gadiyar | 58dcfb3 | 2010-07-14 13:38:49 +0000 | [diff] [blame] | 111 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 | |
| 112 | CHIP_GE_OMAP3630ES1_1), |
Paul Walmsley | 7eb1afc | 2009-02-05 20:45:28 -0700 | [diff] [blame] | 113 | .pwrsts = PWRSTS_OFF_RET_ON, |
Thara Gopinath | 4133a44 | 2010-02-24 12:05:50 -0700 | [diff] [blame] | 114 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
Jean Pihet | 447b8da | 2010-11-17 17:52:11 +0000 | [diff] [blame^] | 115 | /* |
| 116 | * Setting the SAR flag for errata ID i478 which applies |
| 117 | * to 3430 <= ES3.1 |
| 118 | */ |
Paul Walmsley | 7eb1afc | 2009-02-05 20:45:28 -0700 | [diff] [blame] | 119 | .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ |
| 120 | .banks = 2, |
| 121 | .pwrsts_mem_ret = { |
| 122 | [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ |
| 123 | [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */ |
| 124 | }, |
| 125 | .pwrsts_mem_on = { |
| 126 | [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ |
| 127 | [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ |
| 128 | }, |
| 129 | }; |
| 130 | |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 131 | static struct powerdomain dss_pwrdm = { |
| 132 | .name = "dss_pwrdm", |
| 133 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 134 | .prcm_offs = OMAP3430_DSS_MOD, |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 135 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 136 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
| 137 | .banks = 1, |
| 138 | .pwrsts_mem_ret = { |
| 139 | [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ |
| 140 | }, |
| 141 | .pwrsts_mem_on = { |
| 142 | [0] = PWRDM_POWER_ON, /* MEMONSTATE */ |
| 143 | }, |
| 144 | }; |
| 145 | |
Paul Walmsley | be48ea7 | 2009-01-27 19:44:28 -0700 | [diff] [blame] | 146 | /* |
| 147 | * Although the 34XX TRM Rev K Table 4-371 notes that retention is a |
| 148 | * possible SGX powerstate, the SGX device itself does not support |
| 149 | * retention. |
| 150 | */ |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 151 | static struct powerdomain sgx_pwrdm = { |
| 152 | .name = "sgx_pwrdm", |
| 153 | .prcm_offs = OMAP3430ES2_SGX_MOD, |
Paul Walmsley | d41ad52 | 2009-02-05 20:45:25 -0700 | [diff] [blame] | 154 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 155 | /* XXX This is accurate for 3430 SGX, but what about GFX? */ |
Paul Walmsley | be48ea7 | 2009-01-27 19:44:28 -0700 | [diff] [blame] | 156 | .pwrsts = PWRSTS_OFF_ON, |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 157 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
| 158 | .banks = 1, |
| 159 | .pwrsts_mem_ret = { |
| 160 | [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ |
| 161 | }, |
| 162 | .pwrsts_mem_on = { |
| 163 | [0] = PWRDM_POWER_ON, /* MEMONSTATE */ |
| 164 | }, |
| 165 | }; |
| 166 | |
| 167 | static struct powerdomain cam_pwrdm = { |
| 168 | .name = "cam_pwrdm", |
| 169 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 170 | .prcm_offs = OMAP3430_CAM_MOD, |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 171 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 172 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
| 173 | .banks = 1, |
| 174 | .pwrsts_mem_ret = { |
| 175 | [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ |
| 176 | }, |
| 177 | .pwrsts_mem_on = { |
| 178 | [0] = PWRDM_POWER_ON, /* MEMONSTATE */ |
| 179 | }, |
| 180 | }; |
| 181 | |
| 182 | static struct powerdomain per_pwrdm = { |
| 183 | .name = "per_pwrdm", |
| 184 | .prcm_offs = OMAP3430_PER_MOD, |
| 185 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 186 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 187 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| 188 | .banks = 1, |
| 189 | .pwrsts_mem_ret = { |
| 190 | [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ |
| 191 | }, |
| 192 | .pwrsts_mem_on = { |
| 193 | [0] = PWRDM_POWER_ON, /* MEMONSTATE */ |
| 194 | }, |
| 195 | }; |
| 196 | |
| 197 | static struct powerdomain emu_pwrdm = { |
| 198 | .name = "emu_pwrdm", |
| 199 | .prcm_offs = OMAP3430_EMU_MOD, |
| 200 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 201 | }; |
| 202 | |
| 203 | static struct powerdomain neon_pwrdm = { |
| 204 | .name = "neon_pwrdm", |
| 205 | .prcm_offs = OMAP3430_NEON_MOD, |
| 206 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 207 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 208 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
| 209 | }; |
| 210 | |
| 211 | static struct powerdomain usbhost_pwrdm = { |
| 212 | .name = "usbhost_pwrdm", |
| 213 | .prcm_offs = OMAP3430ES2_USBHOST_MOD, |
Paul Walmsley | d41ad52 | 2009-02-05 20:45:25 -0700 | [diff] [blame] | 214 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 215 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 216 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
Kalle Jokiniemi | 867d320 | 2009-04-23 13:58:51 +0300 | [diff] [blame] | 217 | /* |
| 218 | * REVISIT: Enabling usb host save and restore mechanism seems to |
| 219 | * leave the usb host domain permanently in ACTIVE mode after |
| 220 | * changing the usb host power domain state from OFF to active once. |
| 221 | * Disabling for now. |
| 222 | */ |
| 223 | /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */ |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 224 | .banks = 1, |
| 225 | .pwrsts_mem_ret = { |
| 226 | [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ |
| 227 | }, |
| 228 | .pwrsts_mem_on = { |
| 229 | [0] = PWRDM_POWER_ON, /* MEMONSTATE */ |
| 230 | }, |
| 231 | }; |
| 232 | |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame] | 233 | static struct powerdomain dpll1_pwrdm = { |
| 234 | .name = "dpll1_pwrdm", |
| 235 | .prcm_offs = MPU_MOD, |
| 236 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 237 | }; |
| 238 | |
| 239 | static struct powerdomain dpll2_pwrdm = { |
| 240 | .name = "dpll2_pwrdm", |
| 241 | .prcm_offs = OMAP3430_IVA2_MOD, |
| 242 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 243 | }; |
| 244 | |
| 245 | static struct powerdomain dpll3_pwrdm = { |
| 246 | .name = "dpll3_pwrdm", |
| 247 | .prcm_offs = PLL_MOD, |
| 248 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 249 | }; |
| 250 | |
| 251 | static struct powerdomain dpll4_pwrdm = { |
| 252 | .name = "dpll4_pwrdm", |
| 253 | .prcm_offs = PLL_MOD, |
| 254 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 255 | }; |
| 256 | |
| 257 | static struct powerdomain dpll5_pwrdm = { |
| 258 | .name = "dpll5_pwrdm", |
| 259 | .prcm_offs = PLL_MOD, |
Paul Walmsley | d41ad52 | 2009-02-05 20:45:25 -0700 | [diff] [blame] | 260 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame] | 261 | }; |
| 262 | |
| 263 | |
Paul Walmsley | 98fa3d8 | 2010-01-26 20:13:13 -0700 | [diff] [blame] | 264 | #endif /* CONFIG_ARCH_OMAP3 */ |
Paul Walmsley | ecb24aa | 2008-08-19 11:08:43 +0300 | [diff] [blame] | 265 | |
| 266 | |
| 267 | #endif |