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Linus Walleijb43d65f2009-06-09 08:11:42 +01001/*
2 * drivers/spi/amba-pl022.c
3 *
4 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
5 *
6 * Copyright (C) 2008-2009 ST-Ericsson AB
7 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
8 *
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 *
11 * Initial version inspired by:
12 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
13 * Initial adoption to PL022 by:
14 * Sachin Verma <sachin.verma@st.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 */
26
27/*
28 * TODO:
29 * - add timeout on polled transfers
Linus Walleijb43d65f2009-06-09 08:11:42 +010030 */
31
32#include <linux/init.h>
33#include <linux/module.h>
34#include <linux/device.h>
35#include <linux/ioport.h>
36#include <linux/errno.h>
37#include <linux/interrupt.h>
38#include <linux/spi/spi.h>
39#include <linux/workqueue.h>
Linus Walleijb43d65f2009-06-09 08:11:42 +010040#include <linux/delay.h>
41#include <linux/clk.h>
42#include <linux/err.h>
43#include <linux/amba/bus.h>
44#include <linux/amba/pl022.h>
45#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090046#include <linux/slab.h>
Linus Walleijb1b6b9a2010-09-29 17:31:35 +090047#include <linux/dmaengine.h>
48#include <linux/dma-mapping.h>
49#include <linux/scatterlist.h>
Linus Walleijb43d65f2009-06-09 08:11:42 +010050
51/*
52 * This macro is used to define some register default values.
53 * reg is masked with mask, the OR:ed with an (again masked)
54 * val shifted sb steps to the left.
55 */
56#define SSP_WRITE_BITS(reg, val, mask, sb) \
57 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
58
59/*
60 * This macro is also used to define some default values.
61 * It will just shift val by sb steps to the left and mask
62 * the result with mask.
63 */
64#define GEN_MASK_BITS(val, mask, sb) \
65 (((val)<<(sb)) & (mask))
66
67#define DRIVE_TX 0
68#define DO_NOT_DRIVE_TX 1
69
70#define DO_NOT_QUEUE_DMA 0
71#define QUEUE_DMA 1
72
73#define RX_TRANSFER 1
74#define TX_TRANSFER 2
75
76/*
77 * Macros to access SSP Registers with their offsets
78 */
79#define SSP_CR0(r) (r + 0x000)
80#define SSP_CR1(r) (r + 0x004)
81#define SSP_DR(r) (r + 0x008)
82#define SSP_SR(r) (r + 0x00C)
83#define SSP_CPSR(r) (r + 0x010)
84#define SSP_IMSC(r) (r + 0x014)
85#define SSP_RIS(r) (r + 0x018)
86#define SSP_MIS(r) (r + 0x01C)
87#define SSP_ICR(r) (r + 0x020)
88#define SSP_DMACR(r) (r + 0x024)
89#define SSP_ITCR(r) (r + 0x080)
90#define SSP_ITIP(r) (r + 0x084)
91#define SSP_ITOP(r) (r + 0x088)
92#define SSP_TDR(r) (r + 0x08C)
93
94#define SSP_PID0(r) (r + 0xFE0)
95#define SSP_PID1(r) (r + 0xFE4)
96#define SSP_PID2(r) (r + 0xFE8)
97#define SSP_PID3(r) (r + 0xFEC)
98
99#define SSP_CID0(r) (r + 0xFF0)
100#define SSP_CID1(r) (r + 0xFF4)
101#define SSP_CID2(r) (r + 0xFF8)
102#define SSP_CID3(r) (r + 0xFFC)
103
104/*
105 * SSP Control Register 0 - SSP_CR0
106 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000107#define SSP_CR0_MASK_DSS (0x0FUL << 0)
108#define SSP_CR0_MASK_FRF (0x3UL << 4)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100109#define SSP_CR0_MASK_SPO (0x1UL << 6)
110#define SSP_CR0_MASK_SPH (0x1UL << 7)
111#define SSP_CR0_MASK_SCR (0xFFUL << 8)
Linus Walleij556f4ae2010-05-05 09:28:15 +0000112
113/*
114 * The ST version of this block moves som bits
115 * in SSP_CR0 and extends it to 32 bits
116 */
117#define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
118#define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
119#define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
120#define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
121
Linus Walleijb43d65f2009-06-09 08:11:42 +0100122
123/*
124 * SSP Control Register 0 - SSP_CR1
125 */
126#define SSP_CR1_MASK_LBM (0x1UL << 0)
127#define SSP_CR1_MASK_SSE (0x1UL << 1)
128#define SSP_CR1_MASK_MS (0x1UL << 2)
129#define SSP_CR1_MASK_SOD (0x1UL << 3)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100130
131/*
Linus Walleij556f4ae2010-05-05 09:28:15 +0000132 * The ST version of this block adds some bits
133 * in SSP_CR1
Linus Walleijb43d65f2009-06-09 08:11:42 +0100134 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000135#define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
136#define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
137#define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
138#define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
139#define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
Linus Walleij781c7b12010-05-07 08:40:53 +0000140/* This one is only in the PL023 variant */
141#define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100142
143/*
144 * SSP Status Register - SSP_SR
145 */
146#define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
147#define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
148#define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000149#define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
Linus Walleijb43d65f2009-06-09 08:11:42 +0100150#define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
151
152/*
153 * SSP Clock Prescale Register - SSP_CPSR
154 */
155#define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
156
157/*
158 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
159 */
160#define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
161#define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */
162#define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */
163#define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */
164
165/*
166 * SSP Raw Interrupt Status Register - SSP_RIS
167 */
168/* Receive Overrun Raw Interrupt status */
169#define SSP_RIS_MASK_RORRIS (0x1UL << 0)
170/* Receive Timeout Raw Interrupt status */
171#define SSP_RIS_MASK_RTRIS (0x1UL << 1)
172/* Receive FIFO Raw Interrupt status */
173#define SSP_RIS_MASK_RXRIS (0x1UL << 2)
174/* Transmit FIFO Raw Interrupt status */
175#define SSP_RIS_MASK_TXRIS (0x1UL << 3)
176
177/*
178 * SSP Masked Interrupt Status Register - SSP_MIS
179 */
180/* Receive Overrun Masked Interrupt status */
181#define SSP_MIS_MASK_RORMIS (0x1UL << 0)
182/* Receive Timeout Masked Interrupt status */
183#define SSP_MIS_MASK_RTMIS (0x1UL << 1)
184/* Receive FIFO Masked Interrupt status */
185#define SSP_MIS_MASK_RXMIS (0x1UL << 2)
186/* Transmit FIFO Masked Interrupt status */
187#define SSP_MIS_MASK_TXMIS (0x1UL << 3)
188
189/*
190 * SSP Interrupt Clear Register - SSP_ICR
191 */
192/* Receive Overrun Raw Clear Interrupt bit */
193#define SSP_ICR_MASK_RORIC (0x1UL << 0)
194/* Receive Timeout Clear Interrupt bit */
195#define SSP_ICR_MASK_RTIC (0x1UL << 1)
196
197/*
198 * SSP DMA Control Register - SSP_DMACR
199 */
200/* Receive DMA Enable bit */
201#define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
202/* Transmit DMA Enable bit */
203#define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
204
205/*
206 * SSP Integration Test control Register - SSP_ITCR
207 */
208#define SSP_ITCR_MASK_ITEN (0x1UL << 0)
209#define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
210
211/*
212 * SSP Integration Test Input Register - SSP_ITIP
213 */
214#define ITIP_MASK_SSPRXD (0x1UL << 0)
215#define ITIP_MASK_SSPFSSIN (0x1UL << 1)
216#define ITIP_MASK_SSPCLKIN (0x1UL << 2)
217#define ITIP_MASK_RXDMAC (0x1UL << 3)
218#define ITIP_MASK_TXDMAC (0x1UL << 4)
219#define ITIP_MASK_SSPTXDIN (0x1UL << 5)
220
221/*
222 * SSP Integration Test output Register - SSP_ITOP
223 */
224#define ITOP_MASK_SSPTXD (0x1UL << 0)
225#define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
226#define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
227#define ITOP_MASK_SSPOEn (0x1UL << 3)
228#define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
229#define ITOP_MASK_RORINTR (0x1UL << 5)
230#define ITOP_MASK_RTINTR (0x1UL << 6)
231#define ITOP_MASK_RXINTR (0x1UL << 7)
232#define ITOP_MASK_TXINTR (0x1UL << 8)
233#define ITOP_MASK_INTR (0x1UL << 9)
234#define ITOP_MASK_RXDMABREQ (0x1UL << 10)
235#define ITOP_MASK_RXDMASREQ (0x1UL << 11)
236#define ITOP_MASK_TXDMABREQ (0x1UL << 12)
237#define ITOP_MASK_TXDMASREQ (0x1UL << 13)
238
239/*
240 * SSP Test Data Register - SSP_TDR
241 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000242#define TDR_MASK_TESTDATA (0xFFFFFFFF)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100243
244/*
245 * Message State
246 * we use the spi_message.state (void *) pointer to
247 * hold a single state value, that's why all this
248 * (void *) casting is done here.
249 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000250#define STATE_START ((void *) 0)
251#define STATE_RUNNING ((void *) 1)
252#define STATE_DONE ((void *) 2)
253#define STATE_ERROR ((void *) -1)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100254
255/*
Linus Walleijb43d65f2009-06-09 08:11:42 +0100256 * SSP State - Whether Enabled or Disabled
257 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000258#define SSP_DISABLED (0)
259#define SSP_ENABLED (1)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100260
261/*
262 * SSP DMA State - Whether DMA Enabled or Disabled
263 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000264#define SSP_DMA_DISABLED (0)
265#define SSP_DMA_ENABLED (1)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100266
267/*
268 * SSP Clock Defaults
269 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000270#define SSP_DEFAULT_CLKRATE 0x2
271#define SSP_DEFAULT_PRESCALE 0x40
Linus Walleijb43d65f2009-06-09 08:11:42 +0100272
273/*
274 * SSP Clock Parameter ranges
275 */
276#define CPSDVR_MIN 0x02
277#define CPSDVR_MAX 0xFE
278#define SCR_MIN 0x00
279#define SCR_MAX 0xFF
280
281/*
282 * SSP Interrupt related Macros
283 */
284#define DEFAULT_SSP_REG_IMSC 0x0UL
285#define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
286#define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)
287
288#define CLEAR_ALL_INTERRUPTS 0x3
289
290
291/*
292 * The type of reading going on on this chip
293 */
294enum ssp_reading {
295 READING_NULL,
296 READING_U8,
297 READING_U16,
298 READING_U32
299};
300
301/**
302 * The type of writing going on on this chip
303 */
304enum ssp_writing {
305 WRITING_NULL,
306 WRITING_U8,
307 WRITING_U16,
308 WRITING_U32
309};
310
311/**
312 * struct vendor_data - vendor-specific config parameters
313 * for PL022 derivates
314 * @fifodepth: depth of FIFOs (both)
315 * @max_bpw: maximum number of bits per word
316 * @unidir: supports unidirection transfers
Linus Walleij556f4ae2010-05-05 09:28:15 +0000317 * @extended_cr: 32 bit wide control register 0 with extra
318 * features and extra features in CR1 as found in the ST variants
Linus Walleij781c7b12010-05-07 08:40:53 +0000319 * @pl023: supports a subset of the ST extensions called "PL023"
Linus Walleijb43d65f2009-06-09 08:11:42 +0100320 */
321struct vendor_data {
322 int fifodepth;
323 int max_bpw;
324 bool unidir;
Linus Walleij556f4ae2010-05-05 09:28:15 +0000325 bool extended_cr;
Linus Walleij781c7b12010-05-07 08:40:53 +0000326 bool pl023;
Philippe Langlais06fb01f2011-03-23 11:05:16 +0100327 bool loopback;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100328};
329
330/**
331 * struct pl022 - This is the private SSP driver data structure
332 * @adev: AMBA device model hookup
Linus Walleij12e8b322011-02-08 13:03:55 +0100333 * @vendor: vendor data for the IP block
334 * @phybase: the physical memory where the SSP device resides
335 * @virtbase: the virtual memory where the SSP is mapped
336 * @clk: outgoing clock "SPICLK" for the SPI bus
Linus Walleijb43d65f2009-06-09 08:11:42 +0100337 * @master: SPI framework hookup
338 * @master_info: controller-specific data from machine setup
Linus Walleijb43d65f2009-06-09 08:11:42 +0100339 * @workqueue: a workqueue on which any spi_message request is queued
Linus Walleij12e8b322011-02-08 13:03:55 +0100340 * @pump_messages: work struct for scheduling work to the workqueue
341 * @queue_lock: spinlock to syncronise access to message queue
342 * @queue: message queue
Linus Walleijb43d65f2009-06-09 08:11:42 +0100343 * @busy: workqueue is busy
Linus Walleij5e8b8212010-12-22 23:13:59 +0100344 * @running: workqueue is running
Linus Walleijb43d65f2009-06-09 08:11:42 +0100345 * @pump_transfers: Tasklet used in Interrupt Transfer mode
346 * @cur_msg: Pointer to current spi_message being processed
347 * @cur_transfer: Pointer to current spi_transfer
348 * @cur_chip: pointer to current clients chip(assigned from controller_state)
349 * @tx: current position in TX buffer to be read
350 * @tx_end: end position in TX buffer to be read
351 * @rx: current position in RX buffer to be written
352 * @rx_end: end position in RX buffer to be written
Linus Walleij12e8b322011-02-08 13:03:55 +0100353 * @read: the type of read currently going on
354 * @write: the type of write currently going on
355 * @exp_fifo_level: expected FIFO level
356 * @dma_rx_channel: optional channel for RX DMA
357 * @dma_tx_channel: optional channel for TX DMA
358 * @sgt_rx: scattertable for the RX transfer
359 * @sgt_tx: scattertable for the TX transfer
360 * @dummypage: a dummy page used for driving data on the bus with DMA
Linus Walleijb43d65f2009-06-09 08:11:42 +0100361 */
362struct pl022 {
363 struct amba_device *adev;
364 struct vendor_data *vendor;
365 resource_size_t phybase;
366 void __iomem *virtbase;
367 struct clk *clk;
368 struct spi_master *master;
369 struct pl022_ssp_controller *master_info;
370 /* Driver message queue */
371 struct workqueue_struct *workqueue;
372 struct work_struct pump_messages;
373 spinlock_t queue_lock;
374 struct list_head queue;
Linus Walleijdec5a582010-12-22 23:13:48 +0100375 bool busy;
Linus Walleij5e8b8212010-12-22 23:13:59 +0100376 bool running;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100377 /* Message transfer pump */
378 struct tasklet_struct pump_transfers;
379 struct spi_message *cur_msg;
380 struct spi_transfer *cur_transfer;
381 struct chip_data *cur_chip;
382 void *tx;
383 void *tx_end;
384 void *rx;
385 void *rx_end;
386 enum ssp_reading read;
387 enum ssp_writing write;
Linus Walleijfc054752010-01-22 13:53:30 +0100388 u32 exp_fifo_level;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900389 /* DMA settings */
390#ifdef CONFIG_DMA_ENGINE
391 struct dma_chan *dma_rx_channel;
392 struct dma_chan *dma_tx_channel;
393 struct sg_table sgt_rx;
394 struct sg_table sgt_tx;
395 char *dummypage;
396#endif
Linus Walleijb43d65f2009-06-09 08:11:42 +0100397};
398
399/**
400 * struct chip_data - To maintain runtime state of SSP for each client chip
Linus Walleij556f4ae2010-05-05 09:28:15 +0000401 * @cr0: Value of control register CR0 of SSP - on later ST variants this
402 * register is 32 bits wide rather than just 16
Linus Walleijb43d65f2009-06-09 08:11:42 +0100403 * @cr1: Value of control register CR1 of SSP
404 * @dmacr: Value of DMA control Register of SSP
405 * @cpsr: Value of Clock prescale register
406 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
407 * @enable_dma: Whether to enable DMA or not
Linus Walleijb43d65f2009-06-09 08:11:42 +0100408 * @read: function ptr to be used to read when doing xfer for this chip
Linus Walleij12e8b322011-02-08 13:03:55 +0100409 * @write: function ptr to be used to write when doing xfer for this chip
Linus Walleijb43d65f2009-06-09 08:11:42 +0100410 * @cs_control: chip select callback provided by chip
411 * @xfer_type: polling/interrupt/DMA
412 *
413 * Runtime state of the SSP controller, maintained per chip,
414 * This would be set according to the current message that would be served
415 */
416struct chip_data {
Linus Walleij556f4ae2010-05-05 09:28:15 +0000417 u32 cr0;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100418 u16 cr1;
419 u16 dmacr;
420 u16 cpsr;
421 u8 n_bytes;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900422 bool enable_dma;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100423 enum ssp_reading read;
424 enum ssp_writing write;
425 void (*cs_control) (u32 command);
426 int xfer_type;
427};
428
429/**
430 * null_cs_control - Dummy chip select function
431 * @command: select/delect the chip
432 *
433 * If no chip select function is provided by client this is used as dummy
434 * chip select
435 */
436static void null_cs_control(u32 command)
437{
438 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
439}
440
441/**
442 * giveback - current spi_message is over, schedule next message and call
443 * callback of this message. Assumes that caller already
444 * set message->status; dma and pio irqs are blocked
445 * @pl022: SSP driver private data structure
446 */
447static void giveback(struct pl022 *pl022)
448{
449 struct spi_transfer *last_transfer;
450 unsigned long flags;
451 struct spi_message *msg;
452 void (*curr_cs_control) (u32 command);
453
454 /*
455 * This local reference to the chip select function
456 * is needed because we set curr_chip to NULL
457 * as a step toward termininating the message.
458 */
459 curr_cs_control = pl022->cur_chip->cs_control;
460 spin_lock_irqsave(&pl022->queue_lock, flags);
461 msg = pl022->cur_msg;
462 pl022->cur_msg = NULL;
463 pl022->cur_transfer = NULL;
464 pl022->cur_chip = NULL;
465 queue_work(pl022->workqueue, &pl022->pump_messages);
466 spin_unlock_irqrestore(&pl022->queue_lock, flags);
467
468 last_transfer = list_entry(msg->transfers.prev,
469 struct spi_transfer,
470 transfer_list);
471
472 /* Delay if requested before any change in chip select */
473 if (last_transfer->delay_usecs)
474 /*
475 * FIXME: This runs in interrupt context.
476 * Is this really smart?
477 */
478 udelay(last_transfer->delay_usecs);
479
480 /*
481 * Drop chip select UNLESS cs_change is true or we are returning
482 * a message with an error, or next message is for another chip
483 */
484 if (!last_transfer->cs_change)
485 curr_cs_control(SSP_CHIP_DESELECT);
486 else {
487 struct spi_message *next_msg;
488
489 /* Holding of cs was hinted, but we need to make sure
490 * the next message is for the same chip. Don't waste
491 * time with the following tests unless this was hinted.
492 *
493 * We cannot postpone this until pump_messages, because
494 * after calling msg->complete (below) the driver that
495 * sent the current message could be unloaded, which
496 * could invalidate the cs_control() callback...
497 */
498
499 /* get a pointer to the next message, if any */
500 spin_lock_irqsave(&pl022->queue_lock, flags);
501 if (list_empty(&pl022->queue))
502 next_msg = NULL;
503 else
504 next_msg = list_entry(pl022->queue.next,
505 struct spi_message, queue);
506 spin_unlock_irqrestore(&pl022->queue_lock, flags);
507
508 /* see if the next and current messages point
509 * to the same chip
510 */
511 if (next_msg && next_msg->spi != msg->spi)
512 next_msg = NULL;
513 if (!next_msg || msg->state == STATE_ERROR)
514 curr_cs_control(SSP_CHIP_DESELECT);
515 }
516 msg->state = NULL;
517 if (msg->complete)
518 msg->complete(msg->context);
Linus Walleij808f1032011-02-08 13:03:32 +0100519 /* This message is completed, so let's turn off the clocks & power */
Linus Walleijb43d65f2009-06-09 08:11:42 +0100520 clk_disable(pl022->clk);
Linus Walleij545074f2010-08-21 11:07:36 +0200521 amba_pclk_disable(pl022->adev);
Linus Walleij808f1032011-02-08 13:03:32 +0100522 amba_vcore_disable(pl022->adev);
Linus Walleijb43d65f2009-06-09 08:11:42 +0100523}
524
525/**
526 * flush - flush the FIFO to reach a clean state
527 * @pl022: SSP driver private data structure
528 */
529static int flush(struct pl022 *pl022)
530{
531 unsigned long limit = loops_per_jiffy << 1;
532
533 dev_dbg(&pl022->adev->dev, "flush\n");
534 do {
535 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
536 readw(SSP_DR(pl022->virtbase));
537 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
Linus Walleijfc054752010-01-22 13:53:30 +0100538
539 pl022->exp_fifo_level = 0;
540
Linus Walleijb43d65f2009-06-09 08:11:42 +0100541 return limit;
542}
543
544/**
545 * restore_state - Load configuration of current chip
546 * @pl022: SSP driver private data structure
547 */
548static void restore_state(struct pl022 *pl022)
549{
550 struct chip_data *chip = pl022->cur_chip;
551
Linus Walleij556f4ae2010-05-05 09:28:15 +0000552 if (pl022->vendor->extended_cr)
553 writel(chip->cr0, SSP_CR0(pl022->virtbase));
554 else
555 writew(chip->cr0, SSP_CR0(pl022->virtbase));
Linus Walleijb43d65f2009-06-09 08:11:42 +0100556 writew(chip->cr1, SSP_CR1(pl022->virtbase));
557 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
558 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
559 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
560 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
561}
562
Linus Walleijb43d65f2009-06-09 08:11:42 +0100563/*
564 * Default SSP Register Values
565 */
566#define DEFAULT_SSP_REG_CR0 ( \
567 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
Linus Walleij556f4ae2010-05-05 09:28:15 +0000568 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
Linus Walleijb43d65f2009-06-09 08:11:42 +0100569 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
Linus Walleijee2b8052009-08-15 15:12:05 +0100570 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
Linus Walleij556f4ae2010-05-05 09:28:15 +0000571 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
572)
573
574/* ST versions have slightly different bit layout */
575#define DEFAULT_SSP_REG_CR0_ST ( \
576 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
577 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
578 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
579 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
580 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
581 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
582 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
Linus Walleijb43d65f2009-06-09 08:11:42 +0100583)
584
Linus Walleij781c7b12010-05-07 08:40:53 +0000585/* The PL023 version is slightly different again */
586#define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
587 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
588 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
589 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
590 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
591)
592
Linus Walleijb43d65f2009-06-09 08:11:42 +0100593#define DEFAULT_SSP_REG_CR1 ( \
594 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
595 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
596 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
Linus Walleij556f4ae2010-05-05 09:28:15 +0000597 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
Linus Walleijb43d65f2009-06-09 08:11:42 +0100598)
599
Linus Walleij556f4ae2010-05-05 09:28:15 +0000600/* ST versions extend this register to use all 16 bits */
601#define DEFAULT_SSP_REG_CR1_ST ( \
602 DEFAULT_SSP_REG_CR1 | \
603 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
604 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
605 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
606 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
607 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
608)
609
Linus Walleij781c7b12010-05-07 08:40:53 +0000610/*
611 * The PL023 variant has further differences: no loopback mode, no microwire
612 * support, and a new clock feedback delay setting.
613 */
614#define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
615 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
616 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
617 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
618 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
619 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
620 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
621 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
622 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
623)
Linus Walleij556f4ae2010-05-05 09:28:15 +0000624
Linus Walleijb43d65f2009-06-09 08:11:42 +0100625#define DEFAULT_SSP_REG_CPSR ( \
Linus Walleij556f4ae2010-05-05 09:28:15 +0000626 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
Linus Walleijb43d65f2009-06-09 08:11:42 +0100627)
628
629#define DEFAULT_SSP_REG_DMACR (\
630 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
631 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
632)
633
Linus Walleij781c7b12010-05-07 08:40:53 +0000634/**
635 * load_ssp_default_config - Load default configuration for SSP
636 * @pl022: SSP driver private data structure
637 */
Linus Walleijb43d65f2009-06-09 08:11:42 +0100638static void load_ssp_default_config(struct pl022 *pl022)
639{
Linus Walleij781c7b12010-05-07 08:40:53 +0000640 if (pl022->vendor->pl023) {
641 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
642 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
643 } else if (pl022->vendor->extended_cr) {
Linus Walleij556f4ae2010-05-05 09:28:15 +0000644 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
645 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
646 } else {
647 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
648 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
649 }
Linus Walleijb43d65f2009-06-09 08:11:42 +0100650 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
651 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
652 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
653 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
654}
655
656/**
657 * This will write to TX and read from RX according to the parameters
658 * set in pl022.
659 */
660static void readwriter(struct pl022 *pl022)
661{
662
663 /*
664 * The FIFO depth is different inbetween primecell variants.
665 * I believe filling in too much in the FIFO might cause
666 * errons in 8bit wide transfers on ARM variants (just 8 words
667 * FIFO, means only 8x8 = 64 bits in FIFO) at least.
668 *
Linus Walleijfc054752010-01-22 13:53:30 +0100669 * To prevent this issue, the TX FIFO is only filled to the
670 * unused RX FIFO fill length, regardless of what the TX
671 * FIFO status flag indicates.
Linus Walleijb43d65f2009-06-09 08:11:42 +0100672 */
673 dev_dbg(&pl022->adev->dev,
674 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
675 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
676
677 /* Read as much as you can */
678 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
679 && (pl022->rx < pl022->rx_end)) {
680 switch (pl022->read) {
681 case READING_NULL:
682 readw(SSP_DR(pl022->virtbase));
683 break;
684 case READING_U8:
685 *(u8 *) (pl022->rx) =
686 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
687 break;
688 case READING_U16:
689 *(u16 *) (pl022->rx) =
690 (u16) readw(SSP_DR(pl022->virtbase));
691 break;
692 case READING_U32:
693 *(u32 *) (pl022->rx) =
694 readl(SSP_DR(pl022->virtbase));
695 break;
696 }
697 pl022->rx += (pl022->cur_chip->n_bytes);
Linus Walleijfc054752010-01-22 13:53:30 +0100698 pl022->exp_fifo_level--;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100699 }
700 /*
Linus Walleijfc054752010-01-22 13:53:30 +0100701 * Write as much as possible up to the RX FIFO size
Linus Walleijb43d65f2009-06-09 08:11:42 +0100702 */
Linus Walleijfc054752010-01-22 13:53:30 +0100703 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100704 && (pl022->tx < pl022->tx_end)) {
705 switch (pl022->write) {
706 case WRITING_NULL:
707 writew(0x0, SSP_DR(pl022->virtbase));
708 break;
709 case WRITING_U8:
710 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
711 break;
712 case WRITING_U16:
713 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
714 break;
715 case WRITING_U32:
716 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
717 break;
718 }
719 pl022->tx += (pl022->cur_chip->n_bytes);
Linus Walleijfc054752010-01-22 13:53:30 +0100720 pl022->exp_fifo_level++;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100721 /*
722 * This inner reader takes care of things appearing in the RX
723 * FIFO as we're transmitting. This will happen a lot since the
724 * clock starts running when you put things into the TX FIFO,
725 * and then things are continously clocked into the RX FIFO.
726 */
727 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
728 && (pl022->rx < pl022->rx_end)) {
729 switch (pl022->read) {
730 case READING_NULL:
731 readw(SSP_DR(pl022->virtbase));
732 break;
733 case READING_U8:
734 *(u8 *) (pl022->rx) =
735 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
736 break;
737 case READING_U16:
738 *(u16 *) (pl022->rx) =
739 (u16) readw(SSP_DR(pl022->virtbase));
740 break;
741 case READING_U32:
742 *(u32 *) (pl022->rx) =
743 readl(SSP_DR(pl022->virtbase));
744 break;
745 }
746 pl022->rx += (pl022->cur_chip->n_bytes);
Linus Walleijfc054752010-01-22 13:53:30 +0100747 pl022->exp_fifo_level--;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100748 }
749 }
750 /*
751 * When we exit here the TX FIFO should be full and the RX FIFO
752 * should be empty
753 */
754}
755
756
757/**
758 * next_transfer - Move to the Next transfer in the current spi message
759 * @pl022: SSP driver private data structure
760 *
761 * This function moves though the linked list of spi transfers in the
762 * current spi message and returns with the state of current spi
763 * message i.e whether its last transfer is done(STATE_DONE) or
764 * Next transfer is ready(STATE_RUNNING)
765 */
766static void *next_transfer(struct pl022 *pl022)
767{
768 struct spi_message *msg = pl022->cur_msg;
769 struct spi_transfer *trans = pl022->cur_transfer;
770
771 /* Move to next transfer */
772 if (trans->transfer_list.next != &msg->transfers) {
773 pl022->cur_transfer =
774 list_entry(trans->transfer_list.next,
775 struct spi_transfer, transfer_list);
776 return STATE_RUNNING;
777 }
778 return STATE_DONE;
779}
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900780
781/*
782 * This DMA functionality is only compiled in if we have
783 * access to the generic DMA devices/DMA engine.
784 */
785#ifdef CONFIG_DMA_ENGINE
786static void unmap_free_dma_scatter(struct pl022 *pl022)
787{
788 /* Unmap and free the SG tables */
Linus Walleijb7298892010-12-22 23:13:07 +0100789 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900790 pl022->sgt_tx.nents, DMA_TO_DEVICE);
Linus Walleijb7298892010-12-22 23:13:07 +0100791 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900792 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
793 sg_free_table(&pl022->sgt_rx);
794 sg_free_table(&pl022->sgt_tx);
795}
796
797static void dma_callback(void *data)
798{
799 struct pl022 *pl022 = data;
800 struct spi_message *msg = pl022->cur_msg;
801
802 BUG_ON(!pl022->sgt_rx.sgl);
803
804#ifdef VERBOSE_DEBUG
805 /*
806 * Optionally dump out buffers to inspect contents, this is
807 * good if you want to convince yourself that the loopback
808 * read/write contents are the same, when adopting to a new
809 * DMA engine.
810 */
811 {
812 struct scatterlist *sg;
813 unsigned int i;
814
815 dma_sync_sg_for_cpu(&pl022->adev->dev,
816 pl022->sgt_rx.sgl,
817 pl022->sgt_rx.nents,
818 DMA_FROM_DEVICE);
819
820 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
821 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
822 print_hex_dump(KERN_ERR, "SPI RX: ",
823 DUMP_PREFIX_OFFSET,
824 16,
825 1,
826 sg_virt(sg),
827 sg_dma_len(sg),
828 1);
829 }
830 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
831 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
832 print_hex_dump(KERN_ERR, "SPI TX: ",
833 DUMP_PREFIX_OFFSET,
834 16,
835 1,
836 sg_virt(sg),
837 sg_dma_len(sg),
838 1);
839 }
840 }
841#endif
842
843 unmap_free_dma_scatter(pl022);
844
845 /* Update total bytes transfered */
846 msg->actual_length += pl022->cur_transfer->len;
847 if (pl022->cur_transfer->cs_change)
848 pl022->cur_chip->
849 cs_control(SSP_CHIP_DESELECT);
850
851 /* Move to next transfer */
852 msg->state = next_transfer(pl022);
853 tasklet_schedule(&pl022->pump_transfers);
854}
855
856static void setup_dma_scatter(struct pl022 *pl022,
857 void *buffer,
858 unsigned int length,
859 struct sg_table *sgtab)
860{
861 struct scatterlist *sg;
862 int bytesleft = length;
863 void *bufp = buffer;
864 int mapbytes;
865 int i;
866
867 if (buffer) {
868 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
869 /*
870 * If there are less bytes left than what fits
871 * in the current page (plus page alignment offset)
872 * we just feed in this, else we stuff in as much
873 * as we can.
874 */
875 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
876 mapbytes = bytesleft;
877 else
878 mapbytes = PAGE_SIZE - offset_in_page(bufp);
879 sg_set_page(sg, virt_to_page(bufp),
880 mapbytes, offset_in_page(bufp));
881 bufp += mapbytes;
882 bytesleft -= mapbytes;
883 dev_dbg(&pl022->adev->dev,
884 "set RX/TX target page @ %p, %d bytes, %d left\n",
885 bufp, mapbytes, bytesleft);
886 }
887 } else {
888 /* Map the dummy buffer on every page */
889 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
890 if (bytesleft < PAGE_SIZE)
891 mapbytes = bytesleft;
892 else
893 mapbytes = PAGE_SIZE;
894 sg_set_page(sg, virt_to_page(pl022->dummypage),
895 mapbytes, 0);
896 bytesleft -= mapbytes;
897 dev_dbg(&pl022->adev->dev,
898 "set RX/TX to dummy page %d bytes, %d left\n",
899 mapbytes, bytesleft);
900
901 }
902 }
903 BUG_ON(bytesleft);
904}
905
906/**
907 * configure_dma - configures the channels for the next transfer
908 * @pl022: SSP driver's private data structure
909 */
910static int configure_dma(struct pl022 *pl022)
911{
912 struct dma_slave_config rx_conf = {
913 .src_addr = SSP_DR(pl022->phybase),
914 .direction = DMA_FROM_DEVICE,
915 .src_maxburst = pl022->vendor->fifodepth >> 1,
916 };
917 struct dma_slave_config tx_conf = {
918 .dst_addr = SSP_DR(pl022->phybase),
919 .direction = DMA_TO_DEVICE,
920 .dst_maxburst = pl022->vendor->fifodepth >> 1,
921 };
922 unsigned int pages;
923 int ret;
Linus Walleij082086f2010-12-22 23:13:37 +0100924 int rx_sglen, tx_sglen;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900925 struct dma_chan *rxchan = pl022->dma_rx_channel;
926 struct dma_chan *txchan = pl022->dma_tx_channel;
927 struct dma_async_tx_descriptor *rxdesc;
928 struct dma_async_tx_descriptor *txdesc;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900929
930 /* Check that the channels are available */
931 if (!rxchan || !txchan)
932 return -ENODEV;
933
934 switch (pl022->read) {
935 case READING_NULL:
936 /* Use the same as for writing */
937 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
938 break;
939 case READING_U8:
940 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
941 break;
942 case READING_U16:
943 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
944 break;
945 case READING_U32:
946 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
947 break;
948 }
949
950 switch (pl022->write) {
951 case WRITING_NULL:
952 /* Use the same as for reading */
953 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
954 break;
955 case WRITING_U8:
956 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
957 break;
958 case WRITING_U16:
959 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
960 break;
961 case WRITING_U32:
Joe Perchesbc3f67a2010-11-14 19:04:47 -0800962 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900963 break;
964 }
965
966 /* SPI pecularity: we need to read and write the same width */
967 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
968 rx_conf.src_addr_width = tx_conf.dst_addr_width;
969 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
970 tx_conf.dst_addr_width = rx_conf.src_addr_width;
971 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
972
Linus Walleijecd442f2011-02-08 13:03:12 +0100973 dmaengine_slave_config(rxchan, &rx_conf);
974 dmaengine_slave_config(txchan, &tx_conf);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900975
976 /* Create sglists for the transfers */
977 pages = (pl022->cur_transfer->len >> PAGE_SHIFT) + 1;
978 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
979
980 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_KERNEL);
981 if (ret)
982 goto err_alloc_rx_sg;
983
984 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_KERNEL);
985 if (ret)
986 goto err_alloc_tx_sg;
987
988 /* Fill in the scatterlists for the RX+TX buffers */
989 setup_dma_scatter(pl022, pl022->rx,
990 pl022->cur_transfer->len, &pl022->sgt_rx);
991 setup_dma_scatter(pl022, pl022->tx,
992 pl022->cur_transfer->len, &pl022->sgt_tx);
993
994 /* Map DMA buffers */
Linus Walleij082086f2010-12-22 23:13:37 +0100995 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900996 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
Linus Walleij082086f2010-12-22 23:13:37 +0100997 if (!rx_sglen)
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900998 goto err_rx_sgmap;
999
Linus Walleij082086f2010-12-22 23:13:37 +01001000 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001001 pl022->sgt_tx.nents, DMA_TO_DEVICE);
Linus Walleij082086f2010-12-22 23:13:37 +01001002 if (!tx_sglen)
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001003 goto err_tx_sgmap;
1004
1005 /* Send both scatterlists */
1006 rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
1007 pl022->sgt_rx.sgl,
Linus Walleij082086f2010-12-22 23:13:37 +01001008 rx_sglen,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001009 DMA_FROM_DEVICE,
1010 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1011 if (!rxdesc)
1012 goto err_rxdesc;
1013
1014 txdesc = txchan->device->device_prep_slave_sg(txchan,
1015 pl022->sgt_tx.sgl,
Linus Walleij082086f2010-12-22 23:13:37 +01001016 tx_sglen,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001017 DMA_TO_DEVICE,
1018 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1019 if (!txdesc)
1020 goto err_txdesc;
1021
1022 /* Put the callback on the RX transfer only, that should finish last */
1023 rxdesc->callback = dma_callback;
1024 rxdesc->callback_param = pl022;
1025
1026 /* Submit and fire RX and TX with TX last so we're ready to read! */
Linus Walleijecd442f2011-02-08 13:03:12 +01001027 dmaengine_submit(rxdesc);
1028 dmaengine_submit(txdesc);
1029 dma_async_issue_pending(rxchan);
1030 dma_async_issue_pending(txchan);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001031
1032 return 0;
1033
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001034err_txdesc:
Linus Walleijecd442f2011-02-08 13:03:12 +01001035 dmaengine_terminate_all(txchan);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001036err_rxdesc:
Linus Walleijecd442f2011-02-08 13:03:12 +01001037 dmaengine_terminate_all(rxchan);
Linus Walleijb7298892010-12-22 23:13:07 +01001038 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001039 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1040err_tx_sgmap:
Linus Walleijb7298892010-12-22 23:13:07 +01001041 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001042 pl022->sgt_tx.nents, DMA_FROM_DEVICE);
1043err_rx_sgmap:
1044 sg_free_table(&pl022->sgt_tx);
1045err_alloc_tx_sg:
1046 sg_free_table(&pl022->sgt_rx);
1047err_alloc_rx_sg:
1048 return -ENOMEM;
1049}
1050
1051static int __init pl022_dma_probe(struct pl022 *pl022)
1052{
1053 dma_cap_mask_t mask;
1054
1055 /* Try to acquire a generic DMA engine slave channel */
1056 dma_cap_zero(mask);
1057 dma_cap_set(DMA_SLAVE, mask);
1058 /*
1059 * We need both RX and TX channels to do DMA, else do none
1060 * of them.
1061 */
1062 pl022->dma_rx_channel = dma_request_channel(mask,
1063 pl022->master_info->dma_filter,
1064 pl022->master_info->dma_rx_param);
1065 if (!pl022->dma_rx_channel) {
1066 dev_err(&pl022->adev->dev, "no RX DMA channel!\n");
1067 goto err_no_rxchan;
1068 }
1069
1070 pl022->dma_tx_channel = dma_request_channel(mask,
1071 pl022->master_info->dma_filter,
1072 pl022->master_info->dma_tx_param);
1073 if (!pl022->dma_tx_channel) {
1074 dev_err(&pl022->adev->dev, "no TX DMA channel!\n");
1075 goto err_no_txchan;
1076 }
1077
1078 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1079 if (!pl022->dummypage) {
1080 dev_err(&pl022->adev->dev, "no DMA dummypage!\n");
1081 goto err_no_dummypage;
1082 }
1083
1084 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
1085 dma_chan_name(pl022->dma_rx_channel),
1086 dma_chan_name(pl022->dma_tx_channel));
1087
1088 return 0;
1089
1090err_no_dummypage:
1091 dma_release_channel(pl022->dma_tx_channel);
1092err_no_txchan:
1093 dma_release_channel(pl022->dma_rx_channel);
1094 pl022->dma_rx_channel = NULL;
1095err_no_rxchan:
1096 return -ENODEV;
1097}
1098
1099static void terminate_dma(struct pl022 *pl022)
1100{
1101 struct dma_chan *rxchan = pl022->dma_rx_channel;
1102 struct dma_chan *txchan = pl022->dma_tx_channel;
1103
Linus Walleijecd442f2011-02-08 13:03:12 +01001104 dmaengine_terminate_all(rxchan);
1105 dmaengine_terminate_all(txchan);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001106 unmap_free_dma_scatter(pl022);
1107}
1108
1109static void pl022_dma_remove(struct pl022 *pl022)
1110{
1111 if (pl022->busy)
1112 terminate_dma(pl022);
1113 if (pl022->dma_tx_channel)
1114 dma_release_channel(pl022->dma_tx_channel);
1115 if (pl022->dma_rx_channel)
1116 dma_release_channel(pl022->dma_rx_channel);
1117 kfree(pl022->dummypage);
1118}
1119
1120#else
1121static inline int configure_dma(struct pl022 *pl022)
1122{
1123 return -ENODEV;
1124}
1125
1126static inline int pl022_dma_probe(struct pl022 *pl022)
1127{
1128 return 0;
1129}
1130
1131static inline void pl022_dma_remove(struct pl022 *pl022)
1132{
1133}
1134#endif
1135
Linus Walleijb43d65f2009-06-09 08:11:42 +01001136/**
1137 * pl022_interrupt_handler - Interrupt handler for SSP controller
1138 *
1139 * This function handles interrupts generated for an interrupt based transfer.
1140 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
1141 * current message's state as STATE_ERROR and schedule the tasklet
1142 * pump_transfers which will do the postprocessing of the current message by
1143 * calling giveback(). Otherwise it reads data from RX FIFO till there is no
1144 * more data, and writes data in TX FIFO till it is not full. If we complete
1145 * the transfer we move to the next transfer and schedule the tasklet.
1146 */
1147static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
1148{
1149 struct pl022 *pl022 = dev_id;
1150 struct spi_message *msg = pl022->cur_msg;
1151 u16 irq_status = 0;
1152 u16 flag = 0;
1153
1154 if (unlikely(!msg)) {
1155 dev_err(&pl022->adev->dev,
1156 "bad message state in interrupt handler");
1157 /* Never fail */
1158 return IRQ_HANDLED;
1159 }
1160
1161 /* Read the Interrupt Status Register */
1162 irq_status = readw(SSP_MIS(pl022->virtbase));
1163
1164 if (unlikely(!irq_status))
1165 return IRQ_NONE;
1166
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001167 /*
1168 * This handles the FIFO interrupts, the timeout
1169 * interrupts are flatly ignored, they cannot be
1170 * trusted.
1171 */
Linus Walleijb43d65f2009-06-09 08:11:42 +01001172 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
1173 /*
1174 * Overrun interrupt - bail out since our Data has been
1175 * corrupted
1176 */
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001177 dev_err(&pl022->adev->dev, "FIFO overrun\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01001178 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1179 dev_err(&pl022->adev->dev,
1180 "RXFIFO is full\n");
1181 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF)
1182 dev_err(&pl022->adev->dev,
1183 "TXFIFO is full\n");
1184
1185 /*
1186 * Disable and clear interrupts, disable SSP,
1187 * mark message with bad status so it can be
1188 * retried.
1189 */
1190 writew(DISABLE_ALL_INTERRUPTS,
1191 SSP_IMSC(pl022->virtbase));
1192 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1193 writew((readw(SSP_CR1(pl022->virtbase)) &
1194 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1195 msg->state = STATE_ERROR;
1196
1197 /* Schedule message queue handler */
1198 tasklet_schedule(&pl022->pump_transfers);
1199 return IRQ_HANDLED;
1200 }
1201
1202 readwriter(pl022);
1203
1204 if ((pl022->tx == pl022->tx_end) && (flag == 0)) {
1205 flag = 1;
1206 /* Disable Transmit interrupt */
1207 writew(readw(SSP_IMSC(pl022->virtbase)) &
1208 (~SSP_IMSC_MASK_TXIM),
1209 SSP_IMSC(pl022->virtbase));
1210 }
1211
1212 /*
1213 * Since all transactions must write as much as shall be read,
1214 * we can conclude the entire transaction once RX is complete.
1215 * At this point, all TX will always be finished.
1216 */
1217 if (pl022->rx >= pl022->rx_end) {
1218 writew(DISABLE_ALL_INTERRUPTS,
1219 SSP_IMSC(pl022->virtbase));
1220 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1221 if (unlikely(pl022->rx > pl022->rx_end)) {
1222 dev_warn(&pl022->adev->dev, "read %u surplus "
1223 "bytes (did you request an odd "
1224 "number of bytes on a 16bit bus?)\n",
1225 (u32) (pl022->rx - pl022->rx_end));
1226 }
1227 /* Update total bytes transfered */
1228 msg->actual_length += pl022->cur_transfer->len;
1229 if (pl022->cur_transfer->cs_change)
1230 pl022->cur_chip->
1231 cs_control(SSP_CHIP_DESELECT);
1232 /* Move to next transfer */
1233 msg->state = next_transfer(pl022);
1234 tasklet_schedule(&pl022->pump_transfers);
1235 return IRQ_HANDLED;
1236 }
1237
1238 return IRQ_HANDLED;
1239}
1240
1241/**
1242 * This sets up the pointers to memory for the next message to
1243 * send out on the SPI bus.
1244 */
1245static int set_up_next_transfer(struct pl022 *pl022,
1246 struct spi_transfer *transfer)
1247{
1248 int residue;
1249
1250 /* Sanity check the message for this bus width */
1251 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
1252 if (unlikely(residue != 0)) {
1253 dev_err(&pl022->adev->dev,
1254 "message of %u bytes to transmit but the current "
1255 "chip bus has a data width of %u bytes!\n",
1256 pl022->cur_transfer->len,
1257 pl022->cur_chip->n_bytes);
1258 dev_err(&pl022->adev->dev, "skipping this message\n");
1259 return -EIO;
1260 }
1261 pl022->tx = (void *)transfer->tx_buf;
1262 pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
1263 pl022->rx = (void *)transfer->rx_buf;
1264 pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
1265 pl022->write =
1266 pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
1267 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
1268 return 0;
1269}
1270
1271/**
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001272 * pump_transfers - Tasklet function which schedules next transfer
1273 * when running in interrupt or DMA transfer mode.
Linus Walleijb43d65f2009-06-09 08:11:42 +01001274 * @data: SSP driver private data structure
1275 *
1276 */
1277static void pump_transfers(unsigned long data)
1278{
1279 struct pl022 *pl022 = (struct pl022 *) data;
1280 struct spi_message *message = NULL;
1281 struct spi_transfer *transfer = NULL;
1282 struct spi_transfer *previous = NULL;
1283
1284 /* Get current state information */
1285 message = pl022->cur_msg;
1286 transfer = pl022->cur_transfer;
1287
1288 /* Handle for abort */
1289 if (message->state == STATE_ERROR) {
1290 message->status = -EIO;
1291 giveback(pl022);
1292 return;
1293 }
1294
1295 /* Handle end of message */
1296 if (message->state == STATE_DONE) {
1297 message->status = 0;
1298 giveback(pl022);
1299 return;
1300 }
1301
1302 /* Delay if requested at end of transfer before CS change */
1303 if (message->state == STATE_RUNNING) {
1304 previous = list_entry(transfer->transfer_list.prev,
1305 struct spi_transfer,
1306 transfer_list);
1307 if (previous->delay_usecs)
1308 /*
1309 * FIXME: This runs in interrupt context.
1310 * Is this really smart?
1311 */
1312 udelay(previous->delay_usecs);
1313
1314 /* Drop chip select only if cs_change is requested */
1315 if (previous->cs_change)
1316 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1317 } else {
1318 /* STATE_START */
1319 message->state = STATE_RUNNING;
1320 }
1321
1322 if (set_up_next_transfer(pl022, transfer)) {
1323 message->state = STATE_ERROR;
1324 message->status = -EIO;
1325 giveback(pl022);
1326 return;
1327 }
1328 /* Flush the FIFOs and let's go! */
1329 flush(pl022);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001330
1331 if (pl022->cur_chip->enable_dma) {
1332 if (configure_dma(pl022)) {
1333 dev_dbg(&pl022->adev->dev,
1334 "configuration of DMA failed, fall back to interrupt mode\n");
1335 goto err_config_dma;
1336 }
1337 return;
1338 }
1339
1340err_config_dma:
Linus Walleijb43d65f2009-06-09 08:11:42 +01001341 writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
1342}
1343
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001344static void do_interrupt_dma_transfer(struct pl022 *pl022)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001345{
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001346 u32 irqflags = ENABLE_ALL_INTERRUPTS;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001347
1348 /* Enable target chip */
1349 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1350 if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
1351 /* Error path */
1352 pl022->cur_msg->state = STATE_ERROR;
1353 pl022->cur_msg->status = -EIO;
1354 giveback(pl022);
1355 return;
1356 }
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001357 /* If we're using DMA, set up DMA here */
1358 if (pl022->cur_chip->enable_dma) {
1359 /* Configure DMA transfer */
1360 if (configure_dma(pl022)) {
1361 dev_dbg(&pl022->adev->dev,
1362 "configuration of DMA failed, fall back to interrupt mode\n");
1363 goto err_config_dma;
1364 }
1365 /* Disable interrupts in DMA mode, IRQ from DMA controller */
1366 irqflags = DISABLE_ALL_INTERRUPTS;
1367 }
1368err_config_dma:
Linus Walleijb43d65f2009-06-09 08:11:42 +01001369 /* Enable SSP, turn on interrupts */
1370 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1371 SSP_CR1(pl022->virtbase));
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001372 writew(irqflags, SSP_IMSC(pl022->virtbase));
Linus Walleijb43d65f2009-06-09 08:11:42 +01001373}
1374
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001375static void do_polling_transfer(struct pl022 *pl022)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001376{
Linus Walleijb43d65f2009-06-09 08:11:42 +01001377 struct spi_message *message = NULL;
1378 struct spi_transfer *transfer = NULL;
1379 struct spi_transfer *previous = NULL;
1380 struct chip_data *chip;
1381
1382 chip = pl022->cur_chip;
1383 message = pl022->cur_msg;
1384
1385 while (message->state != STATE_DONE) {
1386 /* Handle for abort */
1387 if (message->state == STATE_ERROR)
1388 break;
1389 transfer = pl022->cur_transfer;
1390
1391 /* Delay if requested at end of transfer */
1392 if (message->state == STATE_RUNNING) {
1393 previous =
1394 list_entry(transfer->transfer_list.prev,
1395 struct spi_transfer, transfer_list);
1396 if (previous->delay_usecs)
1397 udelay(previous->delay_usecs);
1398 if (previous->cs_change)
1399 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1400 } else {
1401 /* STATE_START */
1402 message->state = STATE_RUNNING;
1403 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1404 }
1405
1406 /* Configuration Changing Per Transfer */
1407 if (set_up_next_transfer(pl022, transfer)) {
1408 /* Error path */
1409 message->state = STATE_ERROR;
1410 break;
1411 }
1412 /* Flush FIFOs and enable SSP */
1413 flush(pl022);
1414 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1415 SSP_CR1(pl022->virtbase));
1416
Linus Walleij556f4ae2010-05-05 09:28:15 +00001417 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01001418 /* FIXME: insert a timeout so we don't hang here indefinately */
1419 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end)
1420 readwriter(pl022);
1421
1422 /* Update total byte transfered */
1423 message->actual_length += pl022->cur_transfer->len;
1424 if (pl022->cur_transfer->cs_change)
1425 pl022->cur_chip->cs_control(SSP_CHIP_DESELECT);
1426 /* Move to next transfer */
1427 message->state = next_transfer(pl022);
1428 }
1429
1430 /* Handle end of message */
1431 if (message->state == STATE_DONE)
1432 message->status = 0;
1433 else
1434 message->status = -EIO;
1435
1436 giveback(pl022);
1437 return;
1438}
1439
1440/**
1441 * pump_messages - Workqueue function which processes spi message queue
1442 * @data: pointer to private data of SSP driver
1443 *
1444 * This function checks if there is any spi message in the queue that
1445 * needs processing and delegate control to appropriate function
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001446 * do_polling_transfer()/do_interrupt_dma_transfer()
Linus Walleijb43d65f2009-06-09 08:11:42 +01001447 * based on the kind of the transfer
1448 *
1449 */
1450static void pump_messages(struct work_struct *work)
1451{
1452 struct pl022 *pl022 =
1453 container_of(work, struct pl022, pump_messages);
1454 unsigned long flags;
1455
1456 /* Lock queue and check for queue work */
1457 spin_lock_irqsave(&pl022->queue_lock, flags);
Linus Walleij5e8b8212010-12-22 23:13:59 +01001458 if (list_empty(&pl022->queue) || !pl022->running) {
Linus Walleijdec5a582010-12-22 23:13:48 +01001459 pl022->busy = false;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001460 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1461 return;
1462 }
1463 /* Make sure we are not already running a message */
1464 if (pl022->cur_msg) {
1465 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1466 return;
1467 }
1468 /* Extract head of queue */
1469 pl022->cur_msg =
1470 list_entry(pl022->queue.next, struct spi_message, queue);
1471
1472 list_del_init(&pl022->cur_msg->queue);
Linus Walleijdec5a582010-12-22 23:13:48 +01001473 pl022->busy = true;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001474 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1475
1476 /* Initial message state */
1477 pl022->cur_msg->state = STATE_START;
1478 pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next,
1479 struct spi_transfer,
1480 transfer_list);
1481
1482 /* Setup the SPI using the per chip configuration */
1483 pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi);
1484 /*
Linus Walleij808f1032011-02-08 13:03:32 +01001485 * We enable the core voltage and clocks here, then the clocks
1486 * and core will be disabled when giveback() is called in each method
1487 * (poll/interrupt/DMA)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001488 */
Linus Walleij808f1032011-02-08 13:03:32 +01001489 amba_vcore_enable(pl022->adev);
Linus Walleij545074f2010-08-21 11:07:36 +02001490 amba_pclk_enable(pl022->adev);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001491 clk_enable(pl022->clk);
1492 restore_state(pl022);
1493 flush(pl022);
1494
1495 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1496 do_polling_transfer(pl022);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001497 else
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001498 do_interrupt_dma_transfer(pl022);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001499}
1500
1501
1502static int __init init_queue(struct pl022 *pl022)
1503{
1504 INIT_LIST_HEAD(&pl022->queue);
1505 spin_lock_init(&pl022->queue_lock);
1506
Linus Walleij5e8b8212010-12-22 23:13:59 +01001507 pl022->running = false;
Linus Walleijdec5a582010-12-22 23:13:48 +01001508 pl022->busy = false;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001509
1510 tasklet_init(&pl022->pump_transfers,
1511 pump_transfers, (unsigned long)pl022);
1512
1513 INIT_WORK(&pl022->pump_messages, pump_messages);
1514 pl022->workqueue = create_singlethread_workqueue(
1515 dev_name(pl022->master->dev.parent));
1516 if (pl022->workqueue == NULL)
1517 return -EBUSY;
1518
1519 return 0;
1520}
1521
1522
1523static int start_queue(struct pl022 *pl022)
1524{
1525 unsigned long flags;
1526
1527 spin_lock_irqsave(&pl022->queue_lock, flags);
1528
Linus Walleij5e8b8212010-12-22 23:13:59 +01001529 if (pl022->running || pl022->busy) {
Linus Walleijb43d65f2009-06-09 08:11:42 +01001530 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1531 return -EBUSY;
1532 }
1533
Linus Walleij5e8b8212010-12-22 23:13:59 +01001534 pl022->running = true;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001535 pl022->cur_msg = NULL;
1536 pl022->cur_transfer = NULL;
1537 pl022->cur_chip = NULL;
1538 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1539
1540 queue_work(pl022->workqueue, &pl022->pump_messages);
1541
1542 return 0;
1543}
1544
1545
1546static int stop_queue(struct pl022 *pl022)
1547{
1548 unsigned long flags;
1549 unsigned limit = 500;
1550 int status = 0;
1551
1552 spin_lock_irqsave(&pl022->queue_lock, flags);
1553
1554 /* This is a bit lame, but is optimized for the common execution path.
1555 * A wait_queue on the pl022->busy could be used, but then the common
1556 * execution path (pump_messages) would be required to call wake_up or
1557 * friends on every SPI message. Do this instead */
Linus Walleijb43d65f2009-06-09 08:11:42 +01001558 while (!list_empty(&pl022->queue) && pl022->busy && limit--) {
1559 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1560 msleep(10);
1561 spin_lock_irqsave(&pl022->queue_lock, flags);
1562 }
1563
1564 if (!list_empty(&pl022->queue) || pl022->busy)
1565 status = -EBUSY;
Linus Walleij5e8b8212010-12-22 23:13:59 +01001566 else
1567 pl022->running = false;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001568
1569 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1570
1571 return status;
1572}
1573
1574static int destroy_queue(struct pl022 *pl022)
1575{
1576 int status;
1577
1578 status = stop_queue(pl022);
1579 /* we are unloading the module or failing to load (only two calls
1580 * to this routine), and neither call can handle a return value.
1581 * However, destroy_workqueue calls flush_workqueue, and that will
1582 * block until all work is done. If the reason that stop_queue
1583 * timed out is that the work will never finish, then it does no
1584 * good to call destroy_workqueue, so return anyway. */
1585 if (status != 0)
1586 return status;
1587
1588 destroy_workqueue(pl022->workqueue);
1589
1590 return 0;
1591}
1592
1593static int verify_controller_parameters(struct pl022 *pl022,
Linus Walleijf9d629c2010-10-01 13:33:13 +02001594 struct pl022_config_chip const *chip_info)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001595{
Linus Walleijb43d65f2009-06-09 08:11:42 +01001596 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
1597 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001598 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001599 "interface is configured incorrectly\n");
1600 return -EINVAL;
1601 }
1602 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
1603 (!pl022->vendor->unidir)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001604 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001605 "unidirectional mode not supported in this "
1606 "hardware version\n");
1607 return -EINVAL;
1608 }
1609 if ((chip_info->hierarchy != SSP_MASTER)
1610 && (chip_info->hierarchy != SSP_SLAVE)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001611 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001612 "hierarchy is configured incorrectly\n");
1613 return -EINVAL;
1614 }
Linus Walleijb43d65f2009-06-09 08:11:42 +01001615 if ((chip_info->com_mode != INTERRUPT_TRANSFER)
1616 && (chip_info->com_mode != DMA_TRANSFER)
1617 && (chip_info->com_mode != POLLING_TRANSFER)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001618 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001619 "Communication mode is configured incorrectly\n");
1620 return -EINVAL;
1621 }
1622 if ((chip_info->rx_lev_trig < SSP_RX_1_OR_MORE_ELEM)
1623 || (chip_info->rx_lev_trig > SSP_RX_32_OR_MORE_ELEM)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001624 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001625 "RX FIFO Trigger Level is configured incorrectly\n");
1626 return -EINVAL;
1627 }
1628 if ((chip_info->tx_lev_trig < SSP_TX_1_OR_MORE_EMPTY_LOC)
1629 || (chip_info->tx_lev_trig > SSP_TX_32_OR_MORE_EMPTY_LOC)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001630 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001631 "TX FIFO Trigger Level is configured incorrectly\n");
1632 return -EINVAL;
1633 }
Linus Walleijb43d65f2009-06-09 08:11:42 +01001634 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
1635 if ((chip_info->ctrl_len < SSP_BITS_4)
1636 || (chip_info->ctrl_len > SSP_BITS_32)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001637 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001638 "CTRL LEN is configured incorrectly\n");
1639 return -EINVAL;
1640 }
1641 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
1642 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001643 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001644 "Wait State is configured incorrectly\n");
1645 return -EINVAL;
1646 }
Linus Walleij556f4ae2010-05-05 09:28:15 +00001647 /* Half duplex is only available in the ST Micro version */
1648 if (pl022->vendor->extended_cr) {
1649 if ((chip_info->duplex !=
1650 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1651 && (chip_info->duplex !=
Julia Lawall4a4fd472010-09-29 17:31:30 +09001652 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001653 dev_err(&pl022->adev->dev,
Linus Walleij556f4ae2010-05-05 09:28:15 +00001654 "Microwire duplex mode is configured incorrectly\n");
1655 return -EINVAL;
Julia Lawall4a4fd472010-09-29 17:31:30 +09001656 }
Linus Walleij556f4ae2010-05-05 09:28:15 +00001657 } else {
1658 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001659 dev_err(&pl022->adev->dev,
Linus Walleij556f4ae2010-05-05 09:28:15 +00001660 "Microwire half duplex mode requested,"
1661 " but this is only available in the"
1662 " ST version of PL022\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01001663 return -EINVAL;
1664 }
1665 }
Linus Walleijb43d65f2009-06-09 08:11:42 +01001666 return 0;
1667}
1668
1669/**
1670 * pl022_transfer - transfer function registered to SPI master framework
1671 * @spi: spi device which is requesting transfer
1672 * @msg: spi message which is to handled is queued to driver queue
1673 *
1674 * This function is registered to the SPI framework for this SPI master
1675 * controller. It will queue the spi_message in the queue of driver if
1676 * the queue is not stopped and return.
1677 */
1678static int pl022_transfer(struct spi_device *spi, struct spi_message *msg)
1679{
1680 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1681 unsigned long flags;
1682
1683 spin_lock_irqsave(&pl022->queue_lock, flags);
1684
Linus Walleij5e8b8212010-12-22 23:13:59 +01001685 if (!pl022->running) {
Linus Walleijb43d65f2009-06-09 08:11:42 +01001686 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1687 return -ESHUTDOWN;
1688 }
1689 msg->actual_length = 0;
1690 msg->status = -EINPROGRESS;
1691 msg->state = STATE_START;
1692
1693 list_add_tail(&msg->queue, &pl022->queue);
Linus Walleij5e8b8212010-12-22 23:13:59 +01001694 if (pl022->running && !pl022->busy)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001695 queue_work(pl022->workqueue, &pl022->pump_messages);
1696
1697 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1698 return 0;
1699}
1700
1701static int calculate_effective_freq(struct pl022 *pl022,
1702 int freq,
1703 struct ssp_clock_params *clk_freq)
1704{
1705 /* Lets calculate the frequency parameters */
1706 u16 cpsdvsr = 2;
1707 u16 scr = 0;
1708 bool freq_found = false;
1709 u32 rate;
1710 u32 max_tclk;
1711 u32 min_tclk;
1712
1713 rate = clk_get_rate(pl022->clk);
1714 /* cpsdvscr = 2 & scr 0 */
1715 max_tclk = (rate / (CPSDVR_MIN * (1 + SCR_MIN)));
1716 /* cpsdvsr = 254 & scr = 255 */
1717 min_tclk = (rate / (CPSDVR_MAX * (1 + SCR_MAX)));
1718
1719 if ((freq <= max_tclk) && (freq >= min_tclk)) {
1720 while (cpsdvsr <= CPSDVR_MAX && !freq_found) {
1721 while (scr <= SCR_MAX && !freq_found) {
1722 if ((rate /
1723 (cpsdvsr * (1 + scr))) > freq)
1724 scr += 1;
1725 else {
1726 /*
1727 * This bool is made true when
1728 * effective frequency >=
1729 * target frequency is found
1730 */
1731 freq_found = true;
1732 if ((rate /
1733 (cpsdvsr * (1 + scr))) != freq) {
1734 if (scr == SCR_MIN) {
1735 cpsdvsr -= 2;
1736 scr = SCR_MAX;
1737 } else
1738 scr -= 1;
1739 }
1740 }
1741 }
1742 if (!freq_found) {
1743 cpsdvsr += 2;
1744 scr = SCR_MIN;
1745 }
1746 }
1747 if (cpsdvsr != 0) {
1748 dev_dbg(&pl022->adev->dev,
1749 "SSP Effective Frequency is %u\n",
1750 (rate / (cpsdvsr * (1 + scr))));
1751 clk_freq->cpsdvsr = (u8) (cpsdvsr & 0xFF);
1752 clk_freq->scr = (u8) (scr & 0xFF);
1753 dev_dbg(&pl022->adev->dev,
1754 "SSP cpsdvsr = %d, scr = %d\n",
1755 clk_freq->cpsdvsr, clk_freq->scr);
1756 }
1757 } else {
1758 dev_err(&pl022->adev->dev,
1759 "controller data is incorrect: out of range frequency");
1760 return -EINVAL;
1761 }
1762 return 0;
1763}
1764
Linus Walleijf9d629c2010-10-01 13:33:13 +02001765
1766/*
1767 * A piece of default chip info unless the platform
1768 * supplies it.
1769 */
1770static const struct pl022_config_chip pl022_default_chip_info = {
1771 .com_mode = POLLING_TRANSFER,
1772 .iface = SSP_INTERFACE_MOTOROLA_SPI,
1773 .hierarchy = SSP_SLAVE,
1774 .slave_tx_disable = DO_NOT_DRIVE_TX,
1775 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
1776 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
1777 .ctrl_len = SSP_BITS_8,
1778 .wait_state = SSP_MWIRE_WAIT_ZERO,
1779 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
1780 .cs_control = null_cs_control,
1781};
1782
1783
Linus Walleijb43d65f2009-06-09 08:11:42 +01001784/**
Linus Walleijb43d65f2009-06-09 08:11:42 +01001785 * pl022_setup - setup function registered to SPI master framework
1786 * @spi: spi device which is requesting setup
1787 *
1788 * This function is registered to the SPI framework for this SPI master
1789 * controller. If it is the first time when setup is called by this device,
1790 * this function will initialize the runtime state for this chip and save
1791 * the same in the device structure. Else it will update the runtime info
1792 * with the updated chip info. Nothing is really being written to the
1793 * controller hardware here, that is not done until the actual transfer
1794 * commence.
1795 */
Linus Walleijb43d65f2009-06-09 08:11:42 +01001796static int pl022_setup(struct spi_device *spi)
1797{
Linus Walleijf9d629c2010-10-01 13:33:13 +02001798 struct pl022_config_chip const *chip_info;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001799 struct chip_data *chip;
Viresh Kumar94a1b6d2011-01-13 17:24:22 +05301800 struct ssp_clock_params clk_freq = {0, };
Linus Walleijb43d65f2009-06-09 08:11:42 +01001801 int status = 0;
1802 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
Kevin Wellsbde435a2010-09-16 06:18:50 -07001803 unsigned int bits = spi->bits_per_word;
1804 u32 tmp;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001805
1806 if (!spi->max_speed_hz)
1807 return -EINVAL;
1808
1809 /* Get controller_state if one is supplied */
1810 chip = spi_get_ctldata(spi);
1811
1812 if (chip == NULL) {
1813 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1814 if (!chip) {
1815 dev_err(&spi->dev,
1816 "cannot allocate controller state\n");
1817 return -ENOMEM;
1818 }
1819 dev_dbg(&spi->dev,
1820 "allocated memory for controller's runtime state\n");
1821 }
1822
1823 /* Get controller data if one is supplied */
1824 chip_info = spi->controller_data;
1825
1826 if (chip_info == NULL) {
Linus Walleijf9d629c2010-10-01 13:33:13 +02001827 chip_info = &pl022_default_chip_info;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001828 /* spi_board_info.controller_data not is supplied */
1829 dev_dbg(&spi->dev,
1830 "using default controller_data settings\n");
Linus Walleijf9d629c2010-10-01 13:33:13 +02001831 } else
Linus Walleijb43d65f2009-06-09 08:11:42 +01001832 dev_dbg(&spi->dev,
1833 "using user supplied controller_data settings\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01001834
1835 /*
1836 * We can override with custom divisors, else we use the board
1837 * frequency setting
1838 */
1839 if ((0 == chip_info->clk_freq.cpsdvsr)
1840 && (0 == chip_info->clk_freq.scr)) {
1841 status = calculate_effective_freq(pl022,
1842 spi->max_speed_hz,
Linus Walleijf9d629c2010-10-01 13:33:13 +02001843 &clk_freq);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001844 if (status < 0)
1845 goto err_config_params;
1846 } else {
Linus Walleijf9d629c2010-10-01 13:33:13 +02001847 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
1848 if ((clk_freq.cpsdvsr % 2) != 0)
1849 clk_freq.cpsdvsr =
1850 clk_freq.cpsdvsr - 1;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001851 }
Linus Walleijf9d629c2010-10-01 13:33:13 +02001852 if ((clk_freq.cpsdvsr < CPSDVR_MIN)
1853 || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
1854 dev_err(&spi->dev,
1855 "cpsdvsr is configured incorrectly\n");
1856 goto err_config_params;
1857 }
1858
1859
Linus Walleijb43d65f2009-06-09 08:11:42 +01001860 status = verify_controller_parameters(pl022, chip_info);
1861 if (status) {
1862 dev_err(&spi->dev, "controller data is incorrect");
1863 goto err_config_params;
1864 }
Linus Walleijf9d629c2010-10-01 13:33:13 +02001865
Linus Walleijb43d65f2009-06-09 08:11:42 +01001866 /* Now set controller state based on controller data */
1867 chip->xfer_type = chip_info->com_mode;
Linus Walleijf9d629c2010-10-01 13:33:13 +02001868 if (!chip_info->cs_control) {
1869 chip->cs_control = null_cs_control;
1870 dev_warn(&spi->dev,
1871 "chip select function is NULL for this chip\n");
1872 } else
1873 chip->cs_control = chip_info->cs_control;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001874
Kevin Wellsbde435a2010-09-16 06:18:50 -07001875 if (bits <= 3) {
1876 /* PL022 doesn't support less than 4-bits */
1877 status = -ENOTSUPP;
1878 goto err_config_params;
1879 } else if (bits <= 8) {
1880 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01001881 chip->n_bytes = 1;
1882 chip->read = READING_U8;
1883 chip->write = WRITING_U8;
Kevin Wellsbde435a2010-09-16 06:18:50 -07001884 } else if (bits <= 16) {
Linus Walleijb43d65f2009-06-09 08:11:42 +01001885 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
1886 chip->n_bytes = 2;
1887 chip->read = READING_U16;
1888 chip->write = WRITING_U16;
1889 } else {
1890 if (pl022->vendor->max_bpw >= 32) {
1891 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
1892 chip->n_bytes = 4;
1893 chip->read = READING_U32;
1894 chip->write = WRITING_U32;
1895 } else {
1896 dev_err(&spi->dev,
1897 "illegal data size for this controller!\n");
1898 dev_err(&spi->dev,
1899 "a standard pl022 can only handle "
1900 "1 <= n <= 16 bit words\n");
Kevin Wellsbde435a2010-09-16 06:18:50 -07001901 status = -ENOTSUPP;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001902 goto err_config_params;
1903 }
1904 }
1905
1906 /* Now Initialize all register settings required for this chip */
1907 chip->cr0 = 0;
1908 chip->cr1 = 0;
1909 chip->dmacr = 0;
1910 chip->cpsr = 0;
1911 if ((chip_info->com_mode == DMA_TRANSFER)
1912 && ((pl022->master_info)->enable_dma)) {
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001913 chip->enable_dma = true;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001914 dev_dbg(&spi->dev, "DMA mode set in controller state\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01001915 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1916 SSP_DMACR_MASK_RXDMAE, 0);
1917 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1918 SSP_DMACR_MASK_TXDMAE, 1);
1919 } else {
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001920 chip->enable_dma = false;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001921 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
1922 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1923 SSP_DMACR_MASK_RXDMAE, 0);
1924 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1925 SSP_DMACR_MASK_TXDMAE, 1);
1926 }
1927
Linus Walleijf9d629c2010-10-01 13:33:13 +02001928 chip->cpsr = clk_freq.cpsdvsr;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001929
Linus Walleij556f4ae2010-05-05 09:28:15 +00001930 /* Special setup for the ST micro extended control registers */
1931 if (pl022->vendor->extended_cr) {
Kevin Wellsbde435a2010-09-16 06:18:50 -07001932 u32 etx;
1933
Linus Walleij781c7b12010-05-07 08:40:53 +00001934 if (pl022->vendor->pl023) {
1935 /* These bits are only in the PL023 */
1936 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
1937 SSP_CR1_MASK_FBCLKDEL_ST, 13);
1938 } else {
1939 /* These bits are in the PL022 but not PL023 */
1940 SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
1941 SSP_CR0_MASK_HALFDUP_ST, 5);
1942 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
1943 SSP_CR0_MASK_CSS_ST, 16);
1944 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1945 SSP_CR0_MASK_FRF_ST, 21);
1946 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
1947 SSP_CR1_MASK_MWAIT_ST, 6);
1948 }
Kevin Wellsbde435a2010-09-16 06:18:50 -07001949 SSP_WRITE_BITS(chip->cr0, bits - 1,
Linus Walleij556f4ae2010-05-05 09:28:15 +00001950 SSP_CR0_MASK_DSS_ST, 0);
Kevin Wellsbde435a2010-09-16 06:18:50 -07001951
1952 if (spi->mode & SPI_LSB_FIRST) {
1953 tmp = SSP_RX_LSB;
1954 etx = SSP_TX_LSB;
1955 } else {
1956 tmp = SSP_RX_MSB;
1957 etx = SSP_TX_MSB;
1958 }
1959 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
1960 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
Linus Walleij556f4ae2010-05-05 09:28:15 +00001961 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
1962 SSP_CR1_MASK_RXIFLSEL_ST, 7);
1963 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
1964 SSP_CR1_MASK_TXIFLSEL_ST, 10);
1965 } else {
Kevin Wellsbde435a2010-09-16 06:18:50 -07001966 SSP_WRITE_BITS(chip->cr0, bits - 1,
Linus Walleij556f4ae2010-05-05 09:28:15 +00001967 SSP_CR0_MASK_DSS, 0);
1968 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1969 SSP_CR0_MASK_FRF, 4);
1970 }
Kevin Wellsbde435a2010-09-16 06:18:50 -07001971
Linus Walleij556f4ae2010-05-05 09:28:15 +00001972 /* Stuff that is common for all versions */
Kevin Wellsbde435a2010-09-16 06:18:50 -07001973 if (spi->mode & SPI_CPOL)
1974 tmp = SSP_CLK_POL_IDLE_HIGH;
1975 else
1976 tmp = SSP_CLK_POL_IDLE_LOW;
1977 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
1978
1979 if (spi->mode & SPI_CPHA)
1980 tmp = SSP_CLK_SECOND_EDGE;
1981 else
1982 tmp = SSP_CLK_FIRST_EDGE;
1983 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
1984
Linus Walleijf9d629c2010-10-01 13:33:13 +02001985 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
Linus Walleij781c7b12010-05-07 08:40:53 +00001986 /* Loopback is available on all versions except PL023 */
Philippe Langlais06fb01f2011-03-23 11:05:16 +01001987 if (pl022->vendor->loopback) {
Kevin Wellsbde435a2010-09-16 06:18:50 -07001988 if (spi->mode & SPI_LOOP)
1989 tmp = LOOPBACK_ENABLED;
1990 else
1991 tmp = LOOPBACK_DISABLED;
1992 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
1993 }
Linus Walleijb43d65f2009-06-09 08:11:42 +01001994 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
1995 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
1996 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 3);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001997
1998 /* Save controller_state */
1999 spi_set_ctldata(spi, chip);
2000 return status;
2001 err_config_params:
Kevin Wellsbde435a2010-09-16 06:18:50 -07002002 spi_set_ctldata(spi, NULL);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002003 kfree(chip);
2004 return status;
2005}
2006
2007/**
2008 * pl022_cleanup - cleanup function registered to SPI master framework
2009 * @spi: spi device which is requesting cleanup
2010 *
2011 * This function is registered to the SPI framework for this SPI master
2012 * controller. It will free the runtime state of chip.
2013 */
2014static void pl022_cleanup(struct spi_device *spi)
2015{
2016 struct chip_data *chip = spi_get_ctldata(spi);
2017
2018 spi_set_ctldata(spi, NULL);
2019 kfree(chip);
2020}
2021
2022
Kevin Wellsb4225882010-07-27 16:39:30 +00002023static int __devinit
Russell Kingaa25afa2011-02-19 15:55:00 +00002024pl022_probe(struct amba_device *adev, const struct amba_id *id)
Linus Walleijb43d65f2009-06-09 08:11:42 +01002025{
2026 struct device *dev = &adev->dev;
2027 struct pl022_ssp_controller *platform_info = adev->dev.platform_data;
2028 struct spi_master *master;
2029 struct pl022 *pl022 = NULL; /*Data for this driver */
2030 int status = 0;
2031
2032 dev_info(&adev->dev,
2033 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
2034 if (platform_info == NULL) {
2035 dev_err(&adev->dev, "probe - no platform data supplied\n");
2036 status = -ENODEV;
2037 goto err_no_pdata;
2038 }
2039
2040 /* Allocate master with space for data */
2041 master = spi_alloc_master(dev, sizeof(struct pl022));
2042 if (master == NULL) {
2043 dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
2044 status = -ENOMEM;
2045 goto err_no_master;
2046 }
2047
2048 pl022 = spi_master_get_devdata(master);
2049 pl022->master = master;
2050 pl022->master_info = platform_info;
2051 pl022->adev = adev;
2052 pl022->vendor = id->data;
2053
2054 /*
2055 * Bus Number Which has been Assigned to this SSP controller
2056 * on this board
2057 */
2058 master->bus_num = platform_info->bus_id;
2059 master->num_chipselect = platform_info->num_chipselect;
2060 master->cleanup = pl022_cleanup;
2061 master->setup = pl022_setup;
2062 master->transfer = pl022_transfer;
2063
Kevin Wellsbde435a2010-09-16 06:18:50 -07002064 /*
2065 * Supports mode 0-3, loopback, and active low CS. Transfers are
2066 * always MS bit first on the original pl022.
2067 */
2068 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
2069 if (pl022->vendor->extended_cr)
2070 master->mode_bits |= SPI_LSB_FIRST;
2071
Linus Walleijb43d65f2009-06-09 08:11:42 +01002072 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
2073
2074 status = amba_request_regions(adev, NULL);
2075 if (status)
2076 goto err_no_ioregion;
2077
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09002078 pl022->phybase = adev->res.start;
Linus Walleijb43d65f2009-06-09 08:11:42 +01002079 pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res));
2080 if (pl022->virtbase == NULL) {
2081 status = -ENOMEM;
2082 goto err_no_ioremap;
2083 }
2084 printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n",
2085 adev->res.start, pl022->virtbase);
2086
2087 pl022->clk = clk_get(&adev->dev, NULL);
2088 if (IS_ERR(pl022->clk)) {
2089 status = PTR_ERR(pl022->clk);
2090 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
2091 goto err_no_clk;
2092 }
2093
2094 /* Disable SSP */
Linus Walleijb43d65f2009-06-09 08:11:42 +01002095 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
2096 SSP_CR1(pl022->virtbase));
2097 load_ssp_default_config(pl022);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002098
2099 status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022",
2100 pl022);
2101 if (status < 0) {
2102 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
2103 goto err_no_irq;
2104 }
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09002105
2106 /* Get DMA channels */
2107 if (platform_info->enable_dma) {
2108 status = pl022_dma_probe(pl022);
2109 if (status != 0)
2110 goto err_no_dma;
2111 }
2112
Linus Walleijb43d65f2009-06-09 08:11:42 +01002113 /* Initialize and start queue */
2114 status = init_queue(pl022);
2115 if (status != 0) {
2116 dev_err(&adev->dev, "probe - problem initializing queue\n");
2117 goto err_init_queue;
2118 }
2119 status = start_queue(pl022);
2120 if (status != 0) {
2121 dev_err(&adev->dev, "probe - problem starting queue\n");
2122 goto err_start_queue;
2123 }
2124 /* Register with the SPI framework */
2125 amba_set_drvdata(adev, pl022);
2126 status = spi_register_master(master);
2127 if (status != 0) {
2128 dev_err(&adev->dev,
2129 "probe - problem registering spi master\n");
2130 goto err_spi_register;
2131 }
2132 dev_dbg(dev, "probe succeded\n");
Linus Walleij808f1032011-02-08 13:03:32 +01002133 /*
2134 * Disable the silicon block pclk and any voltage domain and just
2135 * power it up and clock it when it's needed
2136 */
Linus Walleij545074f2010-08-21 11:07:36 +02002137 amba_pclk_disable(adev);
Linus Walleij808f1032011-02-08 13:03:32 +01002138 amba_vcore_disable(adev);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002139 return 0;
2140
2141 err_spi_register:
2142 err_start_queue:
2143 err_init_queue:
2144 destroy_queue(pl022);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09002145 pl022_dma_remove(pl022);
2146 err_no_dma:
Linus Walleijb43d65f2009-06-09 08:11:42 +01002147 free_irq(adev->irq[0], pl022);
2148 err_no_irq:
2149 clk_put(pl022->clk);
2150 err_no_clk:
2151 iounmap(pl022->virtbase);
2152 err_no_ioremap:
2153 amba_release_regions(adev);
2154 err_no_ioregion:
2155 spi_master_put(master);
2156 err_no_master:
2157 err_no_pdata:
2158 return status;
2159}
2160
Kevin Wellsb4225882010-07-27 16:39:30 +00002161static int __devexit
Linus Walleijb43d65f2009-06-09 08:11:42 +01002162pl022_remove(struct amba_device *adev)
2163{
2164 struct pl022 *pl022 = amba_get_drvdata(adev);
2165 int status = 0;
2166 if (!pl022)
2167 return 0;
2168
2169 /* Remove the queue */
2170 status = destroy_queue(pl022);
2171 if (status != 0) {
2172 dev_err(&adev->dev,
2173 "queue remove failed (%d)\n", status);
2174 return status;
2175 }
2176 load_ssp_default_config(pl022);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09002177 pl022_dma_remove(pl022);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002178 free_irq(adev->irq[0], pl022);
2179 clk_disable(pl022->clk);
2180 clk_put(pl022->clk);
2181 iounmap(pl022->virtbase);
2182 amba_release_regions(adev);
2183 tasklet_disable(&pl022->pump_transfers);
2184 spi_unregister_master(pl022->master);
2185 spi_master_put(pl022->master);
2186 amba_set_drvdata(adev, NULL);
2187 dev_dbg(&adev->dev, "remove succeded\n");
2188 return 0;
2189}
2190
2191#ifdef CONFIG_PM
2192static int pl022_suspend(struct amba_device *adev, pm_message_t state)
2193{
2194 struct pl022 *pl022 = amba_get_drvdata(adev);
2195 int status = 0;
2196
2197 status = stop_queue(pl022);
2198 if (status) {
2199 dev_warn(&adev->dev, "suspend cannot stop queue\n");
2200 return status;
2201 }
2202
Linus Walleij808f1032011-02-08 13:03:32 +01002203 amba_vcore_enable(adev);
Linus Walleij545074f2010-08-21 11:07:36 +02002204 amba_pclk_enable(adev);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002205 load_ssp_default_config(pl022);
Linus Walleij545074f2010-08-21 11:07:36 +02002206 amba_pclk_disable(adev);
Linus Walleij808f1032011-02-08 13:03:32 +01002207 amba_vcore_disable(adev);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002208 dev_dbg(&adev->dev, "suspended\n");
2209 return 0;
2210}
2211
2212static int pl022_resume(struct amba_device *adev)
2213{
2214 struct pl022 *pl022 = amba_get_drvdata(adev);
2215 int status = 0;
2216
2217 /* Start the queue running */
2218 status = start_queue(pl022);
2219 if (status)
2220 dev_err(&adev->dev, "problem starting queue (%d)\n", status);
2221 else
2222 dev_dbg(&adev->dev, "resumed\n");
2223
2224 return status;
2225}
2226#else
2227#define pl022_suspend NULL
2228#define pl022_resume NULL
2229#endif /* CONFIG_PM */
2230
2231static struct vendor_data vendor_arm = {
2232 .fifodepth = 8,
2233 .max_bpw = 16,
2234 .unidir = false,
Linus Walleij556f4ae2010-05-05 09:28:15 +00002235 .extended_cr = false,
Linus Walleij781c7b12010-05-07 08:40:53 +00002236 .pl023 = false,
Philippe Langlais06fb01f2011-03-23 11:05:16 +01002237 .loopback = true,
Linus Walleijb43d65f2009-06-09 08:11:42 +01002238};
2239
2240
2241static struct vendor_data vendor_st = {
2242 .fifodepth = 32,
2243 .max_bpw = 32,
2244 .unidir = false,
Linus Walleij556f4ae2010-05-05 09:28:15 +00002245 .extended_cr = true,
Linus Walleij781c7b12010-05-07 08:40:53 +00002246 .pl023 = false,
Philippe Langlais06fb01f2011-03-23 11:05:16 +01002247 .loopback = true,
Linus Walleij781c7b12010-05-07 08:40:53 +00002248};
2249
2250static struct vendor_data vendor_st_pl023 = {
2251 .fifodepth = 32,
2252 .max_bpw = 32,
2253 .unidir = false,
2254 .extended_cr = true,
2255 .pl023 = true,
Philippe Langlais06fb01f2011-03-23 11:05:16 +01002256 .loopback = false,
2257};
2258
2259static struct vendor_data vendor_db5500_pl023 = {
2260 .fifodepth = 32,
2261 .max_bpw = 32,
2262 .unidir = false,
2263 .extended_cr = true,
2264 .pl023 = true,
2265 .loopback = true,
Linus Walleijb43d65f2009-06-09 08:11:42 +01002266};
2267
2268static struct amba_id pl022_ids[] = {
2269 {
2270 /*
2271 * ARM PL022 variant, this has a 16bit wide
2272 * and 8 locations deep TX/RX FIFO
2273 */
2274 .id = 0x00041022,
2275 .mask = 0x000fffff,
2276 .data = &vendor_arm,
2277 },
2278 {
2279 /*
2280 * ST Micro derivative, this has 32bit wide
2281 * and 32 locations deep TX/RX FIFO
2282 */
Srinidhi Kasagare89e04f2009-10-05 06:13:53 +01002283 .id = 0x01080022,
Linus Walleijb43d65f2009-06-09 08:11:42 +01002284 .mask = 0xffffffff,
2285 .data = &vendor_st,
2286 },
Linus Walleij781c7b12010-05-07 08:40:53 +00002287 {
2288 /*
2289 * ST-Ericsson derivative "PL023" (this is not
2290 * an official ARM number), this is a PL022 SSP block
2291 * stripped to SPI mode only, it has 32bit wide
2292 * and 32 locations deep TX/RX FIFO but no extended
2293 * CR0/CR1 register
2294 */
2295 .id = 0x00080023,
2296 .mask = 0xffffffff,
2297 .data = &vendor_st_pl023,
2298 },
Philippe Langlais06fb01f2011-03-23 11:05:16 +01002299 {
2300 .id = 0x10080023,
2301 .mask = 0xffffffff,
2302 .data = &vendor_db5500_pl023,
2303 },
Linus Walleijb43d65f2009-06-09 08:11:42 +01002304 { 0, 0 },
2305};
2306
2307static struct amba_driver pl022_driver = {
2308 .drv = {
2309 .name = "ssp-pl022",
2310 },
2311 .id_table = pl022_ids,
2312 .probe = pl022_probe,
Kevin Wellsb4225882010-07-27 16:39:30 +00002313 .remove = __devexit_p(pl022_remove),
Linus Walleijb43d65f2009-06-09 08:11:42 +01002314 .suspend = pl022_suspend,
2315 .resume = pl022_resume,
2316};
2317
2318
2319static int __init pl022_init(void)
2320{
2321 return amba_driver_register(&pl022_driver);
2322}
2323
Linus Walleij25c8e032010-09-06 11:02:12 +02002324subsys_initcall(pl022_init);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002325
2326static void __exit pl022_exit(void)
2327{
2328 amba_driver_unregister(&pl022_driver);
2329}
2330
2331module_exit(pl022_exit);
2332
2333MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
2334MODULE_DESCRIPTION("PL022 SSP Controller Driver");
2335MODULE_LICENSE("GPL");