Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1 | /* |
Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 2 | * Blackfin low-level cache routines |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 3 | * |
Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 4 | * Copyright 2004-2009 Analog Devices Inc. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 5 | * |
Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 6 | * Licensed under the GPL-2 or later. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef _BLACKFIN_CACHEFLUSH_H |
| 10 | #define _BLACKFIN_CACHEFLUSH_H |
| 11 | |
Mike Frysinger | 5d89137 | 2009-04-10 20:52:08 +0000 | [diff] [blame] | 12 | #include <asm/blackfin.h> /* for SSYNC() */ |
Mike Frysinger | bbc51e9 | 2009-10-09 07:34:00 +0000 | [diff] [blame] | 13 | #include <asm/sections.h> /* for _ramend */ |
Mike Frysinger | 5d89137 | 2009-04-10 20:52:08 +0000 | [diff] [blame] | 14 | |
Mike Frysinger | 8fb4f8f | 2008-10-16 23:39:12 +0800 | [diff] [blame] | 15 | extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address); |
| 16 | extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address); |
| 17 | extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address); |
| 18 | extern void blackfin_dflush_page(void *page); |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 19 | extern void blackfin_invalidate_entire_dcache(void); |
Sonic Zhang | 47e9ded | 2009-06-10 08:57:08 +0000 | [diff] [blame] | 20 | extern void blackfin_invalidate_entire_icache(void); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 21 | |
| 22 | #define flush_dcache_mmap_lock(mapping) do { } while (0) |
| 23 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) |
| 24 | #define flush_cache_mm(mm) do { } while (0) |
| 25 | #define flush_cache_range(vma, start, end) do { } while (0) |
| 26 | #define flush_cache_page(vma, vmaddr) do { } while (0) |
| 27 | #define flush_cache_vmap(start, end) do { } while (0) |
| 28 | #define flush_cache_vunmap(start, end) do { } while (0) |
| 29 | |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 30 | #ifdef CONFIG_SMP |
| 31 | #define flush_icache_range_others(start, end) \ |
| 32 | smp_icache_flush_range_others((start), (end)) |
| 33 | #else |
| 34 | #define flush_icache_range_others(start, end) do { } while (0) |
| 35 | #endif |
| 36 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 37 | static inline void flush_icache_range(unsigned start, unsigned end) |
| 38 | { |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 39 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) |
Mike Frysinger | 5d89137 | 2009-04-10 20:52:08 +0000 | [diff] [blame] | 40 | blackfin_dcache_flush_range(start, end); |
| 41 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 42 | |
Mike Frysinger | 5d89137 | 2009-04-10 20:52:08 +0000 | [diff] [blame] | 43 | /* Make sure all write buffers in the data side of the core |
| 44 | * are flushed before trying to invalidate the icache. This |
| 45 | * needs to be after the data flush and before the icache |
| 46 | * flush so that the SSYNC does the right thing in preventing |
| 47 | * the instruction prefetcher from hitting things in cached |
| 48 | * memory at the wrong time -- it runs much further ahead than |
| 49 | * the pipeline. |
| 50 | */ |
| 51 | SSYNC(); |
| 52 | #if defined(CONFIG_BFIN_ICACHE) |
| 53 | blackfin_icache_flush_range(start, end); |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 54 | flush_icache_range_others(start, end); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 55 | #endif |
| 56 | } |
| 57 | |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 58 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ |
| 59 | do { memcpy(dst, src, len); \ |
| 60 | flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \ |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 61 | } while (0) |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 62 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 63 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len) |
| 64 | |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 65 | #if defined(CONFIG_BFIN_DCACHE) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 66 | # define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end)) |
| 67 | #else |
| 68 | # define invalidate_dcache_range(start,end) do { } while (0) |
| 69 | #endif |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 70 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 71 | # define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end)) |
Ilya Loginov | 2d4dc89 | 2009-11-26 09:16:19 +0100 | [diff] [blame] | 72 | #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 73 | # define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 74 | #else |
| 75 | # define flush_dcache_range(start,end) do { } while (0) |
Ilya Loginov | 2d4dc89 | 2009-11-26 09:16:19 +0100 | [diff] [blame] | 76 | #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 77 | # define flush_dcache_page(page) do { } while (0) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 78 | #endif |
| 79 | |
Mike Frysinger | 04be80e | 2008-10-16 23:33:53 +0800 | [diff] [blame] | 80 | extern unsigned long reserved_mem_dcache_on; |
| 81 | extern unsigned long reserved_mem_icache_on; |
| 82 | |
Jie Zhang | 67834fa | 2009-06-10 06:26:26 +0000 | [diff] [blame] | 83 | static inline int bfin_addr_dcacheable(unsigned long addr) |
Mike Frysinger | 04be80e | 2008-10-16 23:33:53 +0800 | [diff] [blame] | 84 | { |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 85 | #ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE |
Mike Frysinger | 04be80e | 2008-10-16 23:33:53 +0800 | [diff] [blame] | 86 | if (addr < (_ramend - DMA_UNCACHED_REGION)) |
| 87 | return 1; |
| 88 | #endif |
| 89 | |
| 90 | if (reserved_mem_dcache_on && |
| 91 | addr >= _ramend && addr < physical_mem_end) |
| 92 | return 1; |
| 93 | |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 94 | #ifdef CONFIG_BFIN_L2_DCACHEABLE |
Mike Frysinger | f339f46 | 2009-05-19 12:58:13 +0000 | [diff] [blame] | 95 | if (addr >= L2_START && addr < L2_START + L2_LENGTH) |
| 96 | return 1; |
| 97 | #endif |
| 98 | |
Mike Frysinger | 04be80e | 2008-10-16 23:33:53 +0800 | [diff] [blame] | 99 | return 0; |
| 100 | } |
| 101 | |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 102 | #endif /* _BLACKFIN_ICACHEFLUSH_H */ |