| Linus Walleij | f55be1b | 2011-09-28 09:11:30 +0100 | [diff] [blame] | 1 | #ifndef __PLAT_PXA_GPIO_H |
| 2 | #define __PLAT_PXA_GPIO_H |
| 3 | |
| 4 | struct irq_data; |
| 5 | |
| 6 | /* |
| 7 | * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with |
| 8 | * one set of registers. The register offsets are organized below: |
| 9 | * |
| 10 | * GPLR GPDR GPSR GPCR GRER GFER GEDR |
| 11 | * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 |
| 12 | * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C |
| 13 | * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 |
| 14 | * |
| 15 | * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 |
| 16 | * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C |
| 17 | * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 |
| 18 | * |
| 19 | * NOTE: |
| 20 | * BANK 3 is only available on PXA27x and later processors. |
| 21 | * BANK 4 and 5 are only available on PXA935 |
| 22 | */ |
| 23 | |
| 24 | #define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n)) |
| 25 | |
| 26 | #define GPLR_OFFSET 0x00 |
| 27 | #define GPDR_OFFSET 0x0C |
| 28 | #define GPSR_OFFSET 0x18 |
| 29 | #define GPCR_OFFSET 0x24 |
| 30 | #define GRER_OFFSET 0x30 |
| 31 | #define GFER_OFFSET 0x3C |
| 32 | #define GEDR_OFFSET 0x48 |
| 33 | |
| 34 | /* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85). |
| 35 | * Those cases currently cause holes in the GPIO number space, the |
| 36 | * actual number of the last GPIO is recorded by 'pxa_last_gpio'. |
| 37 | */ |
| 38 | extern int pxa_last_gpio; |
| 39 | |
| 40 | typedef int (*set_wake_t)(struct irq_data *d, unsigned int on); |
| 41 | |
| 42 | extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn); |
| 43 | |
| 44 | #endif /* __PLAT_PXA_GPIO_H */ |