Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Unmaintained SGI Visual Workstation support. |
| 3 | * Split out from setup.c by davej@suse.de |
| 4 | */ |
| 5 | |
| 6 | #include <linux/smp.h> |
| 7 | #include <linux/init.h> |
| 8 | #include <linux/irq.h> |
| 9 | #include <linux/interrupt.h> |
| 10 | |
| 11 | #include <asm/fixmap.h> |
| 12 | #include <asm/arch_hooks.h> |
| 13 | #include <asm/io.h> |
| 14 | #include "cobalt.h" |
| 15 | #include "piix4.h" |
| 16 | |
Tom Duffy | 46bdac9 | 2005-08-07 09:42:23 -0700 | [diff] [blame^] | 17 | int no_broadcast; |
| 18 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 19 | char visws_board_type = -1; |
| 20 | char visws_board_rev = -1; |
| 21 | |
| 22 | void __init visws_get_board_type_and_rev(void) |
| 23 | { |
| 24 | int raw; |
| 25 | |
| 26 | visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG) |
| 27 | >> PIIX_GPI_BD_SHIFT; |
| 28 | /* |
| 29 | * Get Board rev. |
| 30 | * First, we have to initialize the 307 part to allow us access |
| 31 | * to the GPIO registers. Let's map them at 0x0fc0 which is right |
| 32 | * after the PIIX4 PM section. |
| 33 | */ |
| 34 | outb_p(SIO_DEV_SEL, SIO_INDEX); |
| 35 | outb_p(SIO_GP_DEV, SIO_DATA); /* Talk to GPIO regs. */ |
| 36 | |
| 37 | outb_p(SIO_DEV_MSB, SIO_INDEX); |
| 38 | outb_p(SIO_GP_MSB, SIO_DATA); /* MSB of GPIO base address */ |
| 39 | |
| 40 | outb_p(SIO_DEV_LSB, SIO_INDEX); |
| 41 | outb_p(SIO_GP_LSB, SIO_DATA); /* LSB of GPIO base address */ |
| 42 | |
| 43 | outb_p(SIO_DEV_ENB, SIO_INDEX); |
| 44 | outb_p(1, SIO_DATA); /* Enable GPIO registers. */ |
| 45 | |
| 46 | /* |
| 47 | * Now, we have to map the power management section to write |
| 48 | * a bit which enables access to the GPIO registers. |
| 49 | * What lunatic came up with this shit? |
| 50 | */ |
| 51 | outb_p(SIO_DEV_SEL, SIO_INDEX); |
| 52 | outb_p(SIO_PM_DEV, SIO_DATA); /* Talk to GPIO regs. */ |
| 53 | |
| 54 | outb_p(SIO_DEV_MSB, SIO_INDEX); |
| 55 | outb_p(SIO_PM_MSB, SIO_DATA); /* MSB of PM base address */ |
| 56 | |
| 57 | outb_p(SIO_DEV_LSB, SIO_INDEX); |
| 58 | outb_p(SIO_PM_LSB, SIO_DATA); /* LSB of PM base address */ |
| 59 | |
| 60 | outb_p(SIO_DEV_ENB, SIO_INDEX); |
| 61 | outb_p(1, SIO_DATA); /* Enable PM registers. */ |
| 62 | |
| 63 | /* |
| 64 | * Now, write the PM register which enables the GPIO registers. |
| 65 | */ |
| 66 | outb_p(SIO_PM_FER2, SIO_PM_INDEX); |
| 67 | outb_p(SIO_PM_GP_EN, SIO_PM_DATA); |
| 68 | |
| 69 | /* |
| 70 | * Now, initialize the GPIO registers. |
| 71 | * We want them all to be inputs which is the |
| 72 | * power on default, so let's leave them alone. |
| 73 | * So, let's just read the board rev! |
| 74 | */ |
| 75 | raw = inb_p(SIO_GP_DATA1); |
| 76 | raw &= 0x7f; /* 7 bits of valid board revision ID. */ |
| 77 | |
| 78 | if (visws_board_type == VISWS_320) { |
| 79 | if (raw < 0x6) { |
| 80 | visws_board_rev = 4; |
| 81 | } else if (raw < 0xc) { |
| 82 | visws_board_rev = 5; |
| 83 | } else { |
| 84 | visws_board_rev = 6; |
| 85 | } |
| 86 | } else if (visws_board_type == VISWS_540) { |
| 87 | visws_board_rev = 2; |
| 88 | } else { |
| 89 | visws_board_rev = raw; |
| 90 | } |
| 91 | |
| 92 | printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n", |
| 93 | (visws_board_type == VISWS_320 ? "320" : |
| 94 | (visws_board_type == VISWS_540 ? "540" : |
| 95 | "unknown")), visws_board_rev); |
| 96 | } |
| 97 | |
| 98 | void __init pre_intr_init_hook(void) |
| 99 | { |
| 100 | init_VISWS_APIC_irqs(); |
| 101 | } |
| 102 | |
| 103 | void __init intr_init_hook(void) |
| 104 | { |
| 105 | #ifdef CONFIG_X86_LOCAL_APIC |
| 106 | apic_intr_init(); |
| 107 | #endif |
| 108 | } |
| 109 | |
| 110 | void __init pre_setup_arch_hook() |
| 111 | { |
| 112 | visws_get_board_type_and_rev(); |
| 113 | } |
| 114 | |
| 115 | static struct irqaction irq0 = { |
| 116 | .handler = timer_interrupt, |
| 117 | .flags = SA_INTERRUPT, |
| 118 | .name = "timer", |
| 119 | }; |
| 120 | |
| 121 | void __init time_init_hook(void) |
| 122 | { |
| 123 | printk(KERN_INFO "Starting Cobalt Timer system clock\n"); |
| 124 | |
| 125 | /* Set the countdown value */ |
| 126 | co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ); |
| 127 | |
| 128 | /* Start the timer */ |
| 129 | co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN); |
| 130 | |
| 131 | /* Enable (unmask) the timer interrupt */ |
| 132 | co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK); |
| 133 | |
| 134 | /* Wire cpu IDT entry to s/w handler (and Cobalt APIC to IDT) */ |
| 135 | setup_irq(0, &irq0); |
| 136 | } |