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gerrit-public.fairphone.software / kernel / msm-4.9 / 4719d8f9356a9ea8287ebdac04d759482524e67c / . / arch / arm / boot / dts / imx23.dtsi
blob: 440ee9a4a158dd777defb38274ead1ecaf69241b [file] [log] [blame]
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]12#include "skeleton.dtsi"
13#include "imx23-pinfunc.h"
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]14
15/ {
16 interrupt-parent = <&icoll>;
17
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]18 aliases {
19 gpio0 = &gpio0;
20 gpio1 = &gpio1;
21 gpio2 = &gpio2;
Shawn Guoa4508392012-06-28 11:45:00 +0800[diff] [blame]22 serial0 = &auart0;
23 serial1 = &auart1;
Fabio Estevam6bf6eb02013-07-22 17:57:01 -0300[diff] [blame]24 spi0 = &ssp0;
25 spi1 = &ssp1;
Peter Chen1f35cc62013-12-20 15:52:05 +0800[diff] [blame]26 usbphy0 = &usbphy0;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]27 };
28
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]29 cpus {
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +0100[diff] [blame]30 #address-cells = <0>;
31 #size-cells = <0>;
32
33 cpu {
34 compatible = "arm,arm926ej-s";
35 device_type = "cpu";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]36 };
37 };
38
39 apb@80000000 {
40 compatible = "simple-bus";
41 #address-cells = <1>;
42 #size-cells = <1>;
43 reg = <0x80000000 0x80000>;
44 ranges;
45
46 apbh@80000000 {
47 compatible = "simple-bus";
48 #address-cells = <1>;
49 #size-cells = <1>;
50 reg = <0x80000000 0x40000>;
51 ranges;
52
53 icoll: interrupt-controller@80000000 {
Shawn Guo83a84ef2012-08-20 21:34:56 +0800[diff] [blame]54 compatible = "fsl,imx23-icoll", "fsl,icoll";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]55 interrupt-controller;
56 #interrupt-cells = <1>;
57 reg = <0x80000000 0x2000>;
58 };
59
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]60 dma_apbh: dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800[diff] [blame]61 compatible = "fsl,imx23-dma-apbh";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]62 reg = <0x80004000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]63 interrupts = <0 14 20 0
64 13 13 13 13>;
65 interrupt-names = "empty", "ssp0", "ssp1", "empty",
66 "gpmi0", "gpmi1", "gpmi2", "gpmi3";
67 #dma-cells = <1>;
68 dma-channels = <8>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]69 clocks = <&clks 15>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]70 };
71
72 ecc@80008000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]73 reg = <0x80008000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]74 status = "disabled";
75 };
76
Marek Vasuta217c462012-06-09 01:21:55 +0200[diff] [blame]77 gpmi-nand@8000c000 {
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]78 compatible = "fsl,imx23-gpmi-nand";
79 #address-cells = <1>;
80 #size-cells = <1>;
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]81 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]82 reg-names = "gpmi-nand", "bch";
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]83 interrupts = <56>;
84 interrupt-names = "bch";
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]85 clocks = <&clks 34>;
Huang Shijieb6442552012-10-10 18:27:09 +0800[diff] [blame]86 clock-names = "gpmi_io";
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]87 dmas = <&dma_apbh 4>;
88 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]89 status = "disabled";
90 };
91
92 ssp0: ssp@80010000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]93 reg = <0x80010000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]94 interrupts = <15>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]95 clocks = <&clks 33>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]96 dmas = <&dma_apbh 1>;
97 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]98 status = "disabled";
99 };
100
101 etm@80014000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]102 reg = <0x80014000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]103 status = "disabled";
104 };
105
106 pinctrl@80018000 {
107 #address-cells = <1>;
108 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]109 compatible = "fsl,imx23-pinctrl", "simple-bus";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]110 reg = <0x80018000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]111
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]112 gpio0: gpio@0 {
113 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]114 reg = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]115 interrupts = <16>;
116 gpio-controller;
117 #gpio-cells = <2>;
118 interrupt-controller;
119 #interrupt-cells = <2>;
120 };
121
122 gpio1: gpio@1 {
123 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]124 reg = <1>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]125 interrupts = <17>;
126 gpio-controller;
127 #gpio-cells = <2>;
128 interrupt-controller;
129 #interrupt-cells = <2>;
130 };
131
132 gpio2: gpio@2 {
133 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]134 reg = <2>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]135 interrupts = <18>;
136 gpio-controller;
137 #gpio-cells = <2>;
138 interrupt-controller;
139 #interrupt-cells = <2>;
140 };
141
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]142 duart_pins_a: duart@0 {
143 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]144 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]145 MX23_PAD_PWM0__DUART_RX
146 MX23_PAD_PWM1__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]147 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]148 fsl,drive-strength = <MXS_DRIVE_4mA>;
149 fsl,voltage = <MXS_VOLTAGE_HIGH>;
150 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]151 };
Shawn Guobe1ce302012-05-06 16:29:36 +0800[diff] [blame]152
Shawn Guoa4508392012-06-28 11:45:00 +0800[diff] [blame]153 auart0_pins_a: auart0@0 {
154 reg = <0>;
155 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]156 MX23_PAD_AUART1_RX__AUART1_RX
157 MX23_PAD_AUART1_TX__AUART1_TX
158 MX23_PAD_AUART1_CTS__AUART1_CTS
159 MX23_PAD_AUART1_RTS__AUART1_RTS
Shawn Guoa4508392012-06-28 11:45:00 +0800[diff] [blame]160 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]161 fsl,drive-strength = <MXS_DRIVE_4mA>;
162 fsl,voltage = <MXS_VOLTAGE_HIGH>;
163 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoa4508392012-06-28 11:45:00 +0800[diff] [blame]164 };
165
Fabio Estevam98916a22012-07-30 16:33:44 -0300[diff] [blame]166 auart0_2pins_a: auart0-2pins@0 {
167 reg = <0>;
168 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]169 MX23_PAD_I2C_SCL__AUART1_TX
170 MX23_PAD_I2C_SDA__AUART1_RX
Fabio Estevam98916a22012-07-30 16:33:44 -0300[diff] [blame]171 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]172 fsl,drive-strength = <MXS_DRIVE_4mA>;
173 fsl,voltage = <MXS_VOLTAGE_HIGH>;
174 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam98916a22012-07-30 16:33:44 -0300[diff] [blame]175 };
176
Marek Vasutd33c7312016-06-09 21:43:11 +0200[diff] [blame]177 auart1_2pins_a: auart1-2pins@0 {
178 reg = <0>;
179 fsl,pinmux-ids = <
180 MX23_PAD_GPMI_D14__AUART2_RX
181 MX23_PAD_GPMI_D15__AUART2_TX
182 >;
183 fsl,drive-strength = <MXS_DRIVE_4mA>;
184 fsl,voltage = <MXS_VOLTAGE_HIGH>;
185 fsl,pull-up = <MXS_PULL_DISABLE>;
186 };
187
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]188 gpmi_pins_a: gpmi-nand@0 {
189 reg = <0>;
190 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]191 MX23_PAD_GPMI_D00__GPMI_D00
192 MX23_PAD_GPMI_D01__GPMI_D01
193 MX23_PAD_GPMI_D02__GPMI_D02
194 MX23_PAD_GPMI_D03__GPMI_D03
195 MX23_PAD_GPMI_D04__GPMI_D04
196 MX23_PAD_GPMI_D05__GPMI_D05
197 MX23_PAD_GPMI_D06__GPMI_D06
198 MX23_PAD_GPMI_D07__GPMI_D07
199 MX23_PAD_GPMI_CLE__GPMI_CLE
200 MX23_PAD_GPMI_ALE__GPMI_ALE
201 MX23_PAD_GPMI_RDY0__GPMI_RDY0
202 MX23_PAD_GPMI_RDY1__GPMI_RDY1
203 MX23_PAD_GPMI_WPN__GPMI_WPN
204 MX23_PAD_GPMI_WRN__GPMI_WRN
205 MX23_PAD_GPMI_RDN__GPMI_RDN
206 MX23_PAD_GPMI_CE1N__GPMI_CE1N
207 MX23_PAD_GPMI_CE0N__GPMI_CE0N
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]208 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]209 fsl,drive-strength = <MXS_DRIVE_4mA>;
210 fsl,voltage = <MXS_VOLTAGE_HIGH>;
211 fsl,pull-up = <MXS_PULL_DISABLE>;
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]212 };
213
214 gpmi_pins_fixup: gpmi-pins-fixup {
215 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]216 MX23_PAD_GPMI_WPN__GPMI_WPN
217 MX23_PAD_GPMI_WRN__GPMI_WRN
218 MX23_PAD_GPMI_RDN__GPMI_RDN
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]219 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]220 fsl,drive-strength = <MXS_DRIVE_12mA>;
Huang Shijieb9f25f82012-07-03 12:58:13 +0800[diff] [blame]221 };
222
Shawn Guo72beaba2012-06-28 11:44:59 +0800[diff] [blame]223 mmc0_4bit_pins_a: mmc0-4bit@0 {
224 reg = <0>;
225 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]226 MX23_PAD_SSP1_DATA0__SSP1_DATA0
227 MX23_PAD_SSP1_DATA1__SSP1_DATA1
228 MX23_PAD_SSP1_DATA2__SSP1_DATA2
229 MX23_PAD_SSP1_DATA3__SSP1_DATA3
230 MX23_PAD_SSP1_CMD__SSP1_CMD
231 MX23_PAD_SSP1_SCK__SSP1_SCK
Shawn Guo72beaba2012-06-28 11:44:59 +0800[diff] [blame]232 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]233 fsl,drive-strength = <MXS_DRIVE_8mA>;
234 fsl,voltage = <MXS_VOLTAGE_HIGH>;
235 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo72beaba2012-06-28 11:44:59 +0800[diff] [blame]236 };
237
Shawn Guobe1ce302012-05-06 16:29:36 +0800[diff] [blame]238 mmc0_8bit_pins_a: mmc0-8bit@0 {
239 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]240 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]241 MX23_PAD_SSP1_DATA0__SSP1_DATA0
242 MX23_PAD_SSP1_DATA1__SSP1_DATA1
243 MX23_PAD_SSP1_DATA2__SSP1_DATA2
244 MX23_PAD_SSP1_DATA3__SSP1_DATA3
245 MX23_PAD_GPMI_D08__SSP1_DATA4
246 MX23_PAD_GPMI_D09__SSP1_DATA5
247 MX23_PAD_GPMI_D10__SSP1_DATA6
248 MX23_PAD_GPMI_D11__SSP1_DATA7
249 MX23_PAD_SSP1_CMD__SSP1_CMD
250 MX23_PAD_SSP1_DETECT__SSP1_DETECT
251 MX23_PAD_SSP1_SCK__SSP1_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]252 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]253 fsl,drive-strength = <MXS_DRIVE_8mA>;
254 fsl,voltage = <MXS_VOLTAGE_HIGH>;
255 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guobe1ce302012-05-06 16:29:36 +0800[diff] [blame]256 };
257
258 mmc0_pins_fixup: mmc0-pins-fixup {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]259 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]260 MX23_PAD_SSP1_DETECT__SSP1_DETECT
261 MX23_PAD_SSP1_SCK__SSP1_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]262 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]263 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guobe1ce302012-05-06 16:29:36 +0800[diff] [blame]264 };
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]265
Marek Vasut1ebcb162016-06-09 21:43:10 +0200[diff] [blame]266 mmc1_4bit_pins_a: mmc1-4bit@0 {
267 reg = <0>;
268 fsl,pinmux-ids = <
269 MX23_PAD_GPMI_D00__SSP2_DATA0
270 MX23_PAD_GPMI_D01__SSP2_DATA1
271 MX23_PAD_GPMI_D02__SSP2_DATA2
272 MX23_PAD_GPMI_D03__SSP2_DATA3
273 MX23_PAD_GPMI_RDY1__SSP2_CMD
274 MX23_PAD_GPMI_WRN__SSP2_SCK
275 >;
276 fsl,drive-strength = <MXS_DRIVE_8mA>;
277 fsl,voltage = <MXS_VOLTAGE_HIGH>;
278 fsl,pull-up = <MXS_PULL_ENABLE>;
279 };
280
281 mmc1_8bit_pins_a: mmc1-8bit@0 {
282 reg = <0>;
283 fsl,pinmux-ids = <
284 MX23_PAD_GPMI_D00__SSP2_DATA0
285 MX23_PAD_GPMI_D01__SSP2_DATA1
286 MX23_PAD_GPMI_D02__SSP2_DATA2
287 MX23_PAD_GPMI_D03__SSP2_DATA3
288 MX23_PAD_GPMI_D04__SSP2_DATA4
289 MX23_PAD_GPMI_D05__SSP2_DATA5
290 MX23_PAD_GPMI_D06__SSP2_DATA6
291 MX23_PAD_GPMI_D07__SSP2_DATA7
292 MX23_PAD_GPMI_RDY1__SSP2_CMD
293 MX23_PAD_GPMI_WRN__SSP2_SCK
294 >;
295 fsl,drive-strength = <MXS_DRIVE_8mA>;
296 fsl,voltage = <MXS_VOLTAGE_HIGH>;
297 fsl,pull-up = <MXS_PULL_ENABLE>;
298 };
299
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]300 pwm2_pins_a: pwm2@0 {
301 reg = <0>;
302 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]303 MX23_PAD_PWM2__PWM2
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]304 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]305 fsl,drive-strength = <MXS_DRIVE_4mA>;
306 fsl,voltage = <MXS_VOLTAGE_HIGH>;
307 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]308 };
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]309
310 lcdif_24bit_pins_a: lcdif-24bit@0 {
311 reg = <0>;
312 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]313 MX23_PAD_LCD_D00__LCD_D00
314 MX23_PAD_LCD_D01__LCD_D01
315 MX23_PAD_LCD_D02__LCD_D02
316 MX23_PAD_LCD_D03__LCD_D03
317 MX23_PAD_LCD_D04__LCD_D04
318 MX23_PAD_LCD_D05__LCD_D05
319 MX23_PAD_LCD_D06__LCD_D06
320 MX23_PAD_LCD_D07__LCD_D07
321 MX23_PAD_LCD_D08__LCD_D08
322 MX23_PAD_LCD_D09__LCD_D09
323 MX23_PAD_LCD_D10__LCD_D10
324 MX23_PAD_LCD_D11__LCD_D11
325 MX23_PAD_LCD_D12__LCD_D12
326 MX23_PAD_LCD_D13__LCD_D13
327 MX23_PAD_LCD_D14__LCD_D14
328 MX23_PAD_LCD_D15__LCD_D15
329 MX23_PAD_LCD_D16__LCD_D16
330 MX23_PAD_LCD_D17__LCD_D17
331 MX23_PAD_GPMI_D08__LCD_D18
332 MX23_PAD_GPMI_D09__LCD_D19
333 MX23_PAD_GPMI_D10__LCD_D20
334 MX23_PAD_GPMI_D11__LCD_D21
335 MX23_PAD_GPMI_D12__LCD_D22
336 MX23_PAD_GPMI_D13__LCD_D23
337 MX23_PAD_LCD_DOTCK__LCD_DOTCK
338 MX23_PAD_LCD_ENABLE__LCD_ENABLE
339 MX23_PAD_LCD_HSYNC__LCD_HSYNC
340 MX23_PAD_LCD_VSYNC__LCD_VSYNC
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]341 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]342 fsl,drive-strength = <MXS_DRIVE_4mA>;
343 fsl,voltage = <MXS_VOLTAGE_HIGH>;
344 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]345 };
Fadil Berishaa0487862012-11-17 16:52:32 -0500[diff] [blame]346
347 spi2_pins_a: spi2@0 {
348 reg = <0>;
349 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]350 MX23_PAD_GPMI_WRN__SSP2_SCK
351 MX23_PAD_GPMI_RDY1__SSP2_CMD
352 MX23_PAD_GPMI_D00__SSP2_DATA0
353 MX23_PAD_GPMI_D03__SSP2_DATA3
Fadil Berishaa0487862012-11-17 16:52:32 -0500[diff] [blame]354 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]355 fsl,drive-strength = <MXS_DRIVE_8mA>;
356 fsl,voltage = <MXS_VOLTAGE_HIGH>;
357 fsl,pull-up = <MXS_PULL_ENABLE>;
Fadil Berishaa0487862012-11-17 16:52:32 -0500[diff] [blame]358 };
Harald Geyer71a34d82015-04-17 14:43:24 +0000[diff] [blame]359
360 i2c_pins_a: i2c@0 {
361 reg = <0>;
362 fsl,pinmux-ids = <
363 MX23_PAD_I2C_SCL__I2C_SCL
364 MX23_PAD_I2C_SDA__I2C_SDA
365 >;
366 fsl,drive-strength = <MXS_DRIVE_8mA>;
367 fsl,voltage = <MXS_VOLTAGE_HIGH>;
368 fsl,pull-up = <MXS_PULL_ENABLE>;
369 };
370
371 i2c_pins_b: i2c@1 {
372 reg = <1>;
373 fsl,pinmux-ids = <
374 MX23_PAD_LCD_ENABLE__I2C_SCL
375 MX23_PAD_LCD_HSYNC__I2C_SDA
376 >;
377 fsl,drive-strength = <MXS_DRIVE_8mA>;
378 fsl,voltage = <MXS_VOLTAGE_HIGH>;
379 fsl,pull-up = <MXS_PULL_ENABLE>;
380 };
381
382 i2c_pins_c: i2c@2 {
383 reg = <2>;
384 fsl,pinmux-ids = <
385 MX23_PAD_SSP1_DATA1__I2C_SCL
386 MX23_PAD_SSP1_DATA2__I2C_SDA
387 >;
388 fsl,drive-strength = <MXS_DRIVE_8mA>;
389 fsl,voltage = <MXS_VOLTAGE_HIGH>;
390 fsl,pull-up = <MXS_PULL_ENABLE>;
391 };
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]392 };
393
394 digctl@8001c000 {
Shawn Guo38d65902013-03-26 21:11:02 +0800[diff] [blame]395 compatible = "fsl,imx23-digctl";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]396 reg = <0x8001c000 2000>;
397 status = "disabled";
398 };
399
400 emi@80020000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]401 reg = <0x80020000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]402 status = "disabled";
403 };
404
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]405 dma_apbx: dma-apbx@80024000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800[diff] [blame]406 compatible = "fsl,imx23-dma-apbx";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]407 reg = <0x80024000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]408 interrupts = <7 5 9 26
409 19 0 25 23
410 60 58 9 0
411 0 0 0 0>;
412 interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c",
413 "saif0", "empty", "auart0-rx", "auart0-tx",
414 "auart1-rx", "auart1-tx", "saif1", "empty",
415 "empty", "empty", "empty", "empty";
416 #dma-cells = <1>;
417 dma-channels = <16>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]418 clocks = <&clks 16>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]419 };
420
421 dcp@80028000 {
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]422 compatible = "fsl,imx23-dcp";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]423 reg = <0x80028000 0x2000>;
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]424 interrupts = <53 54>;
425 status = "okay";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]426 };
427
428 pxp@8002a000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]429 reg = <0x8002a000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]430 status = "disabled";
431 };
432
433 ocotp@8002c000 {
Stefan Wahrena7be1e62015-08-12 22:21:56 +0000[diff] [blame]434 compatible = "fsl,imx23-ocotp", "fsl,ocotp";
435 #address-cells = <1>;
436 #size-cells = <1>;
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]437 reg = <0x8002c000 0x2000>;
Stefan Wahrena7be1e62015-08-12 22:21:56 +0000[diff] [blame]438 clocks = <&clks 15>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]439 };
440
441 axi-ahb@8002e000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]442 reg = <0x8002e000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]443 status = "disabled";
444 };
445
446 lcdif@80030000 {
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]447 compatible = "fsl,imx23-lcdif";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]448 reg = <0x80030000 2000>;
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]449 interrupts = <46 45>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]450 clocks = <&clks 38>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]451 status = "disabled";
452 };
453
454 ssp1: ssp@80034000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]455 reg = <0x80034000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]456 interrupts = <2>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]457 clocks = <&clks 33>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]458 dmas = <&dma_apbh 2>;
459 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]460 status = "disabled";
461 };
462
463 tvenc@80038000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]464 reg = <0x80038000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]465 status = "disabled";
466 };
467 };
468
469 apbx@80040000 {
470 compatible = "simple-bus";
471 #address-cells = <1>;
472 #size-cells = <1>;
473 reg = <0x80040000 0x40000>;
474 ranges;
475
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]476 clks: clkctrl@80040000 {
Shawn Guo8f7cf8812013-03-29 09:33:09 +0800[diff] [blame]477 compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]478 reg = <0x80040000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]479 #clock-cells = <1>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]480 };
481
482 saif0: saif@80042000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]483 reg = <0x80042000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]484 dmas = <&dma_apbx 4>;
485 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]486 status = "disabled";
487 };
488
489 power@80044000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]490 reg = <0x80044000 0x2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]491 status = "disabled";
492 };
493
494 saif1: saif@80046000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]495 reg = <0x80046000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]496 dmas = <&dma_apbx 10>;
497 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]498 status = "disabled";
499 };
500
501 audio-out@80048000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]502 reg = <0x80048000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]503 dmas = <&dma_apbx 1>;
504 dma-names = "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]505 status = "disabled";
506 };
507
508 audio-in@8004c000 {
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]509 reg = <0x8004c000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]510 dmas = <&dma_apbx 0>;
511 dma-names = "rx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]512 status = "disabled";
513 };
514
Alexandre Bellonibd798f92013-12-18 19:50:56 +0100[diff] [blame]515 lradc: lradc@80050000 {
Marek Vasut1f451882013-01-21 20:05:00 +0000[diff] [blame]516 compatible = "fsl,imx23-lradc";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]517 reg = <0x80050000 0x2000>;
Marek Vasut1f451882013-01-21 20:05:00 +0000[diff] [blame]518 interrupts = <36 37 38 39 40 41 42 43 44>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]519 status = "disabled";
Juergen Beisert18da7552013-09-23 15:36:00 +0100[diff] [blame]520 clocks = <&clks 26>;
Stefan Wahrene8e94ed2015-06-02 22:03:28 +0000[diff] [blame]521 #io-channel-cells = <1>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]522 };
523
524 spdif@80054000 {
525 reg = <0x80054000 2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]526 dmas = <&dma_apbx 2>;
527 dma-names = "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]528 status = "disabled";
529 };
530
Harald Geyer71a34d82015-04-17 14:43:24 +0000[diff] [blame]531 i2c: i2c@80058000 {
532 #address-cells = <1>;
533 #size-cells = <0>;
534 compatible = "fsl,imx23-i2c";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]535 reg = <0x80058000 0x2000>;
Harald Geyer71a34d82015-04-17 14:43:24 +0000[diff] [blame]536 interrupts = <27>;
537 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]538 dmas = <&dma_apbx 3>;
539 dma-names = "rx-tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]540 status = "disabled";
541 };
542
543 rtc@8005c000 {
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]544 compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]545 reg = <0x8005c000 0x2000>;
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]546 interrupts = <22>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]547 };
548
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]549 pwm: pwm@80064000 {
550 compatible = "fsl,imx23-pwm";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]551 reg = <0x80064000 0x2000>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]552 clocks = <&clks 30>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]553 #pwm-cells = <2>;
554 fsl,pwm-number = <5>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]555 status = "disabled";
556 };
557
558 timrot@80068000 {
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]559 compatible = "fsl,imx23-timrot", "fsl,timrot";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]560 reg = <0x80068000 0x2000>;
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]561 interrupts = <28 29 30 31>;
Shawn Guo2efb9502013-03-25 22:57:14 +0800[diff] [blame]562 clocks = <&clks 28>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]563 };
564
565 auart0: serial@8006c000 {
Shawn Guoa4508392012-06-28 11:45:00 +0800[diff] [blame]566 compatible = "fsl,imx23-auart";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]567 reg = <0x8006c000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]568 interrupts = <24>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]569 clocks = <&clks 32>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]570 dmas = <&dma_apbx 6>, <&dma_apbx 7>;
571 dma-names = "rx", "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]572 status = "disabled";
573 };
574
575 auart1: serial@8006e000 {
Shawn Guoa4508392012-06-28 11:45:00 +0800[diff] [blame]576 compatible = "fsl,imx23-auart";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]577 reg = <0x8006e000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]578 interrupts = <59>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]579 clocks = <&clks 32>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]580 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
581 dma-names = "rx", "tx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]582 status = "disabled";
583 };
584
585 duart: serial@80070000 {
586 compatible = "arm,pl011", "arm,primecell";
587 reg = <0x80070000 0x2000>;
588 interrupts = <0>;
Shawn Guo53f94432012-08-22 21:36:30 +0800[diff] [blame]589 clocks = <&clks 32>, <&clks 16>;
590 clock-names = "uart", "apb_pclk";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]591 status = "disabled";
592 };
593
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300[diff] [blame]594 usbphy0: usbphy@8007c000 {
595 compatible = "fsl,imx23-usbphy";
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]596 reg = <0x8007c000 0x2000>;
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300[diff] [blame]597 clocks = <&clks 41>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]598 status = "disabled";
599 };
600 };
601 };
602
603 ahb@80080000 {
604 compatible = "simple-bus";
605 #address-cells = <1>;
606 #size-cells = <1>;
607 reg = <0x80080000 0x80000>;
608 ranges;
609
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300[diff] [blame]610 usb0: usb@80080000 {
611 compatible = "fsl,imx23-usb", "fsl,imx27-usb";
Fabio Estevam640bf062012-07-30 21:29:18 -0300[diff] [blame]612 reg = <0x80080000 0x40000>;
Fabio Estevamd6475317b2012-09-13 14:33:38 -0300[diff] [blame]613 interrupts = <11>;
614 fsl,usbphy = <&usbphy0>;
615 clocks = <&clks 40>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]616 status = "disabled";
617 };
618 };
Alexandre Bellonibd798f92013-12-18 19:50:56 +0100[diff] [blame]619
Sanchayan Maity0b452cc2016-02-16 10:30:54 +0530[diff] [blame]620 iio-hwmon {
Alexandre Bellonibd798f92013-12-18 19:50:56 +0100[diff] [blame]621 compatible = "iio-hwmon";
622 io-channels = <&lradc 8>;
623 };
Shawn Guo2954ff32012-05-04 21:33:42 +0800[diff] [blame]624};