blob: 27d2bbbf1eae250bf90f7f178e325327a6316344 [file] [log] [blame]
Stephen Warren1bd0bd42012-10-17 16:38:21 -06001#include "tegra20.dtsi"
Thierry Reding307e28e2012-09-20 17:06:06 +02002
3/ {
4 model = "Avionic Design Tamonten SOM";
5 compatible = "ad,tamonten", "nvidia,tegra20";
6
Stephen Warren553c0a22013-12-09 14:43:59 -07007 aliases {
8 rtc0 = "/i2c@7000d000/tps6586x@34";
9 rtc1 = "/rtc@7000e000";
Olof Johanssonc4574aa2014-11-11 12:49:30 -080010 serial0 = &uartd;
Stephen Warren553c0a22013-12-09 14:43:59 -070011 };
12
Jon Hunterf5bbb322016-02-09 13:51:59 +000013 chosen {
14 stdout-path = "serial0:115200n8";
15 };
16
Thierry Reding307e28e2012-09-20 17:06:06 +020017 memory {
18 reg = <0x00000000 0x20000000>;
19 };
20
Stephen Warren58ecb232013-11-25 17:53:16 -070021 host1x@50000000 {
22 hdmi@54280000 {
Thierry Redinge6f09792012-11-16 16:56:50 +010023 vdd-supply = <&hdmi_vdd_reg>;
24 pll-supply = <&hdmi_pll_reg>;
25
26 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070027 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
28 GPIO_ACTIVE_HIGH>;
Thierry Redinge6f09792012-11-16 16:56:50 +010029 };
30 };
31
Stephen Warren58ecb232013-11-25 17:53:16 -070032 pinmux@70000014 {
Thierry Reding307e28e2012-09-20 17:06:06 +020033 pinctrl-names = "default";
34 pinctrl-0 = <&state_default>;
35
36 state_default: pinmux {
37 ata {
38 nvidia,pins = "ata";
39 nvidia,function = "ide";
40 };
41 atb {
42 nvidia,pins = "atb", "gma", "gme";
43 nvidia,function = "sdio4";
44 };
45 atc {
46 nvidia,pins = "atc";
47 nvidia,function = "nand";
48 };
49 atd {
50 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
51 "spia", "spib", "spic";
52 nvidia,function = "gmi";
53 };
54 cdev1 {
55 nvidia,pins = "cdev1";
56 nvidia,function = "plla_out";
57 };
58 cdev2 {
59 nvidia,pins = "cdev2";
60 nvidia,function = "pllp_out4";
61 };
62 crtp {
63 nvidia,pins = "crtp";
64 nvidia,function = "crt";
65 };
66 csus {
67 nvidia,pins = "csus";
68 nvidia,function = "vi_sensor_clk";
69 };
70 dap1 {
71 nvidia,pins = "dap1";
72 nvidia,function = "dap1";
73 };
74 dap2 {
75 nvidia,pins = "dap2";
76 nvidia,function = "dap2";
77 };
78 dap3 {
79 nvidia,pins = "dap3";
80 nvidia,function = "dap3";
81 };
82 dap4 {
83 nvidia,pins = "dap4";
84 nvidia,function = "dap4";
85 };
Thierry Reding307e28e2012-09-20 17:06:06 +020086 dta {
87 nvidia,pins = "dta", "dtd";
88 nvidia,function = "sdio2";
89 };
90 dtb {
91 nvidia,pins = "dtb", "dtc", "dte";
92 nvidia,function = "rsvd1";
93 };
94 dtf {
95 nvidia,pins = "dtf";
96 nvidia,function = "i2c3";
97 };
98 gmc {
99 nvidia,pins = "gmc";
100 nvidia,function = "uartd";
101 };
102 gpu7 {
103 nvidia,pins = "gpu7";
104 nvidia,function = "rtck";
105 };
106 gpv {
107 nvidia,pins = "gpv", "slxa", "slxk";
108 nvidia,function = "pcie";
109 };
110 hdint {
Thierry Redingec319902012-11-09 14:04:50 +0100111 nvidia,pins = "hdint";
Thierry Reding307e28e2012-09-20 17:06:06 +0200112 nvidia,function = "hdmi";
113 };
114 i2cp {
115 nvidia,pins = "i2cp";
116 nvidia,function = "i2cp";
117 };
118 irrx {
119 nvidia,pins = "irrx", "irtx";
120 nvidia,function = "uarta";
121 };
122 kbca {
123 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
124 "kbce", "kbcf";
125 nvidia,function = "kbc";
126 };
127 lcsn {
128 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
129 "ld3", "ld4", "ld5", "ld6", "ld7",
130 "ld8", "ld9", "ld10", "ld11", "ld12",
131 "ld13", "ld14", "ld15", "ld16", "ld17",
132 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
133 "lhs", "lm0", "lm1", "lpp", "lpw0",
134 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
135 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
136 "lvs";
137 nvidia,function = "displaya";
138 };
139 owc {
140 nvidia,pins = "owc", "spdi", "spdo", "uac";
141 nvidia,function = "rsvd2";
142 };
143 pmc {
144 nvidia,pins = "pmc";
145 nvidia,function = "pwr_on";
146 };
147 rm {
148 nvidia,pins = "rm";
149 nvidia,function = "i2c1";
150 };
151 sdb {
152 nvidia,pins = "sdb", "sdc", "sdd";
153 nvidia,function = "pwm";
154 };
155 sdio1 {
156 nvidia,pins = "sdio1";
157 nvidia,function = "sdio1";
158 };
159 slxc {
160 nvidia,pins = "slxc", "slxd";
161 nvidia,function = "spdif";
162 };
163 spid {
164 nvidia,pins = "spid", "spie", "spif";
165 nvidia,function = "spi1";
166 };
167 spig {
168 nvidia,pins = "spig", "spih";
169 nvidia,function = "spi2_alt";
170 };
171 uaa {
172 nvidia,pins = "uaa", "uab", "uda";
173 nvidia,function = "ulpi";
174 };
175 uad {
176 nvidia,pins = "uad";
177 nvidia,function = "irda";
178 };
179 uca {
180 nvidia,pins = "uca", "ucb";
181 nvidia,function = "uartc";
182 };
183 conf_ata {
184 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
185 "cdev1", "cdev2", "dap1", "dtb", "gma",
186 "gmb", "gmc", "gmd", "gme", "gpu7",
187 "gpv", "i2cp", "pta", "rm", "slxa",
188 "slxk", "spia", "spib", "uac";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530189 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
190 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200191 };
192 conf_ck32 {
193 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
194 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530195 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200196 };
197 conf_csus {
198 nvidia,pins = "csus", "spid", "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530199 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
200 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200201 };
202 conf_crtp {
203 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
204 "dtc", "dte", "dtf", "gpu", "sdio1",
205 "slxc", "slxd", "spdi", "spdo", "spig",
206 "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530207 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
208 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200209 };
210 conf_ddc {
211 nvidia,pins = "ddc", "dta", "dtd", "kbca",
212 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
213 "sdc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530214 nvidia,pull = <TEGRA_PIN_PULL_UP>;
215 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200216 };
217 conf_hdint {
218 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
219 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
220 "lvp0", "owc", "sdb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530221 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200222 };
223 conf_irrx {
224 nvidia,pins = "irrx", "irtx", "sdd", "spic",
225 "spie", "spih", "uaa", "uab", "uad",
226 "uca", "ucb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530227 nvidia,pull = <TEGRA_PIN_PULL_UP>;
228 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200229 };
230 conf_lc {
231 nvidia,pins = "lc", "ls";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530232 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200233 };
234 conf_ld0 {
235 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
236 "ld5", "ld6", "ld7", "ld8", "ld9",
237 "ld10", "ld11", "ld12", "ld13", "ld14",
238 "ld15", "ld16", "ld17", "ldi", "lhp0",
239 "lhp1", "lhp2", "lhs", "lm0", "lpp",
240 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
241 "lvs", "pmc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530242 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200243 };
244 conf_ld17_0 {
245 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
246 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530247 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200248 };
249 };
Thierry Redingec319902012-11-09 14:04:50 +0100250
251 state_i2cmux_ddc: pinmux_i2cmux_ddc {
252 ddc {
253 nvidia,pins = "ddc";
254 nvidia,function = "i2c2";
255 };
256 pta {
257 nvidia,pins = "pta";
258 nvidia,function = "rsvd4";
259 };
260 };
261
262 state_i2cmux_pta: pinmux_i2cmux_pta {
263 ddc {
264 nvidia,pins = "ddc";
265 nvidia,function = "rsvd4";
266 };
267 pta {
268 nvidia,pins = "pta";
269 nvidia,function = "i2c2";
270 };
271 };
272
273 state_i2cmux_idle: pinmux_i2cmux_idle {
274 ddc {
275 nvidia,pins = "ddc";
276 nvidia,function = "rsvd4";
277 };
278 pta {
279 nvidia,pins = "pta";
280 nvidia,function = "rsvd4";
281 };
282 };
Thierry Reding307e28e2012-09-20 17:06:06 +0200283 };
284
285 i2s@70002800 {
286 status = "okay";
287 };
288
289 serial@70006300 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200290 status = "okay";
291 };
292
293 i2c@7000c000 {
294 clock-frequency = <400000>;
295 status = "okay";
296 };
297
Thierry Redingec319902012-11-09 14:04:50 +0100298 i2c@7000c400 {
299 clock-frequency = <100000>;
300 status = "okay";
301 };
302
303 i2cmux {
304 compatible = "i2c-mux-pinctrl";
305 #address-cells = <1>;
306 #size-cells = <0>;
307
308 i2c-parent = <&{/i2c@7000c400}>;
309
310 pinctrl-names = "ddc", "pta", "idle";
311 pinctrl-0 = <&state_i2cmux_ddc>;
312 pinctrl-1 = <&state_i2cmux_pta>;
313 pinctrl-2 = <&state_i2cmux_idle>;
314
Thierry Redinge6f09792012-11-16 16:56:50 +0100315 hdmi_ddc: i2c@0 {
Thierry Redingec319902012-11-09 14:04:50 +0100316 reg = <0>;
317 #address-cells = <1>;
318 #size-cells = <0>;
319 };
320
321 i2c@1 {
322 reg = <1>;
323 #address-cells = <1>;
324 #size-cells = <0>;
325 };
326 };
327
Thierry Reding307e28e2012-09-20 17:06:06 +0200328 i2c@7000d000 {
329 clock-frequency = <400000>;
330 status = "okay";
331
332 pmic: tps6586x@34 {
333 compatible = "ti,tps6586x";
334 reg = <0x34>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700335 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200336
337 ti,system-power-controller;
338
339 #gpio-cells = <2>;
340 gpio-controller;
341
Alban Bedel23e63342014-06-19 15:25:49 +0200342 /* vdd_5v0_reg must be provided by the base board */
Thierry Reding307e28e2012-09-20 17:06:06 +0200343 sys-supply = <&vdd_5v0_reg>;
344 vin-sm0-supply = <&sys_reg>;
345 vin-sm1-supply = <&sys_reg>;
346 vin-sm2-supply = <&sys_reg>;
347 vinldo01-supply = <&sm2_reg>;
348 vinldo23-supply = <&sm2_reg>;
349 vinldo4-supply = <&sm2_reg>;
350 vinldo678-supply = <&sm2_reg>;
351 vinldo9-supply = <&sm2_reg>;
352
353 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600354 sys_reg: sys {
Thierry Reding307e28e2012-09-20 17:06:06 +0200355 regulator-name = "vdd_sys";
356 regulator-always-on;
357 };
358
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600359 sm0 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200360 regulator-name = "vdd_sys_sm0,vdd_core";
361 regulator-min-microvolt = <1200000>;
362 regulator-max-microvolt = <1200000>;
363 regulator-always-on;
364 };
365
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600366 sm1 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200367 regulator-name = "vdd_sys_sm1,vdd_cpu";
368 regulator-min-microvolt = <1000000>;
369 regulator-max-microvolt = <1000000>;
370 regulator-always-on;
371 };
372
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600373 sm2_reg: sm2 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200374 regulator-name = "vdd_sys_sm2,vin_ldo*";
375 regulator-min-microvolt = <3700000>;
376 regulator-max-microvolt = <3700000>;
377 regulator-always-on;
378 };
379
Thierry Reding1b2d6b82013-08-09 16:49:20 +0200380 pci_clk_reg: ldo0 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200381 regulator-name = "vdd_ldo0,vddio_pex_clk";
382 regulator-min-microvolt = <3300000>;
383 regulator-max-microvolt = <3300000>;
384 };
385
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600386 ldo1 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200387 regulator-name = "vdd_ldo1,avdd_pll*";
388 regulator-min-microvolt = <1100000>;
389 regulator-max-microvolt = <1100000>;
390 regulator-always-on;
391 };
392
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600393 ldo2 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200394 regulator-name = "vdd_ldo2,vdd_rtc";
395 regulator-min-microvolt = <1200000>;
396 regulator-max-microvolt = <1200000>;
397 };
398
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600399 ldo3 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200400 regulator-name = "vdd_ldo3,avdd_usb*";
401 regulator-min-microvolt = <3300000>;
402 regulator-max-microvolt = <3300000>;
403 regulator-always-on;
404 };
405
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600406 ldo4 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200407 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
408 regulator-min-microvolt = <1800000>;
409 regulator-max-microvolt = <1800000>;
410 regulator-always-on;
411 };
412
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600413 ldo5 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200414 regulator-name = "vdd_ldo5,vcore_mmc";
415 regulator-min-microvolt = <2850000>;
416 regulator-max-microvolt = <2850000>;
417 };
418
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600419 ldo6 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200420 regulator-name = "vdd_ldo6,avdd_vdac";
421 /*
422 * According to the Tegra 2 Automotive
423 * DataSheet, a typical value for this
424 * would be 2.8V, but the PMIC only
425 * supports 2.85V.
426 */
427 regulator-min-microvolt = <2850000>;
428 regulator-max-microvolt = <2850000>;
429 };
430
Thierry Redinge6f09792012-11-16 16:56:50 +0100431 hdmi_vdd_reg: ldo7 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200432 regulator-name = "vdd_ldo7,avdd_hdmi";
433 regulator-min-microvolt = <3300000>;
434 regulator-max-microvolt = <3300000>;
435 };
436
Thierry Redinge6f09792012-11-16 16:56:50 +0100437 hdmi_pll_reg: ldo8 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200438 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
439 regulator-min-microvolt = <1800000>;
440 regulator-max-microvolt = <1800000>;
441 };
442
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600443 ldo9 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200444 regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
445 /*
446 * According to the Tegra 2 Automotive
447 * DataSheet, a typical value for this
448 * would be 2.8V, but the PMIC only
449 * supports 2.85V.
450 */
451 regulator-min-microvolt = <2850000>;
452 regulator-max-microvolt = <2850000>;
453 regulator-always-on;
454 };
455
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600456 ldo_rtc {
Thierry Reding307e28e2012-09-20 17:06:06 +0200457 regulator-name = "vdd_rtc_out";
458 regulator-min-microvolt = <3300000>;
459 regulator-max-microvolt = <3300000>;
460 regulator-always-on;
461 };
462 };
463 };
Thierry Reding840a4082012-11-09 23:00:08 +0100464
465 temperature-sensor@4c {
466 compatible = "onnn,nct1008";
467 reg = <0x4c>;
468 };
Thierry Reding307e28e2012-09-20 17:06:06 +0200469 };
470
Stephen Warren58ecb232013-11-25 17:53:16 -0700471 pmc@7000e400 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200472 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800473 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800474 nvidia,cpu-pwr-good-time = <5000>;
475 nvidia,cpu-pwr-off-time = <5000>;
476 nvidia,core-pwr-good-time = <3845 3845>;
477 nvidia,core-pwr-off-time = <3875>;
478 nvidia,sys-clock-req-active-high;
Thierry Reding307e28e2012-09-20 17:06:06 +0200479 };
480
Stephen Warren58ecb232013-11-25 17:53:16 -0700481 pcie-controller@80003000 {
Thierry Redingcca86142014-05-28 16:49:12 +0200482 avdd-pex-supply = <&pci_vdd_reg>;
483 vdd-pex-supply = <&pci_vdd_reg>;
484 avdd-pex-pll-supply = <&pci_vdd_reg>;
485 avdd-plle-supply = <&pci_vdd_reg>;
486 vddio-pex-clk-supply = <&pci_clk_reg>;
Thierry Reding1b2d6b82013-08-09 16:49:20 +0200487 };
488
Thierry Reding307e28e2012-09-20 17:06:06 +0200489 usb@c5008000 {
490 status = "okay";
491 };
492
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530493 usb-phy@c5008000 {
494 status = "okay";
495 };
496
Thierry Reding307e28e2012-09-20 17:06:06 +0200497 sdhci@c8000600 {
Stephen Warren3325f1b2013-02-12 17:25:15 -0700498 cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
499 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200500 bus-width = <4>;
501 status = "okay";
502 };
503
Joseph Lo7021d122013-04-03 19:31:27 +0800504 clocks {
505 compatible = "simple-bus";
506 #address-cells = <1>;
507 #size-cells = <0>;
508
Stephen Warren58ecb232013-11-25 17:53:16 -0700509 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800510 compatible = "fixed-clock";
Thierry Reding4ec2e602016-06-10 18:55:24 +0200511 reg = <0>;
Joseph Lo7021d122013-04-03 19:31:27 +0800512 #clock-cells = <0>;
513 clock-frequency = <32768>;
514 };
515 };
516
Thierry Reding307e28e2012-09-20 17:06:06 +0200517 regulators {
518 compatible = "simple-bus";
519
520 #address-cells = <1>;
521 #size-cells = <0>;
522
Thierry Reding1b2d6b82013-08-09 16:49:20 +0200523 pci_vdd_reg: regulator@1 {
524 compatible = "regulator-fixed";
525 reg = <1>;
526 regulator-name = "vdd_1v05";
527 regulator-min-microvolt = <1050000>;
528 regulator-max-microvolt = <1050000>;
529 gpio = <&pmic 2 0>;
530 enable-active-high;
531 };
Thierry Reding307e28e2012-09-20 17:06:06 +0200532 };
533};