blob: 1e06f854c8b4146970eb6b2c3ff8a7ae398fdb91 [file] [log] [blame]
Stephen Warrenc80efba2012-04-20 16:57:38 -06001/dts-v1/;
2
Laxman Dewangan6bccbd52013-12-02 18:39:57 +05303#include <dt-bindings/input/input.h>
Stephen Warren1bd0bd42012-10-17 16:38:21 -06004#include "tegra20.dtsi"
Stephen Warrenc80efba2012-04-20 16:57:38 -06005
6/ {
Bryan Wu8fef5df2012-12-20 09:41:29 +00007 model = "NVIDIA Tegra20 Whistler evaluation board";
Stephen Warrenc80efba2012-04-20 16:57:38 -06008 compatible = "nvidia,whistler", "nvidia,tegra20";
9
Stephen Warren553c0a22013-12-09 14:43:59 -070010 aliases {
11 rtc0 = "/i2c@7000d000/max8907@3c";
12 rtc1 = "/rtc@7000e000";
Olof Johanssonc4574aa2014-11-11 12:49:30 -080013 serial0 = &uarta;
Stephen Warren553c0a22013-12-09 14:43:59 -070014 };
15
Jon Hunterf5bbb322016-02-09 13:51:59 +000016 chosen {
17 stdout-path = "serial0:115200n8";
18 };
19
Stephen Warrenc80efba2012-04-20 16:57:38 -060020 memory {
21 reg = <0x00000000 0x20000000>;
22 };
23
Stephen Warren58ecb232013-11-25 17:53:16 -070024 host1x@50000000 {
25 hdmi@54280000 {
Stephen Warren2658ef12012-11-16 10:53:04 -070026 status = "okay";
27
28 vdd-supply = <&hdmi_vdd_reg>;
29 pll-supply = <&hdmi_pll_reg>;
30
31 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070032 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
33 GPIO_ACTIVE_HIGH>;
Stephen Warren2658ef12012-11-16 10:53:04 -070034 };
35 };
36
Stephen Warren58ecb232013-11-25 17:53:16 -070037 pinmux@70000014 {
Stephen Warrenc80efba2012-04-20 16:57:38 -060038 pinctrl-names = "default";
39 pinctrl-0 = <&state_default>;
40
41 state_default: pinmux {
42 ata {
43 nvidia,pins = "ata", "atb", "ate", "gma", "gmb",
44 "gmc", "gmd", "gpu";
45 nvidia,function = "gmi";
46 };
47 atc {
48 nvidia,pins = "atc", "atd";
49 nvidia,function = "sdio4";
50 };
51 cdev1 {
52 nvidia,pins = "cdev1";
53 nvidia,function = "plla_out";
54 };
55 cdev2 {
56 nvidia,pins = "cdev2";
57 nvidia,function = "osc";
58 };
59 crtp {
60 nvidia,pins = "crtp";
61 nvidia,function = "crt";
62 };
63 csus {
64 nvidia,pins = "csus";
65 nvidia,function = "vi_sensor_clk";
66 };
67 dap1 {
68 nvidia,pins = "dap1";
69 nvidia,function = "dap1";
70 };
71 dap2 {
72 nvidia,pins = "dap2";
73 nvidia,function = "dap2";
74 };
75 dap3 {
76 nvidia,pins = "dap3";
77 nvidia,function = "dap3";
78 };
79 dap4 {
80 nvidia,pins = "dap4";
81 nvidia,function = "dap4";
82 };
83 ddc {
84 nvidia,pins = "ddc";
85 nvidia,function = "i2c2";
86 };
87 dta {
88 nvidia,pins = "dta", "dtb", "dtc", "dtd";
89 nvidia,function = "vi";
90 };
91 dte {
92 nvidia,pins = "dte";
93 nvidia,function = "rsvd1";
94 };
95 dtf {
96 nvidia,pins = "dtf";
97 nvidia,function = "i2c3";
98 };
99 gme {
100 nvidia,pins = "gme";
101 nvidia,function = "dap5";
102 };
103 gpu7 {
104 nvidia,pins = "gpu7";
105 nvidia,function = "rtck";
106 };
107 gpv {
108 nvidia,pins = "gpv";
109 nvidia,function = "pcie";
110 };
111 hdint {
112 nvidia,pins = "hdint", "pta";
113 nvidia,function = "hdmi";
114 };
115 i2cp {
116 nvidia,pins = "i2cp";
117 nvidia,function = "i2cp";
118 };
119 irrx {
120 nvidia,pins = "irrx", "irtx";
121 nvidia,function = "uartb";
122 };
123 kbca {
124 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
125 nvidia,function = "kbc";
126 };
127 kbcb {
128 nvidia,pins = "kbcb", "kbcd";
129 nvidia,function = "sdio2";
130 };
131 lcsn {
132 nvidia,pins = "lcsn", "lsck", "lsda", "lsdi",
133 "spia", "spib", "spic";
134 nvidia,function = "spi3";
135 };
136 ld0 {
137 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
138 "ld5", "ld6", "ld7", "ld8", "ld9",
139 "ld10", "ld11", "ld12", "ld13", "ld14",
140 "ld15", "ld16", "ld17", "ldc", "ldi",
141 "lhp0", "lhp1", "lhp2", "lhs", "lm0",
142 "lm1", "lpp", "lpw0", "lpw1", "lpw2",
143 "lsc0", "lsc1", "lspi", "lvp0", "lvp1",
144 "lvs";
145 nvidia,function = "displaya";
146 };
147 owc {
148 nvidia,pins = "owc", "uac";
149 nvidia,function = "owr";
150 };
151 pmc {
152 nvidia,pins = "pmc";
153 nvidia,function = "pwr_on";
154 };
155 rm {
156 nvidia,pins = "rm";
157 nvidia,function = "i2c1";
158 };
159 sdb {
160 nvidia,pins = "sdb", "sdc", "sdd", "slxa",
161 "slxc", "slxd", "slxk";
162 nvidia,function = "sdio3";
163 };
164 sdio1 {
165 nvidia,pins = "sdio1";
166 nvidia,function = "sdio1";
167 };
168 spdi {
169 nvidia,pins = "spdi", "spdo";
170 nvidia,function = "rsvd2";
171 };
172 spid {
173 nvidia,pins = "spid", "spie", "spig", "spih";
174 nvidia,function = "spi2_alt";
175 };
176 spif {
177 nvidia,pins = "spif";
178 nvidia,function = "spi2";
179 };
180 uaa {
181 nvidia,pins = "uaa", "uab";
182 nvidia,function = "uarta";
183 };
184 uad {
185 nvidia,pins = "uad";
186 nvidia,function = "irda";
187 };
188 uca {
189 nvidia,pins = "uca", "ucb";
190 nvidia,function = "uartc";
191 };
192 uda {
193 nvidia,pins = "uda";
194 nvidia,function = "spi1";
195 };
196 conf_ata {
197 nvidia,pins = "ata", "atb", "atc", "ddc", "gma",
198 "gmb", "gmc", "gmd", "irrx", "irtx",
199 "kbca", "kbcb", "kbcc", "kbcd", "kbce",
200 "kbcf", "sdc", "sdd", "spie", "spig",
201 "spih", "uaa", "uab", "uad", "uca",
202 "ucb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530203 nvidia,pull = <TEGRA_PIN_PULL_UP>;
204 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600205 };
206 conf_atd {
207 nvidia,pins = "atd", "ate", "cdev1", "csus",
208 "dap1", "dap2", "dap3", "dap4", "dte",
209 "dtf", "gpu", "gpu7", "gpv", "i2cp",
210 "rm", "sdio1", "slxa", "slxc", "slxd",
211 "slxk", "spdi", "spdo", "uac", "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530212 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
213 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600214 };
215 conf_cdev2 {
216 nvidia,pins = "cdev2", "spia", "spib";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530217 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
218 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600219 };
220 conf_ck32 {
221 nvidia,pins = "ck32", "ddrc", "lc", "pmca",
222 "pmcb", "pmcc", "pmcd", "xm2c",
223 "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530224 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600225 };
226 conf_crtp {
227 nvidia,pins = "crtp";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530228 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
229 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600230 };
231 conf_dta {
232 nvidia,pins = "dta", "dtb", "dtc", "dtd",
233 "spid", "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530234 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
235 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600236 };
237 conf_gme {
238 nvidia,pins = "gme", "owc", "pta", "spic";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530239 nvidia,pull = <TEGRA_PIN_PULL_UP>;
240 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600241 };
242 conf_ld17_0 {
243 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
244 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530245 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600246 };
247 conf_ls {
248 nvidia,pins = "ls", "pmce";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530249 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600250 };
251 drive_dap1 {
252 nvidia,pins = "drive_dap1";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530253 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
254 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
255 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_8>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600256 nvidia,pull-down-strength = <0>;
257 nvidia,pull-up-strength = <0>;
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530258 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
259 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600260 };
261 };
262 };
263
264 i2s@70002800 {
265 status = "okay";
266 };
267
268 serial@70006000 {
269 status = "okay";
Stephen Warrenc80efba2012-04-20 16:57:38 -0600270 };
271
Stephen Warren2658ef12012-11-16 10:53:04 -0700272 hdmi_ddc: i2c@7000c400 {
273 status = "okay";
274 clock-frequency = <100000>;
275 };
276
Stephen Warrenc80efba2012-04-20 16:57:38 -0600277 i2c@7000d000 {
278 status = "okay";
279 clock-frequency = <100000>;
280
281 codec: codec@1a {
282 compatible = "wlf,wm8753";
283 reg = <0x1a>;
284 };
285
286 tca6416: gpio@20 {
287 compatible = "ti,tca6416";
288 reg = <0x20>;
289 gpio-controller;
290 #gpio-cells = <2>;
291 };
Stephen Warrene7765b32012-06-25 16:41:25 -0600292
293 max8907@3c {
294 compatible = "maxim,max8907";
295 reg = <0x3c>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700296 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warrene7765b32012-06-25 16:41:25 -0600297
Stephen Warrenb37ed4a2012-09-11 13:13:05 -0600298 maxim,system-power-controller;
299
Stephen Warrene7765b32012-06-25 16:41:25 -0600300 mbatt-supply = <&usb0_vbus_reg>;
301 in-v1-supply = <&mbatt_reg>;
302 in-v2-supply = <&mbatt_reg>;
303 in-v3-supply = <&mbatt_reg>;
304 in1-supply = <&mbatt_reg>;
305 in2-supply = <&nvvdd_sv3_reg>;
306 in3-supply = <&mbatt_reg>;
307 in4-supply = <&mbatt_reg>;
308 in5-supply = <&mbatt_reg>;
309 in6-supply = <&mbatt_reg>;
310 in7-supply = <&mbatt_reg>;
311 in8-supply = <&mbatt_reg>;
312 in9-supply = <&mbatt_reg>;
313 in10-supply = <&mbatt_reg>;
314 in11-supply = <&mbatt_reg>;
315 in12-supply = <&mbatt_reg>;
316 in13-supply = <&mbatt_reg>;
317 in14-supply = <&mbatt_reg>;
318 in15-supply = <&mbatt_reg>;
319 in16-supply = <&mbatt_reg>;
320 in17-supply = <&nvvdd_sv3_reg>;
321 in18-supply = <&nvvdd_sv3_reg>;
322 in19-supply = <&mbatt_reg>;
323 in20-supply = <&mbatt_reg>;
324
325 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600326 mbatt_reg: mbatt {
Stephen Warrene7765b32012-06-25 16:41:25 -0600327 regulator-name = "vbat_pmu";
328 regulator-always-on;
329 };
330
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600331 sd1 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600332 regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
333 regulator-min-microvolt = <1000000>;
334 regulator-max-microvolt = <1000000>;
335 regulator-always-on;
336 };
337
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600338 sd2 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600339 regulator-name = "nvvdd_sv2,vdd_core";
340 regulator-min-microvolt = <1200000>;
341 regulator-max-microvolt = <1200000>;
342 regulator-always-on;
343 };
344
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600345 nvvdd_sv3_reg: sd3 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600346 regulator-name = "nvvdd_sv3";
347 regulator-min-microvolt = <1800000>;
348 regulator-max-microvolt = <1800000>;
349 regulator-always-on;
350 };
351
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600352 ldo1 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600353 regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
354 regulator-min-microvolt = <3300000>;
355 regulator-max-microvolt = <3300000>;
356 regulator-always-on;
357 };
358
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600359 ldo2 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600360 regulator-name = "nvvdd_ldo2,avdd_pll*";
361 regulator-min-microvolt = <1100000>;
362 regulator-max-microvolt = <1100000>;
363 regulator-always-on;
364 };
365
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600366 ldo3 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600367 regulator-name = "nvvdd_ldo3,vcom_1v8b";
368 regulator-min-microvolt = <1800000>;
369 regulator-max-microvolt = <1800000>;
370 regulator-always-on;
371 };
372
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600373 ldo4 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600374 regulator-name = "nvvdd_ldo4,avdd_usb*";
375 regulator-min-microvolt = <3300000>;
376 regulator-max-microvolt = <3300000>;
377 regulator-always-on;
378 };
379
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600380 ldo5 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600381 regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
382 regulator-min-microvolt = <2800000>;
383 regulator-max-microvolt = <2800000>;
384 regulator-always-on;
385 };
386
Stephen Warren2658ef12012-11-16 10:53:04 -0700387 hdmi_pll_reg: ldo6 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600388 regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
389 regulator-min-microvolt = <1800000>;
390 regulator-max-microvolt = <1800000>;
391 };
392
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600393 ldo7 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600394 regulator-name = "nvvdd_ldo7,avddio_audio";
395 regulator-min-microvolt = <2800000>;
396 regulator-max-microvolt = <2800000>;
397 regulator-always-on;
398 };
399
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600400 ldo8 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600401 regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
402 regulator-min-microvolt = <3000000>;
403 regulator-max-microvolt = <3000000>;
404 };
405
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600406 ldo9 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600407 regulator-name = "nvvdd_ldo9,avdd_cam*";
408 regulator-min-microvolt = <2800000>;
409 regulator-max-microvolt = <2800000>;
410 };
411
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600412 ldo10 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600413 regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
414 regulator-min-microvolt = <3000000>;
415 regulator-max-microvolt = <3000000>;
416 regulator-always-on;
417 };
418
Stephen Warren2658ef12012-11-16 10:53:04 -0700419 hdmi_vdd_reg: ldo11 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600420 regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
421 regulator-min-microvolt = <3300000>;
422 regulator-max-microvolt = <3300000>;
423 };
424
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600425 ldo12 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600426 regulator-name = "nvvdd_ldo12,vddio_sdio";
427 regulator-min-microvolt = <2800000>;
428 regulator-max-microvolt = <2800000>;
429 regulator-always-on;
430 };
431
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600432 ldo13 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600433 regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
434 regulator-min-microvolt = <2800000>;
435 regulator-max-microvolt = <2800000>;
436 };
437
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600438 ldo14 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600439 regulator-name = "nvvdd_ldo14,avdd_vdac";
440 regulator-min-microvolt = <2800000>;
441 regulator-max-microvolt = <2800000>;
442 };
443
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600444 ldo15 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600445 regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
446 regulator-min-microvolt = <3300000>;
447 regulator-max-microvolt = <3300000>;
448 };
449
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600450 ldo16 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600451 regulator-name = "nvvdd_ldo16,vdd_dbrtr";
452 regulator-min-microvolt = <1300000>;
453 regulator-max-microvolt = <1300000>;
454 };
455
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600456 ldo17 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600457 regulator-name = "nvvdd_ldo17,vddio_mipi";
458 regulator-min-microvolt = <1200000>;
459 regulator-max-microvolt = <1200000>;
460 };
461
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600462 ldo18 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600463 regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
464 regulator-min-microvolt = <1800000>;
465 regulator-max-microvolt = <1800000>;
466 };
467
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600468 ldo19 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600469 regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
470 regulator-min-microvolt = <2800000>;
471 regulator-max-microvolt = <2800000>;
472 };
473
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600474 ldo20 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600475 regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
476 regulator-min-microvolt = <1200000>;
477 regulator-max-microvolt = <1200000>;
478 regulator-always-on;
479 };
480
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600481 out5v {
Stephen Warrene7765b32012-06-25 16:41:25 -0600482 regulator-name = "usb0_vbus_reg";
483 };
484
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600485 out33v {
Stephen Warrene7765b32012-06-25 16:41:25 -0600486 regulator-name = "pmu_out3v3";
487 };
488
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600489 bbat {
Stephen Warrene7765b32012-06-25 16:41:25 -0600490 regulator-name = "pmu_bbat";
491 regulator-min-microvolt = <2400000>;
492 regulator-max-microvolt = <2400000>;
493 regulator-always-on;
494 };
495
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600496 sdby {
Stephen Warrene7765b32012-06-25 16:41:25 -0600497 regulator-name = "vdd_aon";
498 regulator-always-on;
499 };
500
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600501 vrtc {
Stephen Warrene7765b32012-06-25 16:41:25 -0600502 regulator-name = "vrtc,pmu_vccadc";
503 regulator-always-on;
504 };
505 };
506 };
507 };
508
Stephen Warren57899052013-11-26 14:43:45 -0700509 kbc@7000e200 {
510 status = "okay";
511 nvidia,debounce-delay-ms = <20>;
512 nvidia,repeat-delay-ms = <160>;
513 nvidia,kbc-row-pins = <0 1 2>;
514 nvidia,kbc-col-pins = <16 17>;
Sudeep Hollad1c04d32016-02-08 21:55:43 +0000515 wakeup-source;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530516 linux,keymap = <MATRIX_KEY(0x00, 0x00, KEY_POWER)
517 MATRIX_KEY(0x01, 0x00, KEY_HOME)
518 MATRIX_KEY(0x01, 0x01, KEY_BACK)
519 MATRIX_KEY(0x02, 0x01, KEY_MENU)>;
Stephen Warren57899052013-11-26 14:43:45 -0700520 };
521
Stephen Warren58ecb232013-11-25 17:53:16 -0700522 pmc@7000e400 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600523 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800524 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800525 nvidia,cpu-pwr-good-time = <2000>;
526 nvidia,cpu-pwr-off-time = <1000>;
527 nvidia,core-pwr-good-time = <0 3845>;
528 nvidia,core-pwr-off-time = <93727>;
529 nvidia,core-power-req-active-high;
530 nvidia,sys-clock-req-active-high;
531 nvidia,combined-power-req;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600532 };
533
534 usb@c5000000 {
535 status = "okay";
Stephen Warrenc80efba2012-04-20 16:57:38 -0600536 };
537
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530538 usb-phy@c5000000 {
539 status = "okay";
540 vbus-supply = <&vbus1_reg>;
541 };
542
Stephen Warrenc80efba2012-04-20 16:57:38 -0600543 usb@c5008000 {
544 status = "okay";
Stephen Warrenc80efba2012-04-20 16:57:38 -0600545 };
546
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530547 usb-phy@c5008000 {
548 status = "okay";
549 vbus-supply = <&vbus3_reg>;
550 };
551
Stephen Warrenc80efba2012-04-20 16:57:38 -0600552 sdhci@c8000400 {
553 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700554 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
555 wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600556 bus-width = <8>;
557 };
558
559 sdhci@c8000600 {
560 status = "okay";
561 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600562 non-removable;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600563 };
564
Joseph Lo7021d122013-04-03 19:31:27 +0800565 clocks {
566 compatible = "simple-bus";
567 #address-cells = <1>;
568 #size-cells = <0>;
569
Stephen Warren58ecb232013-11-25 17:53:16 -0700570 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800571 compatible = "fixed-clock";
Thierry Reding4ec2e602016-06-10 18:55:24 +0200572 reg = <0>;
Joseph Lo7021d122013-04-03 19:31:27 +0800573 #clock-cells = <0>;
574 clock-frequency = <32768>;
575 };
576 };
577
Stephen Warrene7765b32012-06-25 16:41:25 -0600578 regulators {
579 compatible = "simple-bus";
580 #address-cells = <1>;
581 #size-cells = <0>;
582
Stephen Warren58ecb232013-11-25 17:53:16 -0700583 usb0_vbus_reg: regulator@0 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600584 compatible = "regulator-fixed";
585 reg = <0>;
586 regulator-name = "usb0_vbus";
587 regulator-min-microvolt = <5000000>;
588 regulator-max-microvolt = <5000000>;
589 regulator-always-on;
590 };
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530591
592 vbus1_reg: regulator@2 {
593 compatible = "regulator-fixed";
594 reg = <2>;
595 regulator-name = "vbus1";
596 regulator-min-microvolt = <5000000>;
597 regulator-max-microvolt = <5000000>;
Stephen Warren9f310de2013-07-01 15:07:05 -0600598 enable-active-high;
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530599 gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
Stephen Warren30ca2222013-08-20 14:00:13 -0600600 regulator-always-on;
601 regulator-boot-on;
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530602 };
603
604 vbus3_reg: regulator@3 {
605 compatible = "regulator-fixed";
606 reg = <3>;
607 regulator-name = "vbus3";
608 regulator-min-microvolt = <5000000>;
609 regulator-max-microvolt = <5000000>;
Stephen Warren9f310de2013-07-01 15:07:05 -0600610 enable-active-high;
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530611 gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
Stephen Warren30ca2222013-08-20 14:00:13 -0600612 regulator-always-on;
613 regulator-boot-on;
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530614 };
Stephen Warrene7765b32012-06-25 16:41:25 -0600615 };
616
Stephen Warrenc80efba2012-04-20 16:57:38 -0600617 sound {
618 compatible = "nvidia,tegra-audio-wm8753-whistler",
619 "nvidia,tegra-audio-wm8753";
620 nvidia,model = "NVIDIA Tegra Whistler";
621
622 nvidia,audio-routing =
623 "Headphone Jack", "LOUT1",
624 "Headphone Jack", "ROUT1",
625 "MIC2", "Mic Jack",
626 "MIC2N", "Mic Jack";
627
628 nvidia,i2s-controller = <&tegra_i2s1>;
629 nvidia,audio-codec = <&codec>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600630
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300631 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
632 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
633 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600634 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warrenc80efba2012-04-20 16:57:38 -0600635 };
636};