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John Linnb85a3ef2011-06-20 11:47:27 -06001/*
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -07002 * Copyright (C) 2011 - 2014 Xilinx
John Linnb85a3ef2011-06-20 11:47:27 -06003 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
Josh Cartwrighte06f1a92012-10-31 12:24:48 -060013/include/ "skeleton.dtsi"
John Linnb85a3ef2011-06-20 11:47:27 -060014
John Linnb85a3ef2011-06-20 11:47:27 -060015/ {
Josh Cartwrighte06f1a92012-10-31 12:24:48 -060016 compatible = "xlnx,zynq-7000";
John Linnb85a3ef2011-06-20 11:47:27 -060017
Soren Brinkmann41e4cdb2013-11-26 17:04:49 -080018 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
Moritz Fischer400b6a02015-11-09 10:51:51 -080022 cpu0: cpu@0 {
Soren Brinkmann41e4cdb2013-11-26 17:04:49 -080023 compatible = "arm,cortex-a9";
24 device_type = "cpu";
25 reg = <0>;
26 clocks = <&clkc 3>;
Soren Brinkmannb2bf5d42014-04-04 16:14:12 -070027 clock-latency = <1000>;
Soren Brinkmanne1e22df2014-05-02 14:07:32 -070028 cpu0-supply = <&regulator_vccpint>;
Soren Brinkmanncd325292014-02-19 15:14:44 -080029 operating-points = <
30 /* kHz uV */
31 666667 1000000
32 333334 1000000
Soren Brinkmanncd325292014-02-19 15:14:44 -080033 >;
Soren Brinkmann41e4cdb2013-11-26 17:04:49 -080034 };
35
Moritz Fischer400b6a02015-11-09 10:51:51 -080036 cpu1: cpu@1 {
Soren Brinkmann41e4cdb2013-11-26 17:04:49 -080037 compatible = "arm,cortex-a9";
38 device_type = "cpu";
39 reg = <1>;
40 clocks = <&clkc 3>;
41 };
42 };
43
Michal Simek268a8202013-03-20 13:37:01 +010044 pmu {
45 compatible = "arm,cortex-a9-pmu";
46 interrupts = <0 5 4>, <0 6 4>;
47 interrupt-parent = <&intc>;
48 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
49 };
50
Soren Brinkmanne1e22df2014-05-02 14:07:32 -070051 regulator_vccpint: fixedregulator@0 {
52 compatible = "regulator-fixed";
53 regulator-name = "VCCPINT";
54 regulator-min-microvolt = <1000000>;
55 regulator-max-microvolt = <1000000>;
56 regulator-boot-on;
57 regulator-always-on;
58 };
59
Michal Simek6835fe42015-02-12 10:59:17 +010060 amba: amba {
John Linnb85a3ef2011-06-20 11:47:27 -060061 compatible = "simple-bus";
62 #address-cells = <1>;
63 #size-cells = <1>;
Josh Cartwrighte06f1a92012-10-31 12:24:48 -060064 interrupt-parent = <&intc>;
John Linnb85a3ef2011-06-20 11:47:27 -060065 ranges;
66
Michal Simek70472c42014-09-24 15:28:59 +020067 adc: adc@f8007100 {
Soren Brinkmann21555602014-06-05 09:05:23 -070068 compatible = "xlnx,zynq-xadc-1.00.a";
69 reg = <0xf8007100 0x20>;
70 interrupts = <0 7 4>;
71 interrupt-parent = <&intc>;
72 clocks = <&clkc 12>;
Michal Simekfdf26182014-07-23 15:03:03 +020073 };
74
75 can0: can@e0008000 {
76 compatible = "xlnx,zynq-can-1.0";
77 status = "disabled";
78 clocks = <&clkc 19>, <&clkc 36>;
79 clock-names = "can_clk", "pclk";
80 reg = <0xe0008000 0x1000>;
81 interrupts = <0 28 4>;
82 interrupt-parent = <&intc>;
83 tx-fifo-depth = <0x40>;
84 rx-fifo-depth = <0x40>;
85 };
86
87 can1: can@e0009000 {
88 compatible = "xlnx,zynq-can-1.0";
89 status = "disabled";
90 clocks = <&clkc 20>, <&clkc 37>;
91 clock-names = "can_clk", "pclk";
92 reg = <0xe0009000 0x1000>;
93 interrupts = <0 51 4>;
94 interrupt-parent = <&intc>;
95 tx-fifo-depth = <0x40>;
96 rx-fifo-depth = <0x40>;
97 };
Soren Brinkmanne0a5c552014-07-10 11:53:38 -070098
99 gpio0: gpio@e000a000 {
100 compatible = "xlnx,zynq-gpio-1.0";
101 #gpio-cells = <2>;
102 clocks = <&clkc 42>;
103 gpio-controller;
Soren Brinkmanne57f6e52015-10-23 09:25:31 -0700104 interrupt-controller;
105 #interrupt-cells = <2>;
Soren Brinkmanne0a5c552014-07-10 11:53:38 -0700106 interrupt-parent = <&intc>;
107 interrupts = <0 20 4>;
108 reg = <0xe000a000 0x1000>;
Soren Brinkmann21555602014-06-05 09:05:23 -0700109 };
110
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700111 i2c0: i2c@e0004000 {
Soren Brinkmann0f6faa32014-04-04 14:27:56 -0700112 compatible = "cdns,i2c-r1p10";
113 status = "disabled";
114 clocks = <&clkc 38>;
115 interrupt-parent = <&intc>;
116 interrupts = <0 25 4>;
117 reg = <0xe0004000 0x1000>;
118 #address-cells = <1>;
119 #size-cells = <0>;
120 };
121
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700122 i2c1: i2c@e0005000 {
Soren Brinkmann0f6faa32014-04-04 14:27:56 -0700123 compatible = "cdns,i2c-r1p10";
124 status = "disabled";
125 clocks = <&clkc 39>;
126 interrupt-parent = <&intc>;
127 interrupts = <0 48 4>;
128 reg = <0xe0005000 0x1000>;
129 #address-cells = <1>;
130 #size-cells = <0>;
131 };
132
John Linnb85a3ef2011-06-20 11:47:27 -0600133 intc: interrupt-controller@f8f01000 {
Josh Cartwrightf447ed22012-10-17 19:46:49 -0500134 compatible = "arm,cortex-a9-gic";
135 #interrupt-cells = <3>;
John Linnb85a3ef2011-06-20 11:47:27 -0600136 interrupt-controller;
Josh Cartwrightf447ed22012-10-17 19:46:49 -0500137 reg = <0xF8F01000 0x1000>,
138 <0xF8F00100 0x100>;
John Linnb85a3ef2011-06-20 11:47:27 -0600139 };
140
Michal Simek8abef062014-09-24 15:16:01 +0200141 L2: cache-controller@f8f02000 {
Josh Cartwright0fcfdbc2012-10-23 17:34:22 -0500142 compatible = "arm,pl310-cache";
143 reg = <0xF8F02000 0x1000>;
Alex Wilson6de663f2015-07-17 20:23:55 -0600144 interrupts = <0 2 4>;
Soren Brinkmann39c41df92013-07-31 16:24:59 -0700145 arm,data-latency = <3 2 2>;
146 arm,tag-latency = <2 2 2>;
Josh Cartwright0fcfdbc2012-10-23 17:34:22 -0500147 cache-unified;
148 cache-level = <2>;
149 };
150
Michal Simek6c7ba412014-09-24 15:53:39 +0200151 mc: memory-controller@f8006000 {
Soren Brinkmann36ad5ae2014-09-02 14:19:08 -0700152 compatible = "xlnx,zynq-ddrc-a05";
153 reg = <0xf8006000 0x1000>;
Michal Simek2329efb2014-10-20 15:15:47 +0200154 };
Soren Brinkmann36ad5ae2014-09-02 14:19:08 -0700155
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700156 uart0: serial@e0000000 {
Soren Brinkmann8fe93462014-04-04 17:23:45 -0700157 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
Soren Brinkmannec11ebc2013-06-13 09:37:16 -0700158 status = "disabled";
Soren Brinkmann30e1e282013-05-13 10:46:38 -0700159 clocks = <&clkc 23>, <&clkc 40>;
Soren Brinkmann8fe93462014-04-04 17:23:45 -0700160 clock-names = "uart_clk", "pclk";
John Linnb85a3ef2011-06-20 11:47:27 -0600161 reg = <0xE0000000 0x1000>;
Josh Cartwrightf447ed22012-10-17 19:46:49 -0500162 interrupts = <0 27 4>;
John Linnb85a3ef2011-06-20 11:47:27 -0600163 };
Josh Cartwright78d67852012-10-31 13:45:17 -0600164
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700165 uart1: serial@e0001000 {
Soren Brinkmann8fe93462014-04-04 17:23:45 -0700166 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
Soren Brinkmannec11ebc2013-06-13 09:37:16 -0700167 status = "disabled";
Soren Brinkmann30e1e282013-05-13 10:46:38 -0700168 clocks = <&clkc 24>, <&clkc 41>;
Soren Brinkmann8fe93462014-04-04 17:23:45 -0700169 clock-names = "uart_clk", "pclk";
Josh Cartwright78d67852012-10-31 13:45:17 -0600170 reg = <0xE0001000 0x1000>;
171 interrupts = <0 50 4>;
Josh Cartwright78d67852012-10-31 13:45:17 -0600172 };
Josh Cartwright0f586fb2012-11-08 12:04:26 -0600173
Andreas Färberf07ab7a2014-07-25 13:12:31 +0200174 spi0: spi@e0006000 {
175 compatible = "xlnx,zynq-spi-r1p6";
176 reg = <0xe0006000 0x1000>;
177 status = "disabled";
178 interrupt-parent = <&intc>;
179 interrupts = <0 26 4>;
180 clocks = <&clkc 25>, <&clkc 34>;
181 clock-names = "ref_clk", "pclk";
182 #address-cells = <1>;
183 #size-cells = <0>;
184 };
185
186 spi1: spi@e0007000 {
187 compatible = "xlnx,zynq-spi-r1p6";
188 reg = <0xe0007000 0x1000>;
189 status = "disabled";
190 interrupt-parent = <&intc>;
191 interrupts = <0 49 4>;
192 clocks = <&clkc 26>, <&clkc 35>;
193 clock-names = "ref_clk", "pclk";
194 #address-cells = <1>;
195 #size-cells = <0>;
196 };
197
Steffen Trumtrar982264c2013-12-11 09:29:49 -0800198 gem0: ethernet@e000b000 {
Nathan Sullivan4481b182015-05-27 15:00:01 -0500199 compatible = "cdns,zynq-gem", "cdns,gem";
Soren Brinkmannb5241fb2014-09-16 08:08:38 -0700200 reg = <0xe000b000 0x1000>;
Steffen Trumtrar982264c2013-12-11 09:29:49 -0800201 status = "disabled";
202 interrupts = <0 22 4>;
203 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
204 clock-names = "pclk", "hclk", "tx_clk";
Soren Brinkmannedbd35e2014-08-20 08:56:58 -0700205 #address-cells = <1>;
206 #size-cells = <0>;
Steffen Trumtrar982264c2013-12-11 09:29:49 -0800207 };
208
209 gem1: ethernet@e000c000 {
Nathan Sullivan4481b182015-05-27 15:00:01 -0500210 compatible = "cdns,zynq-gem", "cdns,gem";
Soren Brinkmannb5241fb2014-09-16 08:08:38 -0700211 reg = <0xe000c000 0x1000>;
Steffen Trumtrar982264c2013-12-11 09:29:49 -0800212 status = "disabled";
213 interrupts = <0 45 4>;
214 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
215 clock-names = "pclk", "hclk", "tx_clk";
Soren Brinkmannedbd35e2014-08-20 08:56:58 -0700216 #address-cells = <1>;
217 #size-cells = <0>;
Steffen Trumtrar982264c2013-12-11 09:29:49 -0800218 };
219
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700220 sdhci0: sdhci@e0100000 {
Soren Brinkmann3f7c7302013-12-02 10:02:37 -0800221 compatible = "arasan,sdhci-8.9a";
222 status = "disabled";
223 clock-names = "clk_xin", "clk_ahb";
224 clocks = <&clkc 21>, <&clkc 32>;
225 interrupt-parent = <&intc>;
226 interrupts = <0 24 4>;
227 reg = <0xe0100000 0x1000>;
Michal Simeke65b1582014-08-21 12:45:05 +0200228 };
Soren Brinkmann3f7c7302013-12-02 10:02:37 -0800229
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700230 sdhci1: sdhci@e0101000 {
Soren Brinkmann3f7c7302013-12-02 10:02:37 -0800231 compatible = "arasan,sdhci-8.9a";
232 status = "disabled";
233 clock-names = "clk_xin", "clk_ahb";
234 clocks = <&clkc 22>, <&clkc 33>;
235 interrupt-parent = <&intc>;
236 interrupts = <0 47 4>;
237 reg = <0xe0101000 0x1000>;
Michal Simeke65b1582014-08-21 12:45:05 +0200238 };
Soren Brinkmann3f7c7302013-12-02 10:02:37 -0800239
Josh Cartwright0f586fb2012-11-08 12:04:26 -0600240 slcr: slcr@f8000000 {
Michal Simekb0504e32013-11-18 16:48:19 +0100241 #address-cells = <1>;
242 #size-cells = <1>;
Masahiro Yamadabc5ba9b2015-11-05 17:46:06 +0900243 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
Josh Cartwright0f586fb2012-11-08 12:04:26 -0600244 reg = <0xF8000000 0x1000>;
Michal Simekb0504e32013-11-18 16:48:19 +0100245 ranges;
246 clkc: clkc@100 {
247 #clock-cells = <1>;
248 compatible = "xlnx,ps7-clkc";
Michal Simekb0504e32013-11-18 16:48:19 +0100249 fclk-enable = <0>;
250 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
251 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
252 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
253 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
254 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
255 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
256 "gem1_aper", "sdio0_aper", "sdio1_aper",
257 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
258 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
259 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
260 "dbg_trc", "dbg_apb";
261 reg = <0x100 0x100>;
Josh Cartwright0f586fb2012-11-08 12:04:26 -0600262 };
Soren Brinkmannf52948e2015-01-09 07:43:50 -0800263
Moritz Fischer99650c22015-07-30 18:13:55 -0700264 rstc: rstc@200 {
265 compatible = "xlnx,zynq-reset";
266 reg = <0x200 0x48>;
267 #reset-cells = <1>;
268 syscon = <&slcr>;
269 };
270
Soren Brinkmannf52948e2015-01-09 07:43:50 -0800271 pinctrl0: pinctrl@700 {
272 compatible = "xlnx,pinctrl-zynq";
273 reg = <0x700 0x200>;
274 syscon = <&slcr>;
275 };
Josh Cartwright0f586fb2012-11-08 12:04:26 -0600276 };
Josh Cartwright91dc9852012-10-31 13:56:14 -0600277
Andreas Färberfbb4add2014-07-25 01:00:15 +0200278 dmac_s: dmac@f8003000 {
279 compatible = "arm,pl330", "arm,primecell";
280 reg = <0xf8003000 0x1000>;
281 interrupt-parent = <&intc>;
Michal Simek41683582014-08-21 11:27:05 +0200282 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
283 "dma4", "dma5", "dma6", "dma7";
Andreas Färberfbb4add2014-07-25 01:00:15 +0200284 interrupts = <0 13 4>,
285 <0 14 4>, <0 15 4>,
286 <0 16 4>, <0 17 4>,
287 <0 40 4>, <0 41 4>,
288 <0 42 4>, <0 43 4>;
289 #dma-cells = <1>;
290 #dma-channels = <8>;
291 #dma-requests = <4>;
292 clocks = <&clkc 27>;
293 clock-names = "apb_pclk";
294 };
295
Michal Simek00f7dc62013-07-31 09:19:59 +0200296 devcfg: devcfg@f8007000 {
297 compatible = "xlnx,zynq-devcfg-1.0";
298 reg = <0xf8007000 0x100>;
Moritz Fischer20598492015-10-16 15:42:29 -0700299 interrupt-parent = <&intc>;
300 interrupts = <0 8 4>;
301 clocks = <&clkc 12>;
302 clock-names = "ref_clk";
303 syscon = <&slcr>;
Michal Simeke65b1582014-08-21 12:45:05 +0200304 };
Michal Simek00f7dc62013-07-31 09:19:59 +0200305
Soren Brinkmannfa94bd52013-09-18 11:48:38 -0700306 global_timer: timer@f8f00200 {
307 compatible = "arm,cortex-a9-global-timer";
308 reg = <0xf8f00200 0x20>;
309 interrupts = <1 11 0x301>;
310 interrupt-parent = <&intc>;
311 clocks = <&clkc 4>;
312 };
313
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700314 ttc0: timer@f8001000 {
Michal Simeke9329002013-03-20 10:15:28 +0100315 interrupt-parent = <&intc>;
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700316 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
Michal Simeke9329002013-03-20 10:15:28 +0100317 compatible = "cdns,ttc";
Soren Brinkmann30e1e282013-05-13 10:46:38 -0700318 clocks = <&clkc 6>;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600319 reg = <0xF8001000 0x1000>;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600320 };
321
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700322 ttc1: timer@f8002000 {
Michal Simeke9329002013-03-20 10:15:28 +0100323 interrupt-parent = <&intc>;
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700324 interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
Michal Simeke9329002013-03-20 10:15:28 +0100325 compatible = "cdns,ttc";
Soren Brinkmann30e1e282013-05-13 10:46:38 -0700326 clocks = <&clkc 6>;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600327 reg = <0xF8002000 0x1000>;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600328 };
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700329
330 scutimer: timer@f8f00600 {
Michal Simek2f34e0a2013-03-27 13:36:39 +0100331 interrupt-parent = <&intc>;
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700332 interrupts = <1 13 0x301>;
Michal Simek2f34e0a2013-03-27 13:36:39 +0100333 compatible = "arm,cortex-a9-twd-timer";
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700334 reg = <0xf8f00600 0x20>;
Soren Brinkmann30e1e282013-05-13 10:46:38 -0700335 clocks = <&clkc 4>;
Michal Simeke65b1582014-08-21 12:45:05 +0200336 };
Michal Simek67142972014-10-02 15:09:15 +0200337
Soren Brinkmann1643b312014-12-02 08:07:11 -0800338 usb0: usb@e0002000 {
339 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
340 status = "disabled";
341 clocks = <&clkc 28>;
342 interrupt-parent = <&intc>;
343 interrupts = <0 21 4>;
344 reg = <0xe0002000 0x1000>;
345 phy_type = "ulpi";
346 };
347
348 usb1: usb@e0003000 {
349 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
350 status = "disabled";
351 clocks = <&clkc 29>;
352 interrupt-parent = <&intc>;
353 interrupts = <0 44 4>;
354 reg = <0xe0003000 0x1000>;
355 phy_type = "ulpi";
356 };
357
Michal Simek67142972014-10-02 15:09:15 +0200358 watchdog0: watchdog@f8005000 {
359 clocks = <&clkc 45>;
Michal Simek8f63a0b2015-01-15 13:45:08 +0100360 compatible = "cdns,wdt-r1p2";
Michal Simek67142972014-10-02 15:09:15 +0200361 interrupt-parent = <&intc>;
362 interrupts = <0 9 1>;
363 reg = <0xf8005000 0x1000>;
Michal Simek67142972014-10-02 15:09:15 +0200364 timeout-sec = <10>;
365 };
John Linnb85a3ef2011-06-20 11:47:27 -0600366 };
367};