blob: e627eadd357b3d298276247fee6c8e8faa6566d4 [file] [log] [blame]
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001config ARM64
2 def_bool y
Arun Chandran92980402014-10-10 12:31:24 +01003 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01004 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
Riku Voipio957e3fa2014-12-12 16:57:44 -08005 select ARCH_HAS_GCOV_PROFILE_ALL
Laura Abbott308c09f2014-08-08 14:23:25 -07006 select ARCH_HAS_SG_CHAIN
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +01007 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
Sudeep Hollac63c8702014-05-09 10:33:01 +01008 select ARCH_USE_CMPXCHG_LOCKREF
Peter Zijlstra4badad32014-06-06 19:53:16 +02009 select ARCH_SUPPORTS_ATOMIC_RMW
Arnd Bergmann91701002013-02-21 11:42:57 +010010 select ARCH_WANT_OPTIONAL_GPIOLIB
Will Deacon6212a512012-11-07 14:16:28 +000011 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
Catalin Marinasb6f35982013-01-29 18:25:41 +000012 select ARCH_WANT_FRAME_POINTERS
Catalin Marinas25c92a32012-12-18 15:26:13 +000013 select ARM_AMBA
Mark Rutland1aee5d72012-11-20 10:06:00 +000014 select ARM_ARCH_TIMER
Catalin Marinasc4188ed2013-01-14 12:39:31 +000015 select ARM_GIC
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010016 select AUDIT_ARCH_COMPAT_GENERIC
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000017 select ARM_GIC_V2M if PCI_MSI
Marc Zyngier021f6532014-06-30 16:01:31 +010018 select ARM_GIC_V3
Marc Zyngier19812722014-11-24 14:35:19 +000019 select ARM_GIC_V3_ITS if PCI_MSI
Will Deaconadace892013-05-08 17:29:24 +010020 select BUILDTIME_EXTABLE_SORT
Catalin Marinasdb2789b2012-12-18 15:27:25 +000021 select CLONE_BACKWARDS
Deepak Saxena7ca2ef32012-09-22 10:33:36 -070022 select COMMON_CLK
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +000023 select CPU_PM if (SUSPEND || CPU_IDLE)
Will Deacon7bc13fd2013-11-06 19:32:13 +000024 select DCACHE_WORD_ACCESS
Laura Abbottd4932f92014-10-09 15:26:44 -070025 select GENERIC_ALLOCATOR
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010026 select GENERIC_CLOCKEVENTS
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010027 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
Ard Biesheuvel3be1a5c2014-03-04 01:10:04 +000028 select GENERIC_CPU_AUTOPROBE
Mark Salterbf4b5582014-04-07 15:39:52 -070029 select GENERIC_EARLY_IOREMAP
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010030 select GENERIC_IRQ_PROBE
31 select GENERIC_IRQ_SHOW
Arnd Bergmanncb61f672014-11-19 14:09:07 +010032 select GENERIC_PCI_IOMAP
Stephen Boyd65cd4f62013-07-18 16:21:18 -070033 select GENERIC_SCHED_CLOCK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010034 select GENERIC_SMP_IDLE_THREAD
Will Deacon12a0ef72013-11-06 17:20:22 +000035 select GENERIC_STRNCPY_FROM_USER
36 select GENERIC_STRNLEN_USER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010037 select GENERIC_TIME_VSYSCALL
Marc Zyngiera1ddc742014-08-26 11:03:17 +010038 select HANDLE_DOMAIN_IRQ
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010039 select HARDIRQS_SW_RESEND
Steve Capper5284e1b2014-10-24 13:22:20 +010040 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010041 select HAVE_ARCH_AUDITSYSCALL
Jiang Liu9732caf2014-01-07 22:17:13 +080042 select HAVE_ARCH_JUMP_LABEL
Vijaya Kumar K95292472014-01-28 11:20:22 +000043 select HAVE_ARCH_KGDB
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +000044 select HAVE_ARCH_SECCOMP_FILTER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010045 select HAVE_ARCH_TRACEHOOK
Zi Shen Lime54bcde2014-08-26 21:15:30 -070046 select HAVE_BPF_JIT
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010047 select HAVE_C_RECORDMCOUNT
Laura Abbottc0c264a2014-06-25 23:55:03 +010048 select HAVE_CC_STACKPROTECTOR
Steve Capper5284e1b2014-10-24 13:22:20 +010049 select HAVE_CMPXCHG_DOUBLE
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070050 select HAVE_DEBUG_BUGVERBOSE
Catalin Marinasb69ec422012-10-08 16:28:11 -070051 select HAVE_DEBUG_KMEMLEAK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010052 select HAVE_DMA_API_DEBUG
53 select HAVE_DMA_ATTRS
Laura Abbott6ac21042013-12-12 19:28:33 +000054 select HAVE_DMA_CONTIGUOUS
AKASHI Takahirobd7d38d2014-04-30 10:54:34 +010055 select HAVE_DYNAMIC_FTRACE
Will Deacon50afc332013-12-16 17:50:08 +000056 select HAVE_EFFICIENT_UNALIGNED_ACCESS
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010057 select HAVE_FTRACE_MCOUNT_RECORD
AKASHI Takahiro819e50e2014-04-30 18:54:33 +090058 select HAVE_FUNCTION_TRACER
59 select HAVE_FUNCTION_GRAPH_TRACER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010060 select HAVE_GENERIC_DMA_COHERENT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010061 select HAVE_HW_BREAKPOINT if PERF_EVENTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010062 select HAVE_MEMBLOCK
Mark Rutland55834a72014-02-07 17:12:45 +000063 select HAVE_PATA_PLATFORM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010064 select HAVE_PERF_EVENTS
Jean Pihet2ee0d7f2014-02-03 19:18:27 +010065 select HAVE_PERF_REGS
66 select HAVE_PERF_USER_STACK_DUMP
Steve Capper5e5f6dc2014-10-09 15:29:23 -070067 select HAVE_RCU_TABLE_FREE
AKASHI Takahiro055b1212014-04-30 10:54:36 +010068 select HAVE_SYSCALL_TRACEPOINTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010069 select IRQ_DOMAIN
Catalin Marinasfea2aca2012-10-16 11:26:57 +010070 select MODULES_USE_ELF_RELA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010071 select NO_BOOTMEM
72 select OF
73 select OF_EARLY_FLATTREE
Marek Szyprowski9bf14b72014-02-28 14:42:55 +010074 select OF_RESERVED_MEM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010075 select PERF_USE_VMALLOC
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +000076 select POWER_RESET
77 select POWER_SUPPLY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010078 select RTC_LIB
79 select SPARSE_IRQ
Catalin Marinas7ac57a82012-10-08 16:28:16 -070080 select SYSCTL_EXCEPTION_TRACE
Larry Bassel6c81fe72014-05-30 12:34:15 -070081 select HAVE_CONTEXT_TRACKING
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010082 help
83 ARM 64-bit (AArch64) Linux support.
84
85config 64BIT
86 def_bool y
87
88config ARCH_PHYS_ADDR_T_64BIT
89 def_bool y
90
91config MMU
92 def_bool y
93
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -070094config NO_IOPORT_MAP
Liviu Dudaud1e6dc92014-09-29 15:29:31 +010095 def_bool y if !PCI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010096
97config STACKTRACE_SUPPORT
98 def_bool y
99
100config LOCKDEP_SUPPORT
101 def_bool y
102
103config TRACE_IRQFLAGS_SUPPORT
104 def_bool y
105
Will Deaconc209f792014-03-14 17:47:05 +0000106config RWSEM_XCHGADD_ALGORITHM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100107 def_bool y
108
109config GENERIC_HWEIGHT
110 def_bool y
111
112config GENERIC_CSUM
113 def_bool y
114
115config GENERIC_CALIBRATE_DELAY
116 def_bool y
117
Catalin Marinas19e76402014-02-27 12:09:22 +0000118config ZONE_DMA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100119 def_bool y
120
Steve Capper29e56942014-10-09 15:29:25 -0700121config HAVE_GENERIC_RCU_GUP
122 def_bool y
123
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100124config ARCH_DMA_ADDR_T_64BIT
125 def_bool y
126
127config NEED_DMA_MAP_STATE
128 def_bool y
129
130config NEED_SG_DMA_LENGTH
131 def_bool y
132
133config SWIOTLB
134 def_bool y
135
136config IOMMU_HELPER
137 def_bool SWIOTLB
138
Ard Biesheuvel4cfb3612013-07-09 14:18:12 +0100139config KERNEL_MODE_NEON
140 def_bool y
141
Rob Herring92cc15f2014-04-18 17:19:59 -0500142config FIX_EARLYCON_MEM
143 def_bool y
144
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100145source "init/Kconfig"
146
147source "kernel/Kconfig.freezer"
148
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100149menu "Platform selection"
150
Eddie Huang4727a6f2015-12-01 10:14:00 +0100151config ARCH_MEDIATEK
152 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
153 select ARM_GIC
154 help
155 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
156
Suravee Suthikulpanit41904362014-11-26 11:51:09 +0700157config ARCH_SEATTLE
158 bool "AMD Seattle SoC Family"
159 help
160 This enables support for AMD Seattle SOC Family
161
Radha Mohan Chintakuntla28f74202014-04-08 18:47:51 +0530162config ARCH_THUNDER
163 bool "Cavium Inc. Thunder SoC Family"
164 help
165 This enables support for Cavium's Thunder Family of SoCs.
166
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100167config ARCH_VEXPRESS
168 bool "ARMv8 software model (Versatile Express)"
169 select ARCH_REQUIRE_GPIOLIB
170 select COMMON_CLK_VERSATILE
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +0000171 select POWER_RESET_VEXPRESS
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100172 select VEXPRESS_CONFIG
173 help
174 This enables support for the ARMv8 software model (Versatile
175 Express).
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100176
Vinayak Kale15942852013-04-24 10:06:57 +0100177config ARCH_XGENE
178 bool "AppliedMicro X-Gene SOC Family"
179 help
180 This enables support for AppliedMicro X-Gene SOC Family
181
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100182endmenu
183
184menu "Bus support"
185
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100186config PCI
187 bool "PCI support"
188 help
189 This feature enables support for PCI bus system. If you say Y
190 here, the kernel will include drivers and infrastructure code
191 to support PCI bus devices.
192
193config PCI_DOMAINS
194 def_bool PCI
195
196config PCI_DOMAINS_GENERIC
197 def_bool PCI
198
199config PCI_SYSCALL
200 def_bool PCI
201
202source "drivers/pci/Kconfig"
203source "drivers/pci/pcie/Kconfig"
204source "drivers/pci/hotplug/Kconfig"
205
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100206endmenu
207
208menu "Kernel Features"
209
Andre Przywarac0a01b82014-11-14 15:54:12 +0000210menu "ARM errata workarounds via the alternatives framework"
211
212config ARM64_ERRATUM_826319
213 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
214 default y
215 help
216 This option adds an alternative code sequence to work around ARM
217 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
218 AXI master interface and an L2 cache.
219
220 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
221 and is unable to accept a certain write via this interface, it will
222 not progress on read data presented on the read data channel and the
223 system can deadlock.
224
225 The workaround promotes data cache clean instructions to
226 data cache clean-and-invalidate.
227 Please note that this does not necessarily enable the workaround,
228 as it depends on the alternative framework, which will only patch
229 the kernel if an affected CPU is detected.
230
231 If unsure, say Y.
232
233config ARM64_ERRATUM_827319
234 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
235 default y
236 help
237 This option adds an alternative code sequence to work around ARM
238 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
239 master interface and an L2 cache.
240
241 Under certain conditions this erratum can cause a clean line eviction
242 to occur at the same time as another transaction to the same address
243 on the AMBA 5 CHI interface, which can cause data corruption if the
244 interconnect reorders the two transactions.
245
246 The workaround promotes data cache clean instructions to
247 data cache clean-and-invalidate.
248 Please note that this does not necessarily enable the workaround,
249 as it depends on the alternative framework, which will only patch
250 the kernel if an affected CPU is detected.
251
252 If unsure, say Y.
253
254config ARM64_ERRATUM_824069
255 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
256 default y
257 help
258 This option adds an alternative code sequence to work around ARM
259 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
260 to a coherent interconnect.
261
262 If a Cortex-A53 processor is executing a store or prefetch for
263 write instruction at the same time as a processor in another
264 cluster is executing a cache maintenance operation to the same
265 address, then this erratum might cause a clean cache line to be
266 incorrectly marked as dirty.
267
268 The workaround promotes data cache clean instructions to
269 data cache clean-and-invalidate.
270 Please note that this option does not necessarily enable the
271 workaround, as it depends on the alternative framework, which will
272 only patch the kernel if an affected CPU is detected.
273
274 If unsure, say Y.
275
276config ARM64_ERRATUM_819472
277 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
278 default y
279 help
280 This option adds an alternative code sequence to work around ARM
281 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
282 present when it is connected to a coherent interconnect.
283
284 If the processor is executing a load and store exclusive sequence at
285 the same time as a processor in another cluster is executing a cache
286 maintenance operation to the same address, then this erratum might
287 cause data corruption.
288
289 The workaround promotes data cache clean instructions to
290 data cache clean-and-invalidate.
291 Please note that this does not necessarily enable the workaround,
292 as it depends on the alternative framework, which will only patch
293 the kernel if an affected CPU is detected.
294
295 If unsure, say Y.
296
297config ARM64_ERRATUM_832075
298 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
299 default y
300 help
301 This option adds an alternative code sequence to work around ARM
302 erratum 832075 on Cortex-A57 parts up to r1p2.
303
304 Affected Cortex-A57 parts might deadlock when exclusive load/store
305 instructions to Write-Back memory are mixed with Device loads.
306
307 The workaround is to promote device loads to use Load-Acquire
308 semantics.
309 Please note that this does not necessarily enable the workaround,
310 as it depends on the alternative framework, which will only patch
311 the kernel if an affected CPU is detected.
312
313 If unsure, say Y.
314
315endmenu
316
317
Jungseok Leee41ceed2014-05-12 10:40:38 +0100318choice
319 prompt "Page size"
320 default ARM64_4K_PAGES
321 help
322 Page size (translation granule) configuration.
323
324config ARM64_4K_PAGES
325 bool "4KB"
326 help
327 This feature enables 4KB pages support.
328
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100329config ARM64_64K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100330 bool "64KB"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100331 help
332 This feature enables 64KB pages support (4KB by default)
333 allowing only two levels of page tables and faster TLB
334 look-up. AArch32 emulation is not available when this feature
335 is enabled.
336
Jungseok Leee41ceed2014-05-12 10:40:38 +0100337endchoice
338
339choice
340 prompt "Virtual address space size"
341 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
342 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
343 help
344 Allows choosing one of multiple possible virtual address
345 space sizes. The level of translation table is determined by
346 a combination of page size and virtual address space size.
347
348config ARM64_VA_BITS_39
349 bool "39-bit"
350 depends on ARM64_4K_PAGES
351
352config ARM64_VA_BITS_42
353 bool "42-bit"
354 depends on ARM64_64K_PAGES
355
Jungseok Leec79b9542014-05-12 18:40:51 +0900356config ARM64_VA_BITS_48
357 bool "48-bit"
Christoffer Dall04f905a2014-10-10 11:14:30 +0100358 depends on !ARM_SMMU
Jungseok Leec79b9542014-05-12 18:40:51 +0900359
Jungseok Leee41ceed2014-05-12 10:40:38 +0100360endchoice
361
362config ARM64_VA_BITS
363 int
364 default 39 if ARM64_VA_BITS_39
365 default 42 if ARM64_VA_BITS_42
Jungseok Leec79b9542014-05-12 18:40:51 +0900366 default 48 if ARM64_VA_BITS_48
Jungseok Leee41ceed2014-05-12 10:40:38 +0100367
Catalin Marinasabe669d2014-07-15 15:37:21 +0100368config ARM64_PGTABLE_LEVELS
369 int
370 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
Catalin Marinas383c2792014-07-21 15:54:50 +0100371 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
Catalin Marinasabe669d2014-07-15 15:37:21 +0100372 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
373 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
Jungseok Leec79b9542014-05-12 18:40:51 +0900374
Will Deacona8720132013-10-11 14:52:19 +0100375config CPU_BIG_ENDIAN
376 bool "Build big-endian kernel"
377 help
378 Say Y if you plan on running a kernel in big-endian mode.
379
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100380config SMP
381 bool "Symmetric Multi-Processing"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100382 help
383 This enables support for systems with more than one CPU. If
384 you say N here, the kernel will run on single and
385 multiprocessor machines, but will use only one CPU of a
386 multiprocessor machine. If you say Y here, the kernel will run
387 on many, but not all, single processor machines. On a single
388 processor machine, the kernel will run faster if you say N
389 here.
390
391 If you don't know what to do here, say N.
392
Mark Brownf6e763b2014-03-04 07:51:17 +0000393config SCHED_MC
394 bool "Multi-core scheduler support"
395 depends on SMP
396 help
397 Multi-core scheduler support improves the CPU scheduler's decision
398 making when dealing with multi-core CPU chips at a cost of slightly
399 increased overhead in some places. If unsure say N here.
400
401config SCHED_SMT
402 bool "SMT scheduler support"
403 depends on SMP
404 help
405 Improves the CPU scheduler's decision making when dealing with
406 MultiThreading at a cost of slightly increased overhead in some
407 places. If unsure say N here.
408
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100409config NR_CPUS
Robert Richtere3672642014-09-08 12:44:48 +0100410 int "Maximum number of CPUs (2-64)"
411 range 2 64
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100412 depends on SMP
Vinayak Kale15942852013-04-24 10:06:57 +0100413 # These have to remain sorted largest to smallest
Robert Richtere3672642014-09-08 12:44:48 +0100414 default "64"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100415
Mark Rutland9327e2c2013-10-24 20:30:18 +0100416config HOTPLUG_CPU
417 bool "Support for hot-pluggable CPUs"
418 depends on SMP
419 help
420 Say Y here to experiment with turning CPUs off and on. CPUs
421 can be controlled through /sys/devices/system/cpu.
422
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100423source kernel/Kconfig.preempt
424
425config HZ
426 int
427 default 100
428
429config ARCH_HAS_HOLES_MEMORYMODEL
430 def_bool y if SPARSEMEM
431
432config ARCH_SPARSEMEM_ENABLE
433 def_bool y
434 select SPARSEMEM_VMEMMAP_ENABLE
435
436config ARCH_SPARSEMEM_DEFAULT
437 def_bool ARCH_SPARSEMEM_ENABLE
438
439config ARCH_SELECT_MEMORY_MODEL
440 def_bool ARCH_SPARSEMEM_ENABLE
441
442config HAVE_ARCH_PFN_VALID
443 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
444
445config HW_PERF_EVENTS
446 bool "Enable hardware performance counter support for perf events"
447 depends on PERF_EVENTS
448 default y
449 help
450 Enable hardware performance counter support for perf events. If
451 disabled, perf events will use software events only.
452
Steve Capper084bd292013-04-10 13:48:00 +0100453config SYS_SUPPORTS_HUGETLBFS
454 def_bool y
455
456config ARCH_WANT_GENERAL_HUGETLB
457 def_bool y
458
459config ARCH_WANT_HUGE_PMD_SHARE
460 def_bool y if !ARM64_64K_PAGES
461
Steve Capperaf074842013-04-19 16:23:57 +0100462config HAVE_ARCH_TRANSPARENT_HUGEPAGE
463 def_bool y
464
Catalin Marinasa41dc0e2014-04-03 17:48:54 +0100465config ARCH_HAS_CACHE_LINE_SIZE
466 def_bool y
467
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100468source "mm/Kconfig"
469
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +0000470config SECCOMP
471 bool "Enable seccomp to safely compute untrusted bytecode"
472 ---help---
473 This kernel feature is useful for number crunching applications
474 that may need to compute untrusted bytecode during their
475 execution. By using pipes or other transports made available to
476 the process as file descriptors supporting the read/write
477 syscalls, it's possible to isolate those applications in
478 their own address space using seccomp. Once seccomp is
479 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
480 and the task is only allowed to execute a few safe syscalls
481 defined by each seccomp mode.
482
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000483config XEN_DOM0
484 def_bool y
485 depends on XEN
486
487config XEN
Julien Grallc2ba1f72014-09-17 14:07:06 -0700488 bool "Xen guest support on ARM64"
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000489 depends on ARM64 && OF
Stefano Stabellini83862cc2013-10-10 13:40:44 +0000490 select SWIOTLB_XEN
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000491 help
492 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
493
Steve Capperd03bb142013-04-25 15:19:21 +0100494config FORCE_MAX_ZONEORDER
495 int
496 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
497 default "11"
498
Will Deacon1b907f42014-11-20 16:51:10 +0000499menuconfig ARMV8_DEPRECATED
500 bool "Emulate deprecated/obsolete ARMv8 instructions"
501 depends on COMPAT
502 help
503 Legacy software support may require certain instructions
504 that have been deprecated or obsoleted in the architecture.
505
506 Enable this config to enable selective emulation of these
507 features.
508
509 If unsure, say Y
510
511if ARMV8_DEPRECATED
512
513config SWP_EMULATION
514 bool "Emulate SWP/SWPB instructions"
515 help
516 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
517 they are always undefined. Say Y here to enable software
518 emulation of these instructions for userspace using LDXR/STXR.
519
520 In some older versions of glibc [<=2.8] SWP is used during futex
521 trylock() operations with the assumption that the code will not
522 be preempted. This invalid assumption may be more likely to fail
523 with SWP emulation enabled, leading to deadlock of the user
524 application.
525
526 NOTE: when accessing uncached shared regions, LDXR/STXR rely
527 on an external transaction monitoring block called a global
528 monitor to maintain update atomicity. If your system does not
529 implement a global monitor, this option can cause programs that
530 perform SWP operations to uncached memory to deadlock.
531
532 If unsure, say Y
533
534config CP15_BARRIER_EMULATION
535 bool "Emulate CP15 Barrier instructions"
536 help
537 The CP15 barrier instructions - CP15ISB, CP15DSB, and
538 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
539 strongly recommended to use the ISB, DSB, and DMB
540 instructions instead.
541
542 Say Y here to enable software emulation of these
543 instructions for AArch32 userspace code. When this option is
544 enabled, CP15 barrier usage is traced which can help
545 identify software that needs updating.
546
547 If unsure, say Y
548
549endif
550
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100551endmenu
552
553menu "Boot options"
554
555config CMDLINE
556 string "Default kernel command string"
557 default ""
558 help
559 Provide a set of default command-line options at build time by
560 entering them here. As a minimum, you should specify the the
561 root device (e.g. root=/dev/nfs).
562
563config CMDLINE_FORCE
564 bool "Always use the default kernel command string"
565 help
566 Always use the default kernel command string, even if the boot
567 loader passes other arguments to the kernel.
568 This is useful if you cannot or don't want to change the
569 command-line options your boot loader passes to the kernel.
570
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200571config EFI_STUB
572 bool
573
Mark Salterf84d0272014-04-15 21:59:30 -0400574config EFI
575 bool "UEFI runtime support"
576 depends on OF && !CPU_BIG_ENDIAN
577 select LIBFDT
578 select UCS2_STRING
579 select EFI_PARAMS_FROM_FDT
Ard Biesheuvele15dd492014-07-04 19:41:53 +0200580 select EFI_RUNTIME_WRAPPERS
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200581 select EFI_STUB
582 select EFI_ARMSTUB
Mark Salterf84d0272014-04-15 21:59:30 -0400583 default y
584 help
585 This option provides support for runtime services provided
586 by UEFI firmware (such as non-volatile variables, realtime
Mark Salter3c7f2552014-04-15 22:47:52 -0400587 clock, and platform reset). A UEFI stub is also provided to
588 allow the kernel to be booted as an EFI application. This
589 is only useful on systems that have UEFI firmware.
Mark Salterf84d0272014-04-15 21:59:30 -0400590
Yi Lid1ae8c02014-10-04 23:46:43 +0800591config DMI
592 bool "Enable support for SMBIOS (DMI) tables"
593 depends on EFI
594 default y
595 help
596 This enables SMBIOS/DMI feature for systems.
597
598 This option is only useful on systems that have UEFI firmware.
599 However, even with this option, the resultant kernel should
600 continue to boot on existing non-UEFI platforms.
601
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100602endmenu
603
604menu "Userspace binary formats"
605
606source "fs/Kconfig.binfmt"
607
608config COMPAT
609 bool "Kernel support for 32-bit EL0"
610 depends on !ARM64_64K_PAGES
611 select COMPAT_BINFMT_ELF
Catalin Marinasaf1839e2012-10-08 16:28:08 -0700612 select HAVE_UID16
Al Viro84b9e9b2012-12-25 16:29:11 -0500613 select OLD_SIGSUSPEND3
Al Viro51682032012-12-25 19:31:29 -0500614 select COMPAT_OLD_SIGACTION
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100615 help
616 This option enables support for a 32-bit EL0 running under a 64-bit
617 kernel at EL1. AArch32-specific components such as system calls,
618 the user helper functions, VFP support and the ptrace interface are
619 handled appropriately by the kernel.
620
621 If you want to execute 32-bit userspace applications, say Y.
622
623config SYSVIPC_COMPAT
624 def_bool y
625 depends on COMPAT && SYSVIPC
626
627endmenu
628
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000629menu "Power management options"
630
631source "kernel/power/Kconfig"
632
633config ARCH_SUSPEND_POSSIBLE
634 def_bool y
635
636config ARM64_CPU_SUSPEND
637 def_bool PM_SLEEP
638
639endmenu
640
Lorenzo Pieralisi13072202013-07-17 14:54:21 +0100641menu "CPU Power Management"
642
643source "drivers/cpuidle/Kconfig"
644
Rob Herring52e7e812014-02-24 11:27:57 +0900645source "drivers/cpufreq/Kconfig"
646
647endmenu
648
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100649source "net/Kconfig"
650
651source "drivers/Kconfig"
652
Mark Salterf84d0272014-04-15 21:59:30 -0400653source "drivers/firmware/Kconfig"
654
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100655source "fs/Kconfig"
656
Marc Zyngierc3eb5b12013-07-04 13:34:32 +0100657source "arch/arm64/kvm/Kconfig"
658
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100659source "arch/arm64/Kconfig.debug"
660
661source "security/Kconfig"
662
663source "crypto/Kconfig"
Ard Biesheuvel2c988332014-03-06 16:23:33 +0800664if CRYPTO
665source "arch/arm64/crypto/Kconfig"
666endif
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100667
668source "lib/Kconfig"