Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 ARM Ltd. |
| 3 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 17 | */ |
| 18 | |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 19 | #include <linux/cpu.h> |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 20 | #include <linux/kvm.h> |
| 21 | #include <linux/kvm_host.h> |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/io.h> |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 24 | #include <linux/of.h> |
| 25 | #include <linux/of_address.h> |
| 26 | #include <linux/of_irq.h> |
Christoffer Dall | 2a2f3e26 | 2014-02-02 13:41:02 -0800 | [diff] [blame] | 27 | #include <linux/uaccess.h> |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 28 | |
| 29 | #include <linux/irqchip/arm-gic.h> |
| 30 | |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 31 | #include <asm/kvm_emulate.h> |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 32 | #include <asm/kvm_arm.h> |
| 33 | #include <asm/kvm_mmu.h> |
Eric Auger | 174178f | 2015-03-04 11:14:36 +0100 | [diff] [blame] | 34 | #include <trace/events/kvm.h> |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 35 | |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 36 | /* |
| 37 | * How the whole thing works (courtesy of Christoffer Dall): |
| 38 | * |
| 39 | * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if |
Christoffer Dall | 7e36291 | 2014-06-14 22:34:04 +0200 | [diff] [blame] | 40 | * something is pending on the CPU interface. |
| 41 | * - Interrupts that are pending on the distributor are stored on the |
| 42 | * vgic.irq_pending vgic bitmap (this bitmap is updated by both user land |
| 43 | * ioctls and guest mmio ops, and other in-kernel peripherals such as the |
| 44 | * arch. timers). |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 45 | * - Every time the bitmap changes, the irq_pending_on_cpu oracle is |
| 46 | * recalculated |
| 47 | * - To calculate the oracle, we need info for each cpu from |
| 48 | * compute_pending_for_cpu, which considers: |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 49 | * - PPI: dist->irq_pending & dist->irq_enable |
| 50 | * - SPI: dist->irq_pending & dist->irq_enable & dist->irq_spi_target |
Christoffer Dall | 7e36291 | 2014-06-14 22:34:04 +0200 | [diff] [blame] | 51 | * - irq_spi_target is a 'formatted' version of the GICD_ITARGETSRn |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 52 | * registers, stored on each vcpu. We only keep one bit of |
| 53 | * information per interrupt, making sure that only one vcpu can |
| 54 | * accept the interrupt. |
Christoffer Dall | 7e36291 | 2014-06-14 22:34:04 +0200 | [diff] [blame] | 55 | * - If any of the above state changes, we must recalculate the oracle. |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 56 | * - The same is true when injecting an interrupt, except that we only |
| 57 | * consider a single interrupt at a time. The irq_spi_cpu array |
| 58 | * contains the target CPU for each SPI. |
| 59 | * |
| 60 | * The handling of level interrupts adds some extra complexity. We |
| 61 | * need to track when the interrupt has been EOIed, so we can sample |
| 62 | * the 'line' again. This is achieved as such: |
| 63 | * |
| 64 | * - When a level interrupt is moved onto a vcpu, the corresponding |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 65 | * bit in irq_queued is set. As long as this bit is set, the line |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 66 | * will be ignored for further interrupts. The interrupt is injected |
| 67 | * into the vcpu with the GICH_LR_EOI bit set (generate a |
| 68 | * maintenance interrupt on EOI). |
| 69 | * - When the interrupt is EOIed, the maintenance interrupt fires, |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 70 | * and clears the corresponding bit in irq_queued. This allows the |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 71 | * interrupt line to be sampled again. |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 72 | * - Note that level-triggered interrupts can also be set to pending from |
| 73 | * writes to GICD_ISPENDRn and lowering the external input line does not |
| 74 | * cause the interrupt to become inactive in such a situation. |
| 75 | * Conversely, writes to GICD_ICPENDRn do not cause the interrupt to become |
| 76 | * inactive as long as the external input line is held high. |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 77 | */ |
| 78 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 79 | #include "vgic.h" |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 80 | |
Marc Zyngier | a1fcb44 | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 81 | static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu); |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 82 | static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu); |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 83 | static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr); |
| 84 | static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc); |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 85 | |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 86 | static const struct vgic_ops *vgic_ops; |
| 87 | static const struct vgic_params *vgic; |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 88 | |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 89 | static void add_sgi_source(struct kvm_vcpu *vcpu, int irq, int source) |
| 90 | { |
| 91 | vcpu->kvm->arch.vgic.vm_ops.add_sgi_source(vcpu, irq, source); |
| 92 | } |
| 93 | |
| 94 | static bool queue_sgi(struct kvm_vcpu *vcpu, int irq) |
| 95 | { |
| 96 | return vcpu->kvm->arch.vgic.vm_ops.queue_sgi(vcpu, irq); |
| 97 | } |
| 98 | |
| 99 | int kvm_vgic_map_resources(struct kvm *kvm) |
| 100 | { |
| 101 | return kvm->arch.vgic.vm_ops.map_resources(kvm, vgic); |
| 102 | } |
| 103 | |
Victor Kamensky | 9662fb4 | 2014-06-12 09:30:10 -0700 | [diff] [blame] | 104 | /* |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 105 | * struct vgic_bitmap contains a bitmap made of unsigned longs, but |
| 106 | * extracts u32s out of them. |
Victor Kamensky | 9662fb4 | 2014-06-12 09:30:10 -0700 | [diff] [blame] | 107 | * |
| 108 | * This does not work on 64-bit BE systems, because the bitmap access |
| 109 | * will store two consecutive 32-bit words with the higher-addressed |
| 110 | * register's bits at the lower index and the lower-addressed register's |
| 111 | * bits at the higher index. |
| 112 | * |
| 113 | * Therefore, swizzle the register index when accessing the 32-bit word |
| 114 | * registers to access the right register's value. |
| 115 | */ |
| 116 | #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64 |
| 117 | #define REG_OFFSET_SWIZZLE 1 |
| 118 | #else |
| 119 | #define REG_OFFSET_SWIZZLE 0 |
| 120 | #endif |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 121 | |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 122 | static int vgic_init_bitmap(struct vgic_bitmap *b, int nr_cpus, int nr_irqs) |
| 123 | { |
| 124 | int nr_longs; |
| 125 | |
| 126 | nr_longs = nr_cpus + BITS_TO_LONGS(nr_irqs - VGIC_NR_PRIVATE_IRQS); |
| 127 | |
| 128 | b->private = kzalloc(sizeof(unsigned long) * nr_longs, GFP_KERNEL); |
| 129 | if (!b->private) |
| 130 | return -ENOMEM; |
| 131 | |
| 132 | b->shared = b->private + nr_cpus; |
| 133 | |
| 134 | return 0; |
| 135 | } |
| 136 | |
| 137 | static void vgic_free_bitmap(struct vgic_bitmap *b) |
| 138 | { |
| 139 | kfree(b->private); |
| 140 | b->private = NULL; |
| 141 | b->shared = NULL; |
| 142 | } |
| 143 | |
Christoffer Dall | 2df36a5 | 2014-09-28 16:04:26 +0200 | [diff] [blame] | 144 | /* |
| 145 | * Call this function to convert a u64 value to an unsigned long * bitmask |
| 146 | * in a way that works on both 32-bit and 64-bit LE and BE platforms. |
| 147 | * |
| 148 | * Warning: Calling this function may modify *val. |
| 149 | */ |
| 150 | static unsigned long *u64_to_bitmask(u64 *val) |
| 151 | { |
| 152 | #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32 |
| 153 | *val = (*val >> 32) | (*val << 32); |
| 154 | #endif |
| 155 | return (unsigned long *)val; |
| 156 | } |
| 157 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 158 | u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x, int cpuid, u32 offset) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 159 | { |
| 160 | offset >>= 2; |
| 161 | if (!offset) |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 162 | return (u32 *)(x->private + cpuid) + REG_OFFSET_SWIZZLE; |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 163 | else |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 164 | return (u32 *)(x->shared) + ((offset - 1) ^ REG_OFFSET_SWIZZLE); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 165 | } |
| 166 | |
| 167 | static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x, |
| 168 | int cpuid, int irq) |
| 169 | { |
| 170 | if (irq < VGIC_NR_PRIVATE_IRQS) |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 171 | return test_bit(irq, x->private + cpuid); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 172 | |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 173 | return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 174 | } |
| 175 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 176 | void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid, |
| 177 | int irq, int val) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 178 | { |
| 179 | unsigned long *reg; |
| 180 | |
| 181 | if (irq < VGIC_NR_PRIVATE_IRQS) { |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 182 | reg = x->private + cpuid; |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 183 | } else { |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 184 | reg = x->shared; |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 185 | irq -= VGIC_NR_PRIVATE_IRQS; |
| 186 | } |
| 187 | |
| 188 | if (val) |
| 189 | set_bit(irq, reg); |
| 190 | else |
| 191 | clear_bit(irq, reg); |
| 192 | } |
| 193 | |
| 194 | static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid) |
| 195 | { |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 196 | return x->private + cpuid; |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 197 | } |
| 198 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 199 | unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 200 | { |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 201 | return x->shared; |
| 202 | } |
| 203 | |
| 204 | static int vgic_init_bytemap(struct vgic_bytemap *x, int nr_cpus, int nr_irqs) |
| 205 | { |
| 206 | int size; |
| 207 | |
| 208 | size = nr_cpus * VGIC_NR_PRIVATE_IRQS; |
| 209 | size += nr_irqs - VGIC_NR_PRIVATE_IRQS; |
| 210 | |
| 211 | x->private = kzalloc(size, GFP_KERNEL); |
| 212 | if (!x->private) |
| 213 | return -ENOMEM; |
| 214 | |
| 215 | x->shared = x->private + nr_cpus * VGIC_NR_PRIVATE_IRQS / sizeof(u32); |
| 216 | return 0; |
| 217 | } |
| 218 | |
| 219 | static void vgic_free_bytemap(struct vgic_bytemap *b) |
| 220 | { |
| 221 | kfree(b->private); |
| 222 | b->private = NULL; |
| 223 | b->shared = NULL; |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 224 | } |
| 225 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 226 | u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 227 | { |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 228 | u32 *reg; |
| 229 | |
| 230 | if (offset < VGIC_NR_PRIVATE_IRQS) { |
| 231 | reg = x->private; |
| 232 | offset += cpuid * VGIC_NR_PRIVATE_IRQS; |
| 233 | } else { |
| 234 | reg = x->shared; |
| 235 | offset -= VGIC_NR_PRIVATE_IRQS; |
| 236 | } |
| 237 | |
| 238 | return reg + (offset / sizeof(u32)); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 239 | } |
| 240 | |
| 241 | #define VGIC_CFG_LEVEL 0 |
| 242 | #define VGIC_CFG_EDGE 1 |
| 243 | |
| 244 | static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq) |
| 245 | { |
| 246 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 247 | int irq_val; |
| 248 | |
| 249 | irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq); |
| 250 | return irq_val == VGIC_CFG_EDGE; |
| 251 | } |
| 252 | |
| 253 | static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq) |
| 254 | { |
| 255 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 256 | |
| 257 | return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq); |
| 258 | } |
| 259 | |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 260 | static int vgic_irq_is_queued(struct kvm_vcpu *vcpu, int irq) |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 261 | { |
| 262 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 263 | |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 264 | return vgic_bitmap_get_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 265 | } |
| 266 | |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 267 | static int vgic_irq_is_active(struct kvm_vcpu *vcpu, int irq) |
| 268 | { |
| 269 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 270 | |
| 271 | return vgic_bitmap_get_irq_val(&dist->irq_active, vcpu->vcpu_id, irq); |
| 272 | } |
| 273 | |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 274 | static void vgic_irq_set_queued(struct kvm_vcpu *vcpu, int irq) |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 275 | { |
| 276 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 277 | |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 278 | vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 1); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 279 | } |
| 280 | |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 281 | static void vgic_irq_clear_queued(struct kvm_vcpu *vcpu, int irq) |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 282 | { |
| 283 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 284 | |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 285 | vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 0); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 286 | } |
| 287 | |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 288 | static void vgic_irq_set_active(struct kvm_vcpu *vcpu, int irq) |
| 289 | { |
| 290 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 291 | |
| 292 | vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 1); |
| 293 | } |
| 294 | |
| 295 | static void vgic_irq_clear_active(struct kvm_vcpu *vcpu, int irq) |
| 296 | { |
| 297 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 298 | |
| 299 | vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 0); |
| 300 | } |
| 301 | |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 302 | static int vgic_dist_irq_get_level(struct kvm_vcpu *vcpu, int irq) |
| 303 | { |
| 304 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 305 | |
| 306 | return vgic_bitmap_get_irq_val(&dist->irq_level, vcpu->vcpu_id, irq); |
| 307 | } |
| 308 | |
| 309 | static void vgic_dist_irq_set_level(struct kvm_vcpu *vcpu, int irq) |
| 310 | { |
| 311 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 312 | |
| 313 | vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 1); |
| 314 | } |
| 315 | |
| 316 | static void vgic_dist_irq_clear_level(struct kvm_vcpu *vcpu, int irq) |
| 317 | { |
| 318 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 319 | |
| 320 | vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 0); |
| 321 | } |
| 322 | |
| 323 | static int vgic_dist_irq_soft_pend(struct kvm_vcpu *vcpu, int irq) |
| 324 | { |
| 325 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 326 | |
| 327 | return vgic_bitmap_get_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq); |
| 328 | } |
| 329 | |
| 330 | static void vgic_dist_irq_clear_soft_pend(struct kvm_vcpu *vcpu, int irq) |
| 331 | { |
| 332 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 333 | |
| 334 | vgic_bitmap_set_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq, 0); |
| 335 | } |
| 336 | |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 337 | static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq) |
| 338 | { |
| 339 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 340 | |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 341 | return vgic_bitmap_get_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 342 | } |
| 343 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 344 | void vgic_dist_irq_set_pending(struct kvm_vcpu *vcpu, int irq) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 345 | { |
| 346 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 347 | |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 348 | vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 1); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 349 | } |
| 350 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 351 | void vgic_dist_irq_clear_pending(struct kvm_vcpu *vcpu, int irq) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 352 | { |
| 353 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 354 | |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 355 | vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 0); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 356 | } |
| 357 | |
| 358 | static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq) |
| 359 | { |
| 360 | if (irq < VGIC_NR_PRIVATE_IRQS) |
| 361 | set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); |
| 362 | else |
| 363 | set_bit(irq - VGIC_NR_PRIVATE_IRQS, |
| 364 | vcpu->arch.vgic_cpu.pending_shared); |
| 365 | } |
| 366 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 367 | void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 368 | { |
| 369 | if (irq < VGIC_NR_PRIVATE_IRQS) |
| 370 | clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); |
| 371 | else |
| 372 | clear_bit(irq - VGIC_NR_PRIVATE_IRQS, |
| 373 | vcpu->arch.vgic_cpu.pending_shared); |
| 374 | } |
| 375 | |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 376 | static bool vgic_can_sample_irq(struct kvm_vcpu *vcpu, int irq) |
| 377 | { |
| 378 | return vgic_irq_is_edge(vcpu, irq) || !vgic_irq_is_queued(vcpu, irq); |
| 379 | } |
| 380 | |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 381 | /** |
| 382 | * vgic_reg_access - access vgic register |
| 383 | * @mmio: pointer to the data describing the mmio access |
| 384 | * @reg: pointer to the virtual backing of vgic distributor data |
| 385 | * @offset: least significant 2 bits used for word offset |
| 386 | * @mode: ACCESS_ mode (see defines above) |
| 387 | * |
| 388 | * Helper to make vgic register access easier using one of the access |
| 389 | * modes defined for vgic register access |
| 390 | * (read,raz,write-ignored,setbit,clearbit,write) |
| 391 | */ |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 392 | void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg, |
| 393 | phys_addr_t offset, int mode) |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 394 | { |
| 395 | int word_offset = (offset & 3) * 8; |
| 396 | u32 mask = (1UL << (mmio->len * 8)) - 1; |
| 397 | u32 regval; |
| 398 | |
| 399 | /* |
| 400 | * Any alignment fault should have been delivered to the guest |
| 401 | * directly (ARM ARM B3.12.7 "Prioritization of aborts"). |
| 402 | */ |
| 403 | |
| 404 | if (reg) { |
| 405 | regval = *reg; |
| 406 | } else { |
| 407 | BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED)); |
| 408 | regval = 0; |
| 409 | } |
| 410 | |
| 411 | if (mmio->is_write) { |
| 412 | u32 data = mmio_data_read(mmio, mask) << word_offset; |
| 413 | switch (ACCESS_WRITE_MASK(mode)) { |
| 414 | case ACCESS_WRITE_IGNORED: |
| 415 | return; |
| 416 | |
| 417 | case ACCESS_WRITE_SETBIT: |
| 418 | regval |= data; |
| 419 | break; |
| 420 | |
| 421 | case ACCESS_WRITE_CLEARBIT: |
| 422 | regval &= ~data; |
| 423 | break; |
| 424 | |
| 425 | case ACCESS_WRITE_VALUE: |
| 426 | regval = (regval & ~(mask << word_offset)) | data; |
| 427 | break; |
| 428 | } |
| 429 | *reg = regval; |
| 430 | } else { |
| 431 | switch (ACCESS_READ_MASK(mode)) { |
| 432 | case ACCESS_READ_RAZ: |
| 433 | regval = 0; |
| 434 | /* fall through */ |
| 435 | |
| 436 | case ACCESS_READ_VALUE: |
| 437 | mmio_data_write(mmio, mask, regval >> word_offset); |
| 438 | } |
| 439 | } |
| 440 | } |
| 441 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 442 | bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, |
| 443 | phys_addr_t offset) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 444 | { |
| 445 | vgic_reg_access(mmio, NULL, offset, |
| 446 | ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED); |
| 447 | return false; |
| 448 | } |
| 449 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 450 | bool vgic_handle_enable_reg(struct kvm *kvm, struct kvm_exit_mmio *mmio, |
| 451 | phys_addr_t offset, int vcpu_id, int access) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 452 | { |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 453 | u32 *reg; |
| 454 | int mode = ACCESS_READ_VALUE | access; |
| 455 | struct kvm_vcpu *target_vcpu = kvm_get_vcpu(kvm, vcpu_id); |
| 456 | |
| 457 | reg = vgic_bitmap_get_reg(&kvm->arch.vgic.irq_enabled, vcpu_id, offset); |
| 458 | vgic_reg_access(mmio, reg, offset, mode); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 459 | if (mmio->is_write) { |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 460 | if (access & ACCESS_WRITE_CLEARBIT) { |
| 461 | if (offset < 4) /* Force SGI enabled */ |
| 462 | *reg |= 0xffff; |
| 463 | vgic_retire_disabled_irqs(target_vcpu); |
| 464 | } |
| 465 | vgic_update_state(kvm); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 466 | return true; |
| 467 | } |
| 468 | |
| 469 | return false; |
| 470 | } |
| 471 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 472 | bool vgic_handle_set_pending_reg(struct kvm *kvm, |
| 473 | struct kvm_exit_mmio *mmio, |
| 474 | phys_addr_t offset, int vcpu_id) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 475 | { |
Christoffer Dall | 9da48b5 | 2014-06-14 22:30:45 +0200 | [diff] [blame] | 476 | u32 *reg, orig; |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 477 | u32 level_mask; |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 478 | int mode = ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT; |
| 479 | struct vgic_dist *dist = &kvm->arch.vgic; |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 480 | |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 481 | reg = vgic_bitmap_get_reg(&dist->irq_cfg, vcpu_id, offset); |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 482 | level_mask = (~(*reg)); |
| 483 | |
| 484 | /* Mark both level and edge triggered irqs as pending */ |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 485 | reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu_id, offset); |
Christoffer Dall | 9da48b5 | 2014-06-14 22:30:45 +0200 | [diff] [blame] | 486 | orig = *reg; |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 487 | vgic_reg_access(mmio, reg, offset, mode); |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 488 | |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 489 | if (mmio->is_write) { |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 490 | /* Set the soft-pending flag only for level-triggered irqs */ |
| 491 | reg = vgic_bitmap_get_reg(&dist->irq_soft_pend, |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 492 | vcpu_id, offset); |
| 493 | vgic_reg_access(mmio, reg, offset, mode); |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 494 | *reg &= level_mask; |
| 495 | |
Christoffer Dall | 9da48b5 | 2014-06-14 22:30:45 +0200 | [diff] [blame] | 496 | /* Ignore writes to SGIs */ |
| 497 | if (offset < 2) { |
| 498 | *reg &= ~0xffff; |
| 499 | *reg |= orig & 0xffff; |
| 500 | } |
| 501 | |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 502 | vgic_update_state(kvm); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 503 | return true; |
| 504 | } |
| 505 | |
| 506 | return false; |
| 507 | } |
| 508 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 509 | bool vgic_handle_clear_pending_reg(struct kvm *kvm, |
| 510 | struct kvm_exit_mmio *mmio, |
| 511 | phys_addr_t offset, int vcpu_id) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 512 | { |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 513 | u32 *level_active; |
Christoffer Dall | 9da48b5 | 2014-06-14 22:30:45 +0200 | [diff] [blame] | 514 | u32 *reg, orig; |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 515 | int mode = ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT; |
| 516 | struct vgic_dist *dist = &kvm->arch.vgic; |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 517 | |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 518 | reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu_id, offset); |
Christoffer Dall | 9da48b5 | 2014-06-14 22:30:45 +0200 | [diff] [blame] | 519 | orig = *reg; |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 520 | vgic_reg_access(mmio, reg, offset, mode); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 521 | if (mmio->is_write) { |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 522 | /* Re-set level triggered level-active interrupts */ |
| 523 | level_active = vgic_bitmap_get_reg(&dist->irq_level, |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 524 | vcpu_id, offset); |
| 525 | reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu_id, offset); |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 526 | *reg |= *level_active; |
| 527 | |
Christoffer Dall | 9da48b5 | 2014-06-14 22:30:45 +0200 | [diff] [blame] | 528 | /* Ignore writes to SGIs */ |
| 529 | if (offset < 2) { |
| 530 | *reg &= ~0xffff; |
| 531 | *reg |= orig & 0xffff; |
| 532 | } |
| 533 | |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 534 | /* Clear soft-pending flags */ |
| 535 | reg = vgic_bitmap_get_reg(&dist->irq_soft_pend, |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 536 | vcpu_id, offset); |
| 537 | vgic_reg_access(mmio, reg, offset, mode); |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 538 | |
Andre Przywara | d97f683 | 2014-06-11 14:11:49 +0200 | [diff] [blame] | 539 | vgic_update_state(kvm); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 540 | return true; |
| 541 | } |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 542 | return false; |
| 543 | } |
| 544 | |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 545 | bool vgic_handle_set_active_reg(struct kvm *kvm, |
| 546 | struct kvm_exit_mmio *mmio, |
| 547 | phys_addr_t offset, int vcpu_id) |
| 548 | { |
| 549 | u32 *reg; |
| 550 | struct vgic_dist *dist = &kvm->arch.vgic; |
| 551 | |
| 552 | reg = vgic_bitmap_get_reg(&dist->irq_active, vcpu_id, offset); |
| 553 | vgic_reg_access(mmio, reg, offset, |
| 554 | ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT); |
| 555 | |
| 556 | if (mmio->is_write) { |
| 557 | vgic_update_state(kvm); |
| 558 | return true; |
| 559 | } |
| 560 | |
| 561 | return false; |
| 562 | } |
| 563 | |
| 564 | bool vgic_handle_clear_active_reg(struct kvm *kvm, |
| 565 | struct kvm_exit_mmio *mmio, |
| 566 | phys_addr_t offset, int vcpu_id) |
| 567 | { |
| 568 | u32 *reg; |
| 569 | struct vgic_dist *dist = &kvm->arch.vgic; |
| 570 | |
| 571 | reg = vgic_bitmap_get_reg(&dist->irq_active, vcpu_id, offset); |
| 572 | vgic_reg_access(mmio, reg, offset, |
| 573 | ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT); |
| 574 | |
| 575 | if (mmio->is_write) { |
| 576 | vgic_update_state(kvm); |
| 577 | return true; |
| 578 | } |
| 579 | |
| 580 | return false; |
| 581 | } |
| 582 | |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 583 | static u32 vgic_cfg_expand(u16 val) |
| 584 | { |
| 585 | u32 res = 0; |
| 586 | int i; |
| 587 | |
| 588 | /* |
| 589 | * Turn a 16bit value like abcd...mnop into a 32bit word |
| 590 | * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is. |
| 591 | */ |
| 592 | for (i = 0; i < 16; i++) |
| 593 | res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1); |
| 594 | |
| 595 | return res; |
| 596 | } |
| 597 | |
| 598 | static u16 vgic_cfg_compress(u32 val) |
| 599 | { |
| 600 | u16 res = 0; |
| 601 | int i; |
| 602 | |
| 603 | /* |
| 604 | * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like |
| 605 | * abcd...mnop which is what we really care about. |
| 606 | */ |
| 607 | for (i = 0; i < 16; i++) |
| 608 | res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i; |
| 609 | |
| 610 | return res; |
| 611 | } |
| 612 | |
| 613 | /* |
| 614 | * The distributor uses 2 bits per IRQ for the CFG register, but the |
| 615 | * LSB is always 0. As such, we only keep the upper bit, and use the |
| 616 | * two above functions to compress/expand the bits |
| 617 | */ |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 618 | bool vgic_handle_cfg_reg(u32 *reg, struct kvm_exit_mmio *mmio, |
| 619 | phys_addr_t offset) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 620 | { |
| 621 | u32 val; |
Marc Zyngier | 6545eae | 2013-08-29 11:08:23 +0100 | [diff] [blame] | 622 | |
Andre Przywara | f2ae85b | 2014-04-11 00:07:18 +0200 | [diff] [blame] | 623 | if (offset & 4) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 624 | val = *reg >> 16; |
| 625 | else |
| 626 | val = *reg & 0xffff; |
| 627 | |
| 628 | val = vgic_cfg_expand(val); |
| 629 | vgic_reg_access(mmio, &val, offset, |
| 630 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); |
| 631 | if (mmio->is_write) { |
Andre Przywara | f2ae85b | 2014-04-11 00:07:18 +0200 | [diff] [blame] | 632 | if (offset < 8) { |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 633 | *reg = ~0U; /* Force PPIs/SGIs to 1 */ |
| 634 | return false; |
| 635 | } |
| 636 | |
| 637 | val = vgic_cfg_compress(val); |
Andre Przywara | f2ae85b | 2014-04-11 00:07:18 +0200 | [diff] [blame] | 638 | if (offset & 4) { |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 639 | *reg &= 0xffff; |
| 640 | *reg |= val << 16; |
| 641 | } else { |
| 642 | *reg &= 0xffff << 16; |
| 643 | *reg |= val; |
| 644 | } |
| 645 | } |
| 646 | |
| 647 | return false; |
| 648 | } |
| 649 | |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 650 | /** |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 651 | * vgic_unqueue_irqs - move pending/active IRQs from LRs to the distributor |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 652 | * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs |
| 653 | * |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 654 | * Move any IRQs that have already been assigned to LRs back to the |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 655 | * emulated distributor state so that the complete emulated state can be read |
| 656 | * from the main emulation structures without investigating the LRs. |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 657 | */ |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 658 | void vgic_unqueue_irqs(struct kvm_vcpu *vcpu) |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 659 | { |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 660 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 661 | int i; |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 662 | |
| 663 | for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) { |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 664 | struct vgic_lr lr = vgic_get_lr(vcpu, i); |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 665 | |
| 666 | /* |
| 667 | * There are three options for the state bits: |
| 668 | * |
| 669 | * 01: pending |
| 670 | * 10: active |
| 671 | * 11: pending and active |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 672 | */ |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 673 | BUG_ON(!(lr.state & LR_STATE_MASK)); |
| 674 | |
| 675 | /* Reestablish SGI source for pending and active IRQs */ |
| 676 | if (lr.irq < VGIC_NR_SGIS) |
| 677 | add_sgi_source(vcpu, lr.irq, lr.source); |
| 678 | |
| 679 | /* |
| 680 | * If the LR holds an active (10) or a pending and active (11) |
| 681 | * interrupt then move the active state to the |
| 682 | * distributor tracking bit. |
| 683 | */ |
| 684 | if (lr.state & LR_STATE_ACTIVE) { |
| 685 | vgic_irq_set_active(vcpu, lr.irq); |
| 686 | lr.state &= ~LR_STATE_ACTIVE; |
| 687 | } |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 688 | |
| 689 | /* |
| 690 | * Reestablish the pending state on the distributor and the |
| 691 | * CPU interface. It may have already been pending, but that |
| 692 | * is fine, then we are only setting a few bits that were |
| 693 | * already set. |
| 694 | */ |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 695 | if (lr.state & LR_STATE_PENDING) { |
| 696 | vgic_dist_irq_set_pending(vcpu, lr.irq); |
| 697 | lr.state &= ~LR_STATE_PENDING; |
| 698 | } |
| 699 | |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 700 | vgic_set_lr(vcpu, i, lr); |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 701 | |
| 702 | /* |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 703 | * Mark the LR as free for other use. |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 704 | */ |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 705 | BUG_ON(lr.state & LR_STATE_MASK); |
| 706 | vgic_retire_lr(i, lr.irq, vcpu); |
| 707 | vgic_irq_clear_queued(vcpu, lr.irq); |
Christoffer Dall | cbd333a | 2013-11-15 20:51:31 -0800 | [diff] [blame] | 708 | |
| 709 | /* Finally update the VGIC state. */ |
| 710 | vgic_update_state(vcpu->kvm); |
| 711 | } |
| 712 | } |
| 713 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 714 | const |
| 715 | struct kvm_mmio_range *vgic_find_range(const struct kvm_mmio_range *ranges, |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 716 | struct kvm_exit_mmio *mmio, |
Christoffer Dall | 1006e8c | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 717 | phys_addr_t offset) |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 718 | { |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 719 | const struct kvm_mmio_range *r = ranges; |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 720 | |
| 721 | while (r->len) { |
Christoffer Dall | 1006e8c | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 722 | if (offset >= r->base && |
| 723 | (offset + mmio->len) <= (r->base + r->len)) |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 724 | return r; |
| 725 | r++; |
| 726 | } |
| 727 | |
| 728 | return NULL; |
| 729 | } |
| 730 | |
Marc Zyngier | c3c9183 | 2014-07-08 12:09:04 +0100 | [diff] [blame] | 731 | static bool vgic_validate_access(const struct vgic_dist *dist, |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 732 | const struct kvm_mmio_range *range, |
Marc Zyngier | c3c9183 | 2014-07-08 12:09:04 +0100 | [diff] [blame] | 733 | unsigned long offset) |
| 734 | { |
| 735 | int irq; |
| 736 | |
| 737 | if (!range->bits_per_irq) |
| 738 | return true; /* Not an irq-based access */ |
| 739 | |
| 740 | irq = offset * 8 / range->bits_per_irq; |
| 741 | if (irq >= dist->nr_irqs) |
| 742 | return false; |
| 743 | |
| 744 | return true; |
| 745 | } |
| 746 | |
Andre Przywara | 05bc8aa | 2014-06-05 16:07:50 +0200 | [diff] [blame] | 747 | /* |
| 748 | * Call the respective handler function for the given range. |
| 749 | * We split up any 64 bit accesses into two consecutive 32 bit |
| 750 | * handler calls and merge the result afterwards. |
| 751 | * We do this in a little endian fashion regardless of the host's |
| 752 | * or guest's endianness, because the GIC is always LE and the rest of |
| 753 | * the code (vgic_reg_access) also puts it in a LE fashion already. |
| 754 | * At this point we have already identified the handle function, so |
| 755 | * range points to that one entry and offset is relative to this. |
| 756 | */ |
| 757 | static bool call_range_handler(struct kvm_vcpu *vcpu, |
| 758 | struct kvm_exit_mmio *mmio, |
| 759 | unsigned long offset, |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 760 | const struct kvm_mmio_range *range) |
Andre Przywara | 05bc8aa | 2014-06-05 16:07:50 +0200 | [diff] [blame] | 761 | { |
| 762 | u32 *data32 = (void *)mmio->data; |
| 763 | struct kvm_exit_mmio mmio32; |
| 764 | bool ret; |
| 765 | |
| 766 | if (likely(mmio->len <= 4)) |
| 767 | return range->handle_mmio(vcpu, mmio, offset); |
| 768 | |
| 769 | /* |
| 770 | * Any access bigger than 4 bytes (that we currently handle in KVM) |
| 771 | * is actually 8 bytes long, caused by a 64-bit access |
| 772 | */ |
| 773 | |
| 774 | mmio32.len = 4; |
| 775 | mmio32.is_write = mmio->is_write; |
Andre Przywara | 9fedf14 | 2014-11-13 16:21:35 +0000 | [diff] [blame] | 776 | mmio32.private = mmio->private; |
Andre Przywara | 05bc8aa | 2014-06-05 16:07:50 +0200 | [diff] [blame] | 777 | |
| 778 | mmio32.phys_addr = mmio->phys_addr + 4; |
| 779 | if (mmio->is_write) |
| 780 | *(u32 *)mmio32.data = data32[1]; |
| 781 | ret = range->handle_mmio(vcpu, &mmio32, offset + 4); |
| 782 | if (!mmio->is_write) |
| 783 | data32[1] = *(u32 *)mmio32.data; |
| 784 | |
| 785 | mmio32.phys_addr = mmio->phys_addr; |
| 786 | if (mmio->is_write) |
| 787 | *(u32 *)mmio32.data = data32[0]; |
| 788 | ret |= range->handle_mmio(vcpu, &mmio32, offset); |
| 789 | if (!mmio->is_write) |
| 790 | data32[0] = *(u32 *)mmio32.data; |
| 791 | |
| 792 | return ret; |
| 793 | } |
| 794 | |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 795 | /** |
Andre Przywara | 9641525 | 2014-06-02 22:44:37 +0200 | [diff] [blame] | 796 | * vgic_handle_mmio_range - handle an in-kernel MMIO access |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 797 | * @vcpu: pointer to the vcpu performing the access |
| 798 | * @run: pointer to the kvm_run structure |
| 799 | * @mmio: pointer to the data describing the access |
Andre Przywara | 9641525 | 2014-06-02 22:44:37 +0200 | [diff] [blame] | 800 | * @ranges: array of MMIO ranges in a given region |
| 801 | * @mmio_base: base address of that region |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 802 | * |
Andre Przywara | 9641525 | 2014-06-02 22:44:37 +0200 | [diff] [blame] | 803 | * returns true if the MMIO access could be performed |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 804 | */ |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 805 | bool vgic_handle_mmio_range(struct kvm_vcpu *vcpu, struct kvm_run *run, |
Andre Przywara | 9641525 | 2014-06-02 22:44:37 +0200 | [diff] [blame] | 806 | struct kvm_exit_mmio *mmio, |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 807 | const struct kvm_mmio_range *ranges, |
Andre Przywara | 9641525 | 2014-06-02 22:44:37 +0200 | [diff] [blame] | 808 | unsigned long mmio_base) |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 809 | { |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 810 | const struct kvm_mmio_range *range; |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 811 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 812 | bool updated_state; |
| 813 | unsigned long offset; |
| 814 | |
Andre Przywara | 9641525 | 2014-06-02 22:44:37 +0200 | [diff] [blame] | 815 | offset = mmio->phys_addr - mmio_base; |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 816 | range = vgic_find_range(ranges, mmio, offset); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 817 | if (unlikely(!range || !range->handle_mmio)) { |
| 818 | pr_warn("Unhandled access %d %08llx %d\n", |
| 819 | mmio->is_write, mmio->phys_addr, mmio->len); |
| 820 | return false; |
| 821 | } |
| 822 | |
| 823 | spin_lock(&vcpu->kvm->arch.vgic.lock); |
Andre Przywara | 9641525 | 2014-06-02 22:44:37 +0200 | [diff] [blame] | 824 | offset -= range->base; |
Marc Zyngier | c3c9183 | 2014-07-08 12:09:04 +0100 | [diff] [blame] | 825 | if (vgic_validate_access(dist, range, offset)) { |
Andre Przywara | 05bc8aa | 2014-06-05 16:07:50 +0200 | [diff] [blame] | 826 | updated_state = call_range_handler(vcpu, mmio, offset, range); |
Marc Zyngier | c3c9183 | 2014-07-08 12:09:04 +0100 | [diff] [blame] | 827 | } else { |
Andre Przywara | 05bc8aa | 2014-06-05 16:07:50 +0200 | [diff] [blame] | 828 | if (!mmio->is_write) |
| 829 | memset(mmio->data, 0, mmio->len); |
Marc Zyngier | c3c9183 | 2014-07-08 12:09:04 +0100 | [diff] [blame] | 830 | updated_state = false; |
| 831 | } |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 832 | spin_unlock(&vcpu->kvm->arch.vgic.lock); |
| 833 | kvm_prepare_mmio(run, mmio); |
| 834 | kvm_handle_mmio_return(vcpu, run); |
| 835 | |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 836 | if (updated_state) |
| 837 | vgic_kick_vcpus(vcpu->kvm); |
| 838 | |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 839 | return true; |
| 840 | } |
| 841 | |
Andre Przywara | 9641525 | 2014-06-02 22:44:37 +0200 | [diff] [blame] | 842 | /** |
| 843 | * vgic_handle_mmio - handle an in-kernel MMIO access for the GIC emulation |
| 844 | * @vcpu: pointer to the vcpu performing the access |
| 845 | * @run: pointer to the kvm_run structure |
| 846 | * @mmio: pointer to the data describing the access |
| 847 | * |
| 848 | * returns true if the MMIO access has been performed in kernel space, |
| 849 | * and false if it needs to be emulated in user space. |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 850 | * Calls the actual handling routine for the selected VGIC model. |
Andre Przywara | 9641525 | 2014-06-02 22:44:37 +0200 | [diff] [blame] | 851 | */ |
| 852 | bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run, |
| 853 | struct kvm_exit_mmio *mmio) |
| 854 | { |
| 855 | if (!irqchip_in_kernel(vcpu->kvm)) |
| 856 | return false; |
| 857 | |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 858 | /* |
| 859 | * This will currently call either vgic_v2_handle_mmio() or |
| 860 | * vgic_v3_handle_mmio(), which in turn will call |
| 861 | * vgic_handle_mmio_range() defined above. |
| 862 | */ |
| 863 | return vcpu->kvm->arch.vgic.vm_ops.handle_mmio(vcpu, run, mmio); |
Andre Przywara | 9641525 | 2014-06-02 22:44:37 +0200 | [diff] [blame] | 864 | } |
| 865 | |
Marc Zyngier | fb65ab6 | 2014-07-08 12:09:02 +0100 | [diff] [blame] | 866 | static int vgic_nr_shared_irqs(struct vgic_dist *dist) |
| 867 | { |
| 868 | return dist->nr_irqs - VGIC_NR_PRIVATE_IRQS; |
| 869 | } |
| 870 | |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 871 | static int compute_active_for_cpu(struct kvm_vcpu *vcpu) |
| 872 | { |
| 873 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 874 | unsigned long *active, *enabled, *act_percpu, *act_shared; |
| 875 | unsigned long active_private, active_shared; |
| 876 | int nr_shared = vgic_nr_shared_irqs(dist); |
| 877 | int vcpu_id; |
| 878 | |
| 879 | vcpu_id = vcpu->vcpu_id; |
| 880 | act_percpu = vcpu->arch.vgic_cpu.active_percpu; |
| 881 | act_shared = vcpu->arch.vgic_cpu.active_shared; |
| 882 | |
| 883 | active = vgic_bitmap_get_cpu_map(&dist->irq_active, vcpu_id); |
| 884 | enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id); |
| 885 | bitmap_and(act_percpu, active, enabled, VGIC_NR_PRIVATE_IRQS); |
| 886 | |
| 887 | active = vgic_bitmap_get_shared_map(&dist->irq_active); |
| 888 | enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled); |
| 889 | bitmap_and(act_shared, active, enabled, nr_shared); |
| 890 | bitmap_and(act_shared, act_shared, |
| 891 | vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]), |
| 892 | nr_shared); |
| 893 | |
| 894 | active_private = find_first_bit(act_percpu, VGIC_NR_PRIVATE_IRQS); |
| 895 | active_shared = find_first_bit(act_shared, nr_shared); |
| 896 | |
| 897 | return (active_private < VGIC_NR_PRIVATE_IRQS || |
| 898 | active_shared < nr_shared); |
| 899 | } |
| 900 | |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 901 | static int compute_pending_for_cpu(struct kvm_vcpu *vcpu) |
| 902 | { |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 903 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 904 | unsigned long *pending, *enabled, *pend_percpu, *pend_shared; |
| 905 | unsigned long pending_private, pending_shared; |
Marc Zyngier | fb65ab6 | 2014-07-08 12:09:02 +0100 | [diff] [blame] | 906 | int nr_shared = vgic_nr_shared_irqs(dist); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 907 | int vcpu_id; |
| 908 | |
| 909 | vcpu_id = vcpu->vcpu_id; |
| 910 | pend_percpu = vcpu->arch.vgic_cpu.pending_percpu; |
| 911 | pend_shared = vcpu->arch.vgic_cpu.pending_shared; |
| 912 | |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 913 | pending = vgic_bitmap_get_cpu_map(&dist->irq_pending, vcpu_id); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 914 | enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id); |
| 915 | bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS); |
| 916 | |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 917 | pending = vgic_bitmap_get_shared_map(&dist->irq_pending); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 918 | enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled); |
Marc Zyngier | fb65ab6 | 2014-07-08 12:09:02 +0100 | [diff] [blame] | 919 | bitmap_and(pend_shared, pending, enabled, nr_shared); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 920 | bitmap_and(pend_shared, pend_shared, |
| 921 | vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]), |
Marc Zyngier | fb65ab6 | 2014-07-08 12:09:02 +0100 | [diff] [blame] | 922 | nr_shared); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 923 | |
| 924 | pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS); |
Marc Zyngier | fb65ab6 | 2014-07-08 12:09:02 +0100 | [diff] [blame] | 925 | pending_shared = find_first_bit(pend_shared, nr_shared); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 926 | return (pending_private < VGIC_NR_PRIVATE_IRQS || |
Marc Zyngier | fb65ab6 | 2014-07-08 12:09:02 +0100 | [diff] [blame] | 927 | pending_shared < vgic_nr_shared_irqs(dist)); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 928 | } |
| 929 | |
| 930 | /* |
| 931 | * Update the interrupt state and determine which CPUs have pending |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 932 | * or active interrupts. Must be called with distributor lock held. |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 933 | */ |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 934 | void vgic_update_state(struct kvm *kvm) |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 935 | { |
| 936 | struct vgic_dist *dist = &kvm->arch.vgic; |
| 937 | struct kvm_vcpu *vcpu; |
| 938 | int c; |
| 939 | |
| 940 | if (!dist->enabled) { |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 941 | set_bit(0, dist->irq_pending_on_cpu); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 942 | return; |
| 943 | } |
| 944 | |
| 945 | kvm_for_each_vcpu(c, vcpu, kvm) { |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 946 | if (compute_pending_for_cpu(vcpu)) |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 947 | set_bit(c, dist->irq_pending_on_cpu); |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 948 | |
| 949 | if (compute_active_for_cpu(vcpu)) |
| 950 | set_bit(c, dist->irq_active_on_cpu); |
| 951 | else |
| 952 | clear_bit(c, dist->irq_active_on_cpu); |
Marc Zyngier | b47ef92 | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 953 | } |
Marc Zyngier | 1a89dd9 | 2013-01-21 19:36:12 -0500 | [diff] [blame] | 954 | } |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 955 | |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 956 | static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr) |
| 957 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 958 | return vgic_ops->get_lr(vcpu, lr); |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 959 | } |
| 960 | |
| 961 | static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, |
| 962 | struct vgic_lr vlr) |
| 963 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 964 | vgic_ops->set_lr(vcpu, lr, vlr); |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 965 | } |
| 966 | |
Marc Zyngier | 69bb2c9 | 2013-06-04 10:29:39 +0100 | [diff] [blame] | 967 | static void vgic_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr, |
| 968 | struct vgic_lr vlr) |
| 969 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 970 | vgic_ops->sync_lr_elrsr(vcpu, lr, vlr); |
Marc Zyngier | 69bb2c9 | 2013-06-04 10:29:39 +0100 | [diff] [blame] | 971 | } |
| 972 | |
| 973 | static inline u64 vgic_get_elrsr(struct kvm_vcpu *vcpu) |
| 974 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 975 | return vgic_ops->get_elrsr(vcpu); |
Marc Zyngier | 69bb2c9 | 2013-06-04 10:29:39 +0100 | [diff] [blame] | 976 | } |
| 977 | |
Marc Zyngier | 8d6a031 | 2013-06-04 10:33:43 +0100 | [diff] [blame] | 978 | static inline u64 vgic_get_eisr(struct kvm_vcpu *vcpu) |
| 979 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 980 | return vgic_ops->get_eisr(vcpu); |
Marc Zyngier | 8d6a031 | 2013-06-04 10:33:43 +0100 | [diff] [blame] | 981 | } |
| 982 | |
Marc Zyngier | 495dd85 | 2013-06-04 11:02:10 +0100 | [diff] [blame] | 983 | static inline u32 vgic_get_interrupt_status(struct kvm_vcpu *vcpu) |
| 984 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 985 | return vgic_ops->get_interrupt_status(vcpu); |
Marc Zyngier | 495dd85 | 2013-06-04 11:02:10 +0100 | [diff] [blame] | 986 | } |
| 987 | |
Marc Zyngier | 909d9b5 | 2013-06-04 11:24:17 +0100 | [diff] [blame] | 988 | static inline void vgic_enable_underflow(struct kvm_vcpu *vcpu) |
| 989 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 990 | vgic_ops->enable_underflow(vcpu); |
Marc Zyngier | 909d9b5 | 2013-06-04 11:24:17 +0100 | [diff] [blame] | 991 | } |
| 992 | |
| 993 | static inline void vgic_disable_underflow(struct kvm_vcpu *vcpu) |
| 994 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 995 | vgic_ops->disable_underflow(vcpu); |
Marc Zyngier | 909d9b5 | 2013-06-04 11:24:17 +0100 | [diff] [blame] | 996 | } |
| 997 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 998 | void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) |
Marc Zyngier | beee38b | 2014-02-04 17:48:10 +0000 | [diff] [blame] | 999 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1000 | vgic_ops->get_vmcr(vcpu, vmcr); |
Marc Zyngier | beee38b | 2014-02-04 17:48:10 +0000 | [diff] [blame] | 1001 | } |
| 1002 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 1003 | void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) |
Marc Zyngier | beee38b | 2014-02-04 17:48:10 +0000 | [diff] [blame] | 1004 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1005 | vgic_ops->set_vmcr(vcpu, vmcr); |
Marc Zyngier | beee38b | 2014-02-04 17:48:10 +0000 | [diff] [blame] | 1006 | } |
| 1007 | |
Marc Zyngier | da8dafd1 | 2013-06-04 11:36:38 +0100 | [diff] [blame] | 1008 | static inline void vgic_enable(struct kvm_vcpu *vcpu) |
| 1009 | { |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1010 | vgic_ops->enable(vcpu); |
Marc Zyngier | da8dafd1 | 2013-06-04 11:36:38 +0100 | [diff] [blame] | 1011 | } |
| 1012 | |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1013 | static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu) |
| 1014 | { |
| 1015 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
| 1016 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr_nr); |
| 1017 | |
| 1018 | vlr.state = 0; |
| 1019 | vgic_set_lr(vcpu, lr_nr, vlr); |
| 1020 | clear_bit(lr_nr, vgic_cpu->lr_used); |
| 1021 | vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY; |
| 1022 | } |
Marc Zyngier | a1fcb44 | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1023 | |
| 1024 | /* |
| 1025 | * An interrupt may have been disabled after being made pending on the |
| 1026 | * CPU interface (the classic case is a timer running while we're |
| 1027 | * rebooting the guest - the interrupt would kick as soon as the CPU |
| 1028 | * interface gets enabled, with deadly consequences). |
| 1029 | * |
| 1030 | * The solution is to examine already active LRs, and check the |
| 1031 | * interrupt is still enabled. If not, just retire it. |
| 1032 | */ |
| 1033 | static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu) |
| 1034 | { |
| 1035 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
| 1036 | int lr; |
| 1037 | |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1038 | for_each_set_bit(lr, vgic_cpu->lr_used, vgic->nr_lr) { |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1039 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr); |
Marc Zyngier | a1fcb44 | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1040 | |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1041 | if (!vgic_irq_is_enabled(vcpu, vlr.irq)) { |
| 1042 | vgic_retire_lr(lr, vlr.irq, vcpu); |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 1043 | if (vgic_irq_is_queued(vcpu, vlr.irq)) |
| 1044 | vgic_irq_clear_queued(vcpu, vlr.irq); |
Marc Zyngier | a1fcb44 | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1045 | } |
| 1046 | } |
| 1047 | } |
| 1048 | |
Alex Bennée | 7176095 | 2015-03-13 17:02:53 +0000 | [diff] [blame] | 1049 | static void vgic_queue_irq_to_lr(struct kvm_vcpu *vcpu, int irq, |
| 1050 | int lr_nr, struct vgic_lr vlr) |
| 1051 | { |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 1052 | if (vgic_irq_is_active(vcpu, irq)) { |
| 1053 | vlr.state |= LR_STATE_ACTIVE; |
| 1054 | kvm_debug("Set active, clear distributor: 0x%x\n", vlr.state); |
| 1055 | vgic_irq_clear_active(vcpu, irq); |
| 1056 | vgic_update_state(vcpu->kvm); |
| 1057 | } else if (vgic_dist_irq_is_pending(vcpu, irq)) { |
Alex Bennée | 7176095 | 2015-03-13 17:02:53 +0000 | [diff] [blame] | 1058 | vlr.state |= LR_STATE_PENDING; |
| 1059 | kvm_debug("Set pending: 0x%x\n", vlr.state); |
| 1060 | } |
| 1061 | |
| 1062 | if (!vgic_irq_is_edge(vcpu, irq)) |
| 1063 | vlr.state |= LR_EOI_INT; |
| 1064 | |
| 1065 | vgic_set_lr(vcpu, lr_nr, vlr); |
| 1066 | } |
| 1067 | |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1068 | /* |
| 1069 | * Queue an interrupt to a CPU virtual interface. Return true on success, |
| 1070 | * or false if it wasn't possible to queue it. |
Andre Przywara | 1d91622 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 1071 | * sgi_source must be zero for any non-SGI interrupts. |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1072 | */ |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 1073 | bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1074 | { |
| 1075 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
Marc Zyngier | 5fb66da | 2014-07-08 12:09:05 +0100 | [diff] [blame] | 1076 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1077 | struct vgic_lr vlr; |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1078 | int lr; |
| 1079 | |
| 1080 | /* Sanitize the input... */ |
| 1081 | BUG_ON(sgi_source_id & ~7); |
| 1082 | BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS); |
Marc Zyngier | 5fb66da | 2014-07-08 12:09:05 +0100 | [diff] [blame] | 1083 | BUG_ON(irq >= dist->nr_irqs); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1084 | |
| 1085 | kvm_debug("Queue IRQ%d\n", irq); |
| 1086 | |
| 1087 | lr = vgic_cpu->vgic_irq_lr_map[irq]; |
| 1088 | |
| 1089 | /* Do we have an active interrupt for the same CPUID? */ |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1090 | if (lr != LR_EMPTY) { |
| 1091 | vlr = vgic_get_lr(vcpu, lr); |
| 1092 | if (vlr.source == sgi_source_id) { |
| 1093 | kvm_debug("LR%d piggyback for IRQ%d\n", lr, vlr.irq); |
| 1094 | BUG_ON(!test_bit(lr, vgic_cpu->lr_used)); |
Alex Bennée | 7176095 | 2015-03-13 17:02:53 +0000 | [diff] [blame] | 1095 | vgic_queue_irq_to_lr(vcpu, irq, lr, vlr); |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1096 | return true; |
| 1097 | } |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1098 | } |
| 1099 | |
| 1100 | /* Try to use another LR for this interrupt */ |
| 1101 | lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used, |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1102 | vgic->nr_lr); |
| 1103 | if (lr >= vgic->nr_lr) |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1104 | return false; |
| 1105 | |
| 1106 | kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1107 | vgic_cpu->vgic_irq_lr_map[irq] = lr; |
| 1108 | set_bit(lr, vgic_cpu->lr_used); |
| 1109 | |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1110 | vlr.irq = irq; |
| 1111 | vlr.source = sgi_source_id; |
Alex Bennée | 7176095 | 2015-03-13 17:02:53 +0000 | [diff] [blame] | 1112 | vlr.state = 0; |
| 1113 | vgic_queue_irq_to_lr(vcpu, irq, lr, vlr); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1114 | |
| 1115 | return true; |
| 1116 | } |
| 1117 | |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1118 | static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq) |
| 1119 | { |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 1120 | if (!vgic_can_sample_irq(vcpu, irq)) |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1121 | return true; /* level interrupt, already queued */ |
| 1122 | |
| 1123 | if (vgic_queue_irq(vcpu, 0, irq)) { |
| 1124 | if (vgic_irq_is_edge(vcpu, irq)) { |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 1125 | vgic_dist_irq_clear_pending(vcpu, irq); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1126 | vgic_cpu_irq_clear(vcpu, irq); |
| 1127 | } else { |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 1128 | vgic_irq_set_queued(vcpu, irq); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1129 | } |
| 1130 | |
| 1131 | return true; |
| 1132 | } |
| 1133 | |
| 1134 | return false; |
| 1135 | } |
| 1136 | |
| 1137 | /* |
| 1138 | * Fill the list registers with pending interrupts before running the |
| 1139 | * guest. |
| 1140 | */ |
| 1141 | static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) |
| 1142 | { |
| 1143 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
| 1144 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 1145 | unsigned long *pa_percpu, *pa_shared; |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1146 | int i, vcpu_id; |
| 1147 | int overflow = 0; |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 1148 | int nr_shared = vgic_nr_shared_irqs(dist); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1149 | |
| 1150 | vcpu_id = vcpu->vcpu_id; |
| 1151 | |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 1152 | pa_percpu = vcpu->arch.vgic_cpu.pend_act_percpu; |
| 1153 | pa_shared = vcpu->arch.vgic_cpu.pend_act_shared; |
| 1154 | |
| 1155 | bitmap_or(pa_percpu, vgic_cpu->pending_percpu, vgic_cpu->active_percpu, |
| 1156 | VGIC_NR_PRIVATE_IRQS); |
| 1157 | bitmap_or(pa_shared, vgic_cpu->pending_shared, vgic_cpu->active_shared, |
| 1158 | nr_shared); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1159 | /* |
| 1160 | * We may not have any pending interrupt, or the interrupts |
| 1161 | * may have been serviced from another vcpu. In all cases, |
| 1162 | * move along. |
| 1163 | */ |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 1164 | if (!kvm_vgic_vcpu_pending_irq(vcpu) && !kvm_vgic_vcpu_active_irq(vcpu)) |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1165 | goto epilog; |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1166 | |
| 1167 | /* SGIs */ |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 1168 | for_each_set_bit(i, pa_percpu, VGIC_NR_SGIS) { |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 1169 | if (!queue_sgi(vcpu, i)) |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1170 | overflow = 1; |
| 1171 | } |
| 1172 | |
| 1173 | /* PPIs */ |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 1174 | for_each_set_bit_from(i, pa_percpu, VGIC_NR_PRIVATE_IRQS) { |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1175 | if (!vgic_queue_hwirq(vcpu, i)) |
| 1176 | overflow = 1; |
| 1177 | } |
| 1178 | |
| 1179 | /* SPIs */ |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 1180 | for_each_set_bit(i, pa_shared, nr_shared) { |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1181 | if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS)) |
| 1182 | overflow = 1; |
| 1183 | } |
| 1184 | |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 1185 | |
| 1186 | |
| 1187 | |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1188 | epilog: |
| 1189 | if (overflow) { |
Marc Zyngier | 909d9b5 | 2013-06-04 11:24:17 +0100 | [diff] [blame] | 1190 | vgic_enable_underflow(vcpu); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1191 | } else { |
Marc Zyngier | 909d9b5 | 2013-06-04 11:24:17 +0100 | [diff] [blame] | 1192 | vgic_disable_underflow(vcpu); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1193 | /* |
| 1194 | * We're about to run this VCPU, and we've consumed |
| 1195 | * everything the distributor had in store for |
| 1196 | * us. Claim we don't have anything pending. We'll |
| 1197 | * adjust that if needed while exiting. |
| 1198 | */ |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1199 | clear_bit(vcpu_id, dist->irq_pending_on_cpu); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1200 | } |
| 1201 | } |
| 1202 | |
| 1203 | static bool vgic_process_maintenance(struct kvm_vcpu *vcpu) |
| 1204 | { |
Marc Zyngier | 495dd85 | 2013-06-04 11:02:10 +0100 | [diff] [blame] | 1205 | u32 status = vgic_get_interrupt_status(vcpu); |
Eric Auger | 649cf73 | 2015-03-04 11:14:35 +0100 | [diff] [blame] | 1206 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1207 | bool level_pending = false; |
Eric Auger | 174178f | 2015-03-04 11:14:36 +0100 | [diff] [blame] | 1208 | struct kvm *kvm = vcpu->kvm; |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1209 | |
Marc Zyngier | 495dd85 | 2013-06-04 11:02:10 +0100 | [diff] [blame] | 1210 | kvm_debug("STATUS = %08x\n", status); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1211 | |
Marc Zyngier | 495dd85 | 2013-06-04 11:02:10 +0100 | [diff] [blame] | 1212 | if (status & INT_STATUS_EOI) { |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1213 | /* |
| 1214 | * Some level interrupts have been EOIed. Clear their |
| 1215 | * active bit. |
| 1216 | */ |
Marc Zyngier | 8d6a031 | 2013-06-04 10:33:43 +0100 | [diff] [blame] | 1217 | u64 eisr = vgic_get_eisr(vcpu); |
Christoffer Dall | 2df36a5 | 2014-09-28 16:04:26 +0200 | [diff] [blame] | 1218 | unsigned long *eisr_ptr = u64_to_bitmask(&eisr); |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1219 | int lr; |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1220 | |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1221 | for_each_set_bit(lr, eisr_ptr, vgic->nr_lr) { |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1222 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr); |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1223 | WARN_ON(vgic_irq_is_edge(vcpu, vlr.irq)); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1224 | |
Eric Auger | 649cf73 | 2015-03-04 11:14:35 +0100 | [diff] [blame] | 1225 | spin_lock(&dist->lock); |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 1226 | vgic_irq_clear_queued(vcpu, vlr.irq); |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1227 | WARN_ON(vlr.state & LR_STATE_MASK); |
| 1228 | vlr.state = 0; |
| 1229 | vgic_set_lr(vcpu, lr, vlr); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1230 | |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1231 | /* |
| 1232 | * If the IRQ was EOIed it was also ACKed and we we |
| 1233 | * therefore assume we can clear the soft pending |
| 1234 | * state (should it had been set) for this interrupt. |
| 1235 | * |
| 1236 | * Note: if the IRQ soft pending state was set after |
| 1237 | * the IRQ was acked, it actually shouldn't be |
| 1238 | * cleared, but we have no way of knowing that unless |
| 1239 | * we start trapping ACKs when the soft-pending state |
| 1240 | * is set. |
| 1241 | */ |
| 1242 | vgic_dist_irq_clear_soft_pend(vcpu, vlr.irq); |
| 1243 | |
Eric Auger | 174178f | 2015-03-04 11:14:36 +0100 | [diff] [blame] | 1244 | /* |
| 1245 | * kvm_notify_acked_irq calls kvm_set_irq() |
| 1246 | * to reset the IRQ level. Need to release the |
| 1247 | * lock for kvm_set_irq to grab it. |
| 1248 | */ |
| 1249 | spin_unlock(&dist->lock); |
| 1250 | |
| 1251 | kvm_notify_acked_irq(kvm, 0, |
| 1252 | vlr.irq - VGIC_NR_PRIVATE_IRQS); |
| 1253 | spin_lock(&dist->lock); |
| 1254 | |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1255 | /* Any additional pending interrupt? */ |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1256 | if (vgic_dist_irq_get_level(vcpu, vlr.irq)) { |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1257 | vgic_cpu_irq_set(vcpu, vlr.irq); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1258 | level_pending = true; |
| 1259 | } else { |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1260 | vgic_dist_irq_clear_pending(vcpu, vlr.irq); |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1261 | vgic_cpu_irq_clear(vcpu, vlr.irq); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1262 | } |
Marc Zyngier | 75da01e | 2013-01-31 11:25:52 +0000 | [diff] [blame] | 1263 | |
Eric Auger | 649cf73 | 2015-03-04 11:14:35 +0100 | [diff] [blame] | 1264 | spin_unlock(&dist->lock); |
| 1265 | |
Marc Zyngier | 75da01e | 2013-01-31 11:25:52 +0000 | [diff] [blame] | 1266 | /* |
| 1267 | * Despite being EOIed, the LR may not have |
| 1268 | * been marked as empty. |
| 1269 | */ |
Marc Zyngier | 69bb2c9 | 2013-06-04 10:29:39 +0100 | [diff] [blame] | 1270 | vgic_sync_lr_elrsr(vcpu, lr, vlr); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1271 | } |
| 1272 | } |
| 1273 | |
Marc Zyngier | 495dd85 | 2013-06-04 11:02:10 +0100 | [diff] [blame] | 1274 | if (status & INT_STATUS_UNDERFLOW) |
Marc Zyngier | 909d9b5 | 2013-06-04 11:24:17 +0100 | [diff] [blame] | 1275 | vgic_disable_underflow(vcpu); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1276 | |
| 1277 | return level_pending; |
| 1278 | } |
| 1279 | |
Eric Auger | 649cf73 | 2015-03-04 11:14:35 +0100 | [diff] [blame] | 1280 | /* Sync back the VGIC state after a guest run */ |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1281 | static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) |
| 1282 | { |
| 1283 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
| 1284 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
Marc Zyngier | 69bb2c9 | 2013-06-04 10:29:39 +0100 | [diff] [blame] | 1285 | u64 elrsr; |
| 1286 | unsigned long *elrsr_ptr; |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1287 | int lr, pending; |
| 1288 | bool level_pending; |
| 1289 | |
| 1290 | level_pending = vgic_process_maintenance(vcpu); |
Marc Zyngier | 69bb2c9 | 2013-06-04 10:29:39 +0100 | [diff] [blame] | 1291 | elrsr = vgic_get_elrsr(vcpu); |
Christoffer Dall | 2df36a5 | 2014-09-28 16:04:26 +0200 | [diff] [blame] | 1292 | elrsr_ptr = u64_to_bitmask(&elrsr); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1293 | |
| 1294 | /* Clear mappings for empty LRs */ |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1295 | for_each_set_bit(lr, elrsr_ptr, vgic->nr_lr) { |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1296 | struct vgic_lr vlr; |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1297 | |
| 1298 | if (!test_and_clear_bit(lr, vgic_cpu->lr_used)) |
| 1299 | continue; |
| 1300 | |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1301 | vlr = vgic_get_lr(vcpu, lr); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1302 | |
Marc Zyngier | 5fb66da | 2014-07-08 12:09:05 +0100 | [diff] [blame] | 1303 | BUG_ON(vlr.irq >= dist->nr_irqs); |
Marc Zyngier | 8d5c6b0 | 2013-06-03 15:55:02 +0100 | [diff] [blame] | 1304 | vgic_cpu->vgic_irq_lr_map[vlr.irq] = LR_EMPTY; |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1305 | } |
| 1306 | |
| 1307 | /* Check if we still have something up our sleeve... */ |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1308 | pending = find_first_zero_bit(elrsr_ptr, vgic->nr_lr); |
| 1309 | if (level_pending || pending < vgic->nr_lr) |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1310 | set_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1311 | } |
| 1312 | |
| 1313 | void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) |
| 1314 | { |
| 1315 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 1316 | |
| 1317 | if (!irqchip_in_kernel(vcpu->kvm)) |
| 1318 | return; |
| 1319 | |
| 1320 | spin_lock(&dist->lock); |
| 1321 | __kvm_vgic_flush_hwstate(vcpu); |
| 1322 | spin_unlock(&dist->lock); |
| 1323 | } |
| 1324 | |
| 1325 | void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) |
| 1326 | { |
| 1327 | if (!irqchip_in_kernel(vcpu->kvm)) |
| 1328 | return; |
| 1329 | |
| 1330 | __kvm_vgic_sync_hwstate(vcpu); |
| 1331 | } |
| 1332 | |
| 1333 | int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) |
| 1334 | { |
| 1335 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 1336 | |
| 1337 | if (!irqchip_in_kernel(vcpu->kvm)) |
| 1338 | return 0; |
| 1339 | |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1340 | return test_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu); |
Marc Zyngier | 9d949dc | 2013-01-21 19:36:14 -0500 | [diff] [blame] | 1341 | } |
| 1342 | |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 1343 | int kvm_vgic_vcpu_active_irq(struct kvm_vcpu *vcpu) |
| 1344 | { |
| 1345 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
| 1346 | |
| 1347 | if (!irqchip_in_kernel(vcpu->kvm)) |
| 1348 | return 0; |
| 1349 | |
| 1350 | return test_bit(vcpu->vcpu_id, dist->irq_active_on_cpu); |
| 1351 | } |
| 1352 | |
| 1353 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 1354 | void vgic_kick_vcpus(struct kvm *kvm) |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1355 | { |
| 1356 | struct kvm_vcpu *vcpu; |
| 1357 | int c; |
| 1358 | |
| 1359 | /* |
| 1360 | * We've injected an interrupt, time to find out who deserves |
| 1361 | * a good kick... |
| 1362 | */ |
| 1363 | kvm_for_each_vcpu(c, vcpu, kvm) { |
| 1364 | if (kvm_vgic_vcpu_pending_irq(vcpu)) |
| 1365 | kvm_vcpu_kick(vcpu); |
| 1366 | } |
| 1367 | } |
| 1368 | |
| 1369 | static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level) |
| 1370 | { |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 1371 | int edge_triggered = vgic_irq_is_edge(vcpu, irq); |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1372 | |
| 1373 | /* |
| 1374 | * Only inject an interrupt if: |
| 1375 | * - edge triggered and we have a rising edge |
| 1376 | * - level triggered and we change level |
| 1377 | */ |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1378 | if (edge_triggered) { |
| 1379 | int state = vgic_dist_irq_is_pending(vcpu, irq); |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1380 | return level > state; |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1381 | } else { |
| 1382 | int state = vgic_dist_irq_get_level(vcpu, irq); |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1383 | return level != state; |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1384 | } |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1385 | } |
| 1386 | |
Shannon Zhao | 016ed39 | 2014-11-19 10:11:25 +0000 | [diff] [blame] | 1387 | static int vgic_update_irq_pending(struct kvm *kvm, int cpuid, |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1388 | unsigned int irq_num, bool level) |
| 1389 | { |
| 1390 | struct vgic_dist *dist = &kvm->arch.vgic; |
| 1391 | struct kvm_vcpu *vcpu; |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 1392 | int edge_triggered, level_triggered; |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1393 | int enabled; |
Andre Przywara | a0675c2 | 2014-06-07 00:54:51 +0200 | [diff] [blame] | 1394 | bool ret = true, can_inject = true; |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1395 | |
| 1396 | spin_lock(&dist->lock); |
| 1397 | |
| 1398 | vcpu = kvm_get_vcpu(kvm, cpuid); |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 1399 | edge_triggered = vgic_irq_is_edge(vcpu, irq_num); |
| 1400 | level_triggered = !edge_triggered; |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1401 | |
| 1402 | if (!vgic_validate_injection(vcpu, irq_num, level)) { |
| 1403 | ret = false; |
| 1404 | goto out; |
| 1405 | } |
| 1406 | |
| 1407 | if (irq_num >= VGIC_NR_PRIVATE_IRQS) { |
| 1408 | cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS]; |
Andre Przywara | a0675c2 | 2014-06-07 00:54:51 +0200 | [diff] [blame] | 1409 | if (cpuid == VCPU_NOT_ALLOCATED) { |
| 1410 | /* Pretend we use CPU0, and prevent injection */ |
| 1411 | cpuid = 0; |
| 1412 | can_inject = false; |
| 1413 | } |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1414 | vcpu = kvm_get_vcpu(kvm, cpuid); |
| 1415 | } |
| 1416 | |
| 1417 | kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid); |
| 1418 | |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1419 | if (level) { |
| 1420 | if (level_triggered) |
| 1421 | vgic_dist_irq_set_level(vcpu, irq_num); |
Christoffer Dall | 227844f | 2014-06-09 12:27:18 +0200 | [diff] [blame] | 1422 | vgic_dist_irq_set_pending(vcpu, irq_num); |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1423 | } else { |
| 1424 | if (level_triggered) { |
| 1425 | vgic_dist_irq_clear_level(vcpu, irq_num); |
| 1426 | if (!vgic_dist_irq_soft_pend(vcpu, irq_num)) |
| 1427 | vgic_dist_irq_clear_pending(vcpu, irq_num); |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1428 | } |
wanghaibin | 7d39f9e3 | 2014-11-17 09:27:37 +0000 | [diff] [blame] | 1429 | |
| 1430 | ret = false; |
| 1431 | goto out; |
Christoffer Dall | faa1b46 | 2014-06-14 21:54:51 +0200 | [diff] [blame] | 1432 | } |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1433 | |
| 1434 | enabled = vgic_irq_is_enabled(vcpu, irq_num); |
| 1435 | |
Andre Przywara | a0675c2 | 2014-06-07 00:54:51 +0200 | [diff] [blame] | 1436 | if (!enabled || !can_inject) { |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1437 | ret = false; |
| 1438 | goto out; |
| 1439 | } |
| 1440 | |
Christoffer Dall | dbf20f9 | 2014-06-09 12:55:13 +0200 | [diff] [blame] | 1441 | if (!vgic_can_sample_irq(vcpu, irq_num)) { |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1442 | /* |
| 1443 | * Level interrupt in progress, will be picked up |
| 1444 | * when EOId. |
| 1445 | */ |
| 1446 | ret = false; |
| 1447 | goto out; |
| 1448 | } |
| 1449 | |
| 1450 | if (level) { |
| 1451 | vgic_cpu_irq_set(vcpu, irq_num); |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1452 | set_bit(cpuid, dist->irq_pending_on_cpu); |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1453 | } |
| 1454 | |
| 1455 | out: |
| 1456 | spin_unlock(&dist->lock); |
| 1457 | |
Shannon Zhao | 016ed39 | 2014-11-19 10:11:25 +0000 | [diff] [blame] | 1458 | return ret ? cpuid : -EINVAL; |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1459 | } |
| 1460 | |
| 1461 | /** |
| 1462 | * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic |
| 1463 | * @kvm: The VM structure pointer |
| 1464 | * @cpuid: The CPU for PPIs |
| 1465 | * @irq_num: The IRQ number that is assigned to the device |
| 1466 | * @level: Edge-triggered: true: to trigger the interrupt |
| 1467 | * false: to ignore the call |
| 1468 | * Level-sensitive true: activates an interrupt |
| 1469 | * false: deactivates an interrupt |
| 1470 | * |
| 1471 | * The GIC is not concerned with devices being active-LOW or active-HIGH for |
| 1472 | * level-sensitive interrupts. You can think of the level parameter as 1 |
| 1473 | * being HIGH and 0 being LOW and all devices being active-HIGH. |
| 1474 | */ |
| 1475 | int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num, |
| 1476 | bool level) |
| 1477 | { |
Christoffer Dall | ca7d9c8 | 2014-12-09 14:35:33 +0100 | [diff] [blame] | 1478 | int ret = 0; |
Shannon Zhao | 016ed39 | 2014-11-19 10:11:25 +0000 | [diff] [blame] | 1479 | int vcpu_id; |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1480 | |
Christoffer Dall | ca7d9c8 | 2014-12-09 14:35:33 +0100 | [diff] [blame] | 1481 | if (unlikely(!vgic_initialized(kvm))) { |
Andre Przywara | 59892136 | 2014-06-03 09:33:10 +0200 | [diff] [blame] | 1482 | /* |
| 1483 | * We only provide the automatic initialization of the VGIC |
| 1484 | * for the legacy case of a GICv2. Any other type must |
| 1485 | * be explicitly initialized once setup with the respective |
| 1486 | * KVM device call. |
| 1487 | */ |
| 1488 | if (kvm->arch.vgic.vgic_model != KVM_DEV_TYPE_ARM_VGIC_V2) { |
| 1489 | ret = -EBUSY; |
| 1490 | goto out; |
| 1491 | } |
Christoffer Dall | ca7d9c8 | 2014-12-09 14:35:33 +0100 | [diff] [blame] | 1492 | mutex_lock(&kvm->lock); |
| 1493 | ret = vgic_init(kvm); |
| 1494 | mutex_unlock(&kvm->lock); |
| 1495 | |
| 1496 | if (ret) |
| 1497 | goto out; |
Shannon Zhao | 016ed39 | 2014-11-19 10:11:25 +0000 | [diff] [blame] | 1498 | } |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1499 | |
Christoffer Dall | ca7d9c8 | 2014-12-09 14:35:33 +0100 | [diff] [blame] | 1500 | vcpu_id = vgic_update_irq_pending(kvm, cpuid, irq_num, level); |
| 1501 | if (vcpu_id >= 0) { |
| 1502 | /* kick the specified vcpu */ |
| 1503 | kvm_vcpu_kick(kvm_get_vcpu(kvm, vcpu_id)); |
| 1504 | } |
| 1505 | |
| 1506 | out: |
| 1507 | return ret; |
Marc Zyngier | 5863c2c | 2013-01-21 19:36:15 -0500 | [diff] [blame] | 1508 | } |
| 1509 | |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 1510 | static irqreturn_t vgic_maintenance_handler(int irq, void *data) |
| 1511 | { |
| 1512 | /* |
| 1513 | * We cannot rely on the vgic maintenance interrupt to be |
| 1514 | * delivered synchronously. This means we can only use it to |
| 1515 | * exit the VM, and we perform the handling of EOIed |
| 1516 | * interrupts on the exit path (see vgic_process_maintenance). |
| 1517 | */ |
| 1518 | return IRQ_HANDLED; |
| 1519 | } |
| 1520 | |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1521 | void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu) |
| 1522 | { |
| 1523 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
| 1524 | |
| 1525 | kfree(vgic_cpu->pending_shared); |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 1526 | kfree(vgic_cpu->active_shared); |
| 1527 | kfree(vgic_cpu->pend_act_shared); |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1528 | kfree(vgic_cpu->vgic_irq_lr_map); |
| 1529 | vgic_cpu->pending_shared = NULL; |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 1530 | vgic_cpu->active_shared = NULL; |
| 1531 | vgic_cpu->pend_act_shared = NULL; |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1532 | vgic_cpu->vgic_irq_lr_map = NULL; |
| 1533 | } |
| 1534 | |
| 1535 | static int vgic_vcpu_init_maps(struct kvm_vcpu *vcpu, int nr_irqs) |
| 1536 | { |
| 1537 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
| 1538 | |
| 1539 | int sz = (nr_irqs - VGIC_NR_PRIVATE_IRQS) / 8; |
| 1540 | vgic_cpu->pending_shared = kzalloc(sz, GFP_KERNEL); |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 1541 | vgic_cpu->active_shared = kzalloc(sz, GFP_KERNEL); |
| 1542 | vgic_cpu->pend_act_shared = kzalloc(sz, GFP_KERNEL); |
Peter Maydell | 6d3cfbe | 2014-12-04 15:02:24 +0000 | [diff] [blame] | 1543 | vgic_cpu->vgic_irq_lr_map = kmalloc(nr_irqs, GFP_KERNEL); |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1544 | |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 1545 | if (!vgic_cpu->pending_shared |
| 1546 | || !vgic_cpu->active_shared |
| 1547 | || !vgic_cpu->pend_act_shared |
| 1548 | || !vgic_cpu->vgic_irq_lr_map) { |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1549 | kvm_vgic_vcpu_destroy(vcpu); |
| 1550 | return -ENOMEM; |
| 1551 | } |
| 1552 | |
Peter Maydell | 6d3cfbe | 2014-12-04 15:02:24 +0000 | [diff] [blame] | 1553 | memset(vgic_cpu->vgic_irq_lr_map, LR_EMPTY, nr_irqs); |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 1554 | |
| 1555 | /* |
Marc Zyngier | ca85f62 | 2013-06-18 19:17:28 +0100 | [diff] [blame] | 1556 | * Store the number of LRs per vcpu, so we don't have to go |
| 1557 | * all the way to the distributor structure to find out. Only |
| 1558 | * assembly code should use this one. |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 1559 | */ |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1560 | vgic_cpu->nr_lr = vgic->nr_lr; |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 1561 | |
Peter Maydell | 6d3cfbe | 2014-12-04 15:02:24 +0000 | [diff] [blame] | 1562 | return 0; |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 1563 | } |
| 1564 | |
Andre Przywara | 3caa2d8 | 2014-06-02 16:26:01 +0200 | [diff] [blame] | 1565 | /** |
| 1566 | * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW |
| 1567 | * |
| 1568 | * The host's GIC naturally limits the maximum amount of VCPUs a guest |
| 1569 | * can use. |
| 1570 | */ |
| 1571 | int kvm_vgic_get_max_vcpus(void) |
| 1572 | { |
| 1573 | return vgic->max_gic_vcpus; |
| 1574 | } |
| 1575 | |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1576 | void kvm_vgic_destroy(struct kvm *kvm) |
| 1577 | { |
| 1578 | struct vgic_dist *dist = &kvm->arch.vgic; |
| 1579 | struct kvm_vcpu *vcpu; |
| 1580 | int i; |
| 1581 | |
| 1582 | kvm_for_each_vcpu(i, vcpu, kvm) |
| 1583 | kvm_vgic_vcpu_destroy(vcpu); |
| 1584 | |
| 1585 | vgic_free_bitmap(&dist->irq_enabled); |
| 1586 | vgic_free_bitmap(&dist->irq_level); |
| 1587 | vgic_free_bitmap(&dist->irq_pending); |
| 1588 | vgic_free_bitmap(&dist->irq_soft_pend); |
| 1589 | vgic_free_bitmap(&dist->irq_queued); |
| 1590 | vgic_free_bitmap(&dist->irq_cfg); |
| 1591 | vgic_free_bytemap(&dist->irq_priority); |
| 1592 | if (dist->irq_spi_target) { |
| 1593 | for (i = 0; i < dist->nr_cpus; i++) |
| 1594 | vgic_free_bitmap(&dist->irq_spi_target[i]); |
| 1595 | } |
| 1596 | kfree(dist->irq_sgi_sources); |
| 1597 | kfree(dist->irq_spi_cpu); |
Andre Przywara | a0675c2 | 2014-06-07 00:54:51 +0200 | [diff] [blame] | 1598 | kfree(dist->irq_spi_mpidr); |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1599 | kfree(dist->irq_spi_target); |
| 1600 | kfree(dist->irq_pending_on_cpu); |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 1601 | kfree(dist->irq_active_on_cpu); |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1602 | dist->irq_sgi_sources = NULL; |
| 1603 | dist->irq_spi_cpu = NULL; |
| 1604 | dist->irq_spi_target = NULL; |
| 1605 | dist->irq_pending_on_cpu = NULL; |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 1606 | dist->irq_active_on_cpu = NULL; |
Christoffer Dall | 1f57be2 | 2014-12-09 14:30:36 +0100 | [diff] [blame] | 1607 | dist->nr_cpus = 0; |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1608 | } |
| 1609 | |
| 1610 | /* |
| 1611 | * Allocate and initialize the various data structures. Must be called |
| 1612 | * with kvm->lock held! |
| 1613 | */ |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 1614 | int vgic_init(struct kvm *kvm) |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1615 | { |
| 1616 | struct vgic_dist *dist = &kvm->arch.vgic; |
| 1617 | struct kvm_vcpu *vcpu; |
| 1618 | int nr_cpus, nr_irqs; |
Peter Maydell | 6d3cfbe | 2014-12-04 15:02:24 +0000 | [diff] [blame] | 1619 | int ret, i, vcpu_id; |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1620 | |
Christoffer Dall | 1f57be2 | 2014-12-09 14:30:36 +0100 | [diff] [blame] | 1621 | if (vgic_initialized(kvm)) |
Marc Zyngier | 4956f2b | 2014-07-08 12:09:06 +0100 | [diff] [blame] | 1622 | return 0; |
Marc Zyngier | 5fb66da | 2014-07-08 12:09:05 +0100 | [diff] [blame] | 1623 | |
Marc Zyngier | 4956f2b | 2014-07-08 12:09:06 +0100 | [diff] [blame] | 1624 | nr_cpus = dist->nr_cpus = atomic_read(&kvm->online_vcpus); |
| 1625 | if (!nr_cpus) /* No vcpus? Can't be good... */ |
Eric Auger | 66b030e | 2014-12-15 18:43:32 +0100 | [diff] [blame] | 1626 | return -ENODEV; |
Marc Zyngier | 4956f2b | 2014-07-08 12:09:06 +0100 | [diff] [blame] | 1627 | |
| 1628 | /* |
| 1629 | * If nobody configured the number of interrupts, use the |
| 1630 | * legacy one. |
| 1631 | */ |
Marc Zyngier | 5fb66da | 2014-07-08 12:09:05 +0100 | [diff] [blame] | 1632 | if (!dist->nr_irqs) |
| 1633 | dist->nr_irqs = VGIC_NR_IRQS_LEGACY; |
| 1634 | |
| 1635 | nr_irqs = dist->nr_irqs; |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1636 | |
| 1637 | ret = vgic_init_bitmap(&dist->irq_enabled, nr_cpus, nr_irqs); |
| 1638 | ret |= vgic_init_bitmap(&dist->irq_level, nr_cpus, nr_irqs); |
| 1639 | ret |= vgic_init_bitmap(&dist->irq_pending, nr_cpus, nr_irqs); |
| 1640 | ret |= vgic_init_bitmap(&dist->irq_soft_pend, nr_cpus, nr_irqs); |
| 1641 | ret |= vgic_init_bitmap(&dist->irq_queued, nr_cpus, nr_irqs); |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 1642 | ret |= vgic_init_bitmap(&dist->irq_active, nr_cpus, nr_irqs); |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1643 | ret |= vgic_init_bitmap(&dist->irq_cfg, nr_cpus, nr_irqs); |
| 1644 | ret |= vgic_init_bytemap(&dist->irq_priority, nr_cpus, nr_irqs); |
| 1645 | |
| 1646 | if (ret) |
| 1647 | goto out; |
| 1648 | |
| 1649 | dist->irq_sgi_sources = kzalloc(nr_cpus * VGIC_NR_SGIS, GFP_KERNEL); |
| 1650 | dist->irq_spi_cpu = kzalloc(nr_irqs - VGIC_NR_PRIVATE_IRQS, GFP_KERNEL); |
| 1651 | dist->irq_spi_target = kzalloc(sizeof(*dist->irq_spi_target) * nr_cpus, |
| 1652 | GFP_KERNEL); |
| 1653 | dist->irq_pending_on_cpu = kzalloc(BITS_TO_LONGS(nr_cpus) * sizeof(long), |
| 1654 | GFP_KERNEL); |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 1655 | dist->irq_active_on_cpu = kzalloc(BITS_TO_LONGS(nr_cpus) * sizeof(long), |
| 1656 | GFP_KERNEL); |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1657 | if (!dist->irq_sgi_sources || |
| 1658 | !dist->irq_spi_cpu || |
| 1659 | !dist->irq_spi_target || |
Christoffer Dall | 47a98b1 | 2015-03-13 17:02:54 +0000 | [diff] [blame^] | 1660 | !dist->irq_pending_on_cpu || |
| 1661 | !dist->irq_active_on_cpu) { |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1662 | ret = -ENOMEM; |
| 1663 | goto out; |
| 1664 | } |
| 1665 | |
| 1666 | for (i = 0; i < nr_cpus; i++) |
| 1667 | ret |= vgic_init_bitmap(&dist->irq_spi_target[i], |
| 1668 | nr_cpus, nr_irqs); |
| 1669 | |
| 1670 | if (ret) |
| 1671 | goto out; |
| 1672 | |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 1673 | ret = kvm->arch.vgic.vm_ops.init_model(kvm); |
| 1674 | if (ret) |
| 1675 | goto out; |
Peter Maydell | 6d3cfbe | 2014-12-04 15:02:24 +0000 | [diff] [blame] | 1676 | |
| 1677 | kvm_for_each_vcpu(vcpu_id, vcpu, kvm) { |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1678 | ret = vgic_vcpu_init_maps(vcpu, nr_irqs); |
| 1679 | if (ret) { |
| 1680 | kvm_err("VGIC: Failed to allocate vcpu memory\n"); |
| 1681 | break; |
| 1682 | } |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1683 | |
Peter Maydell | 6d3cfbe | 2014-12-04 15:02:24 +0000 | [diff] [blame] | 1684 | for (i = 0; i < dist->nr_irqs; i++) { |
| 1685 | if (i < VGIC_NR_PPIS) |
| 1686 | vgic_bitmap_set_irq_val(&dist->irq_enabled, |
| 1687 | vcpu->vcpu_id, i, 1); |
| 1688 | if (i < VGIC_NR_PRIVATE_IRQS) |
| 1689 | vgic_bitmap_set_irq_val(&dist->irq_cfg, |
| 1690 | vcpu->vcpu_id, i, |
| 1691 | VGIC_CFG_EDGE); |
| 1692 | } |
| 1693 | |
| 1694 | vgic_enable(vcpu); |
| 1695 | } |
Marc Zyngier | 4956f2b | 2014-07-08 12:09:06 +0100 | [diff] [blame] | 1696 | |
Marc Zyngier | c1bfb57 | 2014-07-08 12:09:01 +0100 | [diff] [blame] | 1697 | out: |
| 1698 | if (ret) |
| 1699 | kvm_vgic_destroy(kvm); |
| 1700 | |
| 1701 | return ret; |
| 1702 | } |
| 1703 | |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 1704 | static int init_vgic_model(struct kvm *kvm, int type) |
| 1705 | { |
| 1706 | switch (type) { |
| 1707 | case KVM_DEV_TYPE_ARM_VGIC_V2: |
| 1708 | vgic_v2_init_emulation(kvm); |
| 1709 | break; |
Andre Przywara | b5d84ff | 2014-06-03 10:26:03 +0200 | [diff] [blame] | 1710 | #ifdef CONFIG_ARM_GIC_V3 |
| 1711 | case KVM_DEV_TYPE_ARM_VGIC_V3: |
| 1712 | vgic_v3_init_emulation(kvm); |
| 1713 | break; |
| 1714 | #endif |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 1715 | default: |
| 1716 | return -ENODEV; |
| 1717 | } |
| 1718 | |
Andre Przywara | 3caa2d8 | 2014-06-02 16:26:01 +0200 | [diff] [blame] | 1719 | if (atomic_read(&kvm->online_vcpus) > kvm->arch.max_vcpus) |
| 1720 | return -E2BIG; |
| 1721 | |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 1722 | return 0; |
| 1723 | } |
| 1724 | |
Andre Przywara | 59892136 | 2014-06-03 09:33:10 +0200 | [diff] [blame] | 1725 | int kvm_vgic_create(struct kvm *kvm, u32 type) |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 1726 | { |
Christoffer Dall | 6b50f54 | 2014-11-06 11:47:39 +0000 | [diff] [blame] | 1727 | int i, vcpu_lock_idx = -1, ret; |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 1728 | struct kvm_vcpu *vcpu; |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 1729 | |
| 1730 | mutex_lock(&kvm->lock); |
| 1731 | |
Andre Przywara | 4ce7ebd | 2014-10-26 23:18:14 +0000 | [diff] [blame] | 1732 | if (irqchip_in_kernel(kvm)) { |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 1733 | ret = -EEXIST; |
| 1734 | goto out; |
| 1735 | } |
| 1736 | |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 1737 | /* |
Andre Przywara | b5d84ff | 2014-06-03 10:26:03 +0200 | [diff] [blame] | 1738 | * This function is also called by the KVM_CREATE_IRQCHIP handler, |
| 1739 | * which had no chance yet to check the availability of the GICv2 |
| 1740 | * emulation. So check this here again. KVM_CREATE_DEVICE does |
| 1741 | * the proper checks already. |
| 1742 | */ |
| 1743 | if (type == KVM_DEV_TYPE_ARM_VGIC_V2 && !vgic->can_emulate_gicv2) |
| 1744 | return -ENODEV; |
| 1745 | |
| 1746 | /* |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 1747 | * Any time a vcpu is run, vcpu_load is called which tries to grab the |
| 1748 | * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure |
| 1749 | * that no other VCPUs are run while we create the vgic. |
| 1750 | */ |
Christoffer Dall | 6b50f54 | 2014-11-06 11:47:39 +0000 | [diff] [blame] | 1751 | ret = -EBUSY; |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 1752 | kvm_for_each_vcpu(i, vcpu, kvm) { |
| 1753 | if (!mutex_trylock(&vcpu->mutex)) |
| 1754 | goto out_unlock; |
| 1755 | vcpu_lock_idx = i; |
| 1756 | } |
| 1757 | |
| 1758 | kvm_for_each_vcpu(i, vcpu, kvm) { |
Christoffer Dall | 6b50f54 | 2014-11-06 11:47:39 +0000 | [diff] [blame] | 1759 | if (vcpu->arch.has_run_once) |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 1760 | goto out_unlock; |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 1761 | } |
Christoffer Dall | 6b50f54 | 2014-11-06 11:47:39 +0000 | [diff] [blame] | 1762 | ret = 0; |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 1763 | |
Andre Przywara | b26e5fd | 2014-06-02 16:19:12 +0200 | [diff] [blame] | 1764 | ret = init_vgic_model(kvm, type); |
| 1765 | if (ret) |
| 1766 | goto out_unlock; |
| 1767 | |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 1768 | spin_lock_init(&kvm->arch.vgic.lock); |
Marc Zyngier | f982cf4 | 2014-05-15 10:03:25 +0100 | [diff] [blame] | 1769 | kvm->arch.vgic.in_kernel = true; |
Andre Przywara | 59892136 | 2014-06-03 09:33:10 +0200 | [diff] [blame] | 1770 | kvm->arch.vgic.vgic_model = type; |
Marc Zyngier | 8f186d5 | 2014-02-04 18:13:03 +0000 | [diff] [blame] | 1771 | kvm->arch.vgic.vctrl_base = vgic->vctrl_base; |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 1772 | kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF; |
| 1773 | kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF; |
Andre Przywara | a0675c2 | 2014-06-07 00:54:51 +0200 | [diff] [blame] | 1774 | kvm->arch.vgic.vgic_redist_base = VGIC_ADDR_UNDEF; |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 1775 | |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 1776 | out_unlock: |
| 1777 | for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) { |
| 1778 | vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx); |
| 1779 | mutex_unlock(&vcpu->mutex); |
| 1780 | } |
| 1781 | |
Marc Zyngier | 01ac5e3 | 2013-01-21 19:36:16 -0500 | [diff] [blame] | 1782 | out: |
| 1783 | mutex_unlock(&kvm->lock); |
| 1784 | return ret; |
| 1785 | } |
| 1786 | |
Will Deacon | 1fa451b | 2014-08-26 15:13:24 +0100 | [diff] [blame] | 1787 | static int vgic_ioaddr_overlap(struct kvm *kvm) |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 1788 | { |
| 1789 | phys_addr_t dist = kvm->arch.vgic.vgic_dist_base; |
| 1790 | phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base; |
| 1791 | |
| 1792 | if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu)) |
| 1793 | return 0; |
| 1794 | if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) || |
| 1795 | (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist)) |
| 1796 | return -EBUSY; |
| 1797 | return 0; |
| 1798 | } |
| 1799 | |
| 1800 | static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr, |
| 1801 | phys_addr_t addr, phys_addr_t size) |
| 1802 | { |
| 1803 | int ret; |
| 1804 | |
Christoffer Dall | ce01e4e | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 1805 | if (addr & ~KVM_PHYS_MASK) |
| 1806 | return -E2BIG; |
| 1807 | |
| 1808 | if (addr & (SZ_4K - 1)) |
| 1809 | return -EINVAL; |
| 1810 | |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 1811 | if (!IS_VGIC_ADDR_UNDEF(*ioaddr)) |
| 1812 | return -EEXIST; |
| 1813 | if (addr + size < addr) |
| 1814 | return -EINVAL; |
| 1815 | |
Haibin Wang | 30c2117 | 2014-04-29 14:49:17 +0800 | [diff] [blame] | 1816 | *ioaddr = addr; |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 1817 | ret = vgic_ioaddr_overlap(kvm); |
| 1818 | if (ret) |
Haibin Wang | 30c2117 | 2014-04-29 14:49:17 +0800 | [diff] [blame] | 1819 | *ioaddr = VGIC_ADDR_UNDEF; |
| 1820 | |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 1821 | return ret; |
| 1822 | } |
| 1823 | |
Christoffer Dall | ce01e4e | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 1824 | /** |
| 1825 | * kvm_vgic_addr - set or get vgic VM base addresses |
| 1826 | * @kvm: pointer to the vm struct |
Andre Przywara | ac3d373 | 2014-06-03 10:26:30 +0200 | [diff] [blame] | 1827 | * @type: the VGIC addr type, one of KVM_VGIC_V[23]_ADDR_TYPE_XXX |
Christoffer Dall | ce01e4e | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 1828 | * @addr: pointer to address value |
| 1829 | * @write: if true set the address in the VM address space, if false read the |
| 1830 | * address |
| 1831 | * |
| 1832 | * Set or get the vgic base addresses for the distributor and the virtual CPU |
| 1833 | * interface in the VM physical address space. These addresses are properties |
| 1834 | * of the emulated core/SoC and therefore user space initially knows this |
| 1835 | * information. |
| 1836 | */ |
| 1837 | int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write) |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 1838 | { |
| 1839 | int r = 0; |
| 1840 | struct vgic_dist *vgic = &kvm->arch.vgic; |
Andre Przywara | ac3d373 | 2014-06-03 10:26:30 +0200 | [diff] [blame] | 1841 | int type_needed; |
| 1842 | phys_addr_t *addr_ptr, block_size; |
Andre Przywara | 4fa96afd | 2015-01-13 12:02:13 +0000 | [diff] [blame] | 1843 | phys_addr_t alignment; |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 1844 | |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 1845 | mutex_lock(&kvm->lock); |
| 1846 | switch (type) { |
| 1847 | case KVM_VGIC_V2_ADDR_TYPE_DIST: |
Andre Przywara | ac3d373 | 2014-06-03 10:26:30 +0200 | [diff] [blame] | 1848 | type_needed = KVM_DEV_TYPE_ARM_VGIC_V2; |
| 1849 | addr_ptr = &vgic->vgic_dist_base; |
| 1850 | block_size = KVM_VGIC_V2_DIST_SIZE; |
Andre Przywara | 4fa96afd | 2015-01-13 12:02:13 +0000 | [diff] [blame] | 1851 | alignment = SZ_4K; |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 1852 | break; |
| 1853 | case KVM_VGIC_V2_ADDR_TYPE_CPU: |
Andre Przywara | ac3d373 | 2014-06-03 10:26:30 +0200 | [diff] [blame] | 1854 | type_needed = KVM_DEV_TYPE_ARM_VGIC_V2; |
| 1855 | addr_ptr = &vgic->vgic_cpu_base; |
| 1856 | block_size = KVM_VGIC_V2_CPU_SIZE; |
Andre Przywara | 4fa96afd | 2015-01-13 12:02:13 +0000 | [diff] [blame] | 1857 | alignment = SZ_4K; |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 1858 | break; |
Andre Przywara | ac3d373 | 2014-06-03 10:26:30 +0200 | [diff] [blame] | 1859 | #ifdef CONFIG_ARM_GIC_V3 |
| 1860 | case KVM_VGIC_V3_ADDR_TYPE_DIST: |
| 1861 | type_needed = KVM_DEV_TYPE_ARM_VGIC_V3; |
| 1862 | addr_ptr = &vgic->vgic_dist_base; |
| 1863 | block_size = KVM_VGIC_V3_DIST_SIZE; |
Andre Przywara | 4fa96afd | 2015-01-13 12:02:13 +0000 | [diff] [blame] | 1864 | alignment = SZ_64K; |
Andre Przywara | ac3d373 | 2014-06-03 10:26:30 +0200 | [diff] [blame] | 1865 | break; |
| 1866 | case KVM_VGIC_V3_ADDR_TYPE_REDIST: |
| 1867 | type_needed = KVM_DEV_TYPE_ARM_VGIC_V3; |
| 1868 | addr_ptr = &vgic->vgic_redist_base; |
| 1869 | block_size = KVM_VGIC_V3_REDIST_SIZE; |
Andre Przywara | 4fa96afd | 2015-01-13 12:02:13 +0000 | [diff] [blame] | 1870 | alignment = SZ_64K; |
Andre Przywara | ac3d373 | 2014-06-03 10:26:30 +0200 | [diff] [blame] | 1871 | break; |
| 1872 | #endif |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 1873 | default: |
| 1874 | r = -ENODEV; |
Andre Przywara | ac3d373 | 2014-06-03 10:26:30 +0200 | [diff] [blame] | 1875 | goto out; |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 1876 | } |
| 1877 | |
Andre Przywara | ac3d373 | 2014-06-03 10:26:30 +0200 | [diff] [blame] | 1878 | if (vgic->vgic_model != type_needed) { |
| 1879 | r = -ENODEV; |
| 1880 | goto out; |
| 1881 | } |
| 1882 | |
Andre Przywara | 4fa96afd | 2015-01-13 12:02:13 +0000 | [diff] [blame] | 1883 | if (write) { |
| 1884 | if (!IS_ALIGNED(*addr, alignment)) |
| 1885 | r = -EINVAL; |
| 1886 | else |
| 1887 | r = vgic_ioaddr_assign(kvm, addr_ptr, *addr, |
| 1888 | block_size); |
| 1889 | } else { |
Andre Przywara | ac3d373 | 2014-06-03 10:26:30 +0200 | [diff] [blame] | 1890 | *addr = *addr_ptr; |
Andre Przywara | 4fa96afd | 2015-01-13 12:02:13 +0000 | [diff] [blame] | 1891 | } |
Andre Przywara | ac3d373 | 2014-06-03 10:26:30 +0200 | [diff] [blame] | 1892 | |
| 1893 | out: |
Christoffer Dall | 330690c | 2013-01-21 19:36:13 -0500 | [diff] [blame] | 1894 | mutex_unlock(&kvm->lock); |
| 1895 | return r; |
| 1896 | } |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 1897 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 1898 | int vgic_set_common_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 1899 | { |
Christoffer Dall | ce01e4e | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 1900 | int r; |
| 1901 | |
| 1902 | switch (attr->group) { |
| 1903 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { |
| 1904 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; |
| 1905 | u64 addr; |
| 1906 | unsigned long type = (unsigned long)attr->attr; |
| 1907 | |
| 1908 | if (copy_from_user(&addr, uaddr, sizeof(addr))) |
| 1909 | return -EFAULT; |
| 1910 | |
| 1911 | r = kvm_vgic_addr(dev->kvm, type, &addr, true); |
| 1912 | return (r == -ENODEV) ? -ENXIO : r; |
| 1913 | } |
Marc Zyngier | a98f26f | 2014-07-08 12:09:07 +0100 | [diff] [blame] | 1914 | case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: { |
| 1915 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; |
| 1916 | u32 val; |
| 1917 | int ret = 0; |
| 1918 | |
| 1919 | if (get_user(val, uaddr)) |
| 1920 | return -EFAULT; |
| 1921 | |
| 1922 | /* |
| 1923 | * We require: |
| 1924 | * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs |
| 1925 | * - at most 1024 interrupts |
| 1926 | * - a multiple of 32 interrupts |
| 1927 | */ |
| 1928 | if (val < (VGIC_NR_PRIVATE_IRQS + 32) || |
| 1929 | val > VGIC_MAX_IRQS || |
| 1930 | (val & 31)) |
| 1931 | return -EINVAL; |
| 1932 | |
| 1933 | mutex_lock(&dev->kvm->lock); |
| 1934 | |
Christoffer Dall | c52edf5 | 2014-12-09 14:28:09 +0100 | [diff] [blame] | 1935 | if (vgic_ready(dev->kvm) || dev->kvm->arch.vgic.nr_irqs) |
Marc Zyngier | a98f26f | 2014-07-08 12:09:07 +0100 | [diff] [blame] | 1936 | ret = -EBUSY; |
| 1937 | else |
| 1938 | dev->kvm->arch.vgic.nr_irqs = val; |
| 1939 | |
| 1940 | mutex_unlock(&dev->kvm->lock); |
| 1941 | |
| 1942 | return ret; |
| 1943 | } |
Eric Auger | 065c003 | 2014-12-15 18:43:33 +0100 | [diff] [blame] | 1944 | case KVM_DEV_ARM_VGIC_GRP_CTRL: { |
| 1945 | switch (attr->attr) { |
| 1946 | case KVM_DEV_ARM_VGIC_CTRL_INIT: |
| 1947 | r = vgic_init(dev->kvm); |
| 1948 | return r; |
| 1949 | } |
| 1950 | break; |
| 1951 | } |
Christoffer Dall | ce01e4e | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 1952 | } |
| 1953 | |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 1954 | return -ENXIO; |
| 1955 | } |
| 1956 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 1957 | int vgic_get_common_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 1958 | { |
Christoffer Dall | ce01e4e | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 1959 | int r = -ENXIO; |
| 1960 | |
| 1961 | switch (attr->group) { |
| 1962 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { |
| 1963 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; |
| 1964 | u64 addr; |
| 1965 | unsigned long type = (unsigned long)attr->attr; |
| 1966 | |
| 1967 | r = kvm_vgic_addr(dev->kvm, type, &addr, false); |
| 1968 | if (r) |
| 1969 | return (r == -ENODEV) ? -ENXIO : r; |
| 1970 | |
| 1971 | if (copy_to_user(uaddr, &addr, sizeof(addr))) |
| 1972 | return -EFAULT; |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 1973 | break; |
Christoffer Dall | ce01e4e | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 1974 | } |
Marc Zyngier | a98f26f | 2014-07-08 12:09:07 +0100 | [diff] [blame] | 1975 | case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: { |
| 1976 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; |
Andre Przywara | b60da14 | 2014-08-21 11:08:27 +0100 | [diff] [blame] | 1977 | |
Marc Zyngier | a98f26f | 2014-07-08 12:09:07 +0100 | [diff] [blame] | 1978 | r = put_user(dev->kvm->arch.vgic.nr_irqs, uaddr); |
| 1979 | break; |
| 1980 | } |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 1981 | |
Christoffer Dall | ce01e4e | 2013-09-23 14:55:56 -0700 | [diff] [blame] | 1982 | } |
| 1983 | |
| 1984 | return r; |
Christoffer Dall | 7330672 | 2013-10-25 17:29:18 +0100 | [diff] [blame] | 1985 | } |
| 1986 | |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 1987 | int vgic_has_attr_regs(const struct kvm_mmio_range *ranges, phys_addr_t offset) |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 1988 | { |
| 1989 | struct kvm_exit_mmio dev_attr_mmio; |
| 1990 | |
| 1991 | dev_attr_mmio.len = 4; |
Andre Przywara | 8321581 | 2014-06-07 00:53:08 +0200 | [diff] [blame] | 1992 | if (vgic_find_range(ranges, &dev_attr_mmio, offset)) |
Christoffer Dall | c07a019 | 2013-10-25 21:17:31 +0100 | [diff] [blame] | 1993 | return 0; |
| 1994 | else |
| 1995 | return -ENXIO; |
| 1996 | } |
| 1997 | |
Will Deacon | c06a841 | 2014-09-02 10:27:34 +0100 | [diff] [blame] | 1998 | static void vgic_init_maintenance_interrupt(void *info) |
| 1999 | { |
| 2000 | enable_percpu_irq(vgic->maint_irq, 0); |
| 2001 | } |
| 2002 | |
| 2003 | static int vgic_cpu_notify(struct notifier_block *self, |
| 2004 | unsigned long action, void *cpu) |
| 2005 | { |
| 2006 | switch (action) { |
| 2007 | case CPU_STARTING: |
| 2008 | case CPU_STARTING_FROZEN: |
| 2009 | vgic_init_maintenance_interrupt(NULL); |
| 2010 | break; |
| 2011 | case CPU_DYING: |
| 2012 | case CPU_DYING_FROZEN: |
| 2013 | disable_percpu_irq(vgic->maint_irq); |
| 2014 | break; |
| 2015 | } |
| 2016 | |
| 2017 | return NOTIFY_OK; |
| 2018 | } |
| 2019 | |
| 2020 | static struct notifier_block vgic_cpu_nb = { |
| 2021 | .notifier_call = vgic_cpu_notify, |
| 2022 | }; |
| 2023 | |
| 2024 | static const struct of_device_id vgic_ids[] = { |
Mark Rutland | 0f372475 | 2015-03-05 14:47:44 +0000 | [diff] [blame] | 2025 | { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_probe, }, |
| 2026 | { .compatible = "arm,cortex-a7-gic", .data = vgic_v2_probe, }, |
| 2027 | { .compatible = "arm,gic-400", .data = vgic_v2_probe, }, |
| 2028 | { .compatible = "arm,gic-v3", .data = vgic_v3_probe, }, |
Will Deacon | c06a841 | 2014-09-02 10:27:34 +0100 | [diff] [blame] | 2029 | {}, |
| 2030 | }; |
| 2031 | |
| 2032 | int kvm_vgic_hyp_init(void) |
| 2033 | { |
| 2034 | const struct of_device_id *matched_id; |
Christoffer Dall | a875daf | 2014-09-18 18:15:32 -0700 | [diff] [blame] | 2035 | const int (*vgic_probe)(struct device_node *,const struct vgic_ops **, |
| 2036 | const struct vgic_params **); |
Will Deacon | c06a841 | 2014-09-02 10:27:34 +0100 | [diff] [blame] | 2037 | struct device_node *vgic_node; |
| 2038 | int ret; |
| 2039 | |
| 2040 | vgic_node = of_find_matching_node_and_match(NULL, |
| 2041 | vgic_ids, &matched_id); |
| 2042 | if (!vgic_node) { |
| 2043 | kvm_err("error: no compatible GIC node found\n"); |
| 2044 | return -ENODEV; |
| 2045 | } |
| 2046 | |
| 2047 | vgic_probe = matched_id->data; |
| 2048 | ret = vgic_probe(vgic_node, &vgic_ops, &vgic); |
| 2049 | if (ret) |
| 2050 | return ret; |
| 2051 | |
| 2052 | ret = request_percpu_irq(vgic->maint_irq, vgic_maintenance_handler, |
| 2053 | "vgic", kvm_get_running_vcpus()); |
| 2054 | if (ret) { |
| 2055 | kvm_err("Cannot register interrupt %d\n", vgic->maint_irq); |
| 2056 | return ret; |
| 2057 | } |
| 2058 | |
| 2059 | ret = __register_cpu_notifier(&vgic_cpu_nb); |
| 2060 | if (ret) { |
| 2061 | kvm_err("Cannot register vgic CPU notifier\n"); |
| 2062 | goto out_free_irq; |
| 2063 | } |
| 2064 | |
| 2065 | /* Callback into for arch code for setup */ |
| 2066 | vgic_arch_setup(vgic); |
| 2067 | |
| 2068 | on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1); |
| 2069 | |
Andre Przywara | ea2f83a | 2014-10-26 23:17:00 +0000 | [diff] [blame] | 2070 | return 0; |
Will Deacon | c06a841 | 2014-09-02 10:27:34 +0100 | [diff] [blame] | 2071 | |
| 2072 | out_free_irq: |
| 2073 | free_percpu_irq(vgic->maint_irq, kvm_get_running_vcpus()); |
| 2074 | return ret; |
| 2075 | } |
Eric Auger | 174178f | 2015-03-04 11:14:36 +0100 | [diff] [blame] | 2076 | |
| 2077 | int kvm_irq_map_gsi(struct kvm *kvm, |
| 2078 | struct kvm_kernel_irq_routing_entry *entries, |
| 2079 | int gsi) |
| 2080 | { |
| 2081 | return gsi; |
| 2082 | } |
| 2083 | |
| 2084 | int kvm_irq_map_chip_pin(struct kvm *kvm, unsigned irqchip, unsigned pin) |
| 2085 | { |
| 2086 | return pin; |
| 2087 | } |
| 2088 | |
| 2089 | int kvm_set_irq(struct kvm *kvm, int irq_source_id, |
| 2090 | u32 irq, int level, bool line_status) |
| 2091 | { |
| 2092 | unsigned int spi = irq + VGIC_NR_PRIVATE_IRQS; |
| 2093 | |
| 2094 | trace_kvm_set_irq(irq, level, irq_source_id); |
| 2095 | |
| 2096 | BUG_ON(!vgic_initialized(kvm)); |
| 2097 | |
| 2098 | if (spi > kvm->arch.vgic.nr_irqs) |
| 2099 | return -EINVAL; |
| 2100 | return kvm_vgic_inject_irq(kvm, 0, spi, level); |
| 2101 | |
| 2102 | } |
| 2103 | |
| 2104 | /* MSI not implemented yet */ |
| 2105 | int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e, |
| 2106 | struct kvm *kvm, int irq_source_id, |
| 2107 | int level, bool line_status) |
| 2108 | { |
| 2109 | return 0; |
| 2110 | } |