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H. Peter Anvin1965aae2008-10-22 22:26:29 -07001#ifndef _ASM_X86_PGTABLE_3LEVEL_H
2#define _ASM_X86_PGTABLE_3LEVEL_H
Linus Torvalds1da177e2005-04-16 15:20:36 -07003
Linus Torvalds1da177e2005-04-16 15:20:36 -07004/*
5 * Intel Physical Address Extension (PAE) Mode - three-level page
6 * tables on PPro+ CPUs.
7 *
8 * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
9 */
10
Joe Perches4b01fef2008-03-23 01:03:10 -070011#define pte_ERROR(e) \
12 printk("%s:%d: bad pte %p(%08lx%08lx).\n", \
13 __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
14#define pmd_ERROR(e) \
15 printk("%s:%d: bad pmd %p(%016Lx).\n", \
16 __FILE__, __LINE__, &(e), pmd_val(e))
17#define pgd_ERROR(e) \
18 printk("%s:%d: bad pgd %p(%016Lx).\n", \
19 __FILE__, __LINE__, &(e), pgd_val(e))
Jeremy Fitzhardinge6194ba62008-01-30 13:34:11 +010020
Linus Torvalds1da177e2005-04-16 15:20:36 -070021/* Rules for using set_pte: the pte being assigned *must* be
22 * either not present or in a state where the hardware will
23 * not attempt to update the pte. In places where this is
24 * not possible, use pte_get_and_clear to obtain the old pte
25 * value and then use set_pte to update it. -ben
26 */
Jeremy Fitzhardinge3dc494e2007-05-02 19:27:13 +020027static inline void native_set_pte(pte_t *ptep, pte_t pte)
Linus Torvalds1da177e2005-04-16 15:20:36 -070028{
29 ptep->pte_high = pte.pte_high;
30 smp_wmb();
31 ptep->pte_low = pte.pte_low;
32}
Linus Torvalds1da177e2005-04-16 15:20:36 -070033
Jeremy Fitzhardinge3dc494e2007-05-02 19:27:13 +020034static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
35{
Joe Perches4b01fef2008-03-23 01:03:10 -070036 set_64bit((unsigned long long *)(ptep), native_pte_val(pte));
Jeremy Fitzhardinge3dc494e2007-05-02 19:27:13 +020037}
Joe Perches4b01fef2008-03-23 01:03:10 -070038
Jeremy Fitzhardinge3dc494e2007-05-02 19:27:13 +020039static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
40{
Joe Perches4b01fef2008-03-23 01:03:10 -070041 set_64bit((unsigned long long *)(pmdp), native_pmd_val(pmd));
Jeremy Fitzhardinge3dc494e2007-05-02 19:27:13 +020042}
Joe Perches4b01fef2008-03-23 01:03:10 -070043
Jeremy Fitzhardinge3dc494e2007-05-02 19:27:13 +020044static inline void native_set_pud(pud_t *pudp, pud_t pud)
45{
Joe Perches4b01fef2008-03-23 01:03:10 -070046 set_64bit((unsigned long long *)(pudp), native_pud_val(pud));
Jeremy Fitzhardinge3dc494e2007-05-02 19:27:13 +020047}
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
49/*
Zachary Amsden6e5882c2006-04-27 11:32:29 -070050 * For PTEs and PDEs, we must clear the P-bit first when clearing a page table
51 * entry, so clear the bottom half first and enforce ordering with a compiler
52 * barrier.
53 */
Joe Perches4b01fef2008-03-23 01:03:10 -070054static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr,
55 pte_t *ptep)
Zachary Amsden6e5882c2006-04-27 11:32:29 -070056{
57 ptep->pte_low = 0;
58 smp_wmb();
59 ptep->pte_high = 0;
60}
61
Jeremy Fitzhardinge3dc494e2007-05-02 19:27:13 +020062static inline void native_pmd_clear(pmd_t *pmd)
Zachary Amsden6e5882c2006-04-27 11:32:29 -070063{
64 u32 *tmp = (u32 *)pmd;
65 *tmp = 0;
66 smp_wmb();
67 *(tmp + 1) = 0;
68}
Jeremy Fitzhardinge3dc494e2007-05-02 19:27:13 +020069
Jeremy Fitzhardinge6194ba62008-01-30 13:34:11 +010070static inline void pud_clear(pud_t *pudp)
71{
Jeremy Fitzhardingeedd6bcd2008-02-04 16:48:02 +010072 unsigned long pgd;
73
Jeremy Fitzhardinge6194ba62008-01-30 13:34:11 +010074 set_pud(pudp, __pud(0));
75
76 /*
Jeremy Fitzhardingef5430f92008-02-04 16:48:02 +010077 * According to Intel App note "TLBs, Paging-Structure Caches,
78 * and Their Invalidation", April 2007, document 317080-001,
79 * section 8.1: in PAE mode we explicitly have to flush the
80 * TLB via cr3 if the top-level pgd is changed...
Jeremy Fitzhardinge6194ba62008-01-30 13:34:11 +010081 *
Jeremy Fitzhardingeedd6bcd2008-02-04 16:48:02 +010082 * Make sure the pud entry we're updating is within the
83 * current pgd to avoid unnecessary TLB flushes.
Jeremy Fitzhardinge6194ba62008-01-30 13:34:11 +010084 */
Jeremy Fitzhardingeedd6bcd2008-02-04 16:48:02 +010085 pgd = read_cr3();
Joe Perches4b01fef2008-03-23 01:03:10 -070086 if (__pa(pudp) >= pgd && __pa(pudp) <
87 (pgd + sizeof(pgd_t)*PTRS_PER_PGD))
Jeremy Fitzhardingeedd6bcd2008-02-04 16:48:02 +010088 write_cr3(pgd);
Jeremy Fitzhardinge6194ba62008-01-30 13:34:11 +010089}
Rusty Russellda181a82006-12-07 02:14:08 +010090
Zachary Amsden142dd972007-05-02 19:27:19 +020091#ifdef CONFIG_SMP
Jeremy Fitzhardinge3dc494e2007-05-02 19:27:13 +020092static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
Linus Torvalds1da177e2005-04-16 15:20:36 -070093{
94 pte_t res;
95
96 /* xchg acts as a barrier before the setting of the high bits */
97 res.pte_low = xchg(&ptep->pte_low, 0);
98 res.pte_high = ptep->pte_high;
99 ptep->pte_high = 0;
100
101 return res;
102}
Zachary Amsden142dd972007-05-02 19:27:19 +0200103#else
104#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
105#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106
Johannes Weinerf2d6bfe2011-01-13 15:47:01 -0800107#ifdef CONFIG_SMP
108union split_pmd {
109 struct {
110 u32 pmd_low;
111 u32 pmd_high;
112 };
113 pmd_t pmd;
114};
115static inline pmd_t native_pmdp_get_and_clear(pmd_t *pmdp)
116{
117 union split_pmd res, *orig = (union split_pmd *)pmdp;
118
119 /* xchg acts as a barrier before setting of the high bits */
120 res.pmd_low = xchg(&orig->pmd_low, 0);
121 res.pmd_high = orig->pmd_high;
122 orig->pmd_high = 0;
123
124 return res.pmd;
125}
126#else
127#define native_pmdp_get_and_clear(xp) native_local_pmdp_get_and_clear(xp)
128#endif
129
Linus Torvalds1da177e2005-04-16 15:20:36 -0700130/*
131 * Bits 0, 6 and 7 are taken in the low part of the pte,
132 * put the 32 bits of offset into the high part.
133 */
134#define pte_to_pgoff(pte) ((pte).pte_high)
Joe Perches4b01fef2008-03-23 01:03:10 -0700135#define pgoff_to_pte(off) \
136 ((pte_t) { { .pte_low = _PAGE_FILE, .pte_high = (off) } })
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137#define PTE_FILE_MAX_BITS 32
138
139/* Encode and de-code a swap entry */
Jan Beulich17963162008-12-16 11:35:24 +0000140#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > 5)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141#define __swp_type(x) (((x).val) & 0x1f)
142#define __swp_offset(x) ((x).val >> 5)
143#define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5})
144#define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
Jeremy Fitzhardingec8e53932008-01-30 13:32:57 +0100145#define __swp_entry_to_pte(x) ((pte_t){ { .pte_high = (x).val } })
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146
H. Peter Anvin1965aae2008-10-22 22:26:29 -0700147#endif /* _ASM_X86_PGTABLE_3LEVEL_H */