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gerrit-public.fairphone.software / kernel / msm-4.9 / 4ad9bb85bd143599e76c5d86a8817e50ec96b727 / . / arch / x86 / include / asm / hpet.h
blob: cc285ec4b2c1e94906901b3462d9655b4df28cf1 [file] [log] [blame]
H. Peter Anvin1965aae2008-10-22 22:26:29 -0700[diff] [blame]1#ifndef _ASM_X86_HPET_H
2#define _ASM_X86_HPET_H
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +0200[diff] [blame]3
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -0700[diff] [blame]4#include <linux/msi.h>
5
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +0200[diff] [blame]6#ifdef CONFIG_HPET_TIMER
7
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +0200[diff] [blame]8#define HPET_MMAP_SIZE 1024
9
10#define HPET_ID 0x000
11#define HPET_PERIOD 0x004
12#define HPET_CFG 0x010
13#define HPET_STATUS 0x020
14#define HPET_COUNTER 0x0f0
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -0700[diff] [blame]15
16#define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
17#define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
18#define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
19
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +0200[diff] [blame]20#define HPET_T0_CFG 0x100
21#define HPET_T0_CMP 0x108
22#define HPET_T0_ROUTE 0x110
23#define HPET_T1_CFG 0x120
24#define HPET_T1_CMP 0x128
25#define HPET_T1_ROUTE 0x130
26#define HPET_T2_CFG 0x140
27#define HPET_T2_CMP 0x148
28#define HPET_T2_ROUTE 0x150
29
30#define HPET_ID_REV 0x000000ff
31#define HPET_ID_NUMBER 0x00001f00
32#define HPET_ID_64BIT 0x00002000
33#define HPET_ID_LEGSUP 0x00008000
34#define HPET_ID_VENDOR 0xffff0000
35#define HPET_ID_NUMBER_SHIFT 8
36#define HPET_ID_VENDOR_SHIFT 16
37
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +0200[diff] [blame]38#define HPET_CFG_ENABLE 0x001
39#define HPET_CFG_LEGACY 0x002
40#define HPET_LEGACY_8254 2
41#define HPET_LEGACY_RTC 8
42
43#define HPET_TN_LEVEL 0x0002
44#define HPET_TN_ENABLE 0x0004
45#define HPET_TN_PERIODIC 0x0008
46#define HPET_TN_PERIODIC_CAP 0x0010
47#define HPET_TN_64BIT_CAP 0x0020
48#define HPET_TN_SETVAL 0x0040
49#define HPET_TN_32BIT 0x0100
50#define HPET_TN_ROUTE 0x3e00
51#define HPET_TN_FSB 0x4000
52#define HPET_TN_FSB_CAP 0x8000
53#define HPET_TN_ROUTE_SHIFT 9
54
55/* Max HPET Period is 10^8 femto sec as in HPET spec */
56#define HPET_MAX_PERIOD 100000000UL
57/*
58 * Min HPET period is 10^5 femto sec just for safety. If it is less than this,
59 * then 32 bit HPET counter wrapsaround in less than 0.5 sec.
60 */
61#define HPET_MIN_PERIOD 100000UL
62
63/* hpet memory map physical address */
64extern unsigned long hpet_address;
Venki Pallipadi59c69f22007-10-12 23:04:23 +0200[diff] [blame]65extern unsigned long force_hpet_address;
Jan Beulich3d45ac42015-10-19 04:35:44 -0600[diff] [blame]66extern bool boot_hpet_disable;
Suresh Siddhac8bc6f32009-08-04 12:07:09 -0700[diff] [blame]67extern u8 hpet_blockid;
Jan Beulich3d45ac42015-10-19 04:35:44 -0600[diff] [blame]68extern bool hpet_force_user;
69extern bool hpet_msi_disable;
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +0200[diff] [blame]70extern int is_hpet_enabled(void);
71extern int hpet_enable(void);
OGAWA Hirofumic86c7fb2007-12-03 17:17:10 +0100[diff] [blame]72extern void hpet_disable(void);
Jan Beulich5946fa32009-08-19 08:44:24 +0100[diff] [blame]73extern unsigned int hpet_readl(unsigned int a);
Venki Pallipadibfe0c1c2007-10-12 23:04:24 +0200[diff] [blame]74extern void force_hpet_resume(void);
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +0200[diff] [blame]75
Thomas Gleixnerd0fbca82010-09-28 16:18:39 +0200[diff] [blame]76struct irq_data;
Jiang Liu3cb96f02015-04-13 14:11:34 +0800[diff] [blame]77struct hpet_dev;
78struct irq_domain;
79
Thomas Gleixnerd0fbca82010-09-28 16:18:39 +0200[diff] [blame]80extern void hpet_msi_unmask(struct irq_data *data);
81extern void hpet_msi_mask(struct irq_data *data);
Thomas Gleixnerd0fbca82010-09-28 16:18:39 +0200[diff] [blame]82extern void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg);
83extern void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg);
Jiang Liu3cb96f02015-04-13 14:11:34 +0800[diff] [blame]84extern struct irq_domain *hpet_create_irq_domain(int hpet_id);
85extern int hpet_assign_irq(struct irq_domain *domain,
86 struct hpet_dev *dev, int dev_num);
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -0700[diff] [blame]87
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +0200[diff] [blame]88#ifdef CONFIG_HPET_EMULATE_RTC
89
90#include <linux/interrupt.h>
91
Bernhard Walle1bdbdaa2008-01-30 13:33:28 +0100[diff] [blame]92typedef irqreturn_t (*rtc_irq_handler)(int interrupt, void *cookie);
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +0200[diff] [blame]93extern int hpet_mask_rtc_irq_bit(unsigned long bit_mask);
94extern int hpet_set_rtc_irq_bit(unsigned long bit_mask);
95extern int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
96 unsigned char sec);
97extern int hpet_set_periodic_freq(unsigned long freq);
98extern int hpet_rtc_dropped_irq(void);
99extern int hpet_rtc_timer_init(void);
100extern irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id);
Bernhard Walle1bdbdaa2008-01-30 13:33:28 +0100[diff] [blame]101extern int hpet_register_irq_handler(rtc_irq_handler handler);
102extern void hpet_unregister_irq_handler(rtc_irq_handler handler);
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +0200[diff] [blame]103
104#endif /* CONFIG_HPET_EMULATE_RTC */
105
Ingo Molnardf619e62008-01-30 13:30:02 +0100[diff] [blame]106#else /* CONFIG_HPET_TIMER */
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +0200[diff] [blame]107
108static inline int hpet_enable(void) { return 0; }
Ingo Molnardf619e62008-01-30 13:30:02 +0100[diff] [blame]109static inline int is_hpet_enabled(void) { return 0; }
Alok Katariabfc0f592008-07-01 11:43:24 -0700[diff] [blame]110#define hpet_readl(a) 0
Joerg Roedel71054d82012-09-26 12:44:37 +0200[diff] [blame]111#define default_setup_hpet_msi NULL
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +0200[diff] [blame]112
Ingo Molnardf619e62008-01-30 13:30:02 +0100[diff] [blame]113#endif
H. Peter Anvin1965aae2008-10-22 22:26:29 -0700[diff] [blame]114#endif /* _ASM_X86_HPET_H */