Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | * |
| 3 | * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver |
Jesse Brandeburg | b831607 | 2014-04-05 07:46:11 +0000 | [diff] [blame] | 4 | * Copyright(c) 2013 - 2014 Intel Corporation. |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
Jesse Brandeburg | b831607 | 2014-04-05 07:46:11 +0000 | [diff] [blame] | 15 | * You should have received a copy of the GNU General Public License along |
| 16 | * with this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | * |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 18 | * The full GNU General Public License is included in this distribution in |
| 19 | * the file called "COPYING". |
| 20 | * |
| 21 | * Contact Information: |
| 22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 24 | * |
| 25 | ******************************************************************************/ |
| 26 | |
| 27 | #ifndef _I40E_ADMINQ_CMD_H_ |
| 28 | #define _I40E_ADMINQ_CMD_H_ |
| 29 | |
| 30 | /* This header file defines the i40e Admin Queue commands and is shared between |
| 31 | * i40e Firmware and Software. |
| 32 | * |
| 33 | * This file needs to comply with the Linux Kernel coding style. |
| 34 | */ |
| 35 | |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 36 | #define I40E_FW_API_VERSION_MAJOR 0x0001 |
Greg Rose | cb2f65b | 2015-04-27 14:57:12 -0400 | [diff] [blame] | 37 | #define I40E_FW_API_VERSION_MINOR 0x0004 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 38 | |
| 39 | struct i40e_aq_desc { |
| 40 | __le16 flags; |
| 41 | __le16 opcode; |
| 42 | __le16 datalen; |
| 43 | __le16 retval; |
| 44 | __le32 cookie_high; |
| 45 | __le32 cookie_low; |
| 46 | union { |
| 47 | struct { |
| 48 | __le32 param0; |
| 49 | __le32 param1; |
| 50 | __le32 param2; |
| 51 | __le32 param3; |
| 52 | } internal; |
| 53 | struct { |
| 54 | __le32 param0; |
| 55 | __le32 param1; |
| 56 | __le32 addr_high; |
| 57 | __le32 addr_low; |
| 58 | } external; |
| 59 | u8 raw[16]; |
| 60 | } params; |
| 61 | }; |
| 62 | |
| 63 | /* Flags sub-structure |
| 64 | * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | |
| 65 | * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | |
| 66 | */ |
| 67 | |
| 68 | /* command flags and offsets*/ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 69 | #define I40E_AQ_FLAG_DD_SHIFT 0 |
| 70 | #define I40E_AQ_FLAG_CMP_SHIFT 1 |
| 71 | #define I40E_AQ_FLAG_ERR_SHIFT 2 |
| 72 | #define I40E_AQ_FLAG_VFE_SHIFT 3 |
| 73 | #define I40E_AQ_FLAG_LB_SHIFT 9 |
| 74 | #define I40E_AQ_FLAG_RD_SHIFT 10 |
| 75 | #define I40E_AQ_FLAG_VFC_SHIFT 11 |
| 76 | #define I40E_AQ_FLAG_BUF_SHIFT 12 |
| 77 | #define I40E_AQ_FLAG_SI_SHIFT 13 |
| 78 | #define I40E_AQ_FLAG_EI_SHIFT 14 |
| 79 | #define I40E_AQ_FLAG_FE_SHIFT 15 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 80 | |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 81 | #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ |
| 82 | #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ |
| 83 | #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ |
| 84 | #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ |
| 85 | #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ |
| 86 | #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ |
| 87 | #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ |
| 88 | #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ |
| 89 | #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ |
| 90 | #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ |
| 91 | #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 92 | |
| 93 | /* error codes */ |
| 94 | enum i40e_admin_queue_err { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 95 | I40E_AQ_RC_OK = 0, /* success */ |
| 96 | I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ |
| 97 | I40E_AQ_RC_ENOENT = 2, /* No such element */ |
| 98 | I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ |
| 99 | I40E_AQ_RC_EINTR = 4, /* operation interrupted */ |
| 100 | I40E_AQ_RC_EIO = 5, /* I/O error */ |
| 101 | I40E_AQ_RC_ENXIO = 6, /* No such resource */ |
| 102 | I40E_AQ_RC_E2BIG = 7, /* Arg too long */ |
| 103 | I40E_AQ_RC_EAGAIN = 8, /* Try again */ |
| 104 | I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ |
| 105 | I40E_AQ_RC_EACCES = 10, /* Permission denied */ |
| 106 | I40E_AQ_RC_EFAULT = 11, /* Bad address */ |
| 107 | I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ |
| 108 | I40E_AQ_RC_EEXIST = 13, /* object already exists */ |
| 109 | I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ |
| 110 | I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ |
| 111 | I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ |
| 112 | I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ |
| 113 | I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ |
| 114 | I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ |
| 115 | I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ |
| 116 | I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ |
| 117 | I40E_AQ_RC_EFBIG = 22, /* File too large */ |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 118 | }; |
| 119 | |
| 120 | /* Admin Queue command opcodes */ |
| 121 | enum i40e_admin_queue_opc { |
| 122 | /* aq commands */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 123 | i40e_aqc_opc_get_version = 0x0001, |
| 124 | i40e_aqc_opc_driver_version = 0x0002, |
| 125 | i40e_aqc_opc_queue_shutdown = 0x0003, |
| 126 | i40e_aqc_opc_set_pf_context = 0x0004, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 127 | |
| 128 | /* resource ownership */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 129 | i40e_aqc_opc_request_resource = 0x0008, |
| 130 | i40e_aqc_opc_release_resource = 0x0009, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 131 | |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 132 | i40e_aqc_opc_list_func_capabilities = 0x000A, |
| 133 | i40e_aqc_opc_list_dev_capabilities = 0x000B, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 134 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 135 | /* LAA */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 136 | i40e_aqc_opc_mac_address_read = 0x0107, |
| 137 | i40e_aqc_opc_mac_address_write = 0x0108, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 138 | |
| 139 | /* PXE */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 140 | i40e_aqc_opc_clear_pxe_mode = 0x0110, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 141 | |
| 142 | /* internal switch commands */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 143 | i40e_aqc_opc_get_switch_config = 0x0200, |
| 144 | i40e_aqc_opc_add_statistics = 0x0201, |
| 145 | i40e_aqc_opc_remove_statistics = 0x0202, |
| 146 | i40e_aqc_opc_set_port_parameters = 0x0203, |
| 147 | i40e_aqc_opc_get_switch_resource_alloc = 0x0204, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 148 | |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 149 | i40e_aqc_opc_add_vsi = 0x0210, |
| 150 | i40e_aqc_opc_update_vsi_parameters = 0x0211, |
| 151 | i40e_aqc_opc_get_vsi_parameters = 0x0212, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 152 | |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 153 | i40e_aqc_opc_add_pv = 0x0220, |
| 154 | i40e_aqc_opc_update_pv_parameters = 0x0221, |
| 155 | i40e_aqc_opc_get_pv_parameters = 0x0222, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 156 | |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 157 | i40e_aqc_opc_add_veb = 0x0230, |
| 158 | i40e_aqc_opc_update_veb_parameters = 0x0231, |
| 159 | i40e_aqc_opc_get_veb_parameters = 0x0232, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 160 | |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 161 | i40e_aqc_opc_delete_element = 0x0243, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 162 | |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 163 | i40e_aqc_opc_add_macvlan = 0x0250, |
| 164 | i40e_aqc_opc_remove_macvlan = 0x0251, |
| 165 | i40e_aqc_opc_add_vlan = 0x0252, |
| 166 | i40e_aqc_opc_remove_vlan = 0x0253, |
| 167 | i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, |
| 168 | i40e_aqc_opc_add_tag = 0x0255, |
| 169 | i40e_aqc_opc_remove_tag = 0x0256, |
| 170 | i40e_aqc_opc_add_multicast_etag = 0x0257, |
| 171 | i40e_aqc_opc_remove_multicast_etag = 0x0258, |
| 172 | i40e_aqc_opc_update_tag = 0x0259, |
| 173 | i40e_aqc_opc_add_control_packet_filter = 0x025A, |
| 174 | i40e_aqc_opc_remove_control_packet_filter = 0x025B, |
| 175 | i40e_aqc_opc_add_cloud_filters = 0x025C, |
| 176 | i40e_aqc_opc_remove_cloud_filters = 0x025D, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 177 | |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 178 | i40e_aqc_opc_add_mirror_rule = 0x0260, |
| 179 | i40e_aqc_opc_delete_mirror_rule = 0x0261, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 180 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 181 | /* DCB commands */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 182 | i40e_aqc_opc_dcb_ignore_pfc = 0x0301, |
| 183 | i40e_aqc_opc_dcb_updated = 0x0302, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 184 | |
| 185 | /* TX scheduler */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 186 | i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, |
| 187 | i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, |
| 188 | i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, |
| 189 | i40e_aqc_opc_query_vsi_bw_config = 0x0408, |
| 190 | i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, |
| 191 | i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 192 | |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 193 | i40e_aqc_opc_enable_switching_comp_ets = 0x0413, |
| 194 | i40e_aqc_opc_modify_switching_comp_ets = 0x0414, |
| 195 | i40e_aqc_opc_disable_switching_comp_ets = 0x0415, |
| 196 | i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, |
| 197 | i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, |
| 198 | i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, |
| 199 | i40e_aqc_opc_query_port_ets_config = 0x0419, |
| 200 | i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, |
| 201 | i40e_aqc_opc_suspend_port_tx = 0x041B, |
| 202 | i40e_aqc_opc_resume_port_tx = 0x041C, |
| 203 | i40e_aqc_opc_configure_partition_bw = 0x041D, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 204 | |
| 205 | /* hmc */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 206 | i40e_aqc_opc_query_hmc_resource_profile = 0x0500, |
| 207 | i40e_aqc_opc_set_hmc_resource_profile = 0x0501, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 208 | |
| 209 | /* phy commands*/ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 210 | i40e_aqc_opc_get_phy_abilities = 0x0600, |
| 211 | i40e_aqc_opc_set_phy_config = 0x0601, |
| 212 | i40e_aqc_opc_set_mac_config = 0x0603, |
| 213 | i40e_aqc_opc_set_link_restart_an = 0x0605, |
| 214 | i40e_aqc_opc_get_link_status = 0x0607, |
| 215 | i40e_aqc_opc_set_phy_int_mask = 0x0613, |
| 216 | i40e_aqc_opc_get_local_advt_reg = 0x0614, |
| 217 | i40e_aqc_opc_set_local_advt_reg = 0x0615, |
| 218 | i40e_aqc_opc_get_partner_advt = 0x0616, |
| 219 | i40e_aqc_opc_set_lb_modes = 0x0618, |
| 220 | i40e_aqc_opc_get_phy_wol_caps = 0x0621, |
| 221 | i40e_aqc_opc_set_phy_debug = 0x0622, |
| 222 | i40e_aqc_opc_upload_ext_phy_fm = 0x0625, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 223 | |
| 224 | /* NVM commands */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 225 | i40e_aqc_opc_nvm_read = 0x0701, |
| 226 | i40e_aqc_opc_nvm_erase = 0x0702, |
| 227 | i40e_aqc_opc_nvm_update = 0x0703, |
| 228 | i40e_aqc_opc_nvm_config_read = 0x0704, |
| 229 | i40e_aqc_opc_nvm_config_write = 0x0705, |
Michal Kosiarz | 00ada50 | 2015-11-19 11:34:20 -0800 | [diff] [blame] | 230 | i40e_aqc_opc_oem_post_update = 0x0720, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 231 | |
| 232 | /* virtualization commands */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 233 | i40e_aqc_opc_send_msg_to_pf = 0x0801, |
| 234 | i40e_aqc_opc_send_msg_to_vf = 0x0802, |
| 235 | i40e_aqc_opc_send_msg_to_peer = 0x0803, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 236 | |
| 237 | /* alternate structure */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 238 | i40e_aqc_opc_alternate_write = 0x0900, |
| 239 | i40e_aqc_opc_alternate_write_indirect = 0x0901, |
| 240 | i40e_aqc_opc_alternate_read = 0x0902, |
| 241 | i40e_aqc_opc_alternate_read_indirect = 0x0903, |
| 242 | i40e_aqc_opc_alternate_write_done = 0x0904, |
| 243 | i40e_aqc_opc_alternate_set_mode = 0x0905, |
| 244 | i40e_aqc_opc_alternate_clear_port = 0x0906, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 245 | |
| 246 | /* LLDP commands */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 247 | i40e_aqc_opc_lldp_get_mib = 0x0A00, |
| 248 | i40e_aqc_opc_lldp_update_mib = 0x0A01, |
| 249 | i40e_aqc_opc_lldp_add_tlv = 0x0A02, |
| 250 | i40e_aqc_opc_lldp_update_tlv = 0x0A03, |
| 251 | i40e_aqc_opc_lldp_delete_tlv = 0x0A04, |
| 252 | i40e_aqc_opc_lldp_stop = 0x0A05, |
| 253 | i40e_aqc_opc_lldp_start = 0x0A06, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 254 | |
| 255 | /* Tunnel commands */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 256 | i40e_aqc_opc_add_udp_tunnel = 0x0B00, |
| 257 | i40e_aqc_opc_del_udp_tunnel = 0x0B01, |
Anjali Singhai Jain | e50c8d6 | 2015-06-05 12:20:27 -0400 | [diff] [blame] | 258 | i40e_aqc_opc_set_rss_key = 0x0B02, |
| 259 | i40e_aqc_opc_set_rss_lut = 0x0B03, |
| 260 | i40e_aqc_opc_get_rss_key = 0x0B04, |
| 261 | i40e_aqc_opc_get_rss_lut = 0x0B05, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 262 | |
| 263 | /* Async Events */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 264 | i40e_aqc_opc_event_lan_overflow = 0x1001, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 265 | |
| 266 | /* OEM commands */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 267 | i40e_aqc_opc_oem_parameter_change = 0xFE00, |
| 268 | i40e_aqc_opc_oem_device_status_change = 0xFE01, |
Shannon Nelson | 672415c | 2014-12-14 01:55:13 +0000 | [diff] [blame] | 269 | i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, |
| 270 | i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 271 | |
| 272 | /* debug commands */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 273 | i40e_aqc_opc_debug_read_reg = 0xFF03, |
| 274 | i40e_aqc_opc_debug_write_reg = 0xFF04, |
| 275 | i40e_aqc_opc_debug_modify_reg = 0xFF07, |
| 276 | i40e_aqc_opc_debug_dump_internals = 0xFF08, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 277 | }; |
| 278 | |
| 279 | /* command structures and indirect data structures */ |
| 280 | |
| 281 | /* Structure naming conventions: |
| 282 | * - no suffix for direct command descriptor structures |
| 283 | * - _data for indirect sent data |
| 284 | * - _resp for indirect return data (data which is both will use _data) |
| 285 | * - _completion for direct return data |
| 286 | * - _element_ for repeated elements (may also be _data or _resp) |
| 287 | * |
| 288 | * Command structures are expected to overlay the params.raw member of the basic |
| 289 | * descriptor, and as such cannot exceed 16 bytes in length. |
| 290 | */ |
| 291 | |
| 292 | /* This macro is used to generate a compilation error if a structure |
| 293 | * is not exactly the correct length. It gives a divide by zero error if the |
| 294 | * structure is not of the correct size, otherwise it creates an enum that is |
| 295 | * never used. |
| 296 | */ |
| 297 | #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ |
| 298 | { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } |
| 299 | |
| 300 | /* This macro is used extensively to ensure that command structures are 16 |
| 301 | * bytes in length as they have to map to the raw array of that size. |
| 302 | */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 303 | #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 304 | |
| 305 | /* internal (0x00XX) commands */ |
| 306 | |
| 307 | /* Get version (direct 0x0001) */ |
| 308 | struct i40e_aqc_get_version { |
| 309 | __le32 rom_ver; |
| 310 | __le32 fw_build; |
| 311 | __le16 fw_major; |
| 312 | __le16 fw_minor; |
| 313 | __le16 api_major; |
| 314 | __le16 api_minor; |
| 315 | }; |
| 316 | |
| 317 | I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); |
| 318 | |
| 319 | /* Send driver version (indirect 0x0002) */ |
| 320 | struct i40e_aqc_driver_version { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 321 | u8 driver_major_ver; |
| 322 | u8 driver_minor_ver; |
| 323 | u8 driver_build_ver; |
| 324 | u8 driver_subbuild_ver; |
| 325 | u8 reserved[4]; |
| 326 | __le32 address_high; |
| 327 | __le32 address_low; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 328 | }; |
| 329 | |
| 330 | I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); |
| 331 | |
| 332 | /* Queue Shutdown (direct 0x0003) */ |
| 333 | struct i40e_aqc_queue_shutdown { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 334 | __le32 driver_unloading; |
| 335 | #define I40E_AQ_DRIVER_UNLOADING 0x1 |
| 336 | u8 reserved[12]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 337 | }; |
| 338 | |
| 339 | I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); |
| 340 | |
Shannon Nelson | f94234e | 2014-05-22 06:31:30 +0000 | [diff] [blame] | 341 | /* Set PF context (0x0004, direct) */ |
| 342 | struct i40e_aqc_set_pf_context { |
| 343 | u8 pf_id; |
| 344 | u8 reserved[15]; |
| 345 | }; |
| 346 | |
| 347 | I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); |
| 348 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 349 | /* Request resource ownership (direct 0x0008) |
| 350 | * Release resource ownership (direct 0x0009) |
| 351 | */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 352 | #define I40E_AQ_RESOURCE_NVM 1 |
| 353 | #define I40E_AQ_RESOURCE_SDP 2 |
| 354 | #define I40E_AQ_RESOURCE_ACCESS_READ 1 |
| 355 | #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 |
| 356 | #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 |
| 357 | #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 358 | |
| 359 | struct i40e_aqc_request_resource { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 360 | __le16 resource_id; |
| 361 | __le16 access_type; |
| 362 | __le32 timeout; |
| 363 | __le32 resource_number; |
| 364 | u8 reserved[4]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 365 | }; |
| 366 | |
| 367 | I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); |
| 368 | |
| 369 | /* Get function capabilities (indirect 0x000A) |
| 370 | * Get device capabilities (indirect 0x000B) |
| 371 | */ |
| 372 | struct i40e_aqc_list_capabilites { |
| 373 | u8 command_flags; |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 374 | #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 375 | u8 pf_index; |
| 376 | u8 reserved[2]; |
| 377 | __le32 count; |
| 378 | __le32 addr_high; |
| 379 | __le32 addr_low; |
| 380 | }; |
| 381 | |
| 382 | I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); |
| 383 | |
| 384 | struct i40e_aqc_list_capabilities_element_resp { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 385 | __le16 id; |
| 386 | u8 major_rev; |
| 387 | u8 minor_rev; |
| 388 | __le32 number; |
| 389 | __le32 logical_id; |
| 390 | __le32 phys_id; |
| 391 | u8 reserved[16]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 392 | }; |
| 393 | |
| 394 | /* list of caps */ |
| 395 | |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 396 | #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 |
| 397 | #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 |
| 398 | #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 |
| 399 | #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 |
| 400 | #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 |
| 401 | #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 |
Shannon Nelson | 4ba40bc | 2015-12-22 14:25:09 -0800 | [diff] [blame^] | 402 | #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 403 | #define I40E_AQ_CAP_ID_SRIOV 0x0012 |
| 404 | #define I40E_AQ_CAP_ID_VF 0x0013 |
| 405 | #define I40E_AQ_CAP_ID_VMDQ 0x0014 |
| 406 | #define I40E_AQ_CAP_ID_8021QBG 0x0015 |
| 407 | #define I40E_AQ_CAP_ID_8021QBR 0x0016 |
| 408 | #define I40E_AQ_CAP_ID_VSI 0x0017 |
| 409 | #define I40E_AQ_CAP_ID_DCB 0x0018 |
| 410 | #define I40E_AQ_CAP_ID_FCOE 0x0021 |
Shannon Nelson | 35155fe | 2014-12-12 07:50:07 +0000 | [diff] [blame] | 411 | #define I40E_AQ_CAP_ID_ISCSI 0x0022 |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 412 | #define I40E_AQ_CAP_ID_RSS 0x0040 |
| 413 | #define I40E_AQ_CAP_ID_RXQ 0x0041 |
| 414 | #define I40E_AQ_CAP_ID_TXQ 0x0042 |
| 415 | #define I40E_AQ_CAP_ID_MSIX 0x0043 |
| 416 | #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 |
| 417 | #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 |
| 418 | #define I40E_AQ_CAP_ID_1588 0x0046 |
| 419 | #define I40E_AQ_CAP_ID_IWARP 0x0051 |
| 420 | #define I40E_AQ_CAP_ID_LED 0x0061 |
| 421 | #define I40E_AQ_CAP_ID_SDP 0x0062 |
| 422 | #define I40E_AQ_CAP_ID_MDIO 0x0063 |
Shannon Nelson | 406e734 | 2015-12-10 11:38:49 -0800 | [diff] [blame] | 423 | #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 424 | #define I40E_AQ_CAP_ID_FLEX10 0x00F1 |
| 425 | #define I40E_AQ_CAP_ID_CEM 0x00F2 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 426 | |
| 427 | /* Set CPPM Configuration (direct 0x0103) */ |
| 428 | struct i40e_aqc_cppm_configuration { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 429 | __le16 command_flags; |
| 430 | #define I40E_AQ_CPPM_EN_LTRC 0x0800 |
| 431 | #define I40E_AQ_CPPM_EN_DMCTH 0x1000 |
| 432 | #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 |
| 433 | #define I40E_AQ_CPPM_EN_HPTC 0x4000 |
| 434 | #define I40E_AQ_CPPM_EN_DMARC 0x8000 |
| 435 | __le16 ttlx; |
| 436 | __le32 dmacr; |
| 437 | __le16 dmcth; |
| 438 | u8 hptc; |
| 439 | u8 reserved; |
| 440 | __le32 pfltrc; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 441 | }; |
| 442 | |
| 443 | I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); |
| 444 | |
| 445 | /* Set ARP Proxy command / response (indirect 0x0104) */ |
| 446 | struct i40e_aqc_arp_proxy_data { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 447 | __le16 command_flags; |
| 448 | #define I40E_AQ_ARP_INIT_IPV4 0x0008 |
| 449 | #define I40E_AQ_ARP_UNSUP_CTL 0x0010 |
| 450 | #define I40E_AQ_ARP_ENA 0x0020 |
| 451 | #define I40E_AQ_ARP_ADD_IPV4 0x0040 |
| 452 | #define I40E_AQ_ARP_DEL_IPV4 0x0080 |
| 453 | __le16 table_id; |
| 454 | __le32 pfpm_proxyfc; |
| 455 | __le32 ip_addr; |
| 456 | u8 mac_addr[6]; |
Shannon Nelson | 672415c | 2014-12-14 01:55:13 +0000 | [diff] [blame] | 457 | u8 reserved[2]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 458 | }; |
| 459 | |
Shannon Nelson | 8d5e33a | 2014-12-14 01:55:12 +0000 | [diff] [blame] | 460 | I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); |
| 461 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 462 | /* Set NS Proxy Table Entry Command (indirect 0x0105) */ |
| 463 | struct i40e_aqc_ns_proxy_data { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 464 | __le16 table_idx_mac_addr_0; |
| 465 | __le16 table_idx_mac_addr_1; |
| 466 | __le16 table_idx_ipv6_0; |
| 467 | __le16 table_idx_ipv6_1; |
| 468 | __le16 control; |
| 469 | #define I40E_AQ_NS_PROXY_ADD_0 0x0100 |
| 470 | #define I40E_AQ_NS_PROXY_DEL_0 0x0200 |
| 471 | #define I40E_AQ_NS_PROXY_ADD_1 0x0400 |
| 472 | #define I40E_AQ_NS_PROXY_DEL_1 0x0800 |
| 473 | #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 |
| 474 | #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 |
| 475 | #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 |
| 476 | #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 |
| 477 | #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 |
| 478 | #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 |
| 479 | #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 |
| 480 | u8 mac_addr_0[6]; |
| 481 | u8 mac_addr_1[6]; |
| 482 | u8 local_mac_addr[6]; |
| 483 | u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ |
| 484 | u8 ipv6_addr_1[16]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 485 | }; |
| 486 | |
Shannon Nelson | 8d5e33a | 2014-12-14 01:55:12 +0000 | [diff] [blame] | 487 | I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); |
| 488 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 489 | /* Manage LAA Command (0x0106) - obsolete */ |
| 490 | struct i40e_aqc_mng_laa { |
| 491 | __le16 command_flags; |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 492 | #define I40E_AQ_LAA_FLAG_WR 0x8000 |
| 493 | u8 reserved[2]; |
| 494 | __le32 sal; |
| 495 | __le16 sah; |
| 496 | u8 reserved2[6]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 497 | }; |
| 498 | |
Shannon Nelson | 8d5e33a | 2014-12-14 01:55:12 +0000 | [diff] [blame] | 499 | I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); |
| 500 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 501 | /* Manage MAC Address Read Command (indirect 0x0107) */ |
| 502 | struct i40e_aqc_mac_address_read { |
| 503 | __le16 command_flags; |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 504 | #define I40E_AQC_LAN_ADDR_VALID 0x10 |
| 505 | #define I40E_AQC_SAN_ADDR_VALID 0x20 |
| 506 | #define I40E_AQC_PORT_ADDR_VALID 0x40 |
| 507 | #define I40E_AQC_WOL_ADDR_VALID 0x80 |
Greg Rose | cb2f65b | 2015-04-27 14:57:12 -0400 | [diff] [blame] | 508 | #define I40E_AQC_MC_MAG_EN_VALID 0x100 |
| 509 | #define I40E_AQC_ADDR_VALID_MASK 0x1F0 |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 510 | u8 reserved[6]; |
| 511 | __le32 addr_high; |
| 512 | __le32 addr_low; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 513 | }; |
| 514 | |
| 515 | I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); |
| 516 | |
| 517 | struct i40e_aqc_mac_address_read_data { |
| 518 | u8 pf_lan_mac[6]; |
| 519 | u8 pf_san_mac[6]; |
| 520 | u8 port_mac[6]; |
| 521 | u8 pf_wol_mac[6]; |
| 522 | }; |
| 523 | |
| 524 | I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); |
| 525 | |
| 526 | /* Manage MAC Address Write Command (0x0108) */ |
| 527 | struct i40e_aqc_mac_address_write { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 528 | __le16 command_flags; |
| 529 | #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 |
| 530 | #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 |
| 531 | #define I40E_AQC_WRITE_TYPE_PORT 0x8000 |
Greg Rose | cb2f65b | 2015-04-27 14:57:12 -0400 | [diff] [blame] | 532 | #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 |
| 533 | #define I40E_AQC_WRITE_TYPE_MASK 0xC000 |
| 534 | |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 535 | __le16 mac_sah; |
| 536 | __le32 mac_sal; |
| 537 | u8 reserved[8]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 538 | }; |
| 539 | |
| 540 | I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); |
| 541 | |
| 542 | /* PXE commands (0x011x) */ |
| 543 | |
| 544 | /* Clear PXE Command and response (direct 0x0110) */ |
| 545 | struct i40e_aqc_clear_pxe { |
| 546 | u8 rx_cnt; |
| 547 | u8 reserved[15]; |
| 548 | }; |
| 549 | |
| 550 | I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); |
| 551 | |
| 552 | /* Switch configuration commands (0x02xx) */ |
| 553 | |
| 554 | /* Used by many indirect commands that only pass an seid and a buffer in the |
| 555 | * command |
| 556 | */ |
| 557 | struct i40e_aqc_switch_seid { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 558 | __le16 seid; |
| 559 | u8 reserved[6]; |
| 560 | __le32 addr_high; |
| 561 | __le32 addr_low; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 562 | }; |
| 563 | |
| 564 | I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); |
| 565 | |
| 566 | /* Get Switch Configuration command (indirect 0x0200) |
| 567 | * uses i40e_aqc_switch_seid for the descriptor |
| 568 | */ |
| 569 | struct i40e_aqc_get_switch_config_header_resp { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 570 | __le16 num_reported; |
| 571 | __le16 num_total; |
| 572 | u8 reserved[12]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 573 | }; |
| 574 | |
Shannon Nelson | 8d5e33a | 2014-12-14 01:55:12 +0000 | [diff] [blame] | 575 | I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); |
| 576 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 577 | struct i40e_aqc_switch_config_element_resp { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 578 | u8 element_type; |
| 579 | #define I40E_AQ_SW_ELEM_TYPE_MAC 1 |
| 580 | #define I40E_AQ_SW_ELEM_TYPE_PF 2 |
| 581 | #define I40E_AQ_SW_ELEM_TYPE_VF 3 |
| 582 | #define I40E_AQ_SW_ELEM_TYPE_EMP 4 |
| 583 | #define I40E_AQ_SW_ELEM_TYPE_BMC 5 |
| 584 | #define I40E_AQ_SW_ELEM_TYPE_PV 16 |
| 585 | #define I40E_AQ_SW_ELEM_TYPE_VEB 17 |
| 586 | #define I40E_AQ_SW_ELEM_TYPE_PA 18 |
| 587 | #define I40E_AQ_SW_ELEM_TYPE_VSI 19 |
| 588 | u8 revision; |
| 589 | #define I40E_AQ_SW_ELEM_REV_1 1 |
| 590 | __le16 seid; |
| 591 | __le16 uplink_seid; |
| 592 | __le16 downlink_seid; |
| 593 | u8 reserved[3]; |
| 594 | u8 connection_type; |
| 595 | #define I40E_AQ_CONN_TYPE_REGULAR 0x1 |
| 596 | #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 |
| 597 | #define I40E_AQ_CONN_TYPE_CASCADED 0x3 |
| 598 | __le16 scheduler_id; |
| 599 | __le16 element_info; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 600 | }; |
| 601 | |
Shannon Nelson | 8d5e33a | 2014-12-14 01:55:12 +0000 | [diff] [blame] | 602 | I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); |
| 603 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 604 | /* Get Switch Configuration (indirect 0x0200) |
| 605 | * an array of elements are returned in the response buffer |
| 606 | * the first in the array is the header, remainder are elements |
| 607 | */ |
| 608 | struct i40e_aqc_get_switch_config_resp { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 609 | struct i40e_aqc_get_switch_config_header_resp header; |
| 610 | struct i40e_aqc_switch_config_element_resp element[1]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 611 | }; |
| 612 | |
Shannon Nelson | 8d5e33a | 2014-12-14 01:55:12 +0000 | [diff] [blame] | 613 | I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); |
| 614 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 615 | /* Add Statistics (direct 0x0201) |
| 616 | * Remove Statistics (direct 0x0202) |
| 617 | */ |
| 618 | struct i40e_aqc_add_remove_statistics { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 619 | __le16 seid; |
| 620 | __le16 vlan; |
| 621 | __le16 stat_index; |
| 622 | u8 reserved[10]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 623 | }; |
| 624 | |
| 625 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); |
| 626 | |
| 627 | /* Set Port Parameters command (direct 0x0203) */ |
| 628 | struct i40e_aqc_set_port_parameters { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 629 | __le16 command_flags; |
| 630 | #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 |
| 631 | #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ |
| 632 | #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 |
| 633 | __le16 bad_frame_vsi; |
| 634 | __le16 default_seid; /* reserved for command */ |
| 635 | u8 reserved[10]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 636 | }; |
| 637 | |
| 638 | I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); |
| 639 | |
| 640 | /* Get Switch Resource Allocation (indirect 0x0204) */ |
| 641 | struct i40e_aqc_get_switch_resource_alloc { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 642 | u8 num_entries; /* reserved for command */ |
| 643 | u8 reserved[7]; |
| 644 | __le32 addr_high; |
| 645 | __le32 addr_low; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 646 | }; |
| 647 | |
| 648 | I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); |
| 649 | |
| 650 | /* expect an array of these structs in the response buffer */ |
| 651 | struct i40e_aqc_switch_resource_alloc_element_resp { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 652 | u8 resource_type; |
| 653 | #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 |
| 654 | #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 |
| 655 | #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 |
| 656 | #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 |
| 657 | #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 |
| 658 | #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 |
| 659 | #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 |
| 660 | #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 |
| 661 | #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 |
| 662 | #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 |
| 663 | #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA |
| 664 | #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB |
| 665 | #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC |
| 666 | #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD |
| 667 | #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF |
| 668 | #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 |
| 669 | #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 |
| 670 | #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 |
| 671 | #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 |
| 672 | u8 reserved1; |
| 673 | __le16 guaranteed; |
| 674 | __le16 total; |
| 675 | __le16 used; |
| 676 | __le16 total_unalloced; |
| 677 | u8 reserved2[6]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 678 | }; |
| 679 | |
Shannon Nelson | 8d5e33a | 2014-12-14 01:55:12 +0000 | [diff] [blame] | 680 | I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); |
| 681 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 682 | /* Add VSI (indirect 0x0210) |
| 683 | * this indirect command uses struct i40e_aqc_vsi_properties_data |
| 684 | * as the indirect buffer (128 bytes) |
| 685 | * |
| 686 | * Update VSI (indirect 0x211) |
| 687 | * uses the same data structure as Add VSI |
| 688 | * |
| 689 | * Get VSI (indirect 0x0212) |
| 690 | * uses the same completion and data structure as Add VSI |
| 691 | */ |
| 692 | struct i40e_aqc_add_get_update_vsi { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 693 | __le16 uplink_seid; |
| 694 | u8 connection_type; |
| 695 | #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 |
| 696 | #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 |
| 697 | #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 |
| 698 | u8 reserved1; |
| 699 | u8 vf_id; |
| 700 | u8 reserved2; |
| 701 | __le16 vsi_flags; |
| 702 | #define I40E_AQ_VSI_TYPE_SHIFT 0x0 |
| 703 | #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) |
| 704 | #define I40E_AQ_VSI_TYPE_VF 0x0 |
| 705 | #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 |
| 706 | #define I40E_AQ_VSI_TYPE_PF 0x2 |
| 707 | #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 |
| 708 | #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 |
| 709 | __le32 addr_high; |
| 710 | __le32 addr_low; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 711 | }; |
| 712 | |
| 713 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); |
| 714 | |
| 715 | struct i40e_aqc_add_get_update_vsi_completion { |
| 716 | __le16 seid; |
| 717 | __le16 vsi_number; |
| 718 | __le16 vsi_used; |
| 719 | __le16 vsi_free; |
| 720 | __le32 addr_high; |
| 721 | __le32 addr_low; |
| 722 | }; |
| 723 | |
| 724 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); |
| 725 | |
| 726 | struct i40e_aqc_vsi_properties_data { |
| 727 | /* first 96 byte are written by SW */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 728 | __le16 valid_sections; |
| 729 | #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 |
| 730 | #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 |
| 731 | #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 |
| 732 | #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 |
| 733 | #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 |
| 734 | #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 |
| 735 | #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 |
| 736 | #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 |
| 737 | #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 |
| 738 | #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 739 | /* switch section */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 740 | __le16 switch_id; /* 12bit id combined with flags below */ |
| 741 | #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 |
| 742 | #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) |
| 743 | #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 |
| 744 | #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 |
| 745 | #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 |
| 746 | u8 sw_reserved[2]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 747 | /* security section */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 748 | u8 sec_flags; |
| 749 | #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 |
| 750 | #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 |
| 751 | #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 |
| 752 | u8 sec_reserved; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 753 | /* VLAN section */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 754 | __le16 pvid; /* VLANS include priority bits */ |
| 755 | __le16 fcoe_pvid; |
| 756 | u8 port_vlan_flags; |
| 757 | #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 |
| 758 | #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ |
| 759 | I40E_AQ_VSI_PVLAN_MODE_SHIFT) |
| 760 | #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 |
| 761 | #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 |
| 762 | #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 |
| 763 | #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 |
| 764 | #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 |
| 765 | #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ |
| 766 | I40E_AQ_VSI_PVLAN_EMOD_SHIFT) |
| 767 | #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 |
| 768 | #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 |
| 769 | #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 |
| 770 | #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 |
| 771 | u8 pvlan_reserved[3]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 772 | /* ingress egress up sections */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 773 | __le32 ingress_table; /* bitmap, 3 bits per up */ |
| 774 | #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 |
| 775 | #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ |
| 776 | I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) |
| 777 | #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 |
| 778 | #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ |
| 779 | I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) |
| 780 | #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 |
| 781 | #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ |
| 782 | I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) |
| 783 | #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 |
| 784 | #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ |
| 785 | I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) |
| 786 | #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 |
| 787 | #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ |
| 788 | I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) |
| 789 | #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 |
| 790 | #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ |
| 791 | I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) |
| 792 | #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 |
| 793 | #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ |
| 794 | I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) |
| 795 | #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 |
| 796 | #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ |
| 797 | I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) |
| 798 | __le32 egress_table; /* same defines as for ingress table */ |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 799 | /* cascaded PV section */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 800 | __le16 cas_pv_tag; |
| 801 | u8 cas_pv_flags; |
| 802 | #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 |
| 803 | #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ |
| 804 | I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) |
| 805 | #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 |
| 806 | #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 |
| 807 | #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 |
| 808 | #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 |
| 809 | #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 |
| 810 | #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 |
| 811 | u8 cas_pv_reserved; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 812 | /* queue mapping section */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 813 | __le16 mapping_flags; |
| 814 | #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 |
| 815 | #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 |
| 816 | __le16 queue_mapping[16]; |
| 817 | #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 |
| 818 | #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) |
| 819 | __le16 tc_mapping[8]; |
| 820 | #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 |
| 821 | #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ |
| 822 | I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
| 823 | #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 |
| 824 | #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ |
| 825 | I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 826 | /* queueing option section */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 827 | u8 queueing_opt_flags; |
Anjali Singhai Jain | e50c8d6 | 2015-06-05 12:20:27 -0400 | [diff] [blame] | 828 | #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 |
| 829 | #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 830 | #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 |
| 831 | #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 |
Anjali Singhai Jain | e50c8d6 | 2015-06-05 12:20:27 -0400 | [diff] [blame] | 832 | #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 |
| 833 | #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 834 | u8 queueing_opt_reserved[3]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 835 | /* scheduler section */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 836 | u8 up_enable_bits; |
| 837 | u8 sched_reserved; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 838 | /* outer up section */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 839 | __le32 outer_up_table; /* same structure and defines as ingress tbl */ |
| 840 | u8 cmd_reserved[8]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 841 | /* last 32 bytes are written by FW */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 842 | __le16 qs_handle[8]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 843 | #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 844 | __le16 stat_counter_idx; |
| 845 | __le16 sched_id; |
| 846 | u8 resp_reserved[12]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 847 | }; |
| 848 | |
| 849 | I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); |
| 850 | |
| 851 | /* Add Port Virtualizer (direct 0x0220) |
| 852 | * also used for update PV (direct 0x0221) but only flags are used |
| 853 | * (IS_CTRL_PORT only works on add PV) |
| 854 | */ |
| 855 | struct i40e_aqc_add_update_pv { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 856 | __le16 command_flags; |
| 857 | #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 |
| 858 | #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 |
| 859 | #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 |
| 860 | #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 |
| 861 | __le16 uplink_seid; |
| 862 | __le16 connected_seid; |
| 863 | u8 reserved[10]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 864 | }; |
| 865 | |
| 866 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); |
| 867 | |
| 868 | struct i40e_aqc_add_update_pv_completion { |
| 869 | /* reserved for update; for add also encodes error if rc == ENOSPC */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 870 | __le16 pv_seid; |
| 871 | #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 |
| 872 | #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 |
| 873 | #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 |
| 874 | #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 |
| 875 | u8 reserved[14]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 876 | }; |
| 877 | |
| 878 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); |
| 879 | |
| 880 | /* Get PV Params (direct 0x0222) |
| 881 | * uses i40e_aqc_switch_seid for the descriptor |
| 882 | */ |
| 883 | |
| 884 | struct i40e_aqc_get_pv_params_completion { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 885 | __le16 seid; |
| 886 | __le16 default_stag; |
| 887 | __le16 pv_flags; /* same flags as add_pv */ |
| 888 | #define I40E_AQC_GET_PV_PV_TYPE 0x1 |
| 889 | #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 |
| 890 | #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 |
| 891 | u8 reserved[8]; |
| 892 | __le16 default_port_seid; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 893 | }; |
| 894 | |
| 895 | I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); |
| 896 | |
| 897 | /* Add VEB (direct 0x0230) */ |
| 898 | struct i40e_aqc_add_veb { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 899 | __le16 uplink_seid; |
| 900 | __le16 downlink_seid; |
| 901 | __le16 veb_flags; |
| 902 | #define I40E_AQC_ADD_VEB_FLOATING 0x1 |
| 903 | #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 |
| 904 | #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 905 | I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 906 | #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 |
| 907 | #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 |
| 908 | #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 |
| 909 | u8 enable_tcs; |
| 910 | u8 reserved[9]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 911 | }; |
| 912 | |
| 913 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); |
| 914 | |
| 915 | struct i40e_aqc_add_veb_completion { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 916 | u8 reserved[6]; |
| 917 | __le16 switch_seid; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 918 | /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 919 | __le16 veb_seid; |
| 920 | #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 |
| 921 | #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 |
| 922 | #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 |
| 923 | #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 |
| 924 | __le16 statistic_index; |
| 925 | __le16 vebs_used; |
| 926 | __le16 vebs_free; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 927 | }; |
| 928 | |
| 929 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); |
| 930 | |
| 931 | /* Get VEB Parameters (direct 0x0232) |
| 932 | * uses i40e_aqc_switch_seid for the descriptor |
| 933 | */ |
| 934 | struct i40e_aqc_get_veb_parameters_completion { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 935 | __le16 seid; |
| 936 | __le16 switch_id; |
| 937 | __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ |
| 938 | __le16 statistic_index; |
| 939 | __le16 vebs_used; |
| 940 | __le16 vebs_free; |
| 941 | u8 reserved[4]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 942 | }; |
| 943 | |
| 944 | I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); |
| 945 | |
| 946 | /* Delete Element (direct 0x0243) |
| 947 | * uses the generic i40e_aqc_switch_seid |
| 948 | */ |
| 949 | |
| 950 | /* Add MAC-VLAN (indirect 0x0250) */ |
| 951 | |
| 952 | /* used for the command for most vlan commands */ |
| 953 | struct i40e_aqc_macvlan { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 954 | __le16 num_addresses; |
| 955 | __le16 seid[3]; |
| 956 | #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 |
| 957 | #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 958 | I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 959 | #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 |
| 960 | __le32 addr_high; |
| 961 | __le32 addr_low; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 962 | }; |
| 963 | |
| 964 | I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); |
| 965 | |
| 966 | /* indirect data for command and response */ |
| 967 | struct i40e_aqc_add_macvlan_element_data { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 968 | u8 mac_addr[6]; |
| 969 | __le16 vlan_tag; |
| 970 | __le16 flags; |
| 971 | #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 |
| 972 | #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 |
| 973 | #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 |
| 974 | #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 |
| 975 | __le16 queue_number; |
| 976 | #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 |
| 977 | #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 978 | I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) |
| 979 | /* response section */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 980 | u8 match_method; |
| 981 | #define I40E_AQC_MM_PERFECT_MATCH 0x01 |
| 982 | #define I40E_AQC_MM_HASH_MATCH 0x02 |
| 983 | #define I40E_AQC_MM_ERR_NO_RES 0xFF |
| 984 | u8 reserved1[3]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 985 | }; |
| 986 | |
| 987 | struct i40e_aqc_add_remove_macvlan_completion { |
| 988 | __le16 perfect_mac_used; |
| 989 | __le16 perfect_mac_free; |
| 990 | __le16 unicast_hash_free; |
| 991 | __le16 multicast_hash_free; |
| 992 | __le32 addr_high; |
| 993 | __le32 addr_low; |
| 994 | }; |
| 995 | |
| 996 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); |
| 997 | |
| 998 | /* Remove MAC-VLAN (indirect 0x0251) |
| 999 | * uses i40e_aqc_macvlan for the descriptor |
| 1000 | * data points to an array of num_addresses of elements |
| 1001 | */ |
| 1002 | |
| 1003 | struct i40e_aqc_remove_macvlan_element_data { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1004 | u8 mac_addr[6]; |
| 1005 | __le16 vlan_tag; |
| 1006 | u8 flags; |
| 1007 | #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 |
| 1008 | #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 |
| 1009 | #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 |
| 1010 | #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 |
| 1011 | u8 reserved[3]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1012 | /* reply section */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1013 | u8 error_code; |
| 1014 | #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 |
| 1015 | #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF |
| 1016 | u8 reply_reserved[3]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1017 | }; |
| 1018 | |
| 1019 | /* Add VLAN (indirect 0x0252) |
| 1020 | * Remove VLAN (indirect 0x0253) |
| 1021 | * use the generic i40e_aqc_macvlan for the command |
| 1022 | */ |
| 1023 | struct i40e_aqc_add_remove_vlan_element_data { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1024 | __le16 vlan_tag; |
| 1025 | u8 vlan_flags; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1026 | /* flags for add VLAN */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1027 | #define I40E_AQC_ADD_VLAN_LOCAL 0x1 |
| 1028 | #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 |
| 1029 | #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) |
| 1030 | #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 |
| 1031 | #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 |
| 1032 | #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 |
| 1033 | #define I40E_AQC_VLAN_PTYPE_SHIFT 3 |
| 1034 | #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) |
| 1035 | #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 |
| 1036 | #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 |
| 1037 | #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 |
| 1038 | #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1039 | /* flags for remove VLAN */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1040 | #define I40E_AQC_REMOVE_VLAN_ALL 0x1 |
| 1041 | u8 reserved; |
| 1042 | u8 result; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1043 | /* flags for add VLAN */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1044 | #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 |
| 1045 | #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE |
| 1046 | #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1047 | /* flags for remove VLAN */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1048 | #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 |
| 1049 | #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF |
| 1050 | u8 reserved1[3]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1051 | }; |
| 1052 | |
| 1053 | struct i40e_aqc_add_remove_vlan_completion { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1054 | u8 reserved[4]; |
| 1055 | __le16 vlans_used; |
| 1056 | __le16 vlans_free; |
| 1057 | __le32 addr_high; |
| 1058 | __le32 addr_low; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1059 | }; |
| 1060 | |
| 1061 | /* Set VSI Promiscuous Modes (direct 0x0254) */ |
| 1062 | struct i40e_aqc_set_vsi_promiscuous_modes { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1063 | __le16 promiscuous_flags; |
| 1064 | __le16 valid_flags; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1065 | /* flags used for both fields above */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1066 | #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 |
| 1067 | #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 |
| 1068 | #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 |
| 1069 | #define I40E_AQC_SET_VSI_DEFAULT 0x08 |
| 1070 | #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 |
| 1071 | __le16 seid; |
| 1072 | #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF |
| 1073 | __le16 vlan_tag; |
Greg Rose | cb2f65b | 2015-04-27 14:57:12 -0400 | [diff] [blame] | 1074 | #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1075 | #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 |
| 1076 | u8 reserved[8]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1077 | }; |
| 1078 | |
| 1079 | I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); |
| 1080 | |
| 1081 | /* Add S/E-tag command (direct 0x0255) |
| 1082 | * Uses generic i40e_aqc_add_remove_tag_completion for completion |
| 1083 | */ |
| 1084 | struct i40e_aqc_add_tag { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1085 | __le16 flags; |
| 1086 | #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 |
| 1087 | __le16 seid; |
| 1088 | #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 |
| 1089 | #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1090 | I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1091 | __le16 tag; |
| 1092 | __le16 queue_number; |
| 1093 | u8 reserved[8]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1094 | }; |
| 1095 | |
| 1096 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); |
| 1097 | |
| 1098 | struct i40e_aqc_add_remove_tag_completion { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1099 | u8 reserved[12]; |
| 1100 | __le16 tags_used; |
| 1101 | __le16 tags_free; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1102 | }; |
| 1103 | |
| 1104 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); |
| 1105 | |
| 1106 | /* Remove S/E-tag command (direct 0x0256) |
| 1107 | * Uses generic i40e_aqc_add_remove_tag_completion for completion |
| 1108 | */ |
| 1109 | struct i40e_aqc_remove_tag { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1110 | __le16 seid; |
| 1111 | #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 |
| 1112 | #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1113 | I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1114 | __le16 tag; |
| 1115 | u8 reserved[12]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1116 | }; |
| 1117 | |
Shannon Nelson | 8d5e33a | 2014-12-14 01:55:12 +0000 | [diff] [blame] | 1118 | I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); |
| 1119 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1120 | /* Add multicast E-Tag (direct 0x0257) |
| 1121 | * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields |
| 1122 | * and no external data |
| 1123 | */ |
| 1124 | struct i40e_aqc_add_remove_mcast_etag { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1125 | __le16 pv_seid; |
| 1126 | __le16 etag; |
| 1127 | u8 num_unicast_etags; |
| 1128 | u8 reserved[3]; |
| 1129 | __le32 addr_high; /* address of array of 2-byte s-tags */ |
| 1130 | __le32 addr_low; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1131 | }; |
| 1132 | |
| 1133 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); |
| 1134 | |
| 1135 | struct i40e_aqc_add_remove_mcast_etag_completion { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1136 | u8 reserved[4]; |
| 1137 | __le16 mcast_etags_used; |
| 1138 | __le16 mcast_etags_free; |
| 1139 | __le32 addr_high; |
| 1140 | __le32 addr_low; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1141 | |
| 1142 | }; |
| 1143 | |
| 1144 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); |
| 1145 | |
| 1146 | /* Update S/E-Tag (direct 0x0259) */ |
| 1147 | struct i40e_aqc_update_tag { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1148 | __le16 seid; |
| 1149 | #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 |
| 1150 | #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1151 | I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1152 | __le16 old_tag; |
| 1153 | __le16 new_tag; |
| 1154 | u8 reserved[10]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1155 | }; |
| 1156 | |
| 1157 | I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); |
| 1158 | |
| 1159 | struct i40e_aqc_update_tag_completion { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1160 | u8 reserved[12]; |
| 1161 | __le16 tags_used; |
| 1162 | __le16 tags_free; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1163 | }; |
| 1164 | |
| 1165 | I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); |
| 1166 | |
| 1167 | /* Add Control Packet filter (direct 0x025A) |
| 1168 | * Remove Control Packet filter (direct 0x025B) |
| 1169 | * uses the i40e_aqc_add_oveb_cloud, |
| 1170 | * and the generic direct completion structure |
| 1171 | */ |
| 1172 | struct i40e_aqc_add_remove_control_packet_filter { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1173 | u8 mac[6]; |
| 1174 | __le16 etype; |
| 1175 | __le16 flags; |
| 1176 | #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 |
| 1177 | #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 |
| 1178 | #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 |
| 1179 | #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 |
| 1180 | #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 |
| 1181 | __le16 seid; |
| 1182 | #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 |
| 1183 | #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1184 | I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1185 | __le16 queue; |
| 1186 | u8 reserved[2]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1187 | }; |
| 1188 | |
| 1189 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); |
| 1190 | |
| 1191 | struct i40e_aqc_add_remove_control_packet_filter_completion { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1192 | __le16 mac_etype_used; |
| 1193 | __le16 etype_used; |
| 1194 | __le16 mac_etype_free; |
| 1195 | __le16 etype_free; |
| 1196 | u8 reserved[8]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1197 | }; |
| 1198 | |
| 1199 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); |
| 1200 | |
| 1201 | /* Add Cloud filters (indirect 0x025C) |
| 1202 | * Remove Cloud filters (indirect 0x025D) |
| 1203 | * uses the i40e_aqc_add_remove_cloud_filters, |
| 1204 | * and the generic indirect completion structure |
| 1205 | */ |
| 1206 | struct i40e_aqc_add_remove_cloud_filters { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1207 | u8 num_filters; |
| 1208 | u8 reserved; |
| 1209 | __le16 seid; |
| 1210 | #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 |
| 1211 | #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1212 | I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1213 | u8 reserved2[4]; |
| 1214 | __le32 addr_high; |
| 1215 | __le32 addr_low; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1216 | }; |
| 1217 | |
| 1218 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); |
| 1219 | |
| 1220 | struct i40e_aqc_add_remove_cloud_filters_element_data { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1221 | u8 outer_mac[6]; |
| 1222 | u8 inner_mac[6]; |
| 1223 | __le16 inner_vlan; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1224 | union { |
| 1225 | struct { |
| 1226 | u8 reserved[12]; |
| 1227 | u8 data[4]; |
| 1228 | } v4; |
| 1229 | struct { |
| 1230 | u8 data[16]; |
| 1231 | } v6; |
| 1232 | } ipaddr; |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1233 | __le16 flags; |
| 1234 | #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 |
Shannon Nelson | 35155fe | 2014-12-12 07:50:07 +0000 | [diff] [blame] | 1235 | #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1236 | I40E_AQC_ADD_CLOUD_FILTER_SHIFT) |
| 1237 | /* 0x0000 reserved */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1238 | #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1239 | /* 0x0002 reserved */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1240 | #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 |
| 1241 | #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1242 | /* 0x0005 reserved */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1243 | #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1244 | /* 0x0007 reserved */ |
| 1245 | /* 0x0008 reserved */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1246 | #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 |
| 1247 | #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A |
| 1248 | #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B |
| 1249 | #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1250 | |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1251 | #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 |
| 1252 | #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 |
| 1253 | #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 |
| 1254 | #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 |
| 1255 | #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1256 | |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1257 | #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 |
| 1258 | #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 |
| 1259 | #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0 |
| 1260 | #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 |
| 1261 | #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2 |
| 1262 | #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1263 | |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1264 | __le32 tenant_id; |
| 1265 | u8 reserved[4]; |
| 1266 | __le16 queue_number; |
| 1267 | #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 |
Shannon Nelson | 35155fe | 2014-12-12 07:50:07 +0000 | [diff] [blame] | 1268 | #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1269 | I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) |
| 1270 | u8 reserved2[14]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1271 | /* response section */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1272 | u8 allocation_result; |
| 1273 | #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 |
| 1274 | #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF |
| 1275 | u8 response_reserved[7]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1276 | }; |
| 1277 | |
| 1278 | struct i40e_aqc_remove_cloud_filters_completion { |
| 1279 | __le16 perfect_ovlan_used; |
| 1280 | __le16 perfect_ovlan_free; |
| 1281 | __le16 vlan_used; |
| 1282 | __le16 vlan_free; |
| 1283 | __le32 addr_high; |
| 1284 | __le32 addr_low; |
| 1285 | }; |
| 1286 | |
| 1287 | I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); |
| 1288 | |
| 1289 | /* Add Mirror Rule (indirect or direct 0x0260) |
| 1290 | * Delete Mirror Rule (indirect or direct 0x0261) |
| 1291 | * note: some rule types (4,5) do not use an external buffer. |
| 1292 | * take care to set the flags correctly. |
| 1293 | */ |
| 1294 | struct i40e_aqc_add_delete_mirror_rule { |
| 1295 | __le16 seid; |
| 1296 | __le16 rule_type; |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1297 | #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 |
| 1298 | #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1299 | I40E_AQC_MIRROR_RULE_TYPE_SHIFT) |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1300 | #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 |
| 1301 | #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 |
| 1302 | #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 |
| 1303 | #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 |
| 1304 | #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1305 | __le16 num_entries; |
| 1306 | __le16 destination; /* VSI for add, rule id for delete */ |
| 1307 | __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ |
| 1308 | __le32 addr_low; |
| 1309 | }; |
| 1310 | |
| 1311 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); |
| 1312 | |
| 1313 | struct i40e_aqc_add_delete_mirror_rule_completion { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1314 | u8 reserved[2]; |
| 1315 | __le16 rule_id; /* only used on add */ |
| 1316 | __le16 mirror_rules_used; |
| 1317 | __le16 mirror_rules_free; |
| 1318 | __le32 addr_high; |
| 1319 | __le32 addr_low; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1320 | }; |
| 1321 | |
| 1322 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); |
| 1323 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1324 | /* DCB 0x03xx*/ |
| 1325 | |
| 1326 | /* PFC Ignore (direct 0x0301) |
| 1327 | * the command and response use the same descriptor structure |
| 1328 | */ |
| 1329 | struct i40e_aqc_pfc_ignore { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1330 | u8 tc_bitmap; |
| 1331 | u8 command_flags; /* unused on response */ |
| 1332 | #define I40E_AQC_PFC_IGNORE_SET 0x80 |
| 1333 | #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 |
| 1334 | u8 reserved[14]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1335 | }; |
| 1336 | |
| 1337 | I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); |
| 1338 | |
| 1339 | /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure |
| 1340 | * with no parameters |
| 1341 | */ |
| 1342 | |
| 1343 | /* TX scheduler 0x04xx */ |
| 1344 | |
| 1345 | /* Almost all the indirect commands use |
| 1346 | * this generic struct to pass the SEID in param0 |
| 1347 | */ |
| 1348 | struct i40e_aqc_tx_sched_ind { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1349 | __le16 vsi_seid; |
| 1350 | u8 reserved[6]; |
| 1351 | __le32 addr_high; |
| 1352 | __le32 addr_low; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1353 | }; |
| 1354 | |
| 1355 | I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); |
| 1356 | |
| 1357 | /* Several commands respond with a set of queue set handles */ |
| 1358 | struct i40e_aqc_qs_handles_resp { |
| 1359 | __le16 qs_handles[8]; |
| 1360 | }; |
| 1361 | |
| 1362 | /* Configure VSI BW limits (direct 0x0400) */ |
| 1363 | struct i40e_aqc_configure_vsi_bw_limit { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1364 | __le16 vsi_seid; |
| 1365 | u8 reserved[2]; |
| 1366 | __le16 credit; |
| 1367 | u8 reserved1[2]; |
| 1368 | u8 max_credit; /* 0-3, limit = 2^max */ |
| 1369 | u8 reserved2[7]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1370 | }; |
| 1371 | |
| 1372 | I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); |
| 1373 | |
| 1374 | /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) |
| 1375 | * responds with i40e_aqc_qs_handles_resp |
| 1376 | */ |
| 1377 | struct i40e_aqc_configure_vsi_ets_sla_bw_data { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1378 | u8 tc_valid_bits; |
| 1379 | u8 reserved[15]; |
| 1380 | __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1381 | |
| 1382 | /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1383 | __le16 tc_bw_max[2]; |
| 1384 | u8 reserved1[28]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1385 | }; |
| 1386 | |
Shannon Nelson | 8d5e33a | 2014-12-14 01:55:12 +0000 | [diff] [blame] | 1387 | I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); |
| 1388 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1389 | /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) |
| 1390 | * responds with i40e_aqc_qs_handles_resp |
| 1391 | */ |
| 1392 | struct i40e_aqc_configure_vsi_tc_bw_data { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1393 | u8 tc_valid_bits; |
| 1394 | u8 reserved[3]; |
| 1395 | u8 tc_bw_credits[8]; |
| 1396 | u8 reserved1[4]; |
| 1397 | __le16 qs_handles[8]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1398 | }; |
| 1399 | |
Shannon Nelson | 8d5e33a | 2014-12-14 01:55:12 +0000 | [diff] [blame] | 1400 | I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); |
| 1401 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1402 | /* Query vsi bw configuration (indirect 0x0408) */ |
| 1403 | struct i40e_aqc_query_vsi_bw_config_resp { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1404 | u8 tc_valid_bits; |
| 1405 | u8 tc_suspended_bits; |
| 1406 | u8 reserved[14]; |
| 1407 | __le16 qs_handles[8]; |
| 1408 | u8 reserved1[4]; |
| 1409 | __le16 port_bw_limit; |
| 1410 | u8 reserved2[2]; |
| 1411 | u8 max_bw; /* 0-3, limit = 2^max */ |
| 1412 | u8 reserved3[23]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1413 | }; |
| 1414 | |
Shannon Nelson | 8d5e33a | 2014-12-14 01:55:12 +0000 | [diff] [blame] | 1415 | I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); |
| 1416 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1417 | /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ |
| 1418 | struct i40e_aqc_query_vsi_ets_sla_config_resp { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1419 | u8 tc_valid_bits; |
| 1420 | u8 reserved[3]; |
| 1421 | u8 share_credits[8]; |
| 1422 | __le16 credits[8]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1423 | |
| 1424 | /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1425 | __le16 tc_bw_max[2]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1426 | }; |
| 1427 | |
Shannon Nelson | 8d5e33a | 2014-12-14 01:55:12 +0000 | [diff] [blame] | 1428 | I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); |
| 1429 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1430 | /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ |
| 1431 | struct i40e_aqc_configure_switching_comp_bw_limit { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1432 | __le16 seid; |
| 1433 | u8 reserved[2]; |
| 1434 | __le16 credit; |
| 1435 | u8 reserved1[2]; |
| 1436 | u8 max_bw; /* 0-3, limit = 2^max */ |
| 1437 | u8 reserved2[7]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1438 | }; |
| 1439 | |
| 1440 | I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); |
| 1441 | |
| 1442 | /* Enable Physical Port ETS (indirect 0x0413) |
| 1443 | * Modify Physical Port ETS (indirect 0x0414) |
| 1444 | * Disable Physical Port ETS (indirect 0x0415) |
| 1445 | */ |
| 1446 | struct i40e_aqc_configure_switching_comp_ets_data { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1447 | u8 reserved[4]; |
| 1448 | u8 tc_valid_bits; |
| 1449 | u8 seepage; |
| 1450 | #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 |
| 1451 | u8 tc_strict_priority_flags; |
| 1452 | u8 reserved1[17]; |
| 1453 | u8 tc_bw_share_credits[8]; |
| 1454 | u8 reserved2[96]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1455 | }; |
| 1456 | |
Shannon Nelson | 8d5e33a | 2014-12-14 01:55:12 +0000 | [diff] [blame] | 1457 | I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); |
| 1458 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1459 | /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ |
| 1460 | struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1461 | u8 tc_valid_bits; |
| 1462 | u8 reserved[15]; |
| 1463 | __le16 tc_bw_credit[8]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1464 | |
| 1465 | /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1466 | __le16 tc_bw_max[2]; |
| 1467 | u8 reserved1[28]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1468 | }; |
| 1469 | |
Shannon Nelson | 8d5e33a | 2014-12-14 01:55:12 +0000 | [diff] [blame] | 1470 | I40E_CHECK_STRUCT_LEN(0x40, |
| 1471 | i40e_aqc_configure_switching_comp_ets_bw_limit_data); |
| 1472 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1473 | /* Configure Switching Component Bandwidth Allocation per Tc |
| 1474 | * (indirect 0x0417) |
| 1475 | */ |
| 1476 | struct i40e_aqc_configure_switching_comp_bw_config_data { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1477 | u8 tc_valid_bits; |
| 1478 | u8 reserved[2]; |
| 1479 | u8 absolute_credits; /* bool */ |
| 1480 | u8 tc_bw_share_credits[8]; |
| 1481 | u8 reserved1[20]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1482 | }; |
| 1483 | |
Shannon Nelson | 8d5e33a | 2014-12-14 01:55:12 +0000 | [diff] [blame] | 1484 | I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); |
| 1485 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1486 | /* Query Switching Component Configuration (indirect 0x0418) */ |
| 1487 | struct i40e_aqc_query_switching_comp_ets_config_resp { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1488 | u8 tc_valid_bits; |
| 1489 | u8 reserved[35]; |
| 1490 | __le16 port_bw_limit; |
| 1491 | u8 reserved1[2]; |
| 1492 | u8 tc_bw_max; /* 0-3, limit = 2^max */ |
| 1493 | u8 reserved2[23]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1494 | }; |
| 1495 | |
Shannon Nelson | 8d5e33a | 2014-12-14 01:55:12 +0000 | [diff] [blame] | 1496 | I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); |
| 1497 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1498 | /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ |
| 1499 | struct i40e_aqc_query_port_ets_config_resp { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1500 | u8 reserved[4]; |
| 1501 | u8 tc_valid_bits; |
| 1502 | u8 reserved1; |
| 1503 | u8 tc_strict_priority_bits; |
| 1504 | u8 reserved2; |
| 1505 | u8 tc_bw_share_credits[8]; |
| 1506 | __le16 tc_bw_limits[8]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1507 | |
| 1508 | /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1509 | __le16 tc_bw_max[2]; |
| 1510 | u8 reserved3[32]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1511 | }; |
| 1512 | |
Shannon Nelson | 8d5e33a | 2014-12-14 01:55:12 +0000 | [diff] [blame] | 1513 | I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); |
| 1514 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1515 | /* Query Switching Component Bandwidth Allocation per Traffic Type |
| 1516 | * (indirect 0x041A) |
| 1517 | */ |
| 1518 | struct i40e_aqc_query_switching_comp_bw_config_resp { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1519 | u8 tc_valid_bits; |
| 1520 | u8 reserved[2]; |
| 1521 | u8 absolute_credits_enable; /* bool */ |
| 1522 | u8 tc_bw_share_credits[8]; |
| 1523 | __le16 tc_bw_limits[8]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1524 | |
| 1525 | /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1526 | __le16 tc_bw_max[2]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1527 | }; |
| 1528 | |
Shannon Nelson | 8d5e33a | 2014-12-14 01:55:12 +0000 | [diff] [blame] | 1529 | I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); |
| 1530 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1531 | /* Suspend/resume port TX traffic |
| 1532 | * (direct 0x041B and 0x041C) uses the generic SEID struct |
| 1533 | */ |
| 1534 | |
Shannon Nelson | befc229 | 2014-03-14 07:32:23 +0000 | [diff] [blame] | 1535 | /* Configure partition BW |
| 1536 | * (indirect 0x041D) |
| 1537 | */ |
| 1538 | struct i40e_aqc_configure_partition_bw_data { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1539 | __le16 pf_valid_bits; |
| 1540 | u8 min_bw[16]; /* guaranteed bandwidth */ |
| 1541 | u8 max_bw[16]; /* bandwidth limit */ |
Shannon Nelson | befc229 | 2014-03-14 07:32:23 +0000 | [diff] [blame] | 1542 | }; |
| 1543 | |
Shannon Nelson | 8d5e33a | 2014-12-14 01:55:12 +0000 | [diff] [blame] | 1544 | I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); |
| 1545 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1546 | /* Get and set the active HMC resource profile and status. |
| 1547 | * (direct 0x0500) and (direct 0x0501) |
| 1548 | */ |
| 1549 | struct i40e_aq_get_set_hmc_resource_profile { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1550 | u8 pm_profile; |
| 1551 | u8 pe_vf_enabled; |
| 1552 | u8 reserved[14]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1553 | }; |
| 1554 | |
| 1555 | I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); |
| 1556 | |
| 1557 | enum i40e_aq_hmc_profile { |
| 1558 | /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1559 | I40E_HMC_PROFILE_DEFAULT = 1, |
| 1560 | I40E_HMC_PROFILE_FAVOR_VF = 2, |
| 1561 | I40E_HMC_PROFILE_EQUAL = 3, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1562 | }; |
| 1563 | |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1564 | #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF |
| 1565 | #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1566 | |
| 1567 | /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ |
| 1568 | |
| 1569 | /* set in param0 for get phy abilities to report qualified modules */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1570 | #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 |
| 1571 | #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1572 | |
| 1573 | enum i40e_aq_phy_type { |
| 1574 | I40E_PHY_TYPE_SGMII = 0x0, |
| 1575 | I40E_PHY_TYPE_1000BASE_KX = 0x1, |
| 1576 | I40E_PHY_TYPE_10GBASE_KX4 = 0x2, |
| 1577 | I40E_PHY_TYPE_10GBASE_KR = 0x3, |
| 1578 | I40E_PHY_TYPE_40GBASE_KR4 = 0x4, |
| 1579 | I40E_PHY_TYPE_XAUI = 0x5, |
| 1580 | I40E_PHY_TYPE_XFI = 0x6, |
| 1581 | I40E_PHY_TYPE_SFI = 0x7, |
| 1582 | I40E_PHY_TYPE_XLAUI = 0x8, |
| 1583 | I40E_PHY_TYPE_XLPPI = 0x9, |
| 1584 | I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, |
| 1585 | I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, |
Shannon Nelson | f94234e | 2014-05-22 06:31:30 +0000 | [diff] [blame] | 1586 | I40E_PHY_TYPE_10GBASE_AOC = 0xC, |
| 1587 | I40E_PHY_TYPE_40GBASE_AOC = 0xD, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1588 | I40E_PHY_TYPE_100BASE_TX = 0x11, |
| 1589 | I40E_PHY_TYPE_1000BASE_T = 0x12, |
| 1590 | I40E_PHY_TYPE_10GBASE_T = 0x13, |
| 1591 | I40E_PHY_TYPE_10GBASE_SR = 0x14, |
| 1592 | I40E_PHY_TYPE_10GBASE_LR = 0x15, |
| 1593 | I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, |
| 1594 | I40E_PHY_TYPE_10GBASE_CR1 = 0x17, |
| 1595 | I40E_PHY_TYPE_40GBASE_CR4 = 0x18, |
| 1596 | I40E_PHY_TYPE_40GBASE_SR4 = 0x19, |
| 1597 | I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, |
Shannon Nelson | f94234e | 2014-05-22 06:31:30 +0000 | [diff] [blame] | 1598 | I40E_PHY_TYPE_1000BASE_SX = 0x1B, |
| 1599 | I40E_PHY_TYPE_1000BASE_LX = 0x1C, |
| 1600 | I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, |
| 1601 | I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1602 | I40E_PHY_TYPE_MAX |
| 1603 | }; |
| 1604 | |
| 1605 | #define I40E_LINK_SPEED_100MB_SHIFT 0x1 |
| 1606 | #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 |
| 1607 | #define I40E_LINK_SPEED_10GB_SHIFT 0x3 |
| 1608 | #define I40E_LINK_SPEED_40GB_SHIFT 0x4 |
| 1609 | #define I40E_LINK_SPEED_20GB_SHIFT 0x5 |
| 1610 | |
| 1611 | enum i40e_aq_link_speed { |
| 1612 | I40E_LINK_SPEED_UNKNOWN = 0, |
| 1613 | I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), |
| 1614 | I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), |
| 1615 | I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), |
| 1616 | I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), |
| 1617 | I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) |
| 1618 | }; |
| 1619 | |
| 1620 | struct i40e_aqc_module_desc { |
| 1621 | u8 oui[3]; |
| 1622 | u8 reserved1; |
| 1623 | u8 part_number[16]; |
| 1624 | u8 revision[4]; |
| 1625 | u8 reserved2[8]; |
| 1626 | }; |
| 1627 | |
Shannon Nelson | 8d5e33a | 2014-12-14 01:55:12 +0000 | [diff] [blame] | 1628 | I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); |
| 1629 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1630 | struct i40e_aq_get_phy_abilities_resp { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1631 | __le32 phy_type; /* bitmap using the above enum for offsets */ |
| 1632 | u8 link_speed; /* bitmap using the above enum bit patterns */ |
| 1633 | u8 abilities; |
| 1634 | #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 |
| 1635 | #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 |
| 1636 | #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 |
| 1637 | #define I40E_AQ_PHY_LINK_ENABLED 0x08 |
| 1638 | #define I40E_AQ_PHY_AN_ENABLED 0x10 |
| 1639 | #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 |
| 1640 | __le16 eee_capability; |
| 1641 | #define I40E_AQ_EEE_100BASE_TX 0x0002 |
| 1642 | #define I40E_AQ_EEE_1000BASE_T 0x0004 |
| 1643 | #define I40E_AQ_EEE_10GBASE_T 0x0008 |
| 1644 | #define I40E_AQ_EEE_1000BASE_KX 0x0010 |
| 1645 | #define I40E_AQ_EEE_10GBASE_KX4 0x0020 |
| 1646 | #define I40E_AQ_EEE_10GBASE_KR 0x0040 |
| 1647 | __le32 eeer_val; |
| 1648 | u8 d3_lpan; |
| 1649 | #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 |
| 1650 | u8 reserved[3]; |
| 1651 | u8 phy_id[4]; |
| 1652 | u8 module_type[3]; |
| 1653 | u8 qualified_module_count; |
| 1654 | #define I40E_AQ_PHY_MAX_QMS 16 |
| 1655 | struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1656 | }; |
| 1657 | |
Shannon Nelson | 8d5e33a | 2014-12-14 01:55:12 +0000 | [diff] [blame] | 1658 | I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); |
| 1659 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1660 | /* Set PHY Config (direct 0x0601) */ |
| 1661 | struct i40e_aq_set_phy_config { /* same bits as above in all */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1662 | __le32 phy_type; |
| 1663 | u8 link_speed; |
| 1664 | u8 abilities; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1665 | /* bits 0-2 use the values from get_phy_abilities_resp */ |
| 1666 | #define I40E_AQ_PHY_ENABLE_LINK 0x08 |
| 1667 | #define I40E_AQ_PHY_ENABLE_AN 0x10 |
| 1668 | #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1669 | __le16 eee_capability; |
| 1670 | __le32 eeer; |
| 1671 | u8 low_power_ctrl; |
| 1672 | u8 reserved[3]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1673 | }; |
| 1674 | |
| 1675 | I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); |
| 1676 | |
| 1677 | /* Set MAC Config command data structure (direct 0x0603) */ |
| 1678 | struct i40e_aq_set_mac_config { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1679 | __le16 max_frame_size; |
| 1680 | u8 params; |
| 1681 | #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 |
| 1682 | #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 |
| 1683 | #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 |
| 1684 | #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 |
| 1685 | #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF |
| 1686 | #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 |
| 1687 | #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 |
| 1688 | #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 |
| 1689 | #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 |
| 1690 | #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 |
| 1691 | #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 |
| 1692 | #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 |
| 1693 | #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 |
| 1694 | #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 |
| 1695 | u8 tx_timer_priority; /* bitmap */ |
| 1696 | __le16 tx_timer_value; |
| 1697 | __le16 fc_refresh_threshold; |
| 1698 | u8 reserved[8]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1699 | }; |
| 1700 | |
| 1701 | I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); |
| 1702 | |
| 1703 | /* Restart Auto-Negotiation (direct 0x605) */ |
| 1704 | struct i40e_aqc_set_link_restart_an { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1705 | u8 command; |
| 1706 | #define I40E_AQ_PHY_RESTART_AN 0x02 |
| 1707 | #define I40E_AQ_PHY_LINK_ENABLE 0x04 |
| 1708 | u8 reserved[15]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1709 | }; |
| 1710 | |
| 1711 | I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); |
| 1712 | |
| 1713 | /* Get Link Status cmd & response data structure (direct 0x0607) */ |
| 1714 | struct i40e_aqc_get_link_status { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1715 | __le16 command_flags; /* only field set on command */ |
| 1716 | #define I40E_AQ_LSE_MASK 0x3 |
| 1717 | #define I40E_AQ_LSE_NOP 0x0 |
| 1718 | #define I40E_AQ_LSE_DISABLE 0x2 |
| 1719 | #define I40E_AQ_LSE_ENABLE 0x3 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1720 | /* only response uses this flag */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1721 | #define I40E_AQ_LSE_IS_ENABLED 0x1 |
| 1722 | u8 phy_type; /* i40e_aq_phy_type */ |
| 1723 | u8 link_speed; /* i40e_aq_link_speed */ |
| 1724 | u8 link_info; |
Shannon Nelson | 1d55aa9 | 2015-08-31 19:54:41 -0400 | [diff] [blame] | 1725 | #define I40E_AQ_LINK_UP 0x01 /* obsolete */ |
| 1726 | #define I40E_AQ_LINK_UP_FUNCTION 0x01 |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1727 | #define I40E_AQ_LINK_FAULT 0x02 |
| 1728 | #define I40E_AQ_LINK_FAULT_TX 0x04 |
| 1729 | #define I40E_AQ_LINK_FAULT_RX 0x08 |
| 1730 | #define I40E_AQ_LINK_FAULT_REMOTE 0x10 |
Shannon Nelson | 1d55aa9 | 2015-08-31 19:54:41 -0400 | [diff] [blame] | 1731 | #define I40E_AQ_LINK_UP_PORT 0x20 |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1732 | #define I40E_AQ_MEDIA_AVAILABLE 0x40 |
| 1733 | #define I40E_AQ_SIGNAL_DETECT 0x80 |
| 1734 | u8 an_info; |
| 1735 | #define I40E_AQ_AN_COMPLETED 0x01 |
| 1736 | #define I40E_AQ_LP_AN_ABILITY 0x02 |
| 1737 | #define I40E_AQ_PD_FAULT 0x04 |
| 1738 | #define I40E_AQ_FEC_EN 0x08 |
| 1739 | #define I40E_AQ_PHY_LOW_POWER 0x10 |
| 1740 | #define I40E_AQ_LINK_PAUSE_TX 0x20 |
| 1741 | #define I40E_AQ_LINK_PAUSE_RX 0x40 |
| 1742 | #define I40E_AQ_QUALIFIED_MODULE 0x80 |
| 1743 | u8 ext_info; |
| 1744 | #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 |
| 1745 | #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 |
| 1746 | #define I40E_AQ_LINK_TX_SHIFT 0x02 |
| 1747 | #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) |
| 1748 | #define I40E_AQ_LINK_TX_ACTIVE 0x00 |
| 1749 | #define I40E_AQ_LINK_TX_DRAINED 0x01 |
| 1750 | #define I40E_AQ_LINK_TX_FLUSHED 0x03 |
| 1751 | #define I40E_AQ_LINK_FORCED_40G 0x10 |
| 1752 | u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ |
| 1753 | __le16 max_frame_size; |
| 1754 | u8 config; |
| 1755 | #define I40E_AQ_CONFIG_CRC_ENA 0x04 |
| 1756 | #define I40E_AQ_CONFIG_PACING_MASK 0x78 |
| 1757 | u8 reserved[5]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1758 | }; |
| 1759 | |
| 1760 | I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); |
| 1761 | |
| 1762 | /* Set event mask command (direct 0x613) */ |
| 1763 | struct i40e_aqc_set_phy_int_mask { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1764 | u8 reserved[8]; |
| 1765 | __le16 event_mask; |
| 1766 | #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 |
| 1767 | #define I40E_AQ_EVENT_MEDIA_NA 0x0004 |
| 1768 | #define I40E_AQ_EVENT_LINK_FAULT 0x0008 |
| 1769 | #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 |
| 1770 | #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 |
| 1771 | #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 |
| 1772 | #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 |
| 1773 | #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 |
| 1774 | #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 |
| 1775 | u8 reserved1[6]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1776 | }; |
| 1777 | |
| 1778 | I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); |
| 1779 | |
| 1780 | /* Get Local AN advt register (direct 0x0614) |
| 1781 | * Set Local AN advt register (direct 0x0615) |
| 1782 | * Get Link Partner AN advt register (direct 0x0616) |
| 1783 | */ |
| 1784 | struct i40e_aqc_an_advt_reg { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1785 | __le32 local_an_reg0; |
| 1786 | __le16 local_an_reg1; |
| 1787 | u8 reserved[10]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1788 | }; |
| 1789 | |
| 1790 | I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); |
| 1791 | |
| 1792 | /* Set Loopback mode (0x0618) */ |
| 1793 | struct i40e_aqc_set_lb_mode { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1794 | __le16 lb_mode; |
| 1795 | #define I40E_AQ_LB_PHY_LOCAL 0x01 |
| 1796 | #define I40E_AQ_LB_PHY_REMOTE 0x02 |
| 1797 | #define I40E_AQ_LB_MAC_LOCAL 0x04 |
| 1798 | u8 reserved[14]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1799 | }; |
| 1800 | |
| 1801 | I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); |
| 1802 | |
Shannon Nelson | f94234e | 2014-05-22 06:31:30 +0000 | [diff] [blame] | 1803 | /* Set PHY Debug command (0x0622) */ |
| 1804 | struct i40e_aqc_set_phy_debug { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1805 | u8 command_flags; |
Shannon Nelson | f94234e | 2014-05-22 06:31:30 +0000 | [diff] [blame] | 1806 | #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 |
| 1807 | #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 |
| 1808 | #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ |
| 1809 | I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) |
| 1810 | #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 |
| 1811 | #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 |
| 1812 | #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 |
| 1813 | #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1814 | u8 reserved[15]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1815 | }; |
| 1816 | |
Shannon Nelson | f94234e | 2014-05-22 06:31:30 +0000 | [diff] [blame] | 1817 | I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1818 | |
| 1819 | enum i40e_aq_phy_reg_type { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1820 | I40E_AQC_PHY_REG_INTERNAL = 0x1, |
| 1821 | I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, |
| 1822 | I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1823 | }; |
| 1824 | |
| 1825 | /* NVM Read command (indirect 0x0701) |
| 1826 | * NVM Erase commands (direct 0x0702) |
| 1827 | * NVM Update commands (indirect 0x0703) |
| 1828 | */ |
| 1829 | struct i40e_aqc_nvm_update { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1830 | u8 command_flags; |
| 1831 | #define I40E_AQ_NVM_LAST_CMD 0x01 |
| 1832 | #define I40E_AQ_NVM_FLASH_ONLY 0x80 |
| 1833 | u8 module_pointer; |
| 1834 | __le16 length; |
| 1835 | __le32 offset; |
| 1836 | __le32 addr_high; |
| 1837 | __le32 addr_low; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1838 | }; |
| 1839 | |
| 1840 | I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); |
| 1841 | |
Shannon Nelson | f94234e | 2014-05-22 06:31:30 +0000 | [diff] [blame] | 1842 | /* NVM Config Read (indirect 0x0704) */ |
| 1843 | struct i40e_aqc_nvm_config_read { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1844 | __le16 cmd_flags; |
Jeff Kirsher | e910ca7 | 2015-01-16 05:02:52 -0800 | [diff] [blame] | 1845 | #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 |
| 1846 | #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 |
| 1847 | #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1848 | __le16 element_count; |
Jeff Kirsher | e910ca7 | 2015-01-16 05:02:52 -0800 | [diff] [blame] | 1849 | __le16 element_id; /* Feature/field ID */ |
| 1850 | __le16 element_id_msw; /* MSWord of field ID */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1851 | __le32 address_high; |
| 1852 | __le32 address_low; |
Shannon Nelson | f94234e | 2014-05-22 06:31:30 +0000 | [diff] [blame] | 1853 | }; |
| 1854 | |
| 1855 | I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); |
| 1856 | |
| 1857 | /* NVM Config Write (indirect 0x0705) */ |
| 1858 | struct i40e_aqc_nvm_config_write { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1859 | __le16 cmd_flags; |
| 1860 | __le16 element_count; |
| 1861 | u8 reserved[4]; |
| 1862 | __le32 address_high; |
| 1863 | __le32 address_low; |
Shannon Nelson | f94234e | 2014-05-22 06:31:30 +0000 | [diff] [blame] | 1864 | }; |
| 1865 | |
| 1866 | I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); |
| 1867 | |
Shannon Nelson | 672415c | 2014-12-14 01:55:13 +0000 | [diff] [blame] | 1868 | /* Used for 0x0704 as well as for 0x0705 commands */ |
| 1869 | #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 |
| 1870 | #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ |
| 1871 | (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) |
| 1872 | #define I40E_AQ_ANVM_FEATURE 0 |
| 1873 | #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) |
Shannon Nelson | f94234e | 2014-05-22 06:31:30 +0000 | [diff] [blame] | 1874 | struct i40e_aqc_nvm_config_data_feature { |
| 1875 | __le16 feature_id; |
Shannon Nelson | 672415c | 2014-12-14 01:55:13 +0000 | [diff] [blame] | 1876 | #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 |
| 1877 | #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 |
| 1878 | #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 |
Shannon Nelson | f94234e | 2014-05-22 06:31:30 +0000 | [diff] [blame] | 1879 | __le16 feature_options; |
| 1880 | __le16 feature_selection; |
| 1881 | }; |
| 1882 | |
Shannon Nelson | 672415c | 2014-12-14 01:55:13 +0000 | [diff] [blame] | 1883 | I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); |
| 1884 | |
Shannon Nelson | f94234e | 2014-05-22 06:31:30 +0000 | [diff] [blame] | 1885 | struct i40e_aqc_nvm_config_data_immediate_field { |
Shannon Nelson | 672415c | 2014-12-14 01:55:13 +0000 | [diff] [blame] | 1886 | __le32 field_id; |
| 1887 | __le32 field_value; |
Shannon Nelson | f94234e | 2014-05-22 06:31:30 +0000 | [diff] [blame] | 1888 | __le16 field_options; |
Shannon Nelson | 672415c | 2014-12-14 01:55:13 +0000 | [diff] [blame] | 1889 | __le16 reserved; |
Shannon Nelson | f94234e | 2014-05-22 06:31:30 +0000 | [diff] [blame] | 1890 | }; |
| 1891 | |
Shannon Nelson | 672415c | 2014-12-14 01:55:13 +0000 | [diff] [blame] | 1892 | I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); |
| 1893 | |
Michal Kosiarz | 00ada50 | 2015-11-19 11:34:20 -0800 | [diff] [blame] | 1894 | /* OEM Post Update (indirect 0x0720) |
| 1895 | * no command data struct used |
| 1896 | */ |
| 1897 | struct i40e_aqc_nvm_oem_post_update { |
| 1898 | #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 |
| 1899 | u8 sel_data; |
| 1900 | u8 reserved[7]; |
| 1901 | }; |
| 1902 | |
| 1903 | I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); |
| 1904 | |
| 1905 | struct i40e_aqc_nvm_oem_post_update_buffer { |
| 1906 | u8 str_len; |
| 1907 | u8 dev_addr; |
| 1908 | __le16 eeprom_addr; |
| 1909 | u8 data[36]; |
| 1910 | }; |
| 1911 | |
| 1912 | I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); |
| 1913 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1914 | /* Send to PF command (indirect 0x0801) id is only used by PF |
| 1915 | * Send to VF command (indirect 0x0802) id is only used by PF |
| 1916 | * Send to Peer PF command (indirect 0x0803) |
| 1917 | */ |
| 1918 | struct i40e_aqc_pf_vf_message { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1919 | __le32 id; |
| 1920 | u8 reserved[4]; |
| 1921 | __le32 addr_high; |
| 1922 | __le32 addr_low; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1923 | }; |
| 1924 | |
| 1925 | I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); |
| 1926 | |
| 1927 | /* Alternate structure */ |
| 1928 | |
| 1929 | /* Direct write (direct 0x0900) |
| 1930 | * Direct read (direct 0x0902) |
| 1931 | */ |
| 1932 | struct i40e_aqc_alternate_write { |
| 1933 | __le32 address0; |
| 1934 | __le32 data0; |
| 1935 | __le32 address1; |
| 1936 | __le32 data1; |
| 1937 | }; |
| 1938 | |
| 1939 | I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); |
| 1940 | |
| 1941 | /* Indirect write (indirect 0x0901) |
| 1942 | * Indirect read (indirect 0x0903) |
| 1943 | */ |
| 1944 | |
| 1945 | struct i40e_aqc_alternate_ind_write { |
| 1946 | __le32 address; |
| 1947 | __le32 length; |
| 1948 | __le32 addr_high; |
| 1949 | __le32 addr_low; |
| 1950 | }; |
| 1951 | |
| 1952 | I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); |
| 1953 | |
| 1954 | /* Done alternate write (direct 0x0904) |
| 1955 | * uses i40e_aq_desc |
| 1956 | */ |
| 1957 | struct i40e_aqc_alternate_write_done { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1958 | __le16 cmd_flags; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1959 | #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 |
| 1960 | #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 |
| 1961 | #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 |
| 1962 | #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1963 | u8 reserved[14]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1964 | }; |
| 1965 | |
| 1966 | I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); |
| 1967 | |
| 1968 | /* Set OEM mode (direct 0x0905) */ |
| 1969 | struct i40e_aqc_alternate_set_mode { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1970 | __le32 mode; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1971 | #define I40E_AQ_ALTERNATE_MODE_NONE 0 |
| 1972 | #define I40E_AQ_ALTERNATE_MODE_OEM 1 |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1973 | u8 reserved[12]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1974 | }; |
| 1975 | |
| 1976 | I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); |
| 1977 | |
| 1978 | /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ |
| 1979 | |
| 1980 | /* async events 0x10xx */ |
| 1981 | |
| 1982 | /* Lan Queue Overflow Event (direct, 0x1001) */ |
| 1983 | struct i40e_aqc_lan_overflow { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1984 | __le32 prtdcb_rupto; |
| 1985 | __le32 otx_ctl; |
| 1986 | u8 reserved[8]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1987 | }; |
| 1988 | |
| 1989 | I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); |
| 1990 | |
| 1991 | /* Get LLDP MIB (indirect 0x0A00) */ |
| 1992 | struct i40e_aqc_lldp_get_mib { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 1993 | u8 type; |
| 1994 | u8 reserved1; |
| 1995 | #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 |
| 1996 | #define I40E_AQ_LLDP_MIB_LOCAL 0x0 |
| 1997 | #define I40E_AQ_LLDP_MIB_REMOTE 0x1 |
| 1998 | #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 |
| 1999 | #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC |
| 2000 | #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 |
| 2001 | #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 |
| 2002 | #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 |
| 2003 | #define I40E_AQ_LLDP_TX_SHIFT 0x4 |
| 2004 | #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 2005 | /* TX pause flags use I40E_AQ_LINK_TX_* above */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 2006 | __le16 local_len; |
| 2007 | __le16 remote_len; |
| 2008 | u8 reserved2[2]; |
| 2009 | __le32 addr_high; |
| 2010 | __le32 addr_low; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 2011 | }; |
| 2012 | |
| 2013 | I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); |
| 2014 | |
| 2015 | /* Configure LLDP MIB Change Event (direct 0x0A01) |
| 2016 | * also used for the event (with type in the command field) |
| 2017 | */ |
| 2018 | struct i40e_aqc_lldp_update_mib { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 2019 | u8 command; |
| 2020 | #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 |
| 2021 | #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 |
| 2022 | u8 reserved[7]; |
| 2023 | __le32 addr_high; |
| 2024 | __le32 addr_low; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 2025 | }; |
| 2026 | |
| 2027 | I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); |
| 2028 | |
| 2029 | /* Add LLDP TLV (indirect 0x0A02) |
| 2030 | * Delete LLDP TLV (indirect 0x0A04) |
| 2031 | */ |
| 2032 | struct i40e_aqc_lldp_add_tlv { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 2033 | u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ |
| 2034 | u8 reserved1[1]; |
| 2035 | __le16 len; |
| 2036 | u8 reserved2[4]; |
| 2037 | __le32 addr_high; |
| 2038 | __le32 addr_low; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 2039 | }; |
| 2040 | |
| 2041 | I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); |
| 2042 | |
| 2043 | /* Update LLDP TLV (indirect 0x0A03) */ |
| 2044 | struct i40e_aqc_lldp_update_tlv { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 2045 | u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ |
| 2046 | u8 reserved; |
| 2047 | __le16 old_len; |
| 2048 | __le16 new_offset; |
| 2049 | __le16 new_len; |
| 2050 | __le32 addr_high; |
| 2051 | __le32 addr_low; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 2052 | }; |
| 2053 | |
| 2054 | I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); |
| 2055 | |
| 2056 | /* Stop LLDP (direct 0x0A05) */ |
| 2057 | struct i40e_aqc_lldp_stop { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 2058 | u8 command; |
| 2059 | #define I40E_AQ_LLDP_AGENT_STOP 0x0 |
| 2060 | #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 |
| 2061 | u8 reserved[15]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 2062 | }; |
| 2063 | |
| 2064 | I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); |
| 2065 | |
| 2066 | /* Start LLDP (direct 0x0A06) */ |
| 2067 | |
| 2068 | struct i40e_aqc_lldp_start { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 2069 | u8 command; |
| 2070 | #define I40E_AQ_LLDP_AGENT_START 0x1 |
| 2071 | u8 reserved[15]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 2072 | }; |
| 2073 | |
| 2074 | I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); |
| 2075 | |
| 2076 | /* Apply MIB changes (0x0A07) |
| 2077 | * uses the generic struc as it contains no data |
| 2078 | */ |
| 2079 | |
| 2080 | /* Add Udp Tunnel command and completion (direct 0x0B00) */ |
| 2081 | struct i40e_aqc_add_udp_tunnel { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 2082 | __le16 udp_port; |
| 2083 | u8 reserved0[3]; |
| 2084 | u8 protocol_type; |
Shannon Nelson | 9774dd8 | 2014-04-04 04:43:03 +0000 | [diff] [blame] | 2085 | #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 |
| 2086 | #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 |
| 2087 | #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 2088 | u8 reserved1[10]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 2089 | }; |
| 2090 | |
| 2091 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); |
| 2092 | |
| 2093 | struct i40e_aqc_add_udp_tunnel_completion { |
| 2094 | __le16 udp_port; |
| 2095 | u8 filter_entry_index; |
| 2096 | u8 multiple_pfs; |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 2097 | #define I40E_AQC_SINGLE_PF 0x0 |
| 2098 | #define I40E_AQC_MULTIPLE_PFS 0x1 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 2099 | u8 total_filters; |
| 2100 | u8 reserved[11]; |
| 2101 | }; |
| 2102 | |
| 2103 | I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); |
| 2104 | |
| 2105 | /* remove UDP Tunnel command (0x0B01) */ |
| 2106 | struct i40e_aqc_remove_udp_tunnel { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 2107 | u8 reserved[2]; |
| 2108 | u8 index; /* 0 to 15 */ |
| 2109 | u8 reserved2[13]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 2110 | }; |
| 2111 | |
| 2112 | I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); |
| 2113 | |
| 2114 | struct i40e_aqc_del_udp_tunnel_completion { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 2115 | __le16 udp_port; |
| 2116 | u8 index; /* 0 to 15 */ |
| 2117 | u8 multiple_pfs; |
| 2118 | u8 total_filters_used; |
| 2119 | u8 reserved1[11]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 2120 | }; |
| 2121 | |
| 2122 | I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); |
| 2123 | |
Anjali Singhai Jain | e50c8d6 | 2015-06-05 12:20:27 -0400 | [diff] [blame] | 2124 | struct i40e_aqc_get_set_rss_key { |
| 2125 | #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) |
| 2126 | #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 |
| 2127 | #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ |
| 2128 | I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) |
| 2129 | __le16 vsi_id; |
| 2130 | u8 reserved[6]; |
| 2131 | __le32 addr_high; |
| 2132 | __le32 addr_low; |
| 2133 | }; |
| 2134 | |
| 2135 | I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); |
| 2136 | |
| 2137 | struct i40e_aqc_get_set_rss_key_data { |
| 2138 | u8 standard_rss_key[0x28]; |
| 2139 | u8 extended_hash_key[0xc]; |
| 2140 | }; |
| 2141 | |
| 2142 | I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); |
| 2143 | |
| 2144 | struct i40e_aqc_get_set_rss_lut { |
| 2145 | #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) |
| 2146 | #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 |
| 2147 | #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ |
| 2148 | I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) |
| 2149 | __le16 vsi_id; |
| 2150 | #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 |
| 2151 | #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ |
| 2152 | I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) |
| 2153 | |
| 2154 | #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 |
| 2155 | #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 |
| 2156 | __le16 flags; |
| 2157 | u8 reserved[4]; |
| 2158 | __le32 addr_high; |
| 2159 | __le32 addr_low; |
| 2160 | }; |
| 2161 | |
| 2162 | I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); |
| 2163 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 2164 | /* tunnel key structure 0x0B10 */ |
| 2165 | |
Greg Rose | 90327e7 | 2013-12-21 06:13:21 +0000 | [diff] [blame] | 2166 | struct i40e_aqc_tunnel_key_structure_A0 { |
| 2167 | __le16 key1_off; |
| 2168 | __le16 key1_len; |
| 2169 | __le16 key2_off; |
| 2170 | __le16 key2_len; |
| 2171 | __le16 flags; |
| 2172 | #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 |
| 2173 | /* response flags */ |
| 2174 | #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 |
| 2175 | #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 |
| 2176 | #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 |
| 2177 | u8 resreved[6]; |
| 2178 | }; |
| 2179 | |
| 2180 | I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0); |
| 2181 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 2182 | struct i40e_aqc_tunnel_key_structure { |
| 2183 | u8 key1_off; |
| 2184 | u8 key2_off; |
| 2185 | u8 key1_len; /* 0 to 15 */ |
| 2186 | u8 key2_len; /* 0 to 15 */ |
| 2187 | u8 flags; |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 2188 | #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 2189 | /* response flags */ |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 2190 | #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 |
| 2191 | #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 |
| 2192 | #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 2193 | u8 network_key_index; |
| 2194 | #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 |
| 2195 | #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 |
| 2196 | #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 |
| 2197 | #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 |
| 2198 | u8 reserved[10]; |
| 2199 | }; |
| 2200 | |
| 2201 | I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); |
| 2202 | |
| 2203 | /* OEM mode commands (direct 0xFE0x) */ |
| 2204 | struct i40e_aqc_oem_param_change { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 2205 | __le32 param_type; |
| 2206 | #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 |
| 2207 | #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 |
| 2208 | #define I40E_AQ_OEM_PARAM_MAC 2 |
| 2209 | __le32 param_value1; |
Shannon Nelson | 35155fe | 2014-12-12 07:50:07 +0000 | [diff] [blame] | 2210 | __le16 param_value2; |
| 2211 | u8 reserved[6]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 2212 | }; |
| 2213 | |
| 2214 | I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); |
| 2215 | |
| 2216 | struct i40e_aqc_oem_state_change { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 2217 | __le32 state; |
| 2218 | #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 |
| 2219 | #define I40E_AQ_OEM_STATE_LINK_UP 0x1 |
| 2220 | u8 reserved[12]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 2221 | }; |
| 2222 | |
| 2223 | I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); |
| 2224 | |
Shannon Nelson | 672415c | 2014-12-14 01:55:13 +0000 | [diff] [blame] | 2225 | /* Initialize OCSD (0xFE02, direct) */ |
| 2226 | struct i40e_aqc_opc_oem_ocsd_initialize { |
| 2227 | u8 type_status; |
| 2228 | u8 reserved1[3]; |
| 2229 | __le32 ocsd_memory_block_addr_high; |
| 2230 | __le32 ocsd_memory_block_addr_low; |
| 2231 | __le32 requested_update_interval; |
| 2232 | }; |
| 2233 | |
| 2234 | I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); |
| 2235 | |
| 2236 | /* Initialize OCBB (0xFE03, direct) */ |
| 2237 | struct i40e_aqc_opc_oem_ocbb_initialize { |
| 2238 | u8 type_status; |
| 2239 | u8 reserved1[3]; |
| 2240 | __le32 ocbb_memory_block_addr_high; |
| 2241 | __le32 ocbb_memory_block_addr_low; |
| 2242 | u8 reserved2[4]; |
| 2243 | }; |
| 2244 | |
| 2245 | I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); |
| 2246 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 2247 | /* debug commands */ |
| 2248 | |
| 2249 | /* get device id (0xFF00) uses the generic structure */ |
| 2250 | |
| 2251 | /* set test more (0xFF01, internal) */ |
| 2252 | |
| 2253 | struct i40e_acq_set_test_mode { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 2254 | u8 mode; |
| 2255 | #define I40E_AQ_TEST_PARTIAL 0 |
| 2256 | #define I40E_AQ_TEST_FULL 1 |
| 2257 | #define I40E_AQ_TEST_NVM 2 |
| 2258 | u8 reserved[3]; |
| 2259 | u8 command; |
| 2260 | #define I40E_AQ_TEST_OPEN 0 |
| 2261 | #define I40E_AQ_TEST_CLOSE 1 |
| 2262 | #define I40E_AQ_TEST_INC 2 |
| 2263 | u8 reserved2[3]; |
| 2264 | __le32 address_high; |
| 2265 | __le32 address_low; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 2266 | }; |
| 2267 | |
| 2268 | I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); |
| 2269 | |
| 2270 | /* Debug Read Register command (0xFF03) |
| 2271 | * Debug Write Register command (0xFF04) |
| 2272 | */ |
| 2273 | struct i40e_aqc_debug_reg_read_write { |
| 2274 | __le32 reserved; |
| 2275 | __le32 address; |
| 2276 | __le32 value_high; |
| 2277 | __le32 value_low; |
| 2278 | }; |
| 2279 | |
| 2280 | I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); |
| 2281 | |
| 2282 | /* Scatter/gather Reg Read (indirect 0xFF05) |
| 2283 | * Scatter/gather Reg Write (indirect 0xFF06) |
| 2284 | */ |
| 2285 | |
| 2286 | /* i40e_aq_desc is used for the command */ |
| 2287 | struct i40e_aqc_debug_reg_sg_element_data { |
| 2288 | __le32 address; |
| 2289 | __le32 value; |
| 2290 | }; |
| 2291 | |
| 2292 | /* Debug Modify register (direct 0xFF07) */ |
| 2293 | struct i40e_aqc_debug_modify_reg { |
| 2294 | __le32 address; |
| 2295 | __le32 value; |
| 2296 | __le32 clear_mask; |
| 2297 | __le32 set_mask; |
| 2298 | }; |
| 2299 | |
| 2300 | I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); |
| 2301 | |
| 2302 | /* dump internal data (0xFF08, indirect) */ |
| 2303 | |
| 2304 | #define I40E_AQ_CLUSTER_ID_AUX 0 |
| 2305 | #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 |
| 2306 | #define I40E_AQ_CLUSTER_ID_TXSCHED 2 |
| 2307 | #define I40E_AQ_CLUSTER_ID_HMC 3 |
| 2308 | #define I40E_AQ_CLUSTER_ID_MAC0 4 |
| 2309 | #define I40E_AQ_CLUSTER_ID_MAC1 5 |
| 2310 | #define I40E_AQ_CLUSTER_ID_MAC2 6 |
| 2311 | #define I40E_AQ_CLUSTER_ID_MAC3 7 |
| 2312 | #define I40E_AQ_CLUSTER_ID_DCB 8 |
| 2313 | #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 |
| 2314 | #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 |
| 2315 | #define I40E_AQ_CLUSTER_ID_ALTRAM 11 |
| 2316 | |
| 2317 | struct i40e_aqc_debug_dump_internals { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 2318 | u8 cluster_id; |
| 2319 | u8 table_id; |
| 2320 | __le16 data_size; |
| 2321 | __le32 idx; |
| 2322 | __le32 address_high; |
| 2323 | __le32 address_low; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 2324 | }; |
| 2325 | |
| 2326 | I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); |
| 2327 | |
| 2328 | struct i40e_aqc_debug_modify_internals { |
Jeff Kirsher | 8c570dc | 2014-09-13 07:40:43 +0000 | [diff] [blame] | 2329 | u8 cluster_id; |
| 2330 | u8 cluster_specific_params[7]; |
| 2331 | __le32 address_high; |
| 2332 | __le32 address_low; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 2333 | }; |
| 2334 | |
| 2335 | I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); |
| 2336 | |
Helin Zhang | 2f175f5 | 2015-10-21 19:47:10 -0400 | [diff] [blame] | 2337 | #endif /* _I40E_ADMINQ_CMD_H_ */ |