blob: 29889bbdcc6d54c4a975de0905d65c5b285595db [file] [log] [blame]
Shawn Guo289569f2010-12-18 21:39:28 +08001/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/irq.h>
Shawn Guo83a84ef2012-08-20 21:34:56 +080022#include <linux/irqdomain.h>
Shawn Guo289569f2010-12-18 21:39:28 +080023#include <linux/io.h>
Shawn Guo83a84ef2012-08-20 21:34:56 +080024#include <linux/of.h>
Shawn Guo8256aa72013-03-25 21:13:22 +080025#include <linux/of_address.h>
Shawn Guo83a84ef2012-08-20 21:34:56 +080026#include <linux/of_irq.h>
Shawn Guocec6bae2013-03-25 21:20:05 +080027#include <linux/stmp_device.h>
Shawn Guo4e0a1b82012-08-20 10:14:56 +080028#include <asm/exception.h>
Shawn Guo289569f2010-12-18 21:39:28 +080029
Shawn Guo6a8e95b2013-03-25 21:34:51 +080030#include "irqchip.h"
31
Shawn Guo289569f2010-12-18 21:39:28 +080032#define HW_ICOLL_VECTOR 0x0000
33#define HW_ICOLL_LEVELACK 0x0010
34#define HW_ICOLL_CTRL 0x0020
Shawn Guo4e0a1b82012-08-20 10:14:56 +080035#define HW_ICOLL_STAT_OFFSET 0x0070
Shawn Guo289569f2010-12-18 21:39:28 +080036#define HW_ICOLL_INTERRUPTn_SET(n) (0x0124 + (n) * 0x10)
37#define HW_ICOLL_INTERRUPTn_CLR(n) (0x0128 + (n) * 0x10)
38#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004
39#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1
40
Shawn Guo83a84ef2012-08-20 21:34:56 +080041#define ICOLL_NUM_IRQS 128
42
Shawn Guo8256aa72013-03-25 21:13:22 +080043static void __iomem *icoll_base;
Shawn Guo83a84ef2012-08-20 21:34:56 +080044static struct irq_domain *icoll_domain;
Shawn Guo289569f2010-12-18 21:39:28 +080045
Uwe Kleine-Königbf0c11182011-02-18 21:31:41 +010046static void icoll_ack_irq(struct irq_data *d)
Shawn Guo289569f2010-12-18 21:39:28 +080047{
48 /*
49 * The Interrupt Collector is able to prioritize irqs.
50 * Currently only level 0 is used. So acking can use
51 * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally.
52 */
53 __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0,
54 icoll_base + HW_ICOLL_LEVELACK);
55}
56
Uwe Kleine-Königbf0c11182011-02-18 21:31:41 +010057static void icoll_mask_irq(struct irq_data *d)
Shawn Guo289569f2010-12-18 21:39:28 +080058{
59 __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
Shawn Guo83a84ef2012-08-20 21:34:56 +080060 icoll_base + HW_ICOLL_INTERRUPTn_CLR(d->hwirq));
Shawn Guo289569f2010-12-18 21:39:28 +080061}
62
Uwe Kleine-Königbf0c11182011-02-18 21:31:41 +010063static void icoll_unmask_irq(struct irq_data *d)
Shawn Guo289569f2010-12-18 21:39:28 +080064{
65 __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
Shawn Guo83a84ef2012-08-20 21:34:56 +080066 icoll_base + HW_ICOLL_INTERRUPTn_SET(d->hwirq));
Shawn Guo289569f2010-12-18 21:39:28 +080067}
68
69static struct irq_chip mxs_icoll_chip = {
Uwe Kleine-Königbf0c11182011-02-18 21:31:41 +010070 .irq_ack = icoll_ack_irq,
71 .irq_mask = icoll_mask_irq,
72 .irq_unmask = icoll_unmask_irq,
Shawn Guo289569f2010-12-18 21:39:28 +080073};
74
Shawn Guo4e0a1b82012-08-20 10:14:56 +080075asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
76{
77 u32 irqnr;
78
79 do {
80 irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET);
81 if (irqnr != 0x7f) {
82 __raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR);
Shawn Guo83a84ef2012-08-20 21:34:56 +080083 irqnr = irq_find_mapping(icoll_domain, irqnr);
Shawn Guo4e0a1b82012-08-20 10:14:56 +080084 handle_IRQ(irqnr, regs);
85 continue;
86 }
87 break;
88 } while (1);
89}
90
Shawn Guo83a84ef2012-08-20 21:34:56 +080091static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
92 irq_hw_number_t hw)
Shawn Guo289569f2010-12-18 21:39:28 +080093{
Shawn Guo83a84ef2012-08-20 21:34:56 +080094 irq_set_chip_and_handler(virq, &mxs_icoll_chip, handle_level_irq);
95 set_irq_flags(virq, IRQF_VALID);
Shawn Guo289569f2010-12-18 21:39:28 +080096
Shawn Guo83a84ef2012-08-20 21:34:56 +080097 return 0;
98}
99
100static struct irq_domain_ops icoll_irq_domain_ops = {
101 .map = icoll_irq_domain_map,
102 .xlate = irq_domain_xlate_onecell,
103};
104
Fabio Estevamf26b0162013-02-11 12:01:47 -0200105static void __init icoll_of_init(struct device_node *np,
Shawn Guo83a84ef2012-08-20 21:34:56 +0800106 struct device_node *interrupt_parent)
107{
Shawn Guo8256aa72013-03-25 21:13:22 +0800108 icoll_base = of_iomap(np, 0);
109 WARN_ON(!icoll_base);
110
Shawn Guo289569f2010-12-18 21:39:28 +0800111 /*
112 * Interrupt Collector reset, which initializes the priority
113 * for each irq to level 0.
114 */
Shawn Guocec6bae2013-03-25 21:20:05 +0800115 stmp_reset_block(icoll_base + HW_ICOLL_CTRL);
Shawn Guo289569f2010-12-18 21:39:28 +0800116
Shawn Guo83a84ef2012-08-20 21:34:56 +0800117 icoll_domain = irq_domain_add_linear(np, ICOLL_NUM_IRQS,
118 &icoll_irq_domain_ops, NULL);
119 WARN_ON(!icoll_domain);
120}
Shawn Guo6a8e95b2013-03-25 21:34:51 +0800121IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init);