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Laxman Dewangane9ea0962013-01-08 16:27:44 +05301NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver.
2
3Required properties:
4- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
5- reg: Should contain UART controller registers location and length.
6- interrupts: Should contain UART controller interrupts.
Stephen Warrend8f64792013-11-06 14:00:25 -07007- clocks: Must contain one entry, for the module clock.
8 See ../clocks/clock-bindings.txt for details.
Stephen Warren07999582013-11-07 10:11:27 -07009- resets : Must contain an entry for each entry in reset-names.
10 See ../reset/reset.txt for details.
11- reset-names : Must include the following entries:
12 - serial
Stephen Warrened520c92013-11-11 13:04:19 -070013- dmas : Must contain an entry for each entry in clock-names.
14 See ../dma/dma.txt for details.
15- dma-names : Must include the following entries:
16 - rx
17 - tx
Laxman Dewangane9ea0962013-01-08 16:27:44 +053018
19Optional properties:
20- nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
21 only if all 8 lines of UART controller are pinmuxed.
22
23Example:
24
25serial@70006000 {
26 compatible = "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart";
27 reg = <0x70006000 0x40>;
28 reg-shift = <2>;
29 interrupts = <0 36 0x04>;
Laxman Dewangane9ea0962013-01-08 16:27:44 +053030 nvidia,enable-modem-interrupt;
Stephen Warrend8f64792013-11-06 14:00:25 -070031 clocks = <&tegra_car 6>;
Stephen Warren07999582013-11-07 10:11:27 -070032 resets = <&tegra_car 6>;
33 reset-names = "serial";
Stephen Warrened520c92013-11-11 13:04:19 -070034 dmas = <&apbdma 8>, <&apbdma 8>;
35 dma-names = "rx", "tx";
Laxman Dewangane9ea0962013-01-08 16:27:44 +053036 status = "disabled";
37};