Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | */ |
| 14 | #include <linux/clk.h> |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 15 | #include <linux/dmaengine.h> |
| 16 | #include <linux/dma-mapping.h> |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 17 | #include <linux/interrupt.h> |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 18 | #include <linux/ipc_logging.h> |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 19 | #include <linux/io.h> |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/of.h> |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 22 | #include <linux/of_platform.h> |
Karthikeyan Ramasubramanian | 9a63340 | 2017-04-06 16:01:11 -0600 | [diff] [blame] | 23 | #include <linux/pm_runtime.h> |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 24 | #include <linux/qcom-geni-se.h> |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 25 | #include <linux/msm_gpi.h> |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 26 | #include <linux/spi/spi.h> |
Girish Mahadevan | b06fe0e | 2017-09-06 11:35:19 -0600 | [diff] [blame] | 27 | #include <linux/spi/spi-geni-qcom.h> |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 28 | |
| 29 | #define SPI_NUM_CHIPSELECT (4) |
| 30 | #define SPI_XFER_TIMEOUT_MS (250) |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 31 | /* SPI SE specific registers */ |
| 32 | #define SE_SPI_CPHA (0x224) |
| 33 | #define SE_SPI_LOOPBACK (0x22C) |
| 34 | #define SE_SPI_CPOL (0x230) |
| 35 | #define SE_SPI_DEMUX_OUTPUT_INV (0x24C) |
| 36 | #define SE_SPI_DEMUX_SEL (0x250) |
| 37 | #define SE_SPI_TRANS_CFG (0x25C) |
| 38 | #define SE_SPI_WORD_LEN (0x268) |
| 39 | #define SE_SPI_TX_TRANS_LEN (0x26C) |
| 40 | #define SE_SPI_RX_TRANS_LEN (0x270) |
| 41 | #define SE_SPI_PRE_POST_CMD_DLY (0x274) |
| 42 | #define SE_SPI_DELAY_COUNTERS (0x278) |
| 43 | |
| 44 | /* SE_SPI_CPHA register fields */ |
| 45 | #define CPHA (BIT(0)) |
| 46 | |
| 47 | /* SE_SPI_LOOPBACK register fields */ |
| 48 | #define LOOPBACK_ENABLE (0x1) |
| 49 | #define NORMAL_MODE (0x0) |
| 50 | #define LOOPBACK_MSK (GENMASK(1, 0)) |
| 51 | |
| 52 | /* SE_SPI_CPOL register fields */ |
| 53 | #define CPOL (BIT(2)) |
| 54 | |
| 55 | /* SE_SPI_DEMUX_OUTPUT_INV register fields */ |
| 56 | #define CS_DEMUX_OUTPUT_INV_MSK (GENMASK(3, 0)) |
| 57 | |
| 58 | /* SE_SPI_DEMUX_SEL register fields */ |
| 59 | #define CS_DEMUX_OUTPUT_SEL (GENMASK(3, 0)) |
| 60 | |
| 61 | /* SE_SPI_TX_TRANS_CFG register fields */ |
| 62 | #define CS_TOGGLE (BIT(0)) |
| 63 | |
| 64 | /* SE_SPI_WORD_LEN register fields */ |
| 65 | #define WORD_LEN_MSK (GENMASK(9, 0)) |
| 66 | #define MIN_WORD_LEN (4) |
| 67 | |
| 68 | /* SPI_TX/SPI_RX_TRANS_LEN fields */ |
| 69 | #define TRANS_LEN_MSK (GENMASK(23, 0)) |
| 70 | |
Girish Mahadevan | b06fe0e | 2017-09-06 11:35:19 -0600 | [diff] [blame] | 71 | /* SE_SPI_DELAY_COUNTERS */ |
| 72 | #define SPI_INTER_WORDS_DELAY_MSK (GENMASK(9, 0)) |
| 73 | #define SPI_CS_CLK_DELAY_MSK (GENMASK(19, 10)) |
| 74 | #define SPI_CS_CLK_DELAY_SHFT (10) |
| 75 | |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 76 | /* M_CMD OP codes for SPI */ |
| 77 | #define SPI_TX_ONLY (1) |
| 78 | #define SPI_RX_ONLY (2) |
| 79 | #define SPI_FULL_DUPLEX (3) |
| 80 | #define SPI_TX_RX (7) |
| 81 | #define SPI_CS_ASSERT (8) |
| 82 | #define SPI_CS_DEASSERT (9) |
| 83 | #define SPI_SCK_ONLY (10) |
| 84 | /* M_CMD params for SPI */ |
Girish Mahadevan | 061b9e3 | 2017-05-18 10:25:43 -0600 | [diff] [blame] | 85 | #define SPI_PRE_CMD_DELAY BIT(0) |
| 86 | #define TIMESTAMP_BEFORE BIT(1) |
| 87 | #define FRAGMENTATION BIT(2) |
| 88 | #define TIMESTAMP_AFTER BIT(3) |
| 89 | #define POST_CMD_DELAY BIT(4) |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 90 | |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 91 | #define SPI_CORE2X_VOTE (10000) |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 92 | /* GSI CONFIG0 TRE Params */ |
| 93 | /* Flags bit fields */ |
| 94 | #define GSI_LOOPBACK_EN (BIT(0)) |
| 95 | #define GSI_CS_TOGGLE (BIT(3)) |
| 96 | #define GSI_CPHA (BIT(4)) |
| 97 | #define GSI_CPOL (BIT(5)) |
| 98 | |
| 99 | #define MAX_TX_SG (3) |
| 100 | #define NUM_SPI_XFER (8) |
| 101 | |
| 102 | struct gsi_desc_cb { |
| 103 | struct spi_master *spi; |
| 104 | struct spi_transfer *xfer; |
| 105 | }; |
| 106 | |
| 107 | struct spi_geni_gsi { |
| 108 | struct msm_gpi_tre config0_tre; |
| 109 | struct msm_gpi_tre go_tre; |
| 110 | struct msm_gpi_tre tx_dma_tre; |
| 111 | struct msm_gpi_tre rx_dma_tre; |
| 112 | struct scatterlist tx_sg[MAX_TX_SG]; |
| 113 | struct scatterlist rx_sg; |
| 114 | dma_cookie_t tx_cookie; |
| 115 | dma_cookie_t rx_cookie; |
| 116 | struct msm_gpi_dma_async_tx_cb_param tx_cb_param; |
| 117 | struct msm_gpi_dma_async_tx_cb_param rx_cb_param; |
| 118 | struct dma_async_tx_descriptor *tx_desc; |
| 119 | struct dma_async_tx_descriptor *rx_desc; |
| 120 | struct gsi_desc_cb desc_cb; |
| 121 | }; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 122 | |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 123 | struct spi_geni_master { |
| 124 | struct se_geni_rsc spi_rsc; |
| 125 | resource_size_t phys_addr; |
| 126 | resource_size_t size; |
| 127 | void __iomem *base; |
| 128 | int irq; |
| 129 | struct device *dev; |
| 130 | int rx_fifo_depth; |
| 131 | int tx_fifo_depth; |
| 132 | int tx_fifo_width; |
| 133 | int tx_wm; |
| 134 | bool setup; |
| 135 | u32 cur_speed_hz; |
| 136 | int cur_word_len; |
| 137 | unsigned int tx_rem_bytes; |
| 138 | unsigned int rx_rem_bytes; |
| 139 | struct spi_transfer *cur_xfer; |
| 140 | struct completion xfer_done; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 141 | struct device *wrapper_dev; |
Girish Mahadevan | 96cf38f | 2017-07-31 11:01:55 -0600 | [diff] [blame] | 142 | int oversampling; |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 143 | struct spi_geni_gsi *gsi; |
| 144 | struct dma_chan *tx; |
| 145 | struct dma_chan *rx; |
| 146 | struct msm_gpi_ctrl tx_event; |
| 147 | struct msm_gpi_ctrl rx_event; |
| 148 | struct completion tx_cb; |
| 149 | struct completion rx_cb; |
| 150 | bool qn_err; |
| 151 | int cur_xfer_mode; |
| 152 | int num_tx_eot; |
| 153 | int num_rx_eot; |
| 154 | int num_xfers; |
| 155 | void *ipc; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 156 | }; |
| 157 | |
| 158 | static struct spi_master *get_spi_master(struct device *dev) |
| 159 | { |
| 160 | struct platform_device *pdev = to_platform_device(dev); |
| 161 | struct spi_master *spi = platform_get_drvdata(pdev); |
| 162 | |
| 163 | return spi; |
| 164 | } |
| 165 | |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 166 | static int get_spi_clk_cfg(u32 speed_hz, struct spi_geni_master *mas, |
| 167 | int *clk_idx, int *clk_div) |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 168 | { |
| 169 | unsigned long sclk_freq; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 170 | struct se_geni_rsc *rsc = &mas->spi_rsc; |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 171 | int ret = 0; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 172 | |
Girish Mahadevan | 96cf38f | 2017-07-31 11:01:55 -0600 | [diff] [blame] | 173 | ret = geni_se_clk_freq_match(&mas->spi_rsc, |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 174 | (speed_hz * mas->oversampling), clk_idx, |
| 175 | &sclk_freq, true); |
Girish Mahadevan | 13f3f00 | 2017-06-05 14:27:57 -0600 | [diff] [blame] | 176 | if (ret) { |
| 177 | dev_err(mas->dev, "%s: Failed(%d) to find src clk for 0x%x\n", |
| 178 | __func__, ret, speed_hz); |
| 179 | return ret; |
| 180 | } |
Girish Mahadevan | 6727acc | 2017-04-05 12:40:19 -0600 | [diff] [blame] | 181 | |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 182 | *clk_div = ((sclk_freq / mas->oversampling) / speed_hz); |
| 183 | if (!(*clk_div)) { |
Girish Mahadevan | 96cf38f | 2017-07-31 11:01:55 -0600 | [diff] [blame] | 184 | dev_err(mas->dev, "%s:Err:sclk:%lu oversampling:%d speed:%u\n", |
| 185 | __func__, sclk_freq, mas->oversampling, speed_hz); |
Girish Mahadevan | 6727acc | 2017-04-05 12:40:19 -0600 | [diff] [blame] | 186 | return -EINVAL; |
Girish Mahadevan | 96cf38f | 2017-07-31 11:01:55 -0600 | [diff] [blame] | 187 | } |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 188 | |
Girish Mahadevan | 13f3f00 | 2017-06-05 14:27:57 -0600 | [diff] [blame] | 189 | dev_dbg(mas->dev, "%s: req %u sclk %lu, idx %d, div %d\n", __func__, |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 190 | speed_hz, sclk_freq, *clk_idx, *clk_div); |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 191 | ret = clk_set_rate(rsc->se_clk, sclk_freq); |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 192 | if (ret) |
Girish Mahadevan | 96cf38f | 2017-07-31 11:01:55 -0600 | [diff] [blame] | 193 | dev_err(mas->dev, "%s: clk_set_rate failed %d\n", |
| 194 | __func__, ret); |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 195 | return ret; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 196 | } |
| 197 | |
| 198 | static void spi_setup_word_len(struct spi_geni_master *mas, u32 mode, |
| 199 | int bits_per_word) |
| 200 | { |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 201 | int pack_words = 1; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 202 | bool msb_first = (mode & SPI_LSB_FIRST) ? false : true; |
| 203 | u32 word_len = geni_read_reg(mas->base, SE_SPI_WORD_LEN); |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 204 | unsigned long cfg0, cfg1; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 205 | |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 206 | /* |
| 207 | * If bits_per_word isn't a byte aligned value, set the packing to be |
| 208 | * 1 SPI word per FIFO word. |
| 209 | */ |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 210 | if (!(mas->tx_fifo_width % bits_per_word)) |
| 211 | pack_words = mas->tx_fifo_width / bits_per_word; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 212 | word_len &= ~WORD_LEN_MSK; |
| 213 | word_len |= ((bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK); |
| 214 | se_config_packing(mas->base, bits_per_word, pack_words, msb_first); |
| 215 | geni_write_reg(word_len, mas->base, SE_SPI_WORD_LEN); |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 216 | se_get_packing_config(bits_per_word, pack_words, msb_first, |
| 217 | &cfg0, &cfg1); |
| 218 | GENI_SE_DBG(mas->ipc, false, mas->dev, |
| 219 | "%s: cfg0 %lu cfg1 %lu bpw %d pack_words %d\n", __func__, |
| 220 | cfg0, cfg1, bits_per_word, pack_words); |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 221 | } |
| 222 | |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 223 | static int setup_fifo_params(struct spi_device *spi_slv, |
| 224 | struct spi_master *spi) |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 225 | { |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 226 | struct spi_geni_master *mas = spi_master_get_devdata(spi); |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 227 | u16 mode = spi_slv->mode; |
| 228 | u32 loopback_cfg = geni_read_reg(mas->base, SE_SPI_LOOPBACK); |
| 229 | u32 cpol = geni_read_reg(mas->base, SE_SPI_CPOL); |
| 230 | u32 cpha = geni_read_reg(mas->base, SE_SPI_CPHA); |
Girish Mahadevan | 061b9e3 | 2017-05-18 10:25:43 -0600 | [diff] [blame] | 231 | u32 demux_sel = 0; |
| 232 | u32 demux_output_inv = 0; |
Girish Mahadevan | da00876 | 2017-11-27 11:31:21 -0700 | [diff] [blame] | 233 | u32 clk_sel = 0; |
| 234 | u32 m_clk_cfg = 0; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 235 | int ret = 0; |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 236 | int idx; |
| 237 | int div; |
Girish Mahadevan | b06fe0e | 2017-09-06 11:35:19 -0600 | [diff] [blame] | 238 | struct spi_geni_qcom_ctrl_data *delay_params = NULL; |
| 239 | u32 spi_delay_params = 0; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 240 | |
| 241 | loopback_cfg &= ~LOOPBACK_MSK; |
| 242 | cpol &= ~CPOL; |
| 243 | cpha &= ~CPHA; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 244 | |
| 245 | if (mode & SPI_LOOP) |
| 246 | loopback_cfg |= LOOPBACK_ENABLE; |
| 247 | |
| 248 | if (mode & SPI_CPOL) |
| 249 | cpol |= CPOL; |
| 250 | |
| 251 | if (mode & SPI_CPHA) |
| 252 | cpha |= CPHA; |
| 253 | |
| 254 | if (spi_slv->mode & SPI_CS_HIGH) |
| 255 | demux_output_inv |= BIT(spi_slv->chip_select); |
| 256 | |
Girish Mahadevan | b06fe0e | 2017-09-06 11:35:19 -0600 | [diff] [blame] | 257 | if (spi_slv->controller_data) { |
| 258 | u32 cs_clk_delay = 0; |
| 259 | u32 inter_words_delay = 0; |
| 260 | |
| 261 | delay_params = |
| 262 | (struct spi_geni_qcom_ctrl_data *) spi_slv->controller_data; |
| 263 | cs_clk_delay = |
| 264 | (delay_params->spi_cs_clk_delay << SPI_CS_CLK_DELAY_SHFT) |
| 265 | & SPI_CS_CLK_DELAY_MSK; |
| 266 | inter_words_delay = |
| 267 | delay_params->spi_inter_words_delay & |
| 268 | SPI_INTER_WORDS_DELAY_MSK; |
| 269 | spi_delay_params = |
| 270 | (inter_words_delay | cs_clk_delay); |
| 271 | } |
| 272 | |
Girish Mahadevan | 061b9e3 | 2017-05-18 10:25:43 -0600 | [diff] [blame] | 273 | demux_sel = spi_slv->chip_select; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 274 | mas->cur_speed_hz = spi_slv->max_speed_hz; |
| 275 | mas->cur_word_len = spi_slv->bits_per_word; |
| 276 | |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 277 | ret = get_spi_clk_cfg(mas->cur_speed_hz, mas, &idx, &div); |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 278 | if (ret) { |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 279 | dev_err(mas->dev, "Err setting clks ret(%d) for %d\n", |
Girish Mahadevan | 6727acc | 2017-04-05 12:40:19 -0600 | [diff] [blame] | 280 | ret, mas->cur_speed_hz); |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 281 | goto setup_fifo_params_exit; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 282 | } |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 283 | |
| 284 | clk_sel |= (idx & CLK_SEL_MSK); |
| 285 | m_clk_cfg |= ((div << CLK_DIV_SHFT) | SER_CLK_EN); |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 286 | spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); |
| 287 | geni_write_reg(loopback_cfg, mas->base, SE_SPI_LOOPBACK); |
| 288 | geni_write_reg(demux_sel, mas->base, SE_SPI_DEMUX_SEL); |
| 289 | geni_write_reg(cpha, mas->base, SE_SPI_CPHA); |
| 290 | geni_write_reg(cpol, mas->base, SE_SPI_CPOL); |
| 291 | geni_write_reg(demux_output_inv, mas->base, SE_SPI_DEMUX_OUTPUT_INV); |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 292 | geni_write_reg(clk_sel, mas->base, SE_GENI_CLK_SEL); |
| 293 | geni_write_reg(m_clk_cfg, mas->base, GENI_SER_M_CLK_CFG); |
Girish Mahadevan | b06fe0e | 2017-09-06 11:35:19 -0600 | [diff] [blame] | 294 | geni_write_reg(spi_delay_params, mas->base, SE_SPI_DELAY_COUNTERS); |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 295 | GENI_SE_DBG(mas->ipc, false, mas->dev, |
| 296 | "%s:Loopback%d demux_sel0x%x demux_op_inv 0x%x clk_cfg 0x%x\n", |
| 297 | __func__, loopback_cfg, demux_sel, demux_output_inv, m_clk_cfg); |
| 298 | GENI_SE_DBG(mas->ipc, false, mas->dev, |
Girish Mahadevan | b06fe0e | 2017-09-06 11:35:19 -0600 | [diff] [blame] | 299 | "%s:clk_sel 0x%x cpol %d cpha %d delay 0x%x\n", __func__, |
| 300 | clk_sel, cpol, cpha, spi_delay_params); |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 301 | /* Ensure message level attributes are written before returning */ |
| 302 | mb(); |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 303 | setup_fifo_params_exit: |
| 304 | return ret; |
| 305 | } |
| 306 | |
| 307 | |
| 308 | static int select_xfer_mode(struct spi_master *spi, |
| 309 | struct spi_message *spi_msg) |
| 310 | { |
| 311 | struct spi_geni_master *mas = spi_master_get_devdata(spi); |
| 312 | int mode = FIFO_MODE; |
| 313 | int fifo_disable = (geni_read_reg(mas->base, GENI_IF_FIFO_DISABLE_RO) & |
| 314 | FIFO_IF_DISABLE); |
| 315 | bool dma_chan_valid = |
| 316 | !(IS_ERR_OR_NULL(mas->tx) || IS_ERR_OR_NULL(mas->rx)); |
| 317 | |
| 318 | /* |
| 319 | * If FIFO Interface is disabled and there are no DMA channels then we |
| 320 | * can't do this transfer. |
| 321 | * If FIFO interface is disabled, we can do GSI only, |
| 322 | * else pick FIFO mode. |
| 323 | */ |
| 324 | if (fifo_disable && !dma_chan_valid) |
| 325 | mode = -EINVAL; |
Girish Mahadevan | 5f9df63 | 2017-08-29 13:29:23 -0600 | [diff] [blame] | 326 | else if (dma_chan_valid) |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 327 | mode = GSI_DMA; |
| 328 | else |
| 329 | mode = FIFO_MODE; |
| 330 | return mode; |
| 331 | } |
| 332 | |
| 333 | static struct msm_gpi_tre *setup_config0_tre(struct spi_transfer *xfer, |
Girish Mahadevan | b06fe0e | 2017-09-06 11:35:19 -0600 | [diff] [blame] | 334 | struct spi_geni_master *mas, u16 mode, |
| 335 | u32 cs_clk_delay, u32 inter_words_delay) |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 336 | { |
| 337 | struct msm_gpi_tre *c0_tre = &mas->gsi[mas->num_xfers].config0_tre; |
| 338 | u8 flags = 0; |
| 339 | u8 word_len = 0; |
| 340 | u8 pack = 0; |
| 341 | int div = 0; |
| 342 | int idx = 0; |
| 343 | int ret = 0; |
| 344 | |
| 345 | if (IS_ERR_OR_NULL(c0_tre)) |
| 346 | return c0_tre; |
| 347 | |
| 348 | if (mode & SPI_LOOP) |
| 349 | flags |= GSI_LOOPBACK_EN; |
| 350 | |
| 351 | if (mode & SPI_CPOL) |
| 352 | flags |= GSI_CPOL; |
| 353 | |
| 354 | if (mode & SPI_CPHA) |
| 355 | flags |= GSI_CPHA; |
| 356 | |
| 357 | if (xfer->cs_change) |
| 358 | flags |= GSI_CS_TOGGLE; |
| 359 | |
| 360 | word_len = xfer->bits_per_word - MIN_WORD_LEN; |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 361 | pack |= (GSI_TX_PACK_EN | GSI_RX_PACK_EN); |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 362 | ret = get_spi_clk_cfg(mas->cur_speed_hz, mas, &idx, &div); |
| 363 | if (ret) { |
| 364 | dev_err(mas->dev, "%s:Err setting clks:%d\n", __func__, ret); |
| 365 | return ERR_PTR(ret); |
| 366 | } |
| 367 | c0_tre->dword[0] = MSM_GPI_SPI_CONFIG0_TRE_DWORD0(pack, flags, |
| 368 | word_len); |
Girish Mahadevan | b06fe0e | 2017-09-06 11:35:19 -0600 | [diff] [blame] | 369 | c0_tre->dword[1] = MSM_GPI_SPI_CONFIG0_TRE_DWORD1(0, cs_clk_delay, |
| 370 | inter_words_delay); |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 371 | c0_tre->dword[2] = MSM_GPI_SPI_CONFIG0_TRE_DWORD2(idx, div); |
| 372 | c0_tre->dword[3] = MSM_GPI_SPI_CONFIG0_TRE_DWORD3(0, 0, 0, 1); |
| 373 | GENI_SE_DBG(mas->ipc, false, mas->dev, |
| 374 | "%s: flags 0x%x word %d pack %d idx %d div %d\n", |
| 375 | __func__, flags, word_len, pack, idx, div); |
Girish Mahadevan | b06fe0e | 2017-09-06 11:35:19 -0600 | [diff] [blame] | 376 | GENI_SE_DBG(mas->ipc, false, mas->dev, |
| 377 | "%s: cs_clk_delay %d inter_words_delay %d\n", __func__, |
| 378 | cs_clk_delay, inter_words_delay); |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 379 | return c0_tre; |
| 380 | } |
| 381 | |
| 382 | static struct msm_gpi_tre *setup_go_tre(int cmd, int cs, int rx_len, int flags, |
| 383 | struct spi_geni_master *mas) |
| 384 | { |
| 385 | struct msm_gpi_tre *go_tre = &mas->gsi[mas->num_xfers].go_tre; |
| 386 | int chain; |
| 387 | int eot; |
| 388 | int eob; |
| 389 | |
| 390 | if (IS_ERR_OR_NULL(go_tre)) |
| 391 | return go_tre; |
| 392 | |
| 393 | go_tre->dword[0] = MSM_GPI_SPI_GO_TRE_DWORD0(flags, cs, cmd); |
| 394 | go_tre->dword[1] = MSM_GPI_SPI_GO_TRE_DWORD1; |
| 395 | go_tre->dword[2] = MSM_GPI_SPI_GO_TRE_DWORD2(rx_len); |
| 396 | if (cmd == SPI_RX_ONLY) { |
| 397 | eot = 0; |
| 398 | chain = 0; |
| 399 | eob = 1; |
| 400 | } else { |
| 401 | eot = 0; |
| 402 | chain = 1; |
| 403 | eob = 0; |
| 404 | } |
| 405 | go_tre->dword[3] = MSM_GPI_SPI_GO_TRE_DWORD3(0, eot, eob, chain); |
| 406 | GENI_SE_DBG(mas->ipc, false, mas->dev, |
| 407 | "%s: rx len %d flags 0x%x cs %d cmd %d eot %d eob %d chain %d\n", |
| 408 | __func__, rx_len, flags, cs, cmd, eot, eob, chain); |
| 409 | return go_tre; |
| 410 | } |
| 411 | |
| 412 | static struct msm_gpi_tre *setup_dma_tre(struct msm_gpi_tre *tre, |
| 413 | dma_addr_t buf, u32 len, |
| 414 | struct spi_geni_master *mas, |
| 415 | bool is_tx) |
| 416 | { |
| 417 | if (IS_ERR_OR_NULL(tre)) |
| 418 | return tre; |
| 419 | |
| 420 | tre->dword[0] = MSM_GPI_DMA_W_BUFFER_TRE_DWORD0(buf); |
| 421 | tre->dword[1] = MSM_GPI_DMA_W_BUFFER_TRE_DWORD1(buf); |
| 422 | tre->dword[2] = MSM_GPI_DMA_W_BUFFER_TRE_DWORD2(len); |
| 423 | tre->dword[3] = MSM_GPI_DMA_W_BUFFER_TRE_DWORD3(0, is_tx, 0, 0); |
| 424 | return tre; |
| 425 | } |
| 426 | |
| 427 | static void spi_gsi_ch_cb(struct dma_chan *ch, struct msm_gpi_cb const *cb, |
| 428 | void *ptr) |
| 429 | { |
| 430 | struct spi_master *spi = ptr; |
| 431 | struct spi_geni_master *mas = spi_master_get_devdata(spi); |
| 432 | |
| 433 | switch (cb->cb_event) { |
| 434 | case MSM_GPI_QUP_NOTIFY: |
| 435 | case MSM_GPI_QUP_MAX_EVENT: |
| 436 | GENI_SE_DBG(mas->ipc, false, mas->dev, |
| 437 | "%s:cb_ev%d status%llu ts%llu count%llu\n", |
| 438 | __func__, cb->cb_event, cb->status, |
| 439 | cb->timestamp, cb->count); |
| 440 | break; |
| 441 | case MSM_GPI_QUP_ERROR: |
| 442 | case MSM_GPI_QUP_CH_ERROR: |
| 443 | case MSM_GPI_QUP_FW_ERROR: |
| 444 | case MSM_GPI_QUP_PENDING_EVENT: |
| 445 | case MSM_GPI_QUP_EOT_DESC_MISMATCH: |
| 446 | case MSM_GPI_QUP_SW_ERROR: |
| 447 | GENI_SE_ERR(mas->ipc, true, mas->dev, |
| 448 | "%s: cb_ev %d status %llu ts %llu count %llu\n", |
| 449 | __func__, cb->cb_event, cb->status, |
| 450 | cb->timestamp, cb->count); |
| 451 | GENI_SE_ERR(mas->ipc, true, mas->dev, |
| 452 | "err.routine %u, err.type %u, err.code %u\n", |
| 453 | cb->error_log.routine, |
| 454 | cb->error_log.type, |
| 455 | cb->error_log.error_code); |
| 456 | mas->qn_err = true; |
| 457 | complete_all(&mas->tx_cb); |
| 458 | complete_all(&mas->rx_cb); |
| 459 | |
| 460 | break; |
| 461 | }; |
| 462 | } |
| 463 | |
| 464 | static void spi_gsi_rx_callback(void *cb) |
| 465 | { |
| 466 | struct msm_gpi_dma_async_tx_cb_param *cb_param = |
| 467 | (struct msm_gpi_dma_async_tx_cb_param *)cb; |
| 468 | struct gsi_desc_cb *desc_cb = (struct gsi_desc_cb *)cb_param->userdata; |
| 469 | struct spi_master *spi = desc_cb->spi; |
| 470 | struct spi_transfer *xfer = desc_cb->xfer; |
| 471 | struct spi_geni_master *mas = spi_master_get_devdata(spi); |
| 472 | |
| 473 | if (xfer->rx_buf) { |
| 474 | if (cb_param->status == MSM_GPI_TCE_UNEXP_ERR) { |
| 475 | GENI_SE_ERR(mas->ipc, true, mas->dev, |
| 476 | "%s: Unexpected GSI CB error\n", __func__); |
| 477 | return; |
| 478 | } |
| 479 | if (cb_param->length == xfer->len) { |
| 480 | GENI_SE_DBG(mas->ipc, false, mas->dev, |
| 481 | "%s\n", __func__); |
| 482 | complete(&mas->rx_cb); |
| 483 | } else { |
| 484 | GENI_SE_ERR(mas->ipc, true, mas->dev, |
| 485 | "%s: Length mismatch. Expected %d Callback %d\n", |
| 486 | __func__, xfer->len, cb_param->length); |
| 487 | } |
| 488 | } |
| 489 | } |
| 490 | |
| 491 | static void spi_gsi_tx_callback(void *cb) |
| 492 | { |
| 493 | struct msm_gpi_dma_async_tx_cb_param *cb_param = cb; |
| 494 | struct gsi_desc_cb *desc_cb = (struct gsi_desc_cb *)cb_param->userdata; |
| 495 | struct spi_master *spi = desc_cb->spi; |
| 496 | struct spi_transfer *xfer = desc_cb->xfer; |
| 497 | struct spi_geni_master *mas = spi_master_get_devdata(spi); |
| 498 | |
| 499 | if (xfer->tx_buf) { |
| 500 | if (cb_param->status == MSM_GPI_TCE_UNEXP_ERR) { |
| 501 | GENI_SE_ERR(mas->ipc, true, mas->dev, |
| 502 | "%s: Unexpected GSI CB error\n", __func__); |
| 503 | return; |
| 504 | } |
| 505 | if (cb_param->length == xfer->len) { |
| 506 | GENI_SE_DBG(mas->ipc, false, mas->dev, |
| 507 | "%s\n", __func__); |
| 508 | complete(&mas->tx_cb); |
| 509 | } else { |
| 510 | GENI_SE_ERR(mas->ipc, true, mas->dev, |
| 511 | "%s: Length mismatch. Expected %d Callback %d\n", |
| 512 | __func__, xfer->len, cb_param->length); |
| 513 | } |
| 514 | } |
| 515 | } |
| 516 | |
| 517 | static int setup_gsi_xfer(struct spi_transfer *xfer, |
| 518 | struct spi_geni_master *mas, |
| 519 | struct spi_device *spi_slv, |
| 520 | struct spi_master *spi) |
| 521 | { |
| 522 | int ret = 0; |
| 523 | struct msm_gpi_tre *c0_tre = NULL; |
| 524 | struct msm_gpi_tre *go_tre = NULL; |
| 525 | struct msm_gpi_tre *tx_tre = NULL; |
| 526 | struct msm_gpi_tre *rx_tre = NULL; |
| 527 | struct scatterlist *xfer_tx_sg = mas->gsi[mas->num_xfers].tx_sg; |
| 528 | struct scatterlist *xfer_rx_sg = &mas->gsi[mas->num_xfers].rx_sg; |
| 529 | int rx_nent = 0; |
| 530 | int tx_nent = 0; |
| 531 | u8 cmd = 0; |
| 532 | u8 cs = 0; |
| 533 | u32 rx_len = 0; |
| 534 | int go_flags = 0; |
| 535 | unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK; |
Girish Mahadevan | b06fe0e | 2017-09-06 11:35:19 -0600 | [diff] [blame] | 536 | struct spi_geni_qcom_ctrl_data *delay_params = NULL; |
| 537 | u32 cs_clk_delay = 0; |
| 538 | u32 inter_words_delay = 0; |
| 539 | |
| 540 | if (spi_slv->controller_data) { |
| 541 | delay_params = |
| 542 | (struct spi_geni_qcom_ctrl_data *) spi_slv->controller_data; |
| 543 | |
| 544 | cs_clk_delay = |
| 545 | delay_params->spi_cs_clk_delay; |
| 546 | inter_words_delay = |
| 547 | delay_params->spi_inter_words_delay; |
| 548 | } |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 549 | |
| 550 | if ((xfer->bits_per_word != mas->cur_word_len) || |
| 551 | (xfer->speed_hz != mas->cur_speed_hz)) { |
| 552 | mas->cur_word_len = xfer->bits_per_word; |
| 553 | mas->cur_speed_hz = xfer->speed_hz; |
| 554 | tx_nent++; |
Girish Mahadevan | b06fe0e | 2017-09-06 11:35:19 -0600 | [diff] [blame] | 555 | c0_tre = setup_config0_tre(xfer, mas, spi_slv->mode, |
| 556 | cs_clk_delay, inter_words_delay); |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 557 | if (IS_ERR_OR_NULL(c0_tre)) { |
| 558 | dev_err(mas->dev, "%s:Err setting c0tre:%d\n", |
| 559 | __func__, ret); |
| 560 | return PTR_ERR(c0_tre); |
| 561 | } |
| 562 | } |
| 563 | |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 564 | if (!(mas->cur_word_len % MIN_WORD_LEN)) { |
| 565 | rx_len = ((xfer->len << 3) / mas->cur_word_len); |
| 566 | } else { |
| 567 | int bytes_per_word = (mas->cur_word_len / BITS_PER_BYTE) + 1; |
| 568 | |
| 569 | rx_len = (xfer->len / bytes_per_word); |
| 570 | } |
| 571 | |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 572 | if (xfer->tx_buf && xfer->rx_buf) { |
| 573 | cmd = SPI_FULL_DUPLEX; |
| 574 | tx_nent += 2; |
| 575 | rx_nent++; |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 576 | } else if (xfer->tx_buf) { |
| 577 | cmd = SPI_TX_ONLY; |
| 578 | tx_nent += 2; |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 579 | rx_len = 0; |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 580 | } else if (xfer->rx_buf) { |
| 581 | cmd = SPI_RX_ONLY; |
| 582 | tx_nent++; |
| 583 | rx_nent++; |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 584 | } |
| 585 | |
| 586 | cs |= spi_slv->chip_select; |
| 587 | if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers)) |
| 588 | go_flags |= FRAGMENTATION; |
| 589 | go_tre = setup_go_tre(cmd, cs, rx_len, go_flags, mas); |
| 590 | |
| 591 | sg_init_table(xfer_tx_sg, tx_nent); |
| 592 | if (rx_nent) |
| 593 | sg_init_table(xfer_rx_sg, rx_nent); |
| 594 | |
| 595 | if (c0_tre) |
| 596 | sg_set_buf(xfer_tx_sg++, c0_tre, sizeof(*c0_tre)); |
| 597 | |
| 598 | sg_set_buf(xfer_tx_sg++, go_tre, sizeof(*go_tre)); |
| 599 | mas->gsi[mas->num_xfers].desc_cb.spi = spi; |
| 600 | mas->gsi[mas->num_xfers].desc_cb.xfer = xfer; |
| 601 | if (cmd & SPI_RX_ONLY) { |
| 602 | rx_tre = &mas->gsi[mas->num_xfers].rx_dma_tre; |
| 603 | rx_tre = setup_dma_tre(rx_tre, xfer->rx_dma, xfer->len, mas, 0); |
| 604 | if (IS_ERR_OR_NULL(rx_tre)) { |
| 605 | dev_err(mas->dev, "Err setting up rx tre\n"); |
| 606 | return PTR_ERR(rx_tre); |
| 607 | } |
| 608 | sg_set_buf(xfer_rx_sg, rx_tre, sizeof(*rx_tre)); |
| 609 | mas->gsi[mas->num_xfers].rx_desc = |
| 610 | dmaengine_prep_slave_sg(mas->rx, |
| 611 | &mas->gsi[mas->num_xfers].rx_sg, rx_nent, |
| 612 | DMA_DEV_TO_MEM, flags); |
| 613 | if (IS_ERR_OR_NULL(mas->gsi[mas->num_xfers].rx_desc)) { |
| 614 | dev_err(mas->dev, "Err setting up rx desc\n"); |
| 615 | return -EIO; |
| 616 | } |
| 617 | mas->gsi[mas->num_xfers].rx_desc->callback = |
| 618 | spi_gsi_rx_callback; |
| 619 | mas->gsi[mas->num_xfers].rx_desc->callback_param = |
| 620 | &mas->gsi[mas->num_xfers].rx_cb_param; |
| 621 | mas->gsi[mas->num_xfers].rx_cb_param.userdata = |
| 622 | &mas->gsi[mas->num_xfers].desc_cb; |
| 623 | mas->num_rx_eot++; |
| 624 | } |
| 625 | |
| 626 | if (cmd & SPI_TX_ONLY) { |
| 627 | tx_tre = &mas->gsi[mas->num_xfers].tx_dma_tre; |
| 628 | tx_tre = setup_dma_tre(tx_tre, xfer->tx_dma, xfer->len, mas, 1); |
| 629 | if (IS_ERR_OR_NULL(tx_tre)) { |
| 630 | dev_err(mas->dev, "Err setting up tx tre\n"); |
| 631 | return PTR_ERR(tx_tre); |
| 632 | } |
| 633 | sg_set_buf(xfer_tx_sg++, tx_tre, sizeof(*tx_tre)); |
| 634 | mas->num_tx_eot++; |
| 635 | } |
| 636 | mas->gsi[mas->num_xfers].tx_desc = dmaengine_prep_slave_sg(mas->tx, |
| 637 | mas->gsi[mas->num_xfers].tx_sg, tx_nent, |
| 638 | DMA_MEM_TO_DEV, flags); |
| 639 | if (IS_ERR_OR_NULL(mas->gsi[mas->num_xfers].tx_desc)) { |
| 640 | dev_err(mas->dev, "Err setting up tx desc\n"); |
| 641 | return -EIO; |
| 642 | } |
| 643 | mas->gsi[mas->num_xfers].tx_desc->callback = spi_gsi_tx_callback; |
| 644 | mas->gsi[mas->num_xfers].tx_desc->callback_param = |
| 645 | &mas->gsi[mas->num_xfers].tx_cb_param; |
| 646 | mas->gsi[mas->num_xfers].tx_cb_param.userdata = |
| 647 | &mas->gsi[mas->num_xfers].desc_cb; |
| 648 | mas->gsi[mas->num_xfers].tx_cookie = |
| 649 | dmaengine_submit(mas->gsi[mas->num_xfers].tx_desc); |
| 650 | if (mas->num_rx_eot) |
| 651 | mas->gsi[mas->num_xfers].rx_cookie = |
| 652 | dmaengine_submit(mas->gsi[mas->num_xfers].rx_desc); |
| 653 | dma_async_issue_pending(mas->tx); |
| 654 | if (mas->num_rx_eot) |
| 655 | dma_async_issue_pending(mas->rx); |
| 656 | mas->num_xfers++; |
| 657 | return ret; |
| 658 | } |
| 659 | |
| 660 | static int spi_geni_map_buf(struct spi_geni_master *mas, |
| 661 | struct spi_message *msg) |
| 662 | { |
| 663 | struct spi_transfer *xfer; |
Girish Mahadevan | 5f9df63 | 2017-08-29 13:29:23 -0600 | [diff] [blame] | 664 | int ret = 0; |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 665 | |
| 666 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
| 667 | if (xfer->rx_buf) { |
Girish Mahadevan | 5f9df63 | 2017-08-29 13:29:23 -0600 | [diff] [blame] | 668 | ret = geni_se_iommu_map_buf(mas->wrapper_dev, |
| 669 | &xfer->rx_dma, xfer->rx_buf, |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 670 | xfer->len, DMA_FROM_DEVICE); |
Girish Mahadevan | 5f9df63 | 2017-08-29 13:29:23 -0600 | [diff] [blame] | 671 | if (ret) { |
| 672 | GENI_SE_ERR(mas->ipc, true, mas->dev, |
| 673 | "%s: Mapping Rx buffer %d\n", __func__, ret); |
| 674 | return ret; |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 675 | } |
| 676 | } |
| 677 | |
| 678 | if (xfer->tx_buf) { |
Girish Mahadevan | 5f9df63 | 2017-08-29 13:29:23 -0600 | [diff] [blame] | 679 | ret = geni_se_iommu_map_buf(mas->wrapper_dev, |
| 680 | &xfer->tx_dma, |
| 681 | (void *)xfer->tx_buf, |
| 682 | xfer->len, DMA_TO_DEVICE); |
| 683 | if (ret) { |
| 684 | GENI_SE_ERR(mas->ipc, true, mas->dev, |
| 685 | "%s: Mapping Tx buffer %d\n", __func__, ret); |
| 686 | return ret; |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 687 | } |
| 688 | } |
| 689 | }; |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 690 | return 0; |
| 691 | } |
| 692 | |
| 693 | static void spi_geni_unmap_buf(struct spi_geni_master *mas, |
| 694 | struct spi_message *msg) |
| 695 | { |
| 696 | struct spi_transfer *xfer; |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 697 | |
| 698 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
| 699 | if (xfer->rx_buf) |
Girish Mahadevan | 5f9df63 | 2017-08-29 13:29:23 -0600 | [diff] [blame] | 700 | geni_se_iommu_unmap_buf(mas->wrapper_dev, &xfer->rx_dma, |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 701 | xfer->len, DMA_FROM_DEVICE); |
| 702 | if (xfer->tx_buf) |
Girish Mahadevan | 5f9df63 | 2017-08-29 13:29:23 -0600 | [diff] [blame] | 703 | geni_se_iommu_unmap_buf(mas->wrapper_dev, &xfer->tx_dma, |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 704 | xfer->len, DMA_TO_DEVICE); |
| 705 | }; |
| 706 | } |
| 707 | |
| 708 | static int spi_geni_prepare_message(struct spi_master *spi, |
| 709 | struct spi_message *spi_msg) |
| 710 | { |
| 711 | int ret = 0; |
| 712 | struct spi_geni_master *mas = spi_master_get_devdata(spi); |
| 713 | |
| 714 | mas->cur_xfer_mode = select_xfer_mode(spi, spi_msg); |
| 715 | |
| 716 | if (mas->cur_xfer_mode == FIFO_MODE) { |
| 717 | geni_se_select_mode(mas->base, FIFO_MODE); |
| 718 | reinit_completion(&mas->xfer_done); |
Girish Mahadevan | bf854fc | 2017-10-13 16:02:54 -0600 | [diff] [blame] | 719 | ret = setup_fifo_params(spi_msg->spi, spi); |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 720 | } else if (mas->cur_xfer_mode == GSI_DMA) { |
| 721 | mas->num_tx_eot = 0; |
| 722 | mas->num_rx_eot = 0; |
| 723 | mas->num_xfers = 0; |
| 724 | reinit_completion(&mas->tx_cb); |
| 725 | reinit_completion(&mas->rx_cb); |
| 726 | memset(mas->gsi, 0, |
| 727 | (sizeof(struct spi_geni_gsi) * NUM_SPI_XFER)); |
| 728 | geni_se_select_mode(mas->base, GSI_DMA); |
| 729 | dmaengine_resume(mas->tx); |
| 730 | ret = spi_geni_map_buf(mas, spi_msg); |
| 731 | } else { |
| 732 | dev_err(mas->dev, "%s: Couldn't select mode %d", __func__, |
| 733 | mas->cur_xfer_mode); |
| 734 | ret = -EINVAL; |
| 735 | } |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 736 | return ret; |
| 737 | } |
| 738 | |
| 739 | static int spi_geni_unprepare_message(struct spi_master *spi_mas, |
| 740 | struct spi_message *spi_msg) |
| 741 | { |
| 742 | struct spi_geni_master *mas = spi_master_get_devdata(spi_mas); |
| 743 | |
| 744 | mas->cur_speed_hz = 0; |
| 745 | mas->cur_word_len = 0; |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 746 | if (mas->cur_xfer_mode == GSI_DMA) { |
| 747 | dmaengine_pause(mas->tx); |
| 748 | spi_geni_unmap_buf(mas, spi_msg); |
| 749 | } |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 750 | return 0; |
| 751 | } |
| 752 | |
| 753 | static int spi_geni_prepare_transfer_hardware(struct spi_master *spi) |
| 754 | { |
| 755 | struct spi_geni_master *mas = spi_master_get_devdata(spi); |
| 756 | int ret = 0; |
Girish Mahadevan | 5f9df63 | 2017-08-29 13:29:23 -0600 | [diff] [blame] | 757 | u32 max_speed = spi->cur_msg->spi->max_speed_hz; |
| 758 | struct se_geni_rsc *rsc = &mas->spi_rsc; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 759 | |
Girish Mahadevan | 5f9df63 | 2017-08-29 13:29:23 -0600 | [diff] [blame] | 760 | /* Adjust the AB/IB based on the max speed of the slave.*/ |
| 761 | rsc->ib = max_speed * DEFAULT_BUS_WIDTH; |
| 762 | rsc->ab = max_speed * DEFAULT_BUS_WIDTH; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 763 | ret = pm_runtime_get_sync(mas->dev); |
| 764 | if (ret < 0) { |
| 765 | dev_err(mas->dev, "Error enabling SE resources\n"); |
| 766 | pm_runtime_put_noidle(mas->dev); |
| 767 | goto exit_prepare_transfer_hardware; |
| 768 | } else { |
| 769 | ret = 0; |
| 770 | } |
| 771 | |
| 772 | if (unlikely(!mas->setup)) { |
| 773 | int proto = get_se_proto(mas->base); |
Girish Mahadevan | 96cf38f | 2017-07-31 11:01:55 -0600 | [diff] [blame] | 774 | unsigned int major; |
| 775 | unsigned int minor; |
| 776 | unsigned int step; |
| 777 | int hw_ver; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 778 | |
| 779 | if (unlikely(proto != SPI)) { |
| 780 | dev_err(mas->dev, "Invalid proto %d\n", proto); |
| 781 | return -ENXIO; |
| 782 | } |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 783 | geni_se_init(mas->base, 0x0, (mas->tx_fifo_depth - 2)); |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 784 | mas->tx_fifo_depth = get_tx_fifo_depth(mas->base); |
| 785 | mas->rx_fifo_depth = get_rx_fifo_depth(mas->base); |
| 786 | mas->tx_fifo_width = get_tx_fifo_width(mas->base); |
Girish Mahadevan | 96cf38f | 2017-07-31 11:01:55 -0600 | [diff] [blame] | 787 | mas->oversampling = 1; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 788 | /* Transmit an entire FIFO worth of data per IRQ */ |
| 789 | mas->tx_wm = 1; |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 790 | |
| 791 | mas->tx = dma_request_slave_channel(mas->dev, "tx"); |
| 792 | if (IS_ERR_OR_NULL(mas->tx)) { |
| 793 | dev_info(mas->dev, "Failed to get tx DMA ch %ld", |
| 794 | PTR_ERR(mas->tx)); |
| 795 | } else { |
| 796 | mas->rx = dma_request_slave_channel(mas->dev, "rx"); |
| 797 | if (IS_ERR_OR_NULL(mas->rx)) { |
| 798 | dev_info(mas->dev, "Failed to get rx DMA ch %ld", |
| 799 | PTR_ERR(mas->rx)); |
| 800 | dma_release_channel(mas->tx); |
| 801 | } |
| 802 | mas->gsi = devm_kzalloc(mas->dev, |
| 803 | (sizeof(struct spi_geni_gsi) * NUM_SPI_XFER), |
| 804 | GFP_KERNEL); |
| 805 | if (IS_ERR_OR_NULL(mas->gsi)) { |
| 806 | dev_err(mas->dev, "Failed to get GSI mem\n"); |
| 807 | dma_release_channel(mas->tx); |
| 808 | dma_release_channel(mas->rx); |
| 809 | mas->tx = NULL; |
| 810 | mas->rx = NULL; |
| 811 | goto setup_ipc; |
| 812 | } |
| 813 | mas->tx_event.init.callback = spi_gsi_ch_cb; |
| 814 | mas->tx_event.init.cb_param = spi; |
| 815 | mas->tx_event.cmd = MSM_GPI_INIT; |
| 816 | mas->tx->private = &mas->tx_event; |
| 817 | mas->rx_event.init.callback = spi_gsi_ch_cb; |
| 818 | mas->rx_event.init.cb_param = spi; |
| 819 | mas->rx_event.cmd = MSM_GPI_INIT; |
| 820 | mas->rx->private = &mas->rx_event; |
| 821 | if (dmaengine_slave_config(mas->tx, NULL)) { |
| 822 | dev_err(mas->dev, "Failed to Config Tx\n"); |
| 823 | dma_release_channel(mas->tx); |
| 824 | dma_release_channel(mas->rx); |
| 825 | mas->tx = NULL; |
| 826 | mas->rx = NULL; |
| 827 | goto setup_ipc; |
| 828 | } |
| 829 | if (dmaengine_slave_config(mas->rx, NULL)) { |
| 830 | dev_err(mas->dev, "Failed to Config Rx\n"); |
| 831 | dma_release_channel(mas->tx); |
| 832 | dma_release_channel(mas->rx); |
| 833 | mas->tx = NULL; |
| 834 | mas->rx = NULL; |
| 835 | goto setup_ipc; |
| 836 | } |
| 837 | |
| 838 | } |
| 839 | setup_ipc: |
| 840 | mas->ipc = ipc_log_context_create(4, dev_name(mas->dev), 0); |
| 841 | dev_info(mas->dev, "tx_fifo %d rx_fifo %d tx_width %d\n", |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 842 | mas->tx_fifo_depth, mas->rx_fifo_depth, |
| 843 | mas->tx_fifo_width); |
| 844 | mas->setup = true; |
Girish Mahadevan | 96cf38f | 2017-07-31 11:01:55 -0600 | [diff] [blame] | 845 | hw_ver = geni_se_qupv3_hw_version(mas->wrapper_dev, &major, |
| 846 | &minor, &step); |
| 847 | if (hw_ver) |
| 848 | dev_err(mas->dev, "%s:Err getting HW version %d\n", |
| 849 | __func__, hw_ver); |
| 850 | else { |
Girish Mahadevan | 96cf38f | 2017-07-31 11:01:55 -0600 | [diff] [blame] | 851 | if ((major == 1) && (minor == 0)) |
| 852 | mas->oversampling = 2; |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 853 | GENI_SE_DBG(mas->ipc, false, mas->dev, |
| 854 | "%s:Major:%d Minor:%d step:%dos%d\n", |
| 855 | __func__, major, minor, step, mas->oversampling); |
Girish Mahadevan | 96cf38f | 2017-07-31 11:01:55 -0600 | [diff] [blame] | 856 | } |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 857 | } |
| 858 | exit_prepare_transfer_hardware: |
| 859 | return ret; |
| 860 | } |
| 861 | |
| 862 | static int spi_geni_unprepare_transfer_hardware(struct spi_master *spi) |
| 863 | { |
| 864 | struct spi_geni_master *mas = spi_master_get_devdata(spi); |
| 865 | |
| 866 | pm_runtime_put_sync(mas->dev); |
| 867 | return 0; |
| 868 | } |
| 869 | |
| 870 | static void setup_fifo_xfer(struct spi_transfer *xfer, |
| 871 | struct spi_geni_master *mas, u16 mode, |
| 872 | struct spi_master *spi) |
| 873 | { |
| 874 | u32 m_cmd = 0; |
| 875 | u32 m_param = 0; |
| 876 | u32 spi_tx_cfg = geni_read_reg(mas->base, SE_SPI_TRANS_CFG); |
| 877 | u32 trans_len = 0; |
| 878 | |
| 879 | if (xfer->bits_per_word != mas->cur_word_len) { |
| 880 | spi_setup_word_len(mas, mode, xfer->bits_per_word); |
| 881 | mas->cur_word_len = xfer->bits_per_word; |
| 882 | } |
| 883 | |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 884 | /* Speed and bits per word can be overridden per transfer */ |
| 885 | if (xfer->speed_hz != mas->cur_speed_hz) { |
| 886 | int ret = 0; |
Girish Mahadevan | da00876 | 2017-11-27 11:31:21 -0700 | [diff] [blame] | 887 | u32 clk_sel = 0; |
| 888 | u32 m_clk_cfg = 0; |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 889 | int idx = 0; |
| 890 | int div = 0; |
| 891 | |
| 892 | ret = get_spi_clk_cfg(xfer->speed_hz, mas, &idx, &div); |
| 893 | if (ret) { |
| 894 | dev_err(mas->dev, "%s:Err setting clks:%d\n", |
| 895 | __func__, ret); |
| 896 | return; |
| 897 | } |
| 898 | mas->cur_speed_hz = xfer->speed_hz; |
| 899 | clk_sel |= (idx & CLK_SEL_MSK); |
| 900 | m_clk_cfg |= ((div << CLK_DIV_SHFT) | SER_CLK_EN); |
| 901 | geni_write_reg(clk_sel, mas->base, SE_GENI_CLK_SEL); |
| 902 | geni_write_reg(m_clk_cfg, mas->base, GENI_SER_M_CLK_CFG); |
| 903 | } |
| 904 | |
| 905 | mas->tx_rem_bytes = 0; |
| 906 | mas->rx_rem_bytes = 0; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 907 | if (xfer->tx_buf && xfer->rx_buf) |
| 908 | m_cmd = SPI_FULL_DUPLEX; |
| 909 | else if (xfer->tx_buf) |
| 910 | m_cmd = SPI_TX_ONLY; |
| 911 | else if (xfer->rx_buf) |
| 912 | m_cmd = SPI_RX_ONLY; |
| 913 | |
| 914 | spi_tx_cfg &= ~CS_TOGGLE; |
| 915 | if (xfer->cs_change) |
| 916 | spi_tx_cfg |= CS_TOGGLE; |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 917 | if (!(mas->cur_word_len % MIN_WORD_LEN)) { |
| 918 | trans_len = |
| 919 | ((xfer->len << 3) / mas->cur_word_len) & TRANS_LEN_MSK; |
| 920 | } else { |
| 921 | int bytes_per_word = (mas->cur_word_len / BITS_PER_BYTE) + 1; |
| 922 | |
| 923 | trans_len = (xfer->len / bytes_per_word) & TRANS_LEN_MSK; |
| 924 | } |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 925 | if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers)) |
| 926 | m_param |= FRAGMENTATION; |
| 927 | |
| 928 | mas->cur_xfer = xfer; |
| 929 | if (m_cmd & SPI_TX_ONLY) { |
| 930 | mas->tx_rem_bytes = xfer->len; |
| 931 | geni_write_reg(trans_len, mas->base, SE_SPI_TX_TRANS_LEN); |
| 932 | } |
| 933 | |
| 934 | if (m_cmd & SPI_RX_ONLY) { |
| 935 | geni_write_reg(trans_len, mas->base, SE_SPI_RX_TRANS_LEN); |
| 936 | mas->rx_rem_bytes = xfer->len; |
| 937 | } |
| 938 | geni_write_reg(spi_tx_cfg, mas->base, SE_SPI_TRANS_CFG); |
| 939 | geni_setup_m_cmd(mas->base, m_cmd, m_param); |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 940 | GENI_SE_DBG(mas->ipc, false, mas->dev, |
| 941 | "%s: trans_len %d xferlen%d tx_cfg 0x%x cmd 0x%x\n", |
| 942 | __func__, trans_len, xfer->len, spi_tx_cfg, m_cmd); |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 943 | if (m_cmd & SPI_TX_ONLY) |
| 944 | geni_write_reg(mas->tx_wm, mas->base, SE_GENI_TX_WATERMARK_REG); |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 945 | /* Ensure all writes are done before the WM interrupt */ |
| 946 | mb(); |
| 947 | } |
| 948 | |
| 949 | static void handle_fifo_timeout(struct spi_geni_master *mas) |
| 950 | { |
| 951 | unsigned long timeout; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 952 | |
Girish Mahadevan | 5f9df63 | 2017-08-29 13:29:23 -0600 | [diff] [blame] | 953 | geni_se_dump_dbg_regs(&mas->spi_rsc, mas->base, mas->ipc); |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 954 | reinit_completion(&mas->xfer_done); |
| 955 | geni_cancel_m_cmd(mas->base); |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 956 | geni_write_reg(0, mas->base, SE_GENI_TX_WATERMARK_REG); |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 957 | /* Ensure cmd cancel is written */ |
| 958 | mb(); |
| 959 | timeout = wait_for_completion_timeout(&mas->xfer_done, HZ); |
| 960 | if (!timeout) { |
| 961 | reinit_completion(&mas->xfer_done); |
| 962 | geni_abort_m_cmd(mas->base); |
| 963 | /* Ensure cmd abort is written */ |
| 964 | mb(); |
| 965 | timeout = wait_for_completion_timeout(&mas->xfer_done, |
| 966 | HZ); |
| 967 | if (!timeout) |
| 968 | dev_err(mas->dev, |
| 969 | "Failed to cancel/abort m_cmd\n"); |
| 970 | } |
| 971 | } |
| 972 | |
| 973 | static int spi_geni_transfer_one(struct spi_master *spi, |
| 974 | struct spi_device *slv, |
| 975 | struct spi_transfer *xfer) |
| 976 | { |
| 977 | int ret = 0; |
| 978 | struct spi_geni_master *mas = spi_master_get_devdata(spi); |
| 979 | unsigned long timeout; |
| 980 | |
| 981 | if ((xfer->tx_buf == NULL) && (xfer->rx_buf == NULL)) { |
| 982 | dev_err(mas->dev, "Invalid xfer both tx rx are NULL\n"); |
| 983 | return -EINVAL; |
| 984 | } |
| 985 | |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 986 | if (mas->cur_xfer_mode == FIFO_MODE) { |
| 987 | setup_fifo_xfer(xfer, mas, slv->mode, spi); |
| 988 | timeout = wait_for_completion_timeout(&mas->xfer_done, |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 989 | msecs_to_jiffies(SPI_XFER_TIMEOUT_MS)); |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 990 | if (!timeout) { |
| 991 | GENI_SE_ERR(mas->ipc, true, mas->dev, |
| 992 | "Xfer[len %d tx %pK rx %pK n %d] timed out.\n", |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 993 | xfer->len, xfer->tx_buf, |
| 994 | xfer->rx_buf, |
| 995 | xfer->bits_per_word); |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 996 | mas->cur_xfer = NULL; |
| 997 | ret = -ETIMEDOUT; |
| 998 | goto err_fifo_geni_transfer_one; |
| 999 | } |
| 1000 | } else { |
| 1001 | setup_gsi_xfer(xfer, mas, slv, spi); |
| 1002 | if ((mas->num_xfers >= NUM_SPI_XFER) || |
| 1003 | (list_is_last(&xfer->transfer_list, |
| 1004 | &spi->cur_msg->transfers))) { |
| 1005 | int i; |
| 1006 | |
| 1007 | for (i = 0 ; i < mas->num_tx_eot; i++) { |
| 1008 | timeout = |
| 1009 | wait_for_completion_interruptible_timeout( |
| 1010 | &mas->tx_cb, |
| 1011 | msecs_to_jiffies(SPI_XFER_TIMEOUT_MS)); |
| 1012 | if (timeout <= 0) { |
| 1013 | GENI_SE_ERR(mas->ipc, true, mas->dev, |
| 1014 | "Tx[%d] timeout%lu\n", i, timeout); |
| 1015 | ret = -ETIMEDOUT; |
| 1016 | goto err_gsi_geni_transfer_one; |
| 1017 | } |
| 1018 | } |
| 1019 | for (i = 0 ; i < mas->num_rx_eot; i++) { |
| 1020 | timeout = |
| 1021 | wait_for_completion_interruptible_timeout( |
| 1022 | &mas->rx_cb, |
| 1023 | msecs_to_jiffies(SPI_XFER_TIMEOUT_MS)); |
| 1024 | if (timeout <= 0) { |
| 1025 | GENI_SE_ERR(mas->ipc, true, mas->dev, |
| 1026 | "Rx[%d] timeout%lu\n", i, timeout); |
| 1027 | ret = -ETIMEDOUT; |
| 1028 | goto err_gsi_geni_transfer_one; |
| 1029 | } |
| 1030 | } |
| 1031 | if (mas->qn_err) { |
| 1032 | ret = -EIO; |
| 1033 | mas->qn_err = false; |
| 1034 | goto err_gsi_geni_transfer_one; |
| 1035 | } |
| 1036 | } |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 1037 | } |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 1038 | return ret; |
| 1039 | err_gsi_geni_transfer_one: |
Girish Mahadevan | 5f9df63 | 2017-08-29 13:29:23 -0600 | [diff] [blame] | 1040 | geni_se_dump_dbg_regs(&mas->spi_rsc, mas->base, mas->ipc); |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 1041 | dmaengine_terminate_all(mas->tx); |
| 1042 | return ret; |
| 1043 | err_fifo_geni_transfer_one: |
| 1044 | handle_fifo_timeout(mas); |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 1045 | return ret; |
| 1046 | } |
| 1047 | |
| 1048 | static void geni_spi_handle_tx(struct spi_geni_master *mas) |
| 1049 | { |
| 1050 | int i = 0; |
| 1051 | int tx_fifo_width = (mas->tx_fifo_width >> 3); |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 1052 | int max_bytes = 0; |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 1053 | const u8 *tx_buf = NULL; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 1054 | |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 1055 | if (!mas->cur_xfer) |
| 1056 | return; |
| 1057 | |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 1058 | /* |
| 1059 | * For non-byte aligned bits-per-word values: |
| 1060 | * Assumption is that each SPI word will be accomodated in |
| 1061 | * ceil (bits_per_word / bits_per_byte) |
| 1062 | * and the next SPI word starts at the next byte. |
| 1063 | * In such cases, we can fit 1 SPI word per FIFO word so adjust the |
| 1064 | * max byte that can be sent per IRQ accordingly. |
| 1065 | */ |
| 1066 | if ((mas->tx_fifo_width % mas->cur_word_len)) |
| 1067 | max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * |
| 1068 | ((mas->cur_word_len / BITS_PER_BYTE) + 1); |
| 1069 | else |
| 1070 | max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * tx_fifo_width; |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 1071 | tx_buf = mas->cur_xfer->tx_buf; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 1072 | tx_buf += (mas->cur_xfer->len - mas->tx_rem_bytes); |
| 1073 | max_bytes = min_t(int, mas->tx_rem_bytes, max_bytes); |
| 1074 | while (i < max_bytes) { |
| 1075 | int j; |
| 1076 | u32 fifo_word = 0; |
| 1077 | u8 *fifo_byte; |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 1078 | int bytes_per_fifo = tx_fifo_width; |
| 1079 | int bytes_to_write = 0; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 1080 | |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 1081 | if ((mas->tx_fifo_width % mas->cur_word_len)) |
| 1082 | bytes_per_fifo = |
| 1083 | (mas->cur_word_len / BITS_PER_BYTE) + 1; |
| 1084 | bytes_to_write = min_t(int, (max_bytes - i), bytes_per_fifo); |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 1085 | fifo_byte = (u8 *)&fifo_word; |
| 1086 | for (j = 0; j < bytes_to_write; j++) |
| 1087 | fifo_byte[j] = tx_buf[i++]; |
| 1088 | geni_write_reg(fifo_word, mas->base, SE_GENI_TX_FIFOn); |
| 1089 | /* Ensure FIFO writes are written in order */ |
| 1090 | mb(); |
| 1091 | } |
| 1092 | mas->tx_rem_bytes -= max_bytes; |
| 1093 | if (!mas->tx_rem_bytes) { |
| 1094 | geni_write_reg(0, mas->base, SE_GENI_TX_WATERMARK_REG); |
| 1095 | /* Barrier here before return to prevent further ISRs */ |
| 1096 | mb(); |
| 1097 | } |
| 1098 | } |
| 1099 | |
| 1100 | static void geni_spi_handle_rx(struct spi_geni_master *mas) |
| 1101 | { |
| 1102 | int i = 0; |
| 1103 | int fifo_width = (mas->tx_fifo_width >> 3); |
| 1104 | u32 rx_fifo_status = geni_read_reg(mas->base, SE_GENI_RX_FIFO_STATUS); |
| 1105 | int rx_bytes = 0; |
| 1106 | int rx_wc = 0; |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 1107 | u8 *rx_buf = NULL; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 1108 | |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 1109 | if (!mas->cur_xfer) |
| 1110 | return; |
| 1111 | |
| 1112 | rx_buf = mas->cur_xfer->rx_buf; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 1113 | rx_wc = (rx_fifo_status & RX_FIFO_WC_MSK); |
| 1114 | if (rx_fifo_status & RX_LAST) { |
| 1115 | int rx_last_byte_valid = |
| 1116 | (rx_fifo_status & RX_LAST_BYTE_VALID_MSK) |
| 1117 | >> RX_LAST_BYTE_VALID_SHFT; |
| 1118 | if (rx_last_byte_valid && (rx_last_byte_valid < 4)) { |
| 1119 | rx_wc -= 1; |
| 1120 | rx_bytes += rx_last_byte_valid; |
| 1121 | } |
| 1122 | } |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 1123 | if (!(mas->tx_fifo_width % mas->cur_word_len)) |
| 1124 | rx_bytes += rx_wc * fifo_width; |
| 1125 | else |
| 1126 | rx_bytes += rx_wc * |
| 1127 | ((mas->cur_word_len / BITS_PER_BYTE) + 1); |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 1128 | rx_bytes = min_t(int, mas->rx_rem_bytes, rx_bytes); |
| 1129 | rx_buf += (mas->cur_xfer->len - mas->rx_rem_bytes); |
| 1130 | while (i < rx_bytes) { |
| 1131 | u32 fifo_word = 0; |
| 1132 | u8 *fifo_byte; |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 1133 | int bytes_per_fifo = fifo_width; |
| 1134 | int read_bytes = 0; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 1135 | int j; |
| 1136 | |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 1137 | if ((mas->tx_fifo_width % mas->cur_word_len)) |
| 1138 | bytes_per_fifo = |
| 1139 | (mas->cur_word_len / BITS_PER_BYTE) + 1; |
| 1140 | read_bytes = min_t(int, (rx_bytes - i), bytes_per_fifo); |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 1141 | fifo_word = geni_read_reg(mas->base, SE_GENI_RX_FIFOn); |
| 1142 | fifo_byte = (u8 *)&fifo_word; |
| 1143 | for (j = 0; j < read_bytes; j++) |
| 1144 | rx_buf[i++] = fifo_byte[j]; |
| 1145 | } |
| 1146 | mas->rx_rem_bytes -= rx_bytes; |
| 1147 | } |
| 1148 | |
| 1149 | static irqreturn_t geni_spi_irq(int irq, void *dev) |
| 1150 | { |
| 1151 | struct spi_geni_master *mas = dev; |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 1152 | u32 m_irq = 0; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 1153 | |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 1154 | if (pm_runtime_status_suspended(dev)) { |
| 1155 | GENI_SE_DBG(mas->ipc, false, mas->dev, |
| 1156 | "%s: device is suspended\n", __func__); |
| 1157 | goto exit_geni_spi_irq; |
| 1158 | } |
| 1159 | m_irq = geni_read_reg(mas->base, SE_GENI_M_IRQ_STATUS); |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 1160 | if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN)) |
| 1161 | geni_spi_handle_rx(mas); |
| 1162 | |
| 1163 | if ((m_irq & M_TX_FIFO_WATERMARK_EN)) |
| 1164 | geni_spi_handle_tx(mas); |
| 1165 | |
| 1166 | if ((m_irq & M_CMD_DONE_EN) || (m_irq & M_CMD_CANCEL_EN) || |
| 1167 | (m_irq & M_CMD_ABORT_EN)) { |
| 1168 | complete(&mas->xfer_done); |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 1169 | /* |
| 1170 | * If this happens, then a CMD_DONE came before all the buffer |
| 1171 | * bytes were sent out. This is unusual, log this condition and |
| 1172 | * disable the WM interrupt to prevent the system from stalling |
| 1173 | * due an interrupt storm. |
| 1174 | * If this happens when all Rx bytes haven't been received, log |
| 1175 | * the condition. |
| 1176 | */ |
| 1177 | if (mas->tx_rem_bytes) { |
| 1178 | geni_write_reg(0, mas->base, SE_GENI_TX_WATERMARK_REG); |
| 1179 | GENI_SE_DBG(mas->ipc, false, mas->dev, |
| 1180 | "%s:Premature Done.tx_rem%d bpw%d\n", |
| 1181 | __func__, mas->tx_rem_bytes, mas->cur_word_len); |
| 1182 | } |
| 1183 | if (mas->rx_rem_bytes) |
| 1184 | GENI_SE_DBG(mas->ipc, false, mas->dev, |
| 1185 | "%s:Premature Done.rx_rem%d bpw%d\n", |
| 1186 | __func__, mas->rx_rem_bytes, mas->cur_word_len); |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 1187 | } |
Girish Mahadevan | 1fc2770 | 2017-08-31 12:55:23 -0600 | [diff] [blame] | 1188 | exit_geni_spi_irq: |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 1189 | geni_write_reg(m_irq, mas->base, SE_GENI_M_IRQ_CLEAR); |
| 1190 | return IRQ_HANDLED; |
| 1191 | } |
| 1192 | |
| 1193 | static int spi_geni_probe(struct platform_device *pdev) |
| 1194 | { |
| 1195 | int ret; |
| 1196 | struct spi_master *spi; |
| 1197 | struct spi_geni_master *geni_mas; |
| 1198 | struct se_geni_rsc *rsc; |
| 1199 | struct resource *res; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 1200 | struct platform_device *wrapper_pdev; |
| 1201 | struct device_node *wrapper_ph_node; |
Girish Mahadevan | bf854fc | 2017-10-13 16:02:54 -0600 | [diff] [blame] | 1202 | bool rt_pri; |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 1203 | |
| 1204 | spi = spi_alloc_master(&pdev->dev, sizeof(struct spi_geni_master)); |
| 1205 | if (!spi) { |
| 1206 | ret = -ENOMEM; |
| 1207 | dev_err(&pdev->dev, "Failed to alloc spi struct\n"); |
| 1208 | goto spi_geni_probe_err; |
| 1209 | } |
| 1210 | |
| 1211 | platform_set_drvdata(pdev, spi); |
| 1212 | geni_mas = spi_master_get_devdata(spi); |
| 1213 | rsc = &geni_mas->spi_rsc; |
| 1214 | geni_mas->dev = &pdev->dev; |
| 1215 | spi->dev.of_node = pdev->dev.of_node; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 1216 | wrapper_ph_node = of_parse_phandle(pdev->dev.of_node, |
| 1217 | "qcom,wrapper-core", 0); |
| 1218 | if (IS_ERR_OR_NULL(wrapper_ph_node)) { |
| 1219 | ret = PTR_ERR(wrapper_ph_node); |
| 1220 | dev_err(&pdev->dev, "No wrapper core defined\n"); |
| 1221 | goto spi_geni_probe_err; |
| 1222 | } |
| 1223 | wrapper_pdev = of_find_device_by_node(wrapper_ph_node); |
| 1224 | of_node_put(wrapper_ph_node); |
| 1225 | if (IS_ERR_OR_NULL(wrapper_pdev)) { |
| 1226 | ret = PTR_ERR(wrapper_pdev); |
| 1227 | dev_err(&pdev->dev, "Cannot retrieve wrapper device\n"); |
| 1228 | goto spi_geni_probe_err; |
| 1229 | } |
| 1230 | geni_mas->wrapper_dev = &wrapper_pdev->dev; |
| 1231 | geni_mas->spi_rsc.wrapper_dev = &wrapper_pdev->dev; |
| 1232 | ret = geni_se_resources_init(rsc, SPI_CORE2X_VOTE, |
| 1233 | (DEFAULT_SE_CLK * DEFAULT_BUS_WIDTH)); |
| 1234 | if (ret) { |
| 1235 | dev_err(&pdev->dev, "Error geni_se_resources_init\n"); |
| 1236 | goto spi_geni_probe_err; |
| 1237 | } |
| 1238 | |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 1239 | rsc->geni_pinctrl = devm_pinctrl_get(&pdev->dev); |
| 1240 | if (IS_ERR_OR_NULL(rsc->geni_pinctrl)) { |
| 1241 | dev_err(&pdev->dev, "No pinctrl config specified!\n"); |
| 1242 | ret = PTR_ERR(rsc->geni_pinctrl); |
| 1243 | goto spi_geni_probe_err; |
| 1244 | } |
| 1245 | |
| 1246 | rsc->geni_gpio_active = pinctrl_lookup_state(rsc->geni_pinctrl, |
| 1247 | PINCTRL_DEFAULT); |
| 1248 | if (IS_ERR_OR_NULL(rsc->geni_gpio_active)) { |
| 1249 | dev_err(&pdev->dev, "No default config specified!\n"); |
| 1250 | ret = PTR_ERR(rsc->geni_gpio_active); |
| 1251 | goto spi_geni_probe_err; |
| 1252 | } |
| 1253 | |
| 1254 | rsc->geni_gpio_sleep = pinctrl_lookup_state(rsc->geni_pinctrl, |
| 1255 | PINCTRL_SLEEP); |
| 1256 | if (IS_ERR_OR_NULL(rsc->geni_gpio_sleep)) { |
| 1257 | dev_err(&pdev->dev, "No sleep config specified!\n"); |
| 1258 | ret = PTR_ERR(rsc->geni_gpio_sleep); |
| 1259 | goto spi_geni_probe_err; |
| 1260 | } |
| 1261 | |
| 1262 | rsc->se_clk = devm_clk_get(&pdev->dev, "se-clk"); |
| 1263 | if (IS_ERR(rsc->se_clk)) { |
| 1264 | ret = PTR_ERR(rsc->se_clk); |
| 1265 | dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); |
| 1266 | goto spi_geni_probe_err; |
| 1267 | } |
| 1268 | |
| 1269 | rsc->m_ahb_clk = devm_clk_get(&pdev->dev, "m-ahb"); |
| 1270 | if (IS_ERR(rsc->m_ahb_clk)) { |
| 1271 | ret = PTR_ERR(rsc->m_ahb_clk); |
| 1272 | dev_err(&pdev->dev, "Err getting M AHB clk %d\n", ret); |
| 1273 | goto spi_geni_probe_err; |
| 1274 | } |
| 1275 | |
| 1276 | rsc->s_ahb_clk = devm_clk_get(&pdev->dev, "s-ahb"); |
| 1277 | if (IS_ERR(rsc->s_ahb_clk)) { |
| 1278 | ret = PTR_ERR(rsc->s_ahb_clk); |
| 1279 | dev_err(&pdev->dev, "Err getting S AHB clk %d\n", ret); |
| 1280 | goto spi_geni_probe_err; |
| 1281 | } |
| 1282 | |
| 1283 | if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency", |
| 1284 | &spi->max_speed_hz)) { |
| 1285 | dev_err(&pdev->dev, "Max frequency not specified.\n"); |
| 1286 | ret = -ENXIO; |
| 1287 | goto spi_geni_probe_err; |
| 1288 | } |
| 1289 | |
| 1290 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "se_phys"); |
| 1291 | if (!res) { |
| 1292 | ret = -ENXIO; |
| 1293 | dev_err(&pdev->dev, "Err getting IO region\n"); |
| 1294 | goto spi_geni_probe_err; |
| 1295 | } |
| 1296 | |
Girish Mahadevan | bf854fc | 2017-10-13 16:02:54 -0600 | [diff] [blame] | 1297 | rt_pri = of_property_read_bool(pdev->dev.of_node, "qcom,rt"); |
| 1298 | if (rt_pri) |
| 1299 | spi->rt = true; |
| 1300 | |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 1301 | geni_mas->phys_addr = res->start; |
| 1302 | geni_mas->size = resource_size(res); |
| 1303 | geni_mas->base = devm_ioremap(&pdev->dev, res->start, |
| 1304 | resource_size(res)); |
| 1305 | if (!geni_mas->base) { |
| 1306 | ret = -ENOMEM; |
| 1307 | dev_err(&pdev->dev, "Err IO mapping iomem\n"); |
| 1308 | goto spi_geni_probe_err; |
| 1309 | } |
| 1310 | |
| 1311 | geni_mas->irq = platform_get_irq(pdev, 0); |
| 1312 | if (geni_mas->irq < 0) { |
| 1313 | dev_err(&pdev->dev, "Err getting IRQ\n"); |
| 1314 | ret = geni_mas->irq; |
| 1315 | goto spi_geni_probe_unmap; |
| 1316 | } |
| 1317 | ret = devm_request_irq(&pdev->dev, geni_mas->irq, geni_spi_irq, |
| 1318 | IRQF_TRIGGER_HIGH, "spi_geni", geni_mas); |
| 1319 | if (ret) { |
| 1320 | dev_err(&pdev->dev, "Request_irq failed:%d: err:%d\n", |
| 1321 | geni_mas->irq, ret); |
| 1322 | goto spi_geni_probe_unmap; |
| 1323 | } |
| 1324 | |
| 1325 | spi->mode_bits = (SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH); |
| 1326 | spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
| 1327 | spi->num_chipselect = SPI_NUM_CHIPSELECT; |
| 1328 | spi->prepare_transfer_hardware = spi_geni_prepare_transfer_hardware; |
| 1329 | spi->prepare_message = spi_geni_prepare_message; |
| 1330 | spi->unprepare_message = spi_geni_unprepare_message; |
| 1331 | spi->transfer_one = spi_geni_transfer_one; |
| 1332 | spi->unprepare_transfer_hardware |
| 1333 | = spi_geni_unprepare_transfer_hardware; |
| 1334 | spi->auto_runtime_pm = false; |
| 1335 | |
| 1336 | init_completion(&geni_mas->xfer_done); |
Girish Mahadevan | 9a7c944 | 2017-08-15 12:10:09 -0600 | [diff] [blame] | 1337 | init_completion(&geni_mas->tx_cb); |
| 1338 | init_completion(&geni_mas->rx_cb); |
Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame] | 1339 | pm_runtime_enable(&pdev->dev); |
| 1340 | ret = spi_register_master(spi); |
| 1341 | if (ret) { |
| 1342 | dev_err(&pdev->dev, "Failed to register SPI master\n"); |
| 1343 | goto spi_geni_probe_unmap; |
| 1344 | } |
| 1345 | return ret; |
| 1346 | spi_geni_probe_unmap: |
| 1347 | devm_iounmap(&pdev->dev, geni_mas->base); |
| 1348 | spi_geni_probe_err: |
| 1349 | spi_master_put(spi); |
| 1350 | return ret; |
| 1351 | } |
| 1352 | |
| 1353 | static int spi_geni_remove(struct platform_device *pdev) |
| 1354 | { |
| 1355 | struct spi_master *master = platform_get_drvdata(pdev); |
| 1356 | struct spi_geni_master *geni_mas = spi_master_get_devdata(master); |
| 1357 | |
| 1358 | spi_unregister_master(master); |
| 1359 | se_geni_resources_off(&geni_mas->spi_rsc); |
| 1360 | pm_runtime_put_noidle(&pdev->dev); |
| 1361 | pm_runtime_disable(&pdev->dev); |
| 1362 | return 0; |
| 1363 | } |
| 1364 | |
| 1365 | #ifdef CONFIG_PM |
| 1366 | static int spi_geni_runtime_suspend(struct device *dev) |
| 1367 | { |
| 1368 | int ret = 0; |
| 1369 | struct spi_master *spi = get_spi_master(dev); |
| 1370 | struct spi_geni_master *geni_mas = spi_master_get_devdata(spi); |
| 1371 | |
| 1372 | ret = se_geni_resources_off(&geni_mas->spi_rsc); |
| 1373 | return ret; |
| 1374 | } |
| 1375 | |
| 1376 | static int spi_geni_runtime_resume(struct device *dev) |
| 1377 | { |
| 1378 | int ret = 0; |
| 1379 | struct spi_master *spi = get_spi_master(dev); |
| 1380 | struct spi_geni_master *geni_mas = spi_master_get_devdata(spi); |
| 1381 | |
| 1382 | ret = se_geni_resources_on(&geni_mas->spi_rsc); |
| 1383 | return ret; |
| 1384 | } |
| 1385 | |
| 1386 | static int spi_geni_resume(struct device *dev) |
| 1387 | { |
| 1388 | return 0; |
| 1389 | } |
| 1390 | |
| 1391 | static int spi_geni_suspend(struct device *dev) |
| 1392 | { |
| 1393 | if (!pm_runtime_status_suspended(dev)) |
| 1394 | return -EBUSY; |
| 1395 | return 0; |
| 1396 | } |
| 1397 | #else |
| 1398 | static int spi_geni_runtime_suspend(struct device *dev) |
| 1399 | { |
| 1400 | return 0; |
| 1401 | } |
| 1402 | |
| 1403 | static int spi_geni_runtime_resume(struct device *dev) |
| 1404 | { |
| 1405 | return 0; |
| 1406 | } |
| 1407 | |
| 1408 | static int spi_geni_resume(struct device *dev) |
| 1409 | { |
| 1410 | return 0; |
| 1411 | } |
| 1412 | |
| 1413 | static int spi_geni_suspend(struct device *dev) |
| 1414 | { |
| 1415 | return 0; |
| 1416 | } |
| 1417 | #endif |
| 1418 | |
| 1419 | static const struct dev_pm_ops spi_geni_pm_ops = { |
| 1420 | SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend, |
| 1421 | spi_geni_runtime_resume, NULL) |
| 1422 | SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume) |
| 1423 | }; |
| 1424 | |
| 1425 | static const struct of_device_id spi_geni_dt_match[] = { |
| 1426 | { .compatible = "qcom,spi-geni" }, |
| 1427 | {} |
| 1428 | }; |
| 1429 | |
| 1430 | static struct platform_driver spi_geni_driver = { |
| 1431 | .probe = spi_geni_probe, |
| 1432 | .remove = spi_geni_remove, |
| 1433 | .driver = { |
| 1434 | .name = "spi_geni", |
| 1435 | .pm = &spi_geni_pm_ops, |
| 1436 | .of_match_table = spi_geni_dt_match, |
| 1437 | }, |
| 1438 | }; |
| 1439 | module_platform_driver(spi_geni_driver); |
| 1440 | |
| 1441 | MODULE_LICENSE("GPL v2"); |
| 1442 | MODULE_ALIAS("platform:spi_geni"); |