Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file contains the 64-bit "server" PowerPC variant |
| 3 | * of the low level exception handling including exception |
| 4 | * vectors, exception return, part of the slb and stab |
| 5 | * handling and other fixed offset specific things. |
| 6 | * |
| 7 | * This file is meant to be #included from head_64.S due to |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 8 | * position dependent assembly. |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 9 | * |
| 10 | * Most of this originates from head_64.S and thus has the same |
| 11 | * copyright history. |
| 12 | * |
| 13 | */ |
| 14 | |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 15 | #include <asm/hw_irq.h> |
Benjamin Herrenschmidt | 8aa34ab | 2009-07-14 20:52:52 +0000 | [diff] [blame] | 16 | #include <asm/exception-64s.h> |
Stephen Rothwell | 46f5221 | 2010-11-18 15:06:17 +0000 | [diff] [blame] | 17 | #include <asm/ptrace.h> |
Shreyas B. Prabhu | 7cba160 | 2014-12-10 00:26:52 +0530 | [diff] [blame] | 18 | #include <asm/cpuidle.h> |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 19 | #include <asm/head-64.h> |
Benjamin Herrenschmidt | 8aa34ab | 2009-07-14 20:52:52 +0000 | [diff] [blame] | 20 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 21 | /* |
Nicholas Piggin | 57f2664 | 2016-09-28 11:31:48 +1000 | [diff] [blame] | 22 | * There are a few constraints to be concerned with. |
| 23 | * - Real mode exceptions code/data must be located at their physical location. |
| 24 | * - Virtual mode exceptions must be mapped at their 0xc000... location. |
| 25 | * - Fixed location code must not call directly beyond the __end_interrupts |
| 26 | * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence |
| 27 | * must be used. |
| 28 | * - LOAD_HANDLER targets must be within first 64K of physical 0 / |
| 29 | * virtual 0xc00... |
| 30 | * - Conditional branch targets must be within +/-32K of caller. |
| 31 | * |
| 32 | * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and |
| 33 | * therefore don't have to run in physically located code or rfid to |
| 34 | * virtual mode kernel code. However on relocatable kernels they do have |
| 35 | * to branch to KERNELBASE offset because the rest of the kernel (outside |
| 36 | * the exception vectors) may be located elsewhere. |
| 37 | * |
| 38 | * Virtual exceptions correspond with physical, except their entry points |
| 39 | * are offset by 0xc000000000000000 and also tend to get an added 0x4000 |
| 40 | * offset applied. Virtual exceptions are enabled with the Alternate |
| 41 | * Interrupt Location (AIL) bit set in the LPCR. However this does not |
| 42 | * guarantee they will be delivered virtually. Some conditions (see the ISA) |
| 43 | * cause exceptions to be delivered in real mode. |
| 44 | * |
| 45 | * It's impossible to receive interrupts below 0x300 via AIL. |
| 46 | * |
| 47 | * KVM: None of the virtual exceptions are from the guest. Anything that |
| 48 | * escalated to HV=1 from HV=0 is delivered via real mode handlers. |
| 49 | * |
| 50 | * |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 51 | * We layout physical memory as follows: |
| 52 | * 0x0000 - 0x00ff : Secondary processor spin code |
Nicholas Piggin | 57f2664 | 2016-09-28 11:31:48 +1000 | [diff] [blame] | 53 | * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors |
| 54 | * 0x1900 - 0x3fff : Real mode trampolines |
| 55 | * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors |
| 56 | * 0x5900 - 0x6fff : Relon mode trampolines |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 57 | * 0x7000 - 0x7fff : FWNMI data area |
Nicholas Piggin | 57f2664 | 2016-09-28 11:31:48 +1000 | [diff] [blame] | 58 | * 0x8000 - .... : Common interrupt handlers, remaining early |
| 59 | * setup code, rest of kernel. |
Nicholas Piggin | e031982 | 2016-09-21 17:44:07 +1000 | [diff] [blame] | 60 | * |
| 61 | * We could reclaim 0x4000-0x42ff for real mode trampolines if the space |
| 62 | * is necessary. Until then it's more consistent to explicitly put VIRT_NONE |
| 63 | * vectors there. |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 64 | */ |
Nicholas Piggin | 57f2664 | 2016-09-28 11:31:48 +1000 | [diff] [blame] | 65 | OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) |
| 66 | OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) |
| 67 | OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) |
| 68 | OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) |
| 69 | #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) |
| 70 | /* |
| 71 | * Data area reserved for FWNMI option. |
| 72 | * This address (0x7000) is fixed by the RPA. |
| 73 | * pseries and powernv need to keep the whole page from |
| 74 | * 0x7000 to 0x8000 free for use by the firmware |
| 75 | */ |
| 76 | ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) |
| 77 | OPEN_TEXT_SECTION(0x8000) |
| 78 | #else |
| 79 | OPEN_TEXT_SECTION(0x7000) |
| 80 | #endif |
| 81 | |
| 82 | USE_FIXED_SECTION(real_vectors) |
| 83 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 84 | /* |
| 85 | * This is the start of the interrupt handlers for pSeries |
| 86 | * This code runs with relocation off. |
| 87 | * Code from here to __end_interrupts gets copied down to real |
| 88 | * address 0x100 when we are running a relocatable kernel. |
| 89 | * Therefore any relative branches in this section must only |
| 90 | * branch to labels in this section. |
| 91 | */ |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 92 | .globl __start_interrupts |
| 93 | __start_interrupts: |
| 94 | |
Nicholas Piggin | e031982 | 2016-09-21 17:44:07 +1000 | [diff] [blame] | 95 | /* No virt vectors corresponding with 0x0..0x100 */ |
| 96 | EXC_VIRT_NONE(0x4000, 0x4100) |
| 97 | |
Nicholas Piggin | fb479e4 | 2016-10-13 13:17:14 +1100 | [diff] [blame] | 98 | |
| 99 | #ifdef CONFIG_PPC_P7_NAP |
| 100 | /* |
| 101 | * If running native on arch 2.06 or later, check if we are waking up |
| 102 | * from nap/sleep/winkle, and branch to idle handler. |
| 103 | */ |
| 104 | #define IDLETEST(n) \ |
| 105 | BEGIN_FTR_SECTION ; \ |
| 106 | mfspr r10,SPRN_SRR1 ; \ |
| 107 | rlwinm. r10,r10,47-31,30,31 ; \ |
| 108 | beq- 1f ; \ |
| 109 | cmpwi cr3,r10,2 ; \ |
| 110 | BRANCH_TO_COMMON(r10, system_reset_idle_common) ; \ |
| 111 | 1: \ |
| 112 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
| 113 | #else |
| 114 | #define IDLETEST NOTEST |
| 115 | #endif |
| 116 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 117 | EXC_REAL_BEGIN(system_reset, 0x100, 0x200) |
Benjamin Herrenschmidt | 948cf67 | 2011-01-24 18:42:41 +1100 | [diff] [blame] | 118 | SET_SCRATCH0(r13) |
Nicholas Piggin | f23ed16 | 2016-11-02 17:57:01 +1100 | [diff] [blame] | 119 | GET_PACA(r13) |
| 120 | clrrdi r13,r13,1 /* Last bit of HSPRG0 is set if waking from winkle */ |
| 121 | EXCEPTION_PROLOG_PSERIES_PACA(PACA_EXGEN, system_reset_common, EXC_STD, |
Nicholas Piggin | fb479e4 | 2016-10-13 13:17:14 +1100 | [diff] [blame] | 122 | IDLETEST, 0x100) |
Paul Mackerras | 371fefd | 2011-06-29 00:23:08 +0000 | [diff] [blame] | 123 | |
Nicholas Piggin | fb479e4 | 2016-10-13 13:17:14 +1100 | [diff] [blame] | 124 | EXC_REAL_END(system_reset, 0x100, 0x200) |
| 125 | EXC_VIRT_NONE(0x4100, 0x4200) |
| 126 | |
| 127 | #ifdef CONFIG_PPC_P7_NAP |
| 128 | EXC_COMMON_BEGIN(system_reset_idle_common) |
Nicholas Piggin | f23ed16 | 2016-11-02 17:57:01 +1100 | [diff] [blame] | 129 | BEGIN_FTR_SECTION |
| 130 | GET_PACA(r13) /* Restore HSPRG0 to get the winkle bit in r13 */ |
| 131 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) |
Shreyas B. Prabhu | 5fa6b6b | 2016-07-08 11:50:46 +0530 | [diff] [blame] | 132 | bl pnv_restore_hyp_resource |
Shreyas B. Prabhu | 77b54e9 | 2014-12-10 00:26:53 +0530 | [diff] [blame] | 133 | |
Shreyas B. Prabhu | 7cba160 | 2014-12-10 00:26:52 +0530 | [diff] [blame] | 134 | li r0,PNV_THREAD_RUNNING |
| 135 | stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */ |
Paul Mackerras | 371fefd | 2011-06-29 00:23:08 +0000 | [diff] [blame] | 136 | |
Aneesh Kumar K.V | 3a167bea | 2013-10-07 22:17:53 +0530 | [diff] [blame] | 137 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
Paul Mackerras | f0888f7 | 2012-02-03 00:54:17 +0000 | [diff] [blame] | 138 | li r0,KVM_HWTHREAD_IN_KERNEL |
| 139 | stb r0,HSTATE_HWTHREAD_STATE(r13) |
| 140 | /* Order setting hwthread_state vs. testing hwthread_req */ |
| 141 | sync |
| 142 | lbz r0,HSTATE_HWTHREAD_REQ(r13) |
| 143 | cmpwi r0,0 |
| 144 | beq 1f |
Paul Mackerras | 371fefd | 2011-06-29 00:23:08 +0000 | [diff] [blame] | 145 | b kvm_start_guest |
| 146 | 1: |
| 147 | #endif |
| 148 | |
Paul Mackerras | 56548fc | 2014-12-03 14:48:40 +1100 | [diff] [blame] | 149 | /* Return SRR1 from power7_nap() */ |
| 150 | mfspr r3,SPRN_SRR1 |
Shreyas B. Prabhu | 1706567 | 2016-07-08 11:50:44 +0530 | [diff] [blame] | 151 | blt cr3,2f |
Shreyas B. Prabhu | 5fa6b6b | 2016-07-08 11:50:46 +0530 | [diff] [blame] | 152 | b pnv_wakeup_loss |
| 153 | 2: b pnv_wakeup_noloss |
Nicholas Piggin | fb479e4 | 2016-10-13 13:17:14 +1100 | [diff] [blame] | 154 | #endif |
Vaidyanathan Srinivasan | aca79d2 | 2014-02-26 05:38:25 +0530 | [diff] [blame] | 155 | |
Nicholas Piggin | 582baf4 | 2016-09-21 17:43:30 +1000 | [diff] [blame] | 156 | EXC_COMMON(system_reset_common, 0x100, system_reset_exception) |
| 157 | |
| 158 | #ifdef CONFIG_PPC_PSERIES |
| 159 | /* |
| 160 | * Vectors for the FWNMI option. Share common code. |
| 161 | */ |
| 162 | TRAMP_REAL_BEGIN(system_reset_fwnmi) |
| 163 | SET_SCRATCH0(r13) /* save r13 */ |
| 164 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, |
| 165 | NOTEST, 0x100) |
| 166 | #endif /* CONFIG_PPC_PSERIES */ |
| 167 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 168 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 169 | EXC_REAL_BEGIN(machine_check, 0x200, 0x300) |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 170 | /* This is moved out of line as it can be patched by FW, but |
| 171 | * some code path might still want to branch into the original |
| 172 | * vector |
| 173 | */ |
Paul Mackerras | 1707dd1 | 2013-02-04 18:10:15 +0000 | [diff] [blame] | 174 | SET_SCRATCH0(r13) /* save r13 */ |
Mahesh Salgaonkar | bc14c49 | 2016-08-05 17:34:13 +0530 | [diff] [blame] | 175 | /* |
| 176 | * Running native on arch 2.06 or later, we may wakeup from winkle |
Nicholas Piggin | f23ed16 | 2016-11-02 17:57:01 +1100 | [diff] [blame] | 177 | * inside machine check. If yes, then last bit of HSPRG0 would be set |
Mahesh Salgaonkar | bc14c49 | 2016-08-05 17:34:13 +0530 | [diff] [blame] | 178 | * to 1. Hence clear it unconditionally. |
Mahesh Salgaonkar | 1c51089 | 2013-10-30 20:04:31 +0530 | [diff] [blame] | 179 | */ |
Mahesh Salgaonkar | bc14c49 | 2016-08-05 17:34:13 +0530 | [diff] [blame] | 180 | GET_PACA(r13) |
| 181 | clrrdi r13,r13,1 |
| 182 | SET_PACA(r13) |
Paul Mackerras | 1707dd1 | 2013-02-04 18:10:15 +0000 | [diff] [blame] | 183 | EXCEPTION_PROLOG_0(PACA_EXMC) |
Mahesh Salgaonkar | 1e9b450 | 2013-10-30 20:04:08 +0530 | [diff] [blame] | 184 | BEGIN_FTR_SECTION |
Mahesh Salgaonkar | 2513767 | 2016-03-01 11:17:46 +0530 | [diff] [blame] | 185 | b machine_check_powernv_early |
Mahesh Salgaonkar | 1e9b450 | 2013-10-30 20:04:08 +0530 | [diff] [blame] | 186 | FTR_SECTION_ELSE |
Paul Mackerras | 1707dd1 | 2013-02-04 18:10:15 +0000 | [diff] [blame] | 187 | b machine_check_pSeries_0 |
Mahesh Salgaonkar | 1e9b450 | 2013-10-30 20:04:08 +0530 | [diff] [blame] | 188 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 189 | EXC_REAL_END(machine_check, 0x200, 0x300) |
Nicholas Piggin | afcf009 | 2016-09-21 17:43:31 +1000 | [diff] [blame] | 190 | EXC_VIRT_NONE(0x4200, 0x4300) |
| 191 | TRAMP_REAL_BEGIN(machine_check_powernv_early) |
| 192 | BEGIN_FTR_SECTION |
| 193 | EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200) |
| 194 | /* |
| 195 | * Register contents: |
| 196 | * R13 = PACA |
| 197 | * R9 = CR |
| 198 | * Original R9 to R13 is saved on PACA_EXMC |
| 199 | * |
| 200 | * Switch to mc_emergency stack and handle re-entrancy (we limit |
| 201 | * the nested MCE upto level 4 to avoid stack overflow). |
| 202 | * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 |
| 203 | * |
| 204 | * We use paca->in_mce to check whether this is the first entry or |
| 205 | * nested machine check. We increment paca->in_mce to track nested |
| 206 | * machine checks. |
| 207 | * |
| 208 | * If this is the first entry then set stack pointer to |
| 209 | * paca->mc_emergency_sp, otherwise r1 is already pointing to |
| 210 | * stack frame on mc_emergency stack. |
| 211 | * |
| 212 | * NOTE: We are here with MSR_ME=0 (off), which means we risk a |
| 213 | * checkstop if we get another machine check exception before we do |
| 214 | * rfid with MSR_ME=1. |
| 215 | */ |
| 216 | mr r11,r1 /* Save r1 */ |
| 217 | lhz r10,PACA_IN_MCE(r13) |
| 218 | cmpwi r10,0 /* Are we in nested machine check */ |
| 219 | bne 0f /* Yes, we are. */ |
| 220 | /* First machine check entry */ |
| 221 | ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ |
| 222 | 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ |
| 223 | addi r10,r10,1 /* increment paca->in_mce */ |
| 224 | sth r10,PACA_IN_MCE(r13) |
| 225 | /* Limit nested MCE to level 4 to avoid stack overflow */ |
| 226 | cmpwi r10,4 |
| 227 | bgt 2f /* Check if we hit limit of 4 */ |
| 228 | std r11,GPR1(r1) /* Save r1 on the stack. */ |
| 229 | std r11,0(r1) /* make stack chain pointer */ |
| 230 | mfspr r11,SPRN_SRR0 /* Save SRR0 */ |
| 231 | std r11,_NIP(r1) |
| 232 | mfspr r11,SPRN_SRR1 /* Save SRR1 */ |
| 233 | std r11,_MSR(r1) |
| 234 | mfspr r11,SPRN_DAR /* Save DAR */ |
| 235 | std r11,_DAR(r1) |
| 236 | mfspr r11,SPRN_DSISR /* Save DSISR */ |
| 237 | std r11,_DSISR(r1) |
| 238 | std r9,_CCR(r1) /* Save CR in stackframe */ |
| 239 | /* Save r9 through r13 from EXMC save area to stack frame. */ |
| 240 | EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) |
| 241 | mfmsr r11 /* get MSR value */ |
| 242 | ori r11,r11,MSR_ME /* turn on ME bit */ |
| 243 | ori r11,r11,MSR_RI /* turn on RI bit */ |
| 244 | LOAD_HANDLER(r12, machine_check_handle_early) |
| 245 | 1: mtspr SPRN_SRR0,r12 |
| 246 | mtspr SPRN_SRR1,r11 |
Nicholas Piggin | efe8bc0 | 2018-02-22 23:35:44 +1100 | [diff] [blame] | 247 | RFI_TO_KERNEL |
Nicholas Piggin | afcf009 | 2016-09-21 17:43:31 +1000 | [diff] [blame] | 248 | b . /* prevent speculative execution */ |
| 249 | 2: |
| 250 | /* Stack overflow. Stay on emergency stack and panic. |
| 251 | * Keep the ME bit off while panic-ing, so that if we hit |
| 252 | * another machine check we checkstop. |
| 253 | */ |
| 254 | addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ |
| 255 | ld r11,PACAKMSR(r13) |
| 256 | LOAD_HANDLER(r12, unrecover_mce) |
| 257 | li r10,MSR_ME |
| 258 | andc r11,r11,r10 /* Turn off MSR_ME */ |
| 259 | b 1b |
| 260 | b . /* prevent speculative execution */ |
| 261 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) |
| 262 | |
| 263 | TRAMP_REAL_BEGIN(machine_check_pSeries) |
| 264 | .globl machine_check_fwnmi |
| 265 | machine_check_fwnmi: |
| 266 | SET_SCRATCH0(r13) /* save r13 */ |
| 267 | EXCEPTION_PROLOG_0(PACA_EXMC) |
| 268 | machine_check_pSeries_0: |
| 269 | EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200) |
| 270 | /* |
| 271 | * The following is essentially EXCEPTION_PROLOG_PSERIES_1 with the |
| 272 | * difference that MSR_RI is not enabled, because PACA_EXMC is being |
| 273 | * used, so nested machine check corrupts it. machine_check_common |
| 274 | * enables MSR_RI. |
| 275 | */ |
| 276 | ld r10,PACAKMSR(r13) |
| 277 | xori r10,r10,MSR_RI |
| 278 | mfspr r11,SPRN_SRR0 |
| 279 | LOAD_HANDLER(r12, machine_check_common) |
| 280 | mtspr SPRN_SRR0,r12 |
| 281 | mfspr r12,SPRN_SRR1 |
| 282 | mtspr SPRN_SRR1,r10 |
Nicholas Piggin | efe8bc0 | 2018-02-22 23:35:44 +1100 | [diff] [blame] | 283 | RFI_TO_KERNEL |
Nicholas Piggin | afcf009 | 2016-09-21 17:43:31 +1000 | [diff] [blame] | 284 | b . /* prevent speculative execution */ |
| 285 | |
| 286 | TRAMP_KVM_SKIP(PACA_EXMC, 0x200) |
| 287 | |
| 288 | EXC_COMMON_BEGIN(machine_check_common) |
| 289 | /* |
| 290 | * Machine check is different because we use a different |
| 291 | * save area: PACA_EXMC instead of PACA_EXGEN. |
| 292 | */ |
| 293 | mfspr r10,SPRN_DAR |
| 294 | std r10,PACA_EXMC+EX_DAR(r13) |
| 295 | mfspr r10,SPRN_DSISR |
| 296 | stw r10,PACA_EXMC+EX_DSISR(r13) |
| 297 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) |
| 298 | FINISH_NAP |
| 299 | RECONCILE_IRQ_STATE(r10, r11) |
| 300 | ld r3,PACA_EXMC+EX_DAR(r13) |
| 301 | lwz r4,PACA_EXMC+EX_DSISR(r13) |
| 302 | /* Enable MSR_RI when finished with PACA_EXMC */ |
| 303 | li r10,MSR_RI |
| 304 | mtmsrd r10,1 |
| 305 | std r3,_DAR(r1) |
| 306 | std r4,_DSISR(r1) |
| 307 | bl save_nvgprs |
| 308 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 309 | bl machine_check_exception |
| 310 | b ret_from_except |
| 311 | |
| 312 | #define MACHINE_CHECK_HANDLER_WINDUP \ |
| 313 | /* Clear MSR_RI before setting SRR0 and SRR1. */\ |
| 314 | li r0,MSR_RI; \ |
| 315 | mfmsr r9; /* get MSR value */ \ |
| 316 | andc r9,r9,r0; \ |
| 317 | mtmsrd r9,1; /* Clear MSR_RI */ \ |
| 318 | /* Move original SRR0 and SRR1 into the respective regs */ \ |
| 319 | ld r9,_MSR(r1); \ |
| 320 | mtspr SPRN_SRR1,r9; \ |
| 321 | ld r3,_NIP(r1); \ |
| 322 | mtspr SPRN_SRR0,r3; \ |
| 323 | ld r9,_CTR(r1); \ |
| 324 | mtctr r9; \ |
| 325 | ld r9,_XER(r1); \ |
| 326 | mtxer r9; \ |
| 327 | ld r9,_LINK(r1); \ |
| 328 | mtlr r9; \ |
| 329 | REST_GPR(0, r1); \ |
| 330 | REST_8GPRS(2, r1); \ |
| 331 | REST_GPR(10, r1); \ |
| 332 | ld r11,_CCR(r1); \ |
| 333 | mtcr r11; \ |
| 334 | /* Decrement paca->in_mce. */ \ |
| 335 | lhz r12,PACA_IN_MCE(r13); \ |
| 336 | subi r12,r12,1; \ |
| 337 | sth r12,PACA_IN_MCE(r13); \ |
| 338 | REST_GPR(11, r1); \ |
| 339 | REST_2GPRS(12, r1); \ |
| 340 | /* restore original r1. */ \ |
| 341 | ld r1,GPR1(r1) |
| 342 | |
| 343 | /* |
| 344 | * Handle machine check early in real mode. We come here with |
| 345 | * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. |
| 346 | */ |
| 347 | EXC_COMMON_BEGIN(machine_check_handle_early) |
| 348 | std r0,GPR0(r1) /* Save r0 */ |
| 349 | EXCEPTION_PROLOG_COMMON_3(0x200) |
| 350 | bl save_nvgprs |
| 351 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 352 | bl machine_check_early |
| 353 | std r3,RESULT(r1) /* Save result */ |
| 354 | ld r12,_MSR(r1) |
| 355 | #ifdef CONFIG_PPC_P7_NAP |
| 356 | /* |
| 357 | * Check if thread was in power saving mode. We come here when any |
| 358 | * of the following is true: |
| 359 | * a. thread wasn't in power saving mode |
| 360 | * b. thread was in power saving mode with no state loss, |
| 361 | * supervisor state loss or hypervisor state loss. |
| 362 | * |
| 363 | * Go back to nap/sleep/winkle mode again if (b) is true. |
| 364 | */ |
| 365 | rlwinm. r11,r12,47-31,30,31 /* Was it in power saving mode? */ |
| 366 | beq 4f /* No, it wasn;t */ |
| 367 | /* Thread was in power saving mode. Go back to nap again. */ |
| 368 | cmpwi r11,2 |
| 369 | blt 3f |
| 370 | /* Supervisor/Hypervisor state loss */ |
| 371 | li r0,1 |
| 372 | stb r0,PACA_NAPSTATELOST(r13) |
| 373 | 3: bl machine_check_queue_event |
| 374 | MACHINE_CHECK_HANDLER_WINDUP |
| 375 | GET_PACA(r13) |
| 376 | ld r1,PACAR1(r13) |
| 377 | /* |
| 378 | * Check what idle state this CPU was in and go back to same mode |
| 379 | * again. |
| 380 | */ |
| 381 | lbz r3,PACA_THREAD_IDLE_STATE(r13) |
| 382 | cmpwi r3,PNV_THREAD_NAP |
| 383 | bgt 10f |
| 384 | IDLE_STATE_ENTER_SEQ(PPC_NAP) |
| 385 | /* No return */ |
| 386 | 10: |
| 387 | cmpwi r3,PNV_THREAD_SLEEP |
| 388 | bgt 2f |
| 389 | IDLE_STATE_ENTER_SEQ(PPC_SLEEP) |
| 390 | /* No return */ |
| 391 | |
| 392 | 2: |
| 393 | /* |
| 394 | * Go back to winkle. Please note that this thread was woken up in |
| 395 | * machine check from winkle and have not restored the per-subcore |
Nicholas Piggin | f23ed16 | 2016-11-02 17:57:01 +1100 | [diff] [blame] | 396 | * state. Hence before going back to winkle, set last bit of HSPRG0 |
Nicholas Piggin | afcf009 | 2016-09-21 17:43:31 +1000 | [diff] [blame] | 397 | * to 1. This will make sure that if this thread gets woken up |
| 398 | * again at reset vector 0x100 then it will get chance to restore |
| 399 | * the subcore state. |
| 400 | */ |
| 401 | ori r13,r13,1 |
| 402 | SET_PACA(r13) |
| 403 | IDLE_STATE_ENTER_SEQ(PPC_WINKLE) |
| 404 | /* No return */ |
| 405 | 4: |
| 406 | #endif |
| 407 | /* |
| 408 | * Check if we are coming from hypervisor userspace. If yes then we |
| 409 | * continue in host kernel in V mode to deliver the MC event. |
| 410 | */ |
| 411 | rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ |
| 412 | beq 5f |
| 413 | andi. r11,r12,MSR_PR /* See if coming from user. */ |
| 414 | bne 9f /* continue in V mode if we are. */ |
| 415 | |
| 416 | 5: |
| 417 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
| 418 | /* |
| 419 | * We are coming from kernel context. Check if we are coming from |
| 420 | * guest. if yes, then we can continue. We will fall through |
| 421 | * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. |
| 422 | */ |
| 423 | lbz r11,HSTATE_IN_GUEST(r13) |
| 424 | cmpwi r11,0 /* Check if coming from guest */ |
| 425 | bne 9f /* continue if we are. */ |
| 426 | #endif |
| 427 | /* |
| 428 | * At this point we are not sure about what context we come from. |
| 429 | * Queue up the MCE event and return from the interrupt. |
| 430 | * But before that, check if this is an un-recoverable exception. |
| 431 | * If yes, then stay on emergency stack and panic. |
| 432 | */ |
| 433 | andi. r11,r12,MSR_RI |
| 434 | bne 2f |
| 435 | 1: mfspr r11,SPRN_SRR0 |
| 436 | LOAD_HANDLER(r10,unrecover_mce) |
| 437 | mtspr SPRN_SRR0,r10 |
| 438 | ld r10,PACAKMSR(r13) |
| 439 | /* |
| 440 | * We are going down. But there are chances that we might get hit by |
| 441 | * another MCE during panic path and we may run into unstable state |
| 442 | * with no way out. Hence, turn ME bit off while going down, so that |
| 443 | * when another MCE is hit during panic path, system will checkstop |
| 444 | * and hypervisor will get restarted cleanly by SP. |
| 445 | */ |
| 446 | li r3,MSR_ME |
| 447 | andc r10,r10,r3 /* Turn off MSR_ME */ |
| 448 | mtspr SPRN_SRR1,r10 |
Nicholas Piggin | efe8bc0 | 2018-02-22 23:35:44 +1100 | [diff] [blame] | 449 | RFI_TO_KERNEL |
Nicholas Piggin | afcf009 | 2016-09-21 17:43:31 +1000 | [diff] [blame] | 450 | b . |
| 451 | 2: |
| 452 | /* |
| 453 | * Check if we have successfully handled/recovered from error, if not |
| 454 | * then stay on emergency stack and panic. |
| 455 | */ |
| 456 | ld r3,RESULT(r1) /* Load result */ |
| 457 | cmpdi r3,0 /* see if we handled MCE successfully */ |
| 458 | |
| 459 | beq 1b /* if !handled then panic */ |
| 460 | /* |
| 461 | * Return from MC interrupt. |
| 462 | * Queue up the MCE event so that we can log it later, while |
| 463 | * returning from kernel or opal call. |
| 464 | */ |
| 465 | bl machine_check_queue_event |
| 466 | MACHINE_CHECK_HANDLER_WINDUP |
Nicholas Piggin | efe8bc0 | 2018-02-22 23:35:44 +1100 | [diff] [blame] | 467 | RFI_TO_USER_OR_KERNEL |
Nicholas Piggin | afcf009 | 2016-09-21 17:43:31 +1000 | [diff] [blame] | 468 | 9: |
| 469 | /* Deliver the machine check to host kernel in V mode. */ |
| 470 | MACHINE_CHECK_HANDLER_WINDUP |
| 471 | b machine_check_pSeries |
| 472 | |
| 473 | EXC_COMMON_BEGIN(unrecover_mce) |
| 474 | /* Invoke machine_check_exception to print MCE event and panic. */ |
| 475 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 476 | bl machine_check_exception |
| 477 | /* |
| 478 | * We will not reach here. Even if we did, there is no way out. Call |
| 479 | * unrecoverable_exception and die. |
| 480 | */ |
| 481 | 1: addi r3,r1,STACK_FRAME_OVERHEAD |
| 482 | bl unrecoverable_exception |
| 483 | b 1b |
| 484 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 485 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 486 | EXC_REAL(data_access, 0x300, 0x380) |
Nicholas Piggin | 80795e6 | 2016-09-21 17:43:32 +1000 | [diff] [blame] | 487 | EXC_VIRT(data_access, 0x4300, 0x4380, 0x300) |
| 488 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x300) |
| 489 | |
| 490 | EXC_COMMON_BEGIN(data_access_common) |
| 491 | /* |
| 492 | * Here r13 points to the paca, r9 contains the saved CR, |
| 493 | * SRR0 and SRR1 are saved in r11 and r12, |
| 494 | * r9 - r13 are saved in paca->exgen. |
| 495 | */ |
| 496 | mfspr r10,SPRN_DAR |
| 497 | std r10,PACA_EXGEN+EX_DAR(r13) |
| 498 | mfspr r10,SPRN_DSISR |
| 499 | stw r10,PACA_EXGEN+EX_DSISR(r13) |
| 500 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) |
| 501 | RECONCILE_IRQ_STATE(r10, r11) |
| 502 | ld r12,_MSR(r1) |
| 503 | ld r3,PACA_EXGEN+EX_DAR(r13) |
| 504 | lwz r4,PACA_EXGEN+EX_DSISR(r13) |
| 505 | li r5,0x300 |
| 506 | std r3,_DAR(r1) |
| 507 | std r4,_DSISR(r1) |
| 508 | BEGIN_MMU_FTR_SECTION |
| 509 | b do_hash_page /* Try to handle as hpte fault */ |
| 510 | MMU_FTR_SECTION_ELSE |
| 511 | b handle_page_fault |
| 512 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) |
| 513 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 514 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 515 | EXC_REAL_BEGIN(data_access_slb, 0x380, 0x400) |
Paul Mackerras | 673b189 | 2011-04-05 13:59:58 +1000 | [diff] [blame] | 516 | SET_SCRATCH0(r13) |
Paul Mackerras | 1707dd1 | 2013-02-04 18:10:15 +0000 | [diff] [blame] | 517 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 518 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380) |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 519 | std r3,PACA_EXSLB+EX_R3(r13) |
| 520 | mfspr r3,SPRN_DAR |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 521 | mfspr r12,SPRN_SRR1 |
Paul Mackerras | f0f558b | 2016-09-02 21:49:21 +1000 | [diff] [blame] | 522 | crset 4*cr6+eq |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 523 | #ifndef CONFIG_RELOCATABLE |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 524 | b slb_miss_realmode |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 525 | #else |
| 526 | /* |
Anton Blanchard | ad0289e | 2014-02-04 16:04:52 +1100 | [diff] [blame] | 527 | * We can't just use a direct branch to slb_miss_realmode |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 528 | * because the distance from here to there depends on where |
| 529 | * the kernel ends up being put. |
| 530 | */ |
| 531 | mfctr r11 |
Anton Blanchard | ad0289e | 2014-02-04 16:04:52 +1100 | [diff] [blame] | 532 | LOAD_HANDLER(r10, slb_miss_realmode) |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 533 | mtctr r10 |
| 534 | bctr |
| 535 | #endif |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 536 | EXC_REAL_END(data_access_slb, 0x380, 0x400) |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 537 | |
Nicholas Piggin | 2b9af6e | 2016-09-21 17:43:33 +1000 | [diff] [blame] | 538 | EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x4400) |
| 539 | SET_SCRATCH0(r13) |
| 540 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
| 541 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380) |
| 542 | std r3,PACA_EXSLB+EX_R3(r13) |
| 543 | mfspr r3,SPRN_DAR |
| 544 | mfspr r12,SPRN_SRR1 |
| 545 | crset 4*cr6+eq |
| 546 | #ifndef CONFIG_RELOCATABLE |
| 547 | b slb_miss_realmode |
| 548 | #else |
| 549 | /* |
| 550 | * We can't just use a direct branch to slb_miss_realmode |
| 551 | * because the distance from here to there depends on where |
| 552 | * the kernel ends up being put. |
| 553 | */ |
| 554 | mfctr r11 |
| 555 | LOAD_HANDLER(r10, slb_miss_realmode) |
| 556 | mtctr r10 |
| 557 | bctr |
| 558 | #endif |
| 559 | EXC_VIRT_END(data_access_slb, 0x4380, 0x4400) |
| 560 | TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) |
| 561 | |
| 562 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 563 | EXC_REAL(instruction_access, 0x400, 0x480) |
Nicholas Piggin | 27ce77d | 2016-09-21 17:43:34 +1000 | [diff] [blame] | 564 | EXC_VIRT(instruction_access, 0x4400, 0x4480, 0x400) |
| 565 | TRAMP_KVM(PACA_EXGEN, 0x400) |
| 566 | |
| 567 | EXC_COMMON_BEGIN(instruction_access_common) |
| 568 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) |
| 569 | RECONCILE_IRQ_STATE(r10, r11) |
| 570 | ld r12,_MSR(r1) |
| 571 | ld r3,_NIP(r1) |
| 572 | andis. r4,r12,0x5820 |
| 573 | li r5,0x400 |
| 574 | std r3,_DAR(r1) |
| 575 | std r4,_DSISR(r1) |
| 576 | BEGIN_MMU_FTR_SECTION |
| 577 | b do_hash_page /* Try to handle as hpte fault */ |
| 578 | MMU_FTR_SECTION_ELSE |
| 579 | b handle_page_fault |
| 580 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) |
| 581 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 582 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 583 | EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x500) |
Paul Mackerras | 673b189 | 2011-04-05 13:59:58 +1000 | [diff] [blame] | 584 | SET_SCRATCH0(r13) |
Paul Mackerras | 1707dd1 | 2013-02-04 18:10:15 +0000 | [diff] [blame] | 585 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 586 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480) |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 587 | std r3,PACA_EXSLB+EX_R3(r13) |
| 588 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 589 | mfspr r12,SPRN_SRR1 |
Paul Mackerras | f0f558b | 2016-09-02 21:49:21 +1000 | [diff] [blame] | 590 | crclr 4*cr6+eq |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 591 | #ifndef CONFIG_RELOCATABLE |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 592 | b slb_miss_realmode |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 593 | #else |
| 594 | mfctr r11 |
Anton Blanchard | ad0289e | 2014-02-04 16:04:52 +1100 | [diff] [blame] | 595 | LOAD_HANDLER(r10, slb_miss_realmode) |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 596 | mtctr r10 |
| 597 | bctr |
| 598 | #endif |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 599 | EXC_REAL_END(instruction_access_slb, 0x480, 0x500) |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 600 | |
Nicholas Piggin | 8d04631 | 2016-09-21 17:43:35 +1000 | [diff] [blame] | 601 | EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x4500) |
| 602 | SET_SCRATCH0(r13) |
| 603 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
| 604 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480) |
| 605 | std r3,PACA_EXSLB+EX_R3(r13) |
| 606 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ |
| 607 | mfspr r12,SPRN_SRR1 |
| 608 | crclr 4*cr6+eq |
| 609 | #ifndef CONFIG_RELOCATABLE |
| 610 | b slb_miss_realmode |
| 611 | #else |
| 612 | mfctr r11 |
| 613 | LOAD_HANDLER(r10, slb_miss_realmode) |
| 614 | mtctr r10 |
| 615 | bctr |
| 616 | #endif |
| 617 | EXC_VIRT_END(instruction_access_slb, 0x4480, 0x4500) |
| 618 | TRAMP_KVM(PACA_EXSLB, 0x480) |
| 619 | |
| 620 | |
| 621 | /* This handler is used by both 0x380 and 0x480 slb miss interrupts */ |
| 622 | EXC_COMMON_BEGIN(slb_miss_realmode) |
| 623 | /* |
| 624 | * r13 points to the PACA, r9 contains the saved CR, |
| 625 | * r12 contain the saved SRR1, SRR0 is still ready for return |
| 626 | * r3 has the faulting address |
| 627 | * r9 - r13 are saved in paca->exslb. |
| 628 | * r3 is saved in paca->slb_r3 |
| 629 | * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss |
| 630 | * We assume we aren't going to take any exceptions during this |
| 631 | * procedure. |
| 632 | */ |
| 633 | mflr r10 |
| 634 | #ifdef CONFIG_RELOCATABLE |
| 635 | mtctr r11 |
| 636 | #endif |
| 637 | |
| 638 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ |
| 639 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ |
| 640 | std r3,PACA_EXSLB+EX_DAR(r13) |
| 641 | |
| 642 | crset 4*cr0+eq |
| 643 | #ifdef CONFIG_PPC_STD_MMU_64 |
| 644 | BEGIN_MMU_FTR_SECTION |
| 645 | bl slb_allocate_realmode |
| 646 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX) |
| 647 | #endif |
| 648 | |
| 649 | ld r10,PACA_EXSLB+EX_LR(r13) |
| 650 | ld r3,PACA_EXSLB+EX_R3(r13) |
| 651 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ |
| 652 | mtlr r10 |
| 653 | |
| 654 | beq 8f /* if bad address, make full stack frame */ |
| 655 | |
| 656 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ |
| 657 | beq- 2f |
Nicholas Piggin | 48cc95d | 2018-01-10 03:07:15 +1100 | [diff] [blame] | 658 | andi. r10,r12,MSR_PR /* check for user mode (PR != 0) */ |
| 659 | bne 1f |
Nicholas Piggin | 8d04631 | 2016-09-21 17:43:35 +1000 | [diff] [blame] | 660 | |
| 661 | /* All done -- return from exception. */ |
| 662 | |
| 663 | .machine push |
| 664 | .machine "power4" |
| 665 | mtcrf 0x80,r9 |
| 666 | mtcrf 0x02,r9 /* I/D indication is in cr6 */ |
| 667 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ |
| 668 | .machine pop |
| 669 | |
| 670 | RESTORE_PPR_PACA(PACA_EXSLB, r9) |
| 671 | ld r9,PACA_EXSLB+EX_R9(r13) |
| 672 | ld r10,PACA_EXSLB+EX_R10(r13) |
| 673 | ld r11,PACA_EXSLB+EX_R11(r13) |
| 674 | ld r12,PACA_EXSLB+EX_R12(r13) |
| 675 | ld r13,PACA_EXSLB+EX_R13(r13) |
Nicholas Piggin | 48cc95d | 2018-01-10 03:07:15 +1100 | [diff] [blame] | 676 | RFI_TO_KERNEL |
| 677 | b . /* prevent speculative execution */ |
| 678 | |
| 679 | 1: |
| 680 | .machine push |
| 681 | .machine "power4" |
| 682 | mtcrf 0x80,r9 |
Michael Ellerman | 3146a32 | 2018-02-22 23:35:43 +1100 | [diff] [blame] | 683 | mtcrf 0x02,r9 /* I/D indication is in cr6 */ |
Nicholas Piggin | 48cc95d | 2018-01-10 03:07:15 +1100 | [diff] [blame] | 684 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ |
| 685 | .machine pop |
| 686 | |
| 687 | RESTORE_PPR_PACA(PACA_EXSLB, r9) |
| 688 | ld r9,PACA_EXSLB+EX_R9(r13) |
| 689 | ld r10,PACA_EXSLB+EX_R10(r13) |
| 690 | ld r11,PACA_EXSLB+EX_R11(r13) |
| 691 | ld r12,PACA_EXSLB+EX_R12(r13) |
| 692 | ld r13,PACA_EXSLB+EX_R13(r13) |
| 693 | RFI_TO_USER |
Nicholas Piggin | 8d04631 | 2016-09-21 17:43:35 +1000 | [diff] [blame] | 694 | b . /* prevent speculative execution */ |
| 695 | |
| 696 | 2: mfspr r11,SPRN_SRR0 |
| 697 | LOAD_HANDLER(r10,unrecov_slb) |
| 698 | mtspr SPRN_SRR0,r10 |
| 699 | ld r10,PACAKMSR(r13) |
| 700 | mtspr SPRN_SRR1,r10 |
Nicholas Piggin | 48cc95d | 2018-01-10 03:07:15 +1100 | [diff] [blame] | 701 | RFI_TO_KERNEL |
Nicholas Piggin | 8d04631 | 2016-09-21 17:43:35 +1000 | [diff] [blame] | 702 | b . |
| 703 | |
| 704 | 8: mfspr r11,SPRN_SRR0 |
| 705 | LOAD_HANDLER(r10,bad_addr_slb) |
| 706 | mtspr SPRN_SRR0,r10 |
| 707 | ld r10,PACAKMSR(r13) |
| 708 | mtspr SPRN_SRR1,r10 |
Nicholas Piggin | efe8bc0 | 2018-02-22 23:35:44 +1100 | [diff] [blame] | 709 | RFI_TO_KERNEL |
Nicholas Piggin | 8d04631 | 2016-09-21 17:43:35 +1000 | [diff] [blame] | 710 | b . |
| 711 | |
| 712 | EXC_COMMON_BEGIN(unrecov_slb) |
| 713 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) |
| 714 | RECONCILE_IRQ_STATE(r10, r11) |
| 715 | bl save_nvgprs |
| 716 | 1: addi r3,r1,STACK_FRAME_OVERHEAD |
| 717 | bl unrecoverable_exception |
| 718 | b 1b |
| 719 | |
| 720 | EXC_COMMON_BEGIN(bad_addr_slb) |
| 721 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB) |
| 722 | RECONCILE_IRQ_STATE(r10, r11) |
| 723 | ld r3, PACA_EXSLB+EX_DAR(r13) |
| 724 | std r3, _DAR(r1) |
| 725 | beq cr6, 2f |
| 726 | li r10, 0x480 /* fix trap number for I-SLB miss */ |
| 727 | std r10, _TRAP(r1) |
| 728 | 2: bl save_nvgprs |
| 729 | addi r3, r1, STACK_FRAME_OVERHEAD |
| 730 | bl slb_miss_bad_addr |
| 731 | b ret_from_except |
| 732 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 733 | EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x600) |
Benjamin Herrenschmidt | b3e6b5d | 2011-04-05 14:27:11 +1000 | [diff] [blame] | 734 | .globl hardware_interrupt_hv; |
Benjamin Herrenschmidt | b3e6b5d | 2011-04-05 14:27:11 +1000 | [diff] [blame] | 735 | hardware_interrupt_hv: |
Benjamin Herrenschmidt | a5d4f3a | 2011-04-05 14:20:31 +1000 | [diff] [blame] | 736 | BEGIN_FTR_SECTION |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 737 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 738 | EXC_HV, SOFTEN_TEST_HV) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 739 | do_kvm_H0x500: |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 740 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x502) |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 741 | FTR_SECTION_ELSE |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 742 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, |
Paul Mackerras | 31a40e2 | 2015-11-12 16:44:42 +1100 | [diff] [blame] | 743 | EXC_STD, SOFTEN_TEST_PR) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 744 | do_kvm_0x500: |
Paul Mackerras | de56a94 | 2011-06-29 00:21:34 +0000 | [diff] [blame] | 745 | KVM_HANDLER(PACA_EXGEN, EXC_STD, 0x500) |
Paul Mackerras | 969391c | 2011-06-29 00:26:11 +0000 | [diff] [blame] | 746 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 747 | EXC_REAL_END(hardware_interrupt, 0x500, 0x600) |
Benjamin Herrenschmidt | a5d4f3a | 2011-04-05 14:20:31 +1000 | [diff] [blame] | 748 | |
Nicholas Piggin | c138e58 | 2016-09-21 17:43:36 +1000 | [diff] [blame] | 749 | EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x4600) |
| 750 | .globl hardware_interrupt_relon_hv; |
| 751 | hardware_interrupt_relon_hv: |
| 752 | BEGIN_FTR_SECTION |
| 753 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV) |
| 754 | FTR_SECTION_ELSE |
| 755 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR) |
| 756 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
| 757 | EXC_VIRT_END(hardware_interrupt, 0x4500, 0x4600) |
| 758 | |
| 759 | EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) |
| 760 | |
| 761 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 762 | EXC_REAL(alignment, 0x600, 0x700) |
Nicholas Piggin | f9aa671 | 2016-09-21 17:43:37 +1000 | [diff] [blame] | 763 | EXC_VIRT(alignment, 0x4600, 0x4700, 0x600) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 764 | TRAMP_KVM(PACA_EXGEN, 0x600) |
Nicholas Piggin | f9aa671 | 2016-09-21 17:43:37 +1000 | [diff] [blame] | 765 | EXC_COMMON_BEGIN(alignment_common) |
| 766 | mfspr r10,SPRN_DAR |
| 767 | std r10,PACA_EXGEN+EX_DAR(r13) |
| 768 | mfspr r10,SPRN_DSISR |
| 769 | stw r10,PACA_EXGEN+EX_DSISR(r13) |
| 770 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) |
| 771 | ld r3,PACA_EXGEN+EX_DAR(r13) |
| 772 | lwz r4,PACA_EXGEN+EX_DSISR(r13) |
| 773 | std r3,_DAR(r1) |
| 774 | std r4,_DSISR(r1) |
| 775 | bl save_nvgprs |
| 776 | RECONCILE_IRQ_STATE(r10, r11) |
| 777 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 778 | bl alignment_exception |
| 779 | b ret_from_except |
| 780 | |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 781 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 782 | EXC_REAL(program_check, 0x700, 0x800) |
Nicholas Piggin | 11e8734 | 2016-09-21 17:43:38 +1000 | [diff] [blame] | 783 | EXC_VIRT(program_check, 0x4700, 0x4800, 0x700) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 784 | TRAMP_KVM(PACA_EXGEN, 0x700) |
Nicholas Piggin | 11e8734 | 2016-09-21 17:43:38 +1000 | [diff] [blame] | 785 | EXC_COMMON_BEGIN(program_check_common) |
Cyril Bur | afebf5e | 2017-08-17 20:42:26 +1000 | [diff] [blame] | 786 | /* |
| 787 | * It's possible to receive a TM Bad Thing type program check with |
| 788 | * userspace register values (in particular r1), but with SRR1 reporting |
| 789 | * that we came from the kernel. Normally that would confuse the bad |
| 790 | * stack logic, and we would report a bad kernel stack pointer. Instead |
| 791 | * we switch to the emergency stack if we're taking a TM Bad Thing from |
| 792 | * the kernel. |
| 793 | */ |
| 794 | li r10,MSR_PR /* Build a mask of MSR_PR .. */ |
| 795 | oris r10,r10,0x200000@h /* .. and SRR1_PROGTM */ |
| 796 | and r10,r10,r12 /* Mask SRR1 with that. */ |
| 797 | srdi r10,r10,8 /* Shift it so we can compare */ |
| 798 | cmpldi r10,(0x200000 >> 8) /* .. with an immediate. */ |
| 799 | bne 1f /* If != go to normal path. */ |
| 800 | |
| 801 | /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack */ |
| 802 | andi. r10,r12,MSR_PR; /* Set CR0 correctly for label */ |
| 803 | /* 3 in EXCEPTION_PROLOG_COMMON */ |
| 804 | mr r10,r1 /* Save r1 */ |
| 805 | ld r1,PACAEMERGSP(r13) /* Use emergency stack */ |
| 806 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ |
| 807 | b 3f /* Jump into the macro !! */ |
| 808 | 1: EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) |
Nicholas Piggin | 11e8734 | 2016-09-21 17:43:38 +1000 | [diff] [blame] | 809 | bl save_nvgprs |
| 810 | RECONCILE_IRQ_STATE(r10, r11) |
| 811 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 812 | bl program_check_exception |
| 813 | b ret_from_except |
| 814 | |
Paul Mackerras | a485c70 | 2013-04-25 17:51:40 +0000 | [diff] [blame] | 815 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 816 | EXC_REAL(fp_unavailable, 0x800, 0x900) |
Nicholas Piggin | c78d9b9 | 2016-09-21 17:43:39 +1000 | [diff] [blame] | 817 | EXC_VIRT(fp_unavailable, 0x4800, 0x4900, 0x800) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 818 | TRAMP_KVM(PACA_EXGEN, 0x800) |
Nicholas Piggin | c78d9b9 | 2016-09-21 17:43:39 +1000 | [diff] [blame] | 819 | EXC_COMMON_BEGIN(fp_unavailable_common) |
| 820 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) |
| 821 | bne 1f /* if from user, just load it up */ |
| 822 | bl save_nvgprs |
| 823 | RECONCILE_IRQ_STATE(r10, r11) |
| 824 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 825 | bl kernel_fp_unavailable_exception |
| 826 | BUG_OPCODE |
| 827 | 1: |
| 828 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
| 829 | BEGIN_FTR_SECTION |
| 830 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in |
| 831 | * transaction), go do TM stuff |
| 832 | */ |
| 833 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) |
| 834 | bne- 2f |
| 835 | END_FTR_SECTION_IFSET(CPU_FTR_TM) |
| 836 | #endif |
| 837 | bl load_up_fpu |
| 838 | b fast_exception_return |
| 839 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
| 840 | 2: /* User process was in a transaction */ |
| 841 | bl save_nvgprs |
| 842 | RECONCILE_IRQ_STATE(r10, r11) |
| 843 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 844 | bl fp_unavailable_tm |
| 845 | b ret_from_except |
| 846 | #endif |
| 847 | |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 848 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 849 | EXC_REAL_MASKABLE(decrementer, 0x900, 0x980) |
Nicholas Piggin | 39c0da5 | 2016-09-21 17:43:40 +1000 | [diff] [blame] | 850 | EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x4980, 0x900) |
| 851 | TRAMP_KVM(PACA_EXGEN, 0x900) |
| 852 | EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) |
| 853 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 854 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 855 | EXC_REAL_HV(hdecrementer, 0x980, 0xa00) |
Nicholas Piggin | facc6d7 | 2016-09-21 17:43:41 +1000 | [diff] [blame] | 856 | EXC_VIRT_HV(hdecrementer, 0x4980, 0x4a00, 0x980) |
| 857 | TRAMP_KVM_HV(PACA_EXGEN, 0x980) |
| 858 | EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) |
| 859 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 860 | |
| 861 | EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0xb00) |
Nicholas Piggin | ca24316 | 2016-09-21 17:43:42 +1000 | [diff] [blame] | 862 | EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x4b00, 0xa00) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 863 | TRAMP_KVM(PACA_EXGEN, 0xa00) |
Nicholas Piggin | ca24316 | 2016-09-21 17:43:42 +1000 | [diff] [blame] | 864 | #ifdef CONFIG_PPC_DOORBELL |
| 865 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) |
| 866 | #else |
| 867 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) |
| 868 | #endif |
| 869 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 870 | |
| 871 | EXC_REAL(trap_0b, 0xb00, 0xc00) |
Nicholas Piggin | 341215d | 2016-09-21 17:43:43 +1000 | [diff] [blame] | 872 | EXC_VIRT(trap_0b, 0x4b00, 0x4c00, 0xb00) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 873 | TRAMP_KVM(PACA_EXGEN, 0xb00) |
Nicholas Piggin | 341215d | 2016-09-21 17:43:43 +1000 | [diff] [blame] | 874 | EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) |
| 875 | |
Nicholas Piggin | fb479e4 | 2016-10-13 13:17:14 +1100 | [diff] [blame] | 876 | #define LOAD_SYSCALL_HANDLER(reg) \ |
| 877 | __LOAD_HANDLER(reg, system_call_common) |
Nicholas Piggin | d807ad3 | 2016-09-21 17:43:44 +1000 | [diff] [blame] | 878 | |
| 879 | /* Syscall routine is used twice, in reloc-off and reloc-on paths */ |
| 880 | #define SYSCALL_PSERIES_1 \ |
| 881 | BEGIN_FTR_SECTION \ |
| 882 | cmpdi r0,0x1ebe ; \ |
| 883 | beq- 1f ; \ |
| 884 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ |
| 885 | mr r9,r13 ; \ |
| 886 | GET_PACA(r13) ; \ |
| 887 | mfspr r11,SPRN_SRR0 ; \ |
| 888 | 0: |
| 889 | |
| 890 | #define SYSCALL_PSERIES_2_RFID \ |
| 891 | mfspr r12,SPRN_SRR1 ; \ |
| 892 | LOAD_SYSCALL_HANDLER(r10) ; \ |
| 893 | mtspr SPRN_SRR0,r10 ; \ |
| 894 | ld r10,PACAKMSR(r13) ; \ |
| 895 | mtspr SPRN_SRR1,r10 ; \ |
Nicholas Piggin | efe8bc0 | 2018-02-22 23:35:44 +1100 | [diff] [blame] | 896 | RFI_TO_KERNEL ; \ |
Nicholas Piggin | d807ad3 | 2016-09-21 17:43:44 +1000 | [diff] [blame] | 897 | b . ; /* prevent speculative execution */ |
| 898 | |
| 899 | #define SYSCALL_PSERIES_3 \ |
| 900 | /* Fast LE/BE switch system call */ \ |
| 901 | 1: mfspr r12,SPRN_SRR1 ; \ |
| 902 | xori r12,r12,MSR_LE ; \ |
| 903 | mtspr SPRN_SRR1,r12 ; \ |
Nicholas Piggin | efe8bc0 | 2018-02-22 23:35:44 +1100 | [diff] [blame] | 904 | RFI_TO_USER ; /* return to userspace */ \ |
Nicholas Piggin | d807ad3 | 2016-09-21 17:43:44 +1000 | [diff] [blame] | 905 | b . ; /* prevent speculative execution */ |
| 906 | |
| 907 | #if defined(CONFIG_RELOCATABLE) |
| 908 | /* |
| 909 | * We can't branch directly so we do it via the CTR which |
| 910 | * is volatile across system calls. |
| 911 | */ |
| 912 | #define SYSCALL_PSERIES_2_DIRECT \ |
| 913 | LOAD_SYSCALL_HANDLER(r12) ; \ |
| 914 | mtctr r12 ; \ |
| 915 | mfspr r12,SPRN_SRR1 ; \ |
| 916 | li r10,MSR_RI ; \ |
| 917 | mtmsrd r10,1 ; \ |
| 918 | bctr ; |
| 919 | #else |
| 920 | /* We can branch directly */ |
| 921 | #define SYSCALL_PSERIES_2_DIRECT \ |
| 922 | mfspr r12,SPRN_SRR1 ; \ |
| 923 | li r10,MSR_RI ; \ |
| 924 | mtmsrd r10,1 ; /* Set RI (EE=0) */ \ |
| 925 | b system_call_common ; |
| 926 | #endif |
| 927 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 928 | EXC_REAL_BEGIN(system_call, 0xc00, 0xd00) |
Suresh E. Warrier | 8b91a25 | 2014-11-03 15:46:42 +1100 | [diff] [blame] | 929 | /* |
| 930 | * If CONFIG_KVM_BOOK3S_64_HANDLER is set, save the PPR (on systems |
| 931 | * that support it) before changing to HMT_MEDIUM. That allows the KVM |
| 932 | * code to save that value into the guest state (it is the guest's PPR |
| 933 | * value). Otherwise just change to HMT_MEDIUM as userspace has |
| 934 | * already saved the PPR. |
| 935 | */ |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 936 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
| 937 | SET_SCRATCH0(r13) |
| 938 | GET_PACA(r13) |
| 939 | std r9,PACA_EXGEN+EX_R9(r13) |
Suresh E. Warrier | 8b91a25 | 2014-11-03 15:46:42 +1100 | [diff] [blame] | 940 | OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); |
| 941 | HMT_MEDIUM; |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 942 | std r10,PACA_EXGEN+EX_R10(r13) |
Suresh E. Warrier | 8b91a25 | 2014-11-03 15:46:42 +1100 | [diff] [blame] | 943 | OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r9, CPU_FTR_HAS_PPR); |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 944 | mfcr r9 |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 945 | KVMTEST_PR(0xc00) |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 946 | GET_SCRATCH0(r13) |
Suresh E. Warrier | 8b91a25 | 2014-11-03 15:46:42 +1100 | [diff] [blame] | 947 | #else |
| 948 | HMT_MEDIUM; |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 949 | #endif |
Michael Neuling | 742415d | 2012-11-02 17:16:01 +1100 | [diff] [blame] | 950 | SYSCALL_PSERIES_1 |
| 951 | SYSCALL_PSERIES_2_RFID |
| 952 | SYSCALL_PSERIES_3 |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 953 | EXC_REAL_END(system_call, 0xc00, 0xd00) |
Paul Mackerras | b01c8b5 | 2011-06-29 00:18:26 +0000 | [diff] [blame] | 954 | |
Nicholas Piggin | d807ad3 | 2016-09-21 17:43:44 +1000 | [diff] [blame] | 955 | EXC_VIRT_BEGIN(system_call, 0x4c00, 0x4d00) |
| 956 | HMT_MEDIUM |
| 957 | SYSCALL_PSERIES_1 |
| 958 | SYSCALL_PSERIES_2_DIRECT |
| 959 | SYSCALL_PSERIES_3 |
| 960 | EXC_VIRT_END(system_call, 0x4c00, 0x4d00) |
| 961 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 962 | TRAMP_KVM(PACA_EXGEN, 0xc00) |
| 963 | |
Nicholas Piggin | d807ad3 | 2016-09-21 17:43:44 +1000 | [diff] [blame] | 964 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 965 | EXC_REAL(single_step, 0xd00, 0xe00) |
Nicholas Piggin | bc6675c | 2016-09-21 17:43:45 +1000 | [diff] [blame] | 966 | EXC_VIRT(single_step, 0x4d00, 0x4e00, 0xd00) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 967 | TRAMP_KVM(PACA_EXGEN, 0xd00) |
Nicholas Piggin | bc6675c | 2016-09-21 17:43:45 +1000 | [diff] [blame] | 968 | EXC_COMMON(single_step_common, 0xd00, single_step_exception) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 969 | |
Nicholas Piggin | a33532a | 2016-09-21 17:44:06 +1000 | [diff] [blame] | 970 | EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0xe20) |
Nicholas Piggin | e031982 | 2016-09-21 17:44:07 +1000 | [diff] [blame] | 971 | EXC_VIRT_NONE(0x4e00, 0x4e20) |
Nicholas Piggin | f5c32c1 | 2016-09-21 17:43:46 +1000 | [diff] [blame] | 972 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) |
| 973 | EXC_COMMON_BEGIN(h_data_storage_common) |
| 974 | mfspr r10,SPRN_HDAR |
| 975 | std r10,PACA_EXGEN+EX_DAR(r13) |
| 976 | mfspr r10,SPRN_HDSISR |
| 977 | stw r10,PACA_EXGEN+EX_DSISR(r13) |
| 978 | EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) |
| 979 | bl save_nvgprs |
| 980 | RECONCILE_IRQ_STATE(r10, r11) |
| 981 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 982 | bl unknown_exception |
| 983 | b ret_from_except |
Nicholas Piggin | f5c32c1 | 2016-09-21 17:43:46 +1000 | [diff] [blame] | 984 | |
Paul Mackerras | 1707dd1 | 2013-02-04 18:10:15 +0000 | [diff] [blame] | 985 | |
Nicholas Piggin | a33532a | 2016-09-21 17:44:06 +1000 | [diff] [blame] | 986 | EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0xe40) |
Nicholas Piggin | e031982 | 2016-09-21 17:44:07 +1000 | [diff] [blame] | 987 | EXC_VIRT_NONE(0x4e20, 0x4e40) |
Nicholas Piggin | 82517ca | 2016-09-21 17:43:47 +1000 | [diff] [blame] | 988 | TRAMP_KVM_HV(PACA_EXGEN, 0xe20) |
| 989 | EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) |
| 990 | |
Paul Mackerras | 1707dd1 | 2013-02-04 18:10:15 +0000 | [diff] [blame] | 991 | |
Nicholas Piggin | a33532a | 2016-09-21 17:44:06 +1000 | [diff] [blame] | 992 | EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0xe60) |
| 993 | EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x4e60, 0xe40) |
Nicholas Piggin | 031b402 | 2016-09-21 17:43:48 +1000 | [diff] [blame] | 994 | TRAMP_KVM_HV(PACA_EXGEN, 0xe40) |
| 995 | EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) |
| 996 | |
Paul Mackerras | 1707dd1 | 2013-02-04 18:10:15 +0000 | [diff] [blame] | 997 | |
Nicholas Piggin | e031982 | 2016-09-21 17:44:07 +1000 | [diff] [blame] | 998 | /* |
| 999 | * hmi_exception trampoline is a special case. It jumps to hmi_exception_early |
| 1000 | * first, and then eventaully from there to the trampoline to get into virtual |
| 1001 | * mode. |
| 1002 | */ |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1003 | __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0xe80, hmi_exception_early) |
Nicholas Piggin | 62f9b03 | 2016-09-21 17:43:49 +1000 | [diff] [blame] | 1004 | __TRAMP_REAL_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60) |
Nicholas Piggin | e031982 | 2016-09-21 17:44:07 +1000 | [diff] [blame] | 1005 | EXC_VIRT_NONE(0x4e60, 0x4e80) |
Nicholas Piggin | 62f9b03 | 2016-09-21 17:43:49 +1000 | [diff] [blame] | 1006 | TRAMP_KVM_HV(PACA_EXGEN, 0xe60) |
| 1007 | TRAMP_REAL_BEGIN(hmi_exception_early) |
| 1008 | EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60) |
| 1009 | mr r10,r1 /* Save r1 */ |
| 1010 | ld r1,PACAEMERGSP(r13) /* Use emergency stack */ |
| 1011 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ |
| 1012 | std r9,_CCR(r1) /* save CR in stackframe */ |
| 1013 | mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ |
| 1014 | std r11,_NIP(r1) /* save HSRR0 in stackframe */ |
| 1015 | mfspr r12,SPRN_HSRR1 /* Save SRR1 */ |
| 1016 | std r12,_MSR(r1) /* save SRR1 in stackframe */ |
| 1017 | std r10,0(r1) /* make stack chain pointer */ |
| 1018 | std r0,GPR0(r1) /* save r0 in stackframe */ |
| 1019 | std r10,GPR1(r1) /* save r1 in stackframe */ |
| 1020 | EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) |
| 1021 | EXCEPTION_PROLOG_COMMON_3(0xe60) |
| 1022 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 1023 | bl hmi_exception_realmode |
| 1024 | /* Windup the stack. */ |
| 1025 | /* Move original HSRR0 and HSRR1 into the respective regs */ |
| 1026 | ld r9,_MSR(r1) |
| 1027 | mtspr SPRN_HSRR1,r9 |
| 1028 | ld r3,_NIP(r1) |
| 1029 | mtspr SPRN_HSRR0,r3 |
| 1030 | ld r9,_CTR(r1) |
| 1031 | mtctr r9 |
| 1032 | ld r9,_XER(r1) |
| 1033 | mtxer r9 |
| 1034 | ld r9,_LINK(r1) |
| 1035 | mtlr r9 |
| 1036 | REST_GPR(0, r1) |
| 1037 | REST_8GPRS(2, r1) |
| 1038 | REST_GPR(10, r1) |
| 1039 | ld r11,_CCR(r1) |
| 1040 | mtcr r11 |
| 1041 | REST_GPR(11, r1) |
| 1042 | REST_2GPRS(12, r1) |
| 1043 | /* restore original r1. */ |
| 1044 | ld r1,GPR1(r1) |
| 1045 | |
| 1046 | /* |
| 1047 | * Go to virtual mode and pull the HMI event information from |
| 1048 | * firmware. |
| 1049 | */ |
| 1050 | .globl hmi_exception_after_realmode |
| 1051 | hmi_exception_after_realmode: |
| 1052 | SET_SCRATCH0(r13) |
| 1053 | EXCEPTION_PROLOG_0(PACA_EXGEN) |
| 1054 | b tramp_real_hmi_exception |
| 1055 | |
| 1056 | EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception) |
| 1057 | |
Paul Mackerras | 1707dd1 | 2013-02-04 18:10:15 +0000 | [diff] [blame] | 1058 | |
Nicholas Piggin | a33532a | 2016-09-21 17:44:06 +1000 | [diff] [blame] | 1059 | EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0xea0) |
| 1060 | EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x4ea0, 0xe80) |
Nicholas Piggin | 9bcb81b | 2016-09-21 17:43:50 +1000 | [diff] [blame] | 1061 | TRAMP_KVM_HV(PACA_EXGEN, 0xe80) |
| 1062 | #ifdef CONFIG_PPC_DOORBELL |
| 1063 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) |
| 1064 | #else |
| 1065 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) |
| 1066 | #endif |
| 1067 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1068 | |
Nicholas Piggin | a33532a | 2016-09-21 17:44:06 +1000 | [diff] [blame] | 1069 | EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0xec0) |
| 1070 | EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x4ec0, 0xea0) |
Nicholas Piggin | 7440877 | 2016-09-21 17:43:51 +1000 | [diff] [blame] | 1071 | TRAMP_KVM_HV(PACA_EXGEN, 0xea0) |
| 1072 | EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) |
| 1073 | |
Benjamin Herrenschmidt | 9baaef0a | 2016-07-08 16:37:06 +1000 | [diff] [blame] | 1074 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1075 | EXC_REAL_NONE(0xec0, 0xf00) |
Nicholas Piggin | bda7fea | 2016-09-21 17:43:52 +1000 | [diff] [blame] | 1076 | EXC_VIRT_NONE(0x4ec0, 0x4f00) |
| 1077 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1078 | |
Nicholas Piggin | a33532a | 2016-09-21 17:44:06 +1000 | [diff] [blame] | 1079 | EXC_REAL_OOL(performance_monitor, 0xf00, 0xf20) |
| 1080 | EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x4f20, 0xf00) |
Nicholas Piggin | b1c7f15 | 2016-09-21 17:43:53 +1000 | [diff] [blame] | 1081 | TRAMP_KVM(PACA_EXGEN, 0xf00) |
| 1082 | EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) |
| 1083 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1084 | |
Nicholas Piggin | a33532a | 2016-09-21 17:44:06 +1000 | [diff] [blame] | 1085 | EXC_REAL_OOL(altivec_unavailable, 0xf20, 0xf40) |
| 1086 | EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x4f40, 0xf20) |
Nicholas Piggin | d1a0ca9 | 2016-09-21 17:43:54 +1000 | [diff] [blame] | 1087 | TRAMP_KVM(PACA_EXGEN, 0xf20) |
| 1088 | EXC_COMMON_BEGIN(altivec_unavailable_common) |
| 1089 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) |
| 1090 | #ifdef CONFIG_ALTIVEC |
| 1091 | BEGIN_FTR_SECTION |
| 1092 | beq 1f |
| 1093 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
| 1094 | BEGIN_FTR_SECTION_NESTED(69) |
| 1095 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in |
| 1096 | * transaction), go do TM stuff |
| 1097 | */ |
| 1098 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) |
| 1099 | bne- 2f |
| 1100 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) |
| 1101 | #endif |
| 1102 | bl load_up_altivec |
| 1103 | b fast_exception_return |
| 1104 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
| 1105 | 2: /* User process was in a transaction */ |
| 1106 | bl save_nvgprs |
| 1107 | RECONCILE_IRQ_STATE(r10, r11) |
| 1108 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 1109 | bl altivec_unavailable_tm |
| 1110 | b ret_from_except |
| 1111 | #endif |
| 1112 | 1: |
| 1113 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) |
| 1114 | #endif |
| 1115 | bl save_nvgprs |
| 1116 | RECONCILE_IRQ_STATE(r10, r11) |
| 1117 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 1118 | bl altivec_unavailable_exception |
| 1119 | b ret_from_except |
| 1120 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1121 | |
Nicholas Piggin | a33532a | 2016-09-21 17:44:06 +1000 | [diff] [blame] | 1122 | EXC_REAL_OOL(vsx_unavailable, 0xf40, 0xf60) |
| 1123 | EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x4f60, 0xf40) |
Nicholas Piggin | 792cbdd | 2016-09-21 17:43:55 +1000 | [diff] [blame] | 1124 | TRAMP_KVM(PACA_EXGEN, 0xf40) |
| 1125 | EXC_COMMON_BEGIN(vsx_unavailable_common) |
| 1126 | EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) |
| 1127 | #ifdef CONFIG_VSX |
| 1128 | BEGIN_FTR_SECTION |
| 1129 | beq 1f |
| 1130 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
| 1131 | BEGIN_FTR_SECTION_NESTED(69) |
| 1132 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in |
| 1133 | * transaction), go do TM stuff |
| 1134 | */ |
| 1135 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) |
| 1136 | bne- 2f |
| 1137 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) |
| 1138 | #endif |
| 1139 | b load_up_vsx |
| 1140 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
| 1141 | 2: /* User process was in a transaction */ |
| 1142 | bl save_nvgprs |
| 1143 | RECONCILE_IRQ_STATE(r10, r11) |
| 1144 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 1145 | bl vsx_unavailable_tm |
| 1146 | b ret_from_except |
| 1147 | #endif |
| 1148 | 1: |
| 1149 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) |
| 1150 | #endif |
| 1151 | bl save_nvgprs |
| 1152 | RECONCILE_IRQ_STATE(r10, r11) |
| 1153 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 1154 | bl vsx_unavailable_exception |
| 1155 | b ret_from_except |
| 1156 | |
Michael Neuling | d0c0c9a | 2013-02-13 16:21:38 +0000 | [diff] [blame] | 1157 | |
Nicholas Piggin | a33532a | 2016-09-21 17:44:06 +1000 | [diff] [blame] | 1158 | EXC_REAL_OOL(facility_unavailable, 0xf60, 0xf80) |
| 1159 | EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x4f80, 0xf60) |
Nicholas Piggin | 1134713 | 2016-09-21 17:43:56 +1000 | [diff] [blame] | 1160 | TRAMP_KVM(PACA_EXGEN, 0xf60) |
| 1161 | EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) |
| 1162 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1163 | |
Nicholas Piggin | a33532a | 2016-09-21 17:44:06 +1000 | [diff] [blame] | 1164 | EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0xfa0) |
| 1165 | EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x4fa0, 0xf80) |
Nicholas Piggin | 14b0072 | 2016-09-21 17:43:57 +1000 | [diff] [blame] | 1166 | TRAMP_KVM_HV(PACA_EXGEN, 0xf80) |
| 1167 | EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) |
| 1168 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1169 | |
| 1170 | EXC_REAL_NONE(0xfa0, 0x1200) |
Nicholas Piggin | e46b964 | 2016-09-21 17:43:58 +1000 | [diff] [blame] | 1171 | EXC_VIRT_NONE(0x4fa0, 0x5200) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1172 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1173 | #ifdef CONFIG_CBE_RAS |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1174 | EXC_REAL_HV(cbe_system_error, 0x1200, 0x1300) |
Nicholas Piggin | ff1b320 | 2016-09-21 17:43:59 +1000 | [diff] [blame] | 1175 | EXC_VIRT_NONE(0x5200, 0x5300) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1176 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) |
Nicholas Piggin | ff1b320 | 2016-09-21 17:43:59 +1000 | [diff] [blame] | 1177 | EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1178 | #else /* CONFIG_CBE_RAS */ |
| 1179 | EXC_REAL_NONE(0x1200, 0x1300) |
Nicholas Piggin | e031982 | 2016-09-21 17:44:07 +1000 | [diff] [blame] | 1180 | EXC_VIRT_NONE(0x5200, 0x5300) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1181 | #endif |
| 1182 | |
Nicholas Piggin | ff1b320 | 2016-09-21 17:43:59 +1000 | [diff] [blame] | 1183 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1184 | EXC_REAL(instruction_breakpoint, 0x1300, 0x1400) |
Nicholas Piggin | 4e96dbb | 2016-09-21 17:44:00 +1000 | [diff] [blame] | 1185 | EXC_VIRT(instruction_breakpoint, 0x5300, 0x5400, 0x1300) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1186 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) |
Nicholas Piggin | 4e96dbb | 2016-09-21 17:44:00 +1000 | [diff] [blame] | 1187 | EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) |
| 1188 | |
Nicholas Piggin | e031982 | 2016-09-21 17:44:07 +1000 | [diff] [blame] | 1189 | EXC_REAL_NONE(0x1400, 0x1500) |
| 1190 | EXC_VIRT_NONE(0x5400, 0x5500) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1191 | |
| 1192 | EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x1600) |
Michael Neuling | b92a66a | 2012-09-10 00:35:26 +0000 | [diff] [blame] | 1193 | mtspr SPRN_SPRG_HSCRATCH0,r13 |
Paul Mackerras | 1707dd1 | 2013-02-04 18:10:15 +0000 | [diff] [blame] | 1194 | EXCEPTION_PROLOG_0(PACA_EXGEN) |
Paul Mackerras | 630573c | 2013-08-12 16:12:06 +1000 | [diff] [blame] | 1195 | EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500) |
Michael Neuling | b92a66a | 2012-09-10 00:35:26 +0000 | [diff] [blame] | 1196 | |
| 1197 | #ifdef CONFIG_PPC_DENORMALISATION |
| 1198 | mfspr r10,SPRN_HSRR1 |
| 1199 | mfspr r11,SPRN_HSRR0 /* save HSRR0 */ |
| 1200 | andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ |
| 1201 | addi r11,r11,-4 /* HSRR0 is next instruction */ |
| 1202 | bne+ denorm_assist |
| 1203 | #endif |
| 1204 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1205 | KVMTEST_PR(0x1500) |
Michael Neuling | b92a66a | 2012-09-10 00:35:26 +0000 | [diff] [blame] | 1206 | EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV) |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1207 | EXC_REAL_END(denorm_exception_hv, 0x1500, 0x1600) |
| 1208 | |
Nicholas Piggin | d7e8984 | 2016-09-21 17:44:01 +1000 | [diff] [blame] | 1209 | #ifdef CONFIG_PPC_DENORMALISATION |
| 1210 | EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x5600) |
| 1211 | b exc_real_0x1500_denorm_exception_hv |
| 1212 | EXC_VIRT_END(denorm_exception, 0x5500, 0x5600) |
| 1213 | #else |
| 1214 | EXC_VIRT_NONE(0x5500, 0x5600) |
| 1215 | #endif |
| 1216 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1217 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500) |
Michael Neuling | b92a66a | 2012-09-10 00:35:26 +0000 | [diff] [blame] | 1218 | |
Michael Neuling | b92a66a | 2012-09-10 00:35:26 +0000 | [diff] [blame] | 1219 | #ifdef CONFIG_PPC_DENORMALISATION |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1220 | TRAMP_REAL_BEGIN(denorm_assist) |
Michael Neuling | b92a66a | 2012-09-10 00:35:26 +0000 | [diff] [blame] | 1221 | BEGIN_FTR_SECTION |
| 1222 | /* |
| 1223 | * To denormalise we need to move a copy of the register to itself. |
| 1224 | * For POWER6 do that here for all FP regs. |
| 1225 | */ |
| 1226 | mfmsr r10 |
| 1227 | ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) |
| 1228 | xori r10,r10,(MSR_FE0|MSR_FE1) |
| 1229 | mtmsrd r10 |
| 1230 | sync |
Michael Neuling | d7c67fb | 2013-05-29 21:33:18 +0000 | [diff] [blame] | 1231 | |
| 1232 | #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 |
| 1233 | #define FMR4(n) FMR2(n) ; FMR2(n+2) |
| 1234 | #define FMR8(n) FMR4(n) ; FMR4(n+4) |
| 1235 | #define FMR16(n) FMR8(n) ; FMR8(n+8) |
| 1236 | #define FMR32(n) FMR16(n) ; FMR16(n+16) |
| 1237 | FMR32(0) |
| 1238 | |
Michael Neuling | b92a66a | 2012-09-10 00:35:26 +0000 | [diff] [blame] | 1239 | FTR_SECTION_ELSE |
| 1240 | /* |
| 1241 | * To denormalise we need to move a copy of the register to itself. |
| 1242 | * For POWER7 do that here for the first 32 VSX registers only. |
| 1243 | */ |
| 1244 | mfmsr r10 |
| 1245 | oris r10,r10,MSR_VSX@h |
| 1246 | mtmsrd r10 |
| 1247 | sync |
Michael Neuling | d7c67fb | 2013-05-29 21:33:18 +0000 | [diff] [blame] | 1248 | |
| 1249 | #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) |
| 1250 | #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) |
| 1251 | #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) |
| 1252 | #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) |
| 1253 | #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) |
| 1254 | XVCPSGNDP32(0) |
| 1255 | |
Michael Neuling | b92a66a | 2012-09-10 00:35:26 +0000 | [diff] [blame] | 1256 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) |
Michael Neuling | fb0fce3 | 2013-05-29 21:33:19 +0000 | [diff] [blame] | 1257 | |
| 1258 | BEGIN_FTR_SECTION |
| 1259 | b denorm_done |
| 1260 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) |
| 1261 | /* |
| 1262 | * To denormalise we need to move a copy of the register to itself. |
| 1263 | * For POWER8 we need to do that for all 64 VSX registers |
| 1264 | */ |
| 1265 | XVCPSGNDP32(32) |
| 1266 | denorm_done: |
Michael Neuling | b92a66a | 2012-09-10 00:35:26 +0000 | [diff] [blame] | 1267 | mtspr SPRN_HSRR0,r11 |
| 1268 | mtcrf 0x80,r9 |
| 1269 | ld r9,PACA_EXGEN+EX_R9(r13) |
Haren Myneni | 44e9309 | 2012-12-06 21:51:04 +0000 | [diff] [blame] | 1270 | RESTORE_PPR_PACA(PACA_EXGEN, r10) |
Paul Mackerras | 630573c | 2013-08-12 16:12:06 +1000 | [diff] [blame] | 1271 | BEGIN_FTR_SECTION |
| 1272 | ld r10,PACA_EXGEN+EX_CFAR(r13) |
| 1273 | mtspr SPRN_CFAR,r10 |
| 1274 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) |
Michael Neuling | b92a66a | 2012-09-10 00:35:26 +0000 | [diff] [blame] | 1275 | ld r10,PACA_EXGEN+EX_R10(r13) |
| 1276 | ld r11,PACA_EXGEN+EX_R11(r13) |
| 1277 | ld r12,PACA_EXGEN+EX_R12(r13) |
| 1278 | ld r13,PACA_EXGEN+EX_R13(r13) |
Nicholas Piggin | efe8bc0 | 2018-02-22 23:35:44 +1100 | [diff] [blame] | 1279 | HRFI_TO_UNKNOWN |
Michael Neuling | b92a66a | 2012-09-10 00:35:26 +0000 | [diff] [blame] | 1280 | b . |
| 1281 | #endif |
| 1282 | |
Nicholas Piggin | d7e8984 | 2016-09-21 17:44:01 +1000 | [diff] [blame] | 1283 | EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception) |
| 1284 | |
| 1285 | |
| 1286 | #ifdef CONFIG_CBE_RAS |
| 1287 | EXC_REAL_HV(cbe_maintenance, 0x1600, 0x1700) |
Nicholas Piggin | 69a7934 | 2016-09-21 17:44:02 +1000 | [diff] [blame] | 1288 | EXC_VIRT_NONE(0x5600, 0x5700) |
Nicholas Piggin | d7e8984 | 2016-09-21 17:44:01 +1000 | [diff] [blame] | 1289 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) |
Nicholas Piggin | 69a7934 | 2016-09-21 17:44:02 +1000 | [diff] [blame] | 1290 | EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) |
Nicholas Piggin | d7e8984 | 2016-09-21 17:44:01 +1000 | [diff] [blame] | 1291 | #else /* CONFIG_CBE_RAS */ |
| 1292 | EXC_REAL_NONE(0x1600, 0x1700) |
Nicholas Piggin | e031982 | 2016-09-21 17:44:07 +1000 | [diff] [blame] | 1293 | EXC_VIRT_NONE(0x5600, 0x5700) |
Nicholas Piggin | d7e8984 | 2016-09-21 17:44:01 +1000 | [diff] [blame] | 1294 | #endif |
| 1295 | |
Nicholas Piggin | 69a7934 | 2016-09-21 17:44:02 +1000 | [diff] [blame] | 1296 | |
Nicholas Piggin | d7e8984 | 2016-09-21 17:44:01 +1000 | [diff] [blame] | 1297 | EXC_REAL(altivec_assist, 0x1700, 0x1800) |
Nicholas Piggin | b51c079 | 2016-09-21 17:44:03 +1000 | [diff] [blame] | 1298 | EXC_VIRT(altivec_assist, 0x5700, 0x5800, 0x1700) |
Nicholas Piggin | d7e8984 | 2016-09-21 17:44:01 +1000 | [diff] [blame] | 1299 | TRAMP_KVM(PACA_EXGEN, 0x1700) |
Nicholas Piggin | b51c079 | 2016-09-21 17:44:03 +1000 | [diff] [blame] | 1300 | #ifdef CONFIG_ALTIVEC |
| 1301 | EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) |
| 1302 | #else |
| 1303 | EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) |
| 1304 | #endif |
| 1305 | |
Nicholas Piggin | d7e8984 | 2016-09-21 17:44:01 +1000 | [diff] [blame] | 1306 | |
| 1307 | #ifdef CONFIG_CBE_RAS |
| 1308 | EXC_REAL_HV(cbe_thermal, 0x1800, 0x1900) |
Nicholas Piggin | 3965f8a | 2016-09-21 17:44:04 +1000 | [diff] [blame] | 1309 | EXC_VIRT_NONE(0x5800, 0x5900) |
Nicholas Piggin | d7e8984 | 2016-09-21 17:44:01 +1000 | [diff] [blame] | 1310 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) |
Nicholas Piggin | 3965f8a | 2016-09-21 17:44:04 +1000 | [diff] [blame] | 1311 | EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) |
Nicholas Piggin | d7e8984 | 2016-09-21 17:44:01 +1000 | [diff] [blame] | 1312 | #else /* CONFIG_CBE_RAS */ |
| 1313 | EXC_REAL_NONE(0x1800, 0x1900) |
Nicholas Piggin | e031982 | 2016-09-21 17:44:07 +1000 | [diff] [blame] | 1314 | EXC_VIRT_NONE(0x5800, 0x5900) |
Nicholas Piggin | d7e8984 | 2016-09-21 17:44:01 +1000 | [diff] [blame] | 1315 | #endif |
| 1316 | |
| 1317 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1318 | /* |
Ian Munsie | fe9e1d5 | 2012-11-14 18:49:48 +0000 | [diff] [blame] | 1319 | * An interrupt came in while soft-disabled. We set paca->irq_happened, then: |
| 1320 | * - If it was a decrementer interrupt, we bump the dec to max and and return. |
| 1321 | * - If it was a doorbell we return immediately since doorbells are edge |
| 1322 | * triggered and won't automatically refire. |
Mahesh Salgaonkar | 0869b6f | 2014-07-29 18:40:01 +0530 | [diff] [blame] | 1323 | * - If it was a HMI we return immediately since we handled it in realmode |
| 1324 | * and it won't refire. |
Ian Munsie | fe9e1d5 | 2012-11-14 18:49:48 +0000 | [diff] [blame] | 1325 | * - else we hard disable and return. |
| 1326 | * This is called with r10 containing the value to OR to the paca field. |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1327 | */ |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1328 | #define MASKED_INTERRUPT(_H) \ |
| 1329 | masked_##_H##interrupt: \ |
| 1330 | std r11,PACA_EXGEN+EX_R11(r13); \ |
| 1331 | lbz r11,PACAIRQHAPPENED(r13); \ |
| 1332 | or r11,r11,r10; \ |
| 1333 | stb r11,PACAIRQHAPPENED(r13); \ |
Ian Munsie | fe9e1d5 | 2012-11-14 18:49:48 +0000 | [diff] [blame] | 1334 | cmpwi r10,PACA_IRQ_DEC; \ |
| 1335 | bne 1f; \ |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1336 | lis r10,0x7fff; \ |
| 1337 | ori r10,r10,0xffff; \ |
| 1338 | mtspr SPRN_DEC,r10; \ |
| 1339 | b 2f; \ |
Ian Munsie | fe9e1d5 | 2012-11-14 18:49:48 +0000 | [diff] [blame] | 1340 | 1: cmpwi r10,PACA_IRQ_DBELL; \ |
| 1341 | beq 2f; \ |
Mahesh Salgaonkar | 0869b6f | 2014-07-29 18:40:01 +0530 | [diff] [blame] | 1342 | cmpwi r10,PACA_IRQ_HMI; \ |
| 1343 | beq 2f; \ |
Ian Munsie | fe9e1d5 | 2012-11-14 18:49:48 +0000 | [diff] [blame] | 1344 | mfspr r10,SPRN_##_H##SRR1; \ |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1345 | rldicl r10,r10,48,1; /* clear MSR_EE */ \ |
| 1346 | rotldi r10,r10,16; \ |
| 1347 | mtspr SPRN_##_H##SRR1,r10; \ |
| 1348 | 2: mtcrf 0x80,r9; \ |
| 1349 | ld r9,PACA_EXGEN+EX_R9(r13); \ |
| 1350 | ld r10,PACA_EXGEN+EX_R10(r13); \ |
| 1351 | ld r11,PACA_EXGEN+EX_R11(r13); \ |
| 1352 | GET_SCRATCH0(r13); \ |
Nicholas Piggin | efe8bc0 | 2018-02-22 23:35:44 +1100 | [diff] [blame] | 1353 | ##_H##RFI_TO_KERNEL; \ |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1354 | b . |
Nicholas Piggin | 57f2664 | 2016-09-28 11:31:48 +1000 | [diff] [blame] | 1355 | |
| 1356 | /* |
| 1357 | * Real mode exceptions actually use this too, but alternate |
| 1358 | * instruction code patches (which end up in the common .text area) |
| 1359 | * cannot reach these if they are put there. |
| 1360 | */ |
| 1361 | USE_FIXED_SECTION(virt_trampolines) |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1362 | MASKED_INTERRUPT() |
| 1363 | MASKED_INTERRUPT(H) |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1364 | |
Paul Mackerras | 4f6c11d | 2013-09-20 14:52:50 +1000 | [diff] [blame] | 1365 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1366 | TRAMP_REAL_BEGIN(kvmppc_skip_interrupt) |
Paul Mackerras | 4f6c11d | 2013-09-20 14:52:50 +1000 | [diff] [blame] | 1367 | /* |
| 1368 | * Here all GPRs are unchanged from when the interrupt happened |
| 1369 | * except for r13, which is saved in SPRG_SCRATCH0. |
| 1370 | */ |
| 1371 | mfspr r13, SPRN_SRR0 |
| 1372 | addi r13, r13, 4 |
| 1373 | mtspr SPRN_SRR0, r13 |
| 1374 | GET_SCRATCH0(r13) |
Nicholas Piggin | efe8bc0 | 2018-02-22 23:35:44 +1100 | [diff] [blame] | 1375 | RFI_TO_KERNEL |
Paul Mackerras | 4f6c11d | 2013-09-20 14:52:50 +1000 | [diff] [blame] | 1376 | b . |
| 1377 | |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1378 | TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) |
Paul Mackerras | 4f6c11d | 2013-09-20 14:52:50 +1000 | [diff] [blame] | 1379 | /* |
| 1380 | * Here all GPRs are unchanged from when the interrupt happened |
| 1381 | * except for r13, which is saved in SPRG_SCRATCH0. |
| 1382 | */ |
| 1383 | mfspr r13, SPRN_HSRR0 |
| 1384 | addi r13, r13, 4 |
| 1385 | mtspr SPRN_HSRR0, r13 |
| 1386 | GET_SCRATCH0(r13) |
Nicholas Piggin | efe8bc0 | 2018-02-22 23:35:44 +1100 | [diff] [blame] | 1387 | HRFI_TO_KERNEL |
Paul Mackerras | 4f6c11d | 2013-09-20 14:52:50 +1000 | [diff] [blame] | 1388 | b . |
| 1389 | #endif |
| 1390 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1391 | /* |
Hari Bathini | 057b6d7 | 2016-04-08 03:30:34 +0530 | [diff] [blame] | 1392 | * Ensure that any handlers that get invoked from the exception prologs |
| 1393 | * above are below the first 64KB (0x10000) of the kernel image because |
| 1394 | * the prologs assemble the addresses of these handlers using the |
| 1395 | * LOAD_HANDLER macro, which uses an ori instruction. |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1396 | */ |
| 1397 | |
| 1398 | /*** Common interrupt handlers ***/ |
| 1399 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1400 | |
Michael Neuling | c1fb681 | 2012-11-02 17:21:43 +1100 | [diff] [blame] | 1401 | /* |
| 1402 | * Relocation-on interrupts: A subset of the interrupts can be delivered |
| 1403 | * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering |
| 1404 | * it. Addresses are the same as the original interrupt addresses, but |
| 1405 | * offset by 0xc000000000004000. |
| 1406 | * It's impossible to receive interrupts below 0x300 via this mechanism. |
| 1407 | * KVM: None of these traps are from the guest ; anything that escalated |
| 1408 | * to HV=1 from HV=0 is delivered via real mode handlers. |
| 1409 | */ |
| 1410 | |
| 1411 | /* |
| 1412 | * This uses the standard macro, since the original 0x300 vector |
| 1413 | * only has extra guff for STAB-based processors -- which never |
| 1414 | * come here. |
| 1415 | */ |
Michael Ellerman | da2bc46 | 2016-09-30 19:43:18 +1000 | [diff] [blame] | 1416 | |
Nicholas Piggin | 57f2664 | 2016-09-28 11:31:48 +1000 | [diff] [blame] | 1417 | EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1418 | b __ppc64_runlatch_on |
Benjamin Herrenschmidt | fe1952f | 2012-03-01 12:45:27 +1100 | [diff] [blame] | 1419 | |
Nicholas Piggin | 57f2664 | 2016-09-28 11:31:48 +1000 | [diff] [blame] | 1420 | USE_FIXED_SECTION(virt_trampolines) |
Hari Bathini | 8ed8ab4 | 2016-04-15 22:48:02 +1000 | [diff] [blame] | 1421 | /* |
| 1422 | * The __end_interrupts marker must be past the out-of-line (OOL) |
| 1423 | * handlers, so that they are copied to real address 0x100 when running |
| 1424 | * a relocatable kernel. This ensures they can be reached from the short |
| 1425 | * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch |
| 1426 | * directly, without using LOAD_HANDLER(). |
| 1427 | */ |
| 1428 | .align 7 |
| 1429 | .globl __end_interrupts |
| 1430 | __end_interrupts: |
Nicholas Piggin | 57f2664 | 2016-09-28 11:31:48 +1000 | [diff] [blame] | 1431 | DEFINE_FIXED_SYMBOL(__end_interrupts) |
Benjamin Herrenschmidt | 6138340 | 2013-01-10 17:44:19 +1100 | [diff] [blame] | 1432 | |
Chen Gang | 087aa03 | 2013-03-25 09:31:31 +0800 | [diff] [blame] | 1433 | #ifdef CONFIG_PPC_970_NAP |
Nicholas Piggin | 7c8cb4b | 2016-10-11 18:47:56 +1100 | [diff] [blame] | 1434 | EXC_COMMON_BEGIN(power4_fixup_nap) |
Chen Gang | 087aa03 | 2013-03-25 09:31:31 +0800 | [diff] [blame] | 1435 | andc r9,r9,r10 |
| 1436 | std r9,TI_LOCAL_FLAGS(r11) |
| 1437 | ld r10,_LINK(r1) /* make idle task do the */ |
| 1438 | std r10,_NIP(r1) /* equivalent of a blr */ |
| 1439 | blr |
| 1440 | #endif |
| 1441 | |
Nicholas Piggin | 57f2664 | 2016-09-28 11:31:48 +1000 | [diff] [blame] | 1442 | CLOSE_FIXED_SECTION(real_vectors); |
| 1443 | CLOSE_FIXED_SECTION(real_trampolines); |
| 1444 | CLOSE_FIXED_SECTION(virt_vectors); |
| 1445 | CLOSE_FIXED_SECTION(virt_trampolines); |
| 1446 | |
| 1447 | USE_TEXT_SECTION() |
| 1448 | |
Chen Gang | 087aa03 | 2013-03-25 09:31:31 +0800 | [diff] [blame] | 1449 | /* |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1450 | * Hash table stuff |
| 1451 | */ |
| 1452 | .align 7 |
Anton Blanchard | 6a3bab9 | 2014-02-04 16:06:11 +1100 | [diff] [blame] | 1453 | do_hash_page: |
Aneesh Kumar K.V | caca285 | 2016-04-29 23:26:07 +1000 | [diff] [blame] | 1454 | #ifdef CONFIG_PPC_STD_MMU_64 |
Naveen N. Rao | 8eaa481 | 2017-06-14 00:12:00 +0530 | [diff] [blame] | 1455 | andis. r0,r4,0xa450 /* weird error? */ |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1456 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
Stuart Yoder | 9778b69 | 2012-07-05 04:41:35 +0000 | [diff] [blame] | 1457 | CURRENT_THREAD_INFO(r11, r1) |
Paul Mackerras | 9c1e105 | 2009-08-17 15:17:54 +1000 | [diff] [blame] | 1458 | lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ |
| 1459 | andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ |
| 1460 | bne 77f /* then don't call hash_page now */ |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1461 | |
| 1462 | /* |
| 1463 | * r3 contains the faulting address |
Aneesh Kumar K.V | 106713a | 2015-12-01 09:06:44 +0530 | [diff] [blame] | 1464 | * r4 msr |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1465 | * r5 contains the trap number |
Aneesh Kumar K.V | aefa568 | 2014-12-04 11:00:14 +0530 | [diff] [blame] | 1466 | * r6 contains dsisr |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1467 | * |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1468 | * at return r3 = 0 for success, 1 for page fault, negative for error |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1469 | */ |
Aneesh Kumar K.V | 106713a | 2015-12-01 09:06:44 +0530 | [diff] [blame] | 1470 | mr r4,r12 |
Aneesh Kumar K.V | aefa568 | 2014-12-04 11:00:14 +0530 | [diff] [blame] | 1471 | ld r6,_DSISR(r1) |
Aneesh Kumar K.V | 106713a | 2015-12-01 09:06:44 +0530 | [diff] [blame] | 1472 | bl __hash_page /* build HPTE if possible */ |
| 1473 | cmpdi r3,0 /* see if __hash_page succeeded */ |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1474 | |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1475 | /* Success */ |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1476 | beq fast_exc_return_irq /* Return from exception on success */ |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1477 | |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 1478 | /* Error */ |
| 1479 | blt- 13f |
Naveen N. Rao | 8eaa481 | 2017-06-14 00:12:00 +0530 | [diff] [blame] | 1480 | |
| 1481 | /* Reload DSISR into r4 for the DABR check below */ |
| 1482 | ld r4,_DSISR(r1) |
Aneesh Kumar K.V | caca285 | 2016-04-29 23:26:07 +1000 | [diff] [blame] | 1483 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1484 | |
Benjamin Herrenschmidt | a546498 | 2012-03-07 16:48:45 +1100 | [diff] [blame] | 1485 | /* Here we have a page fault that hash_page can't handle. */ |
| 1486 | handle_page_fault: |
Naveen N. Rao | 8eaa481 | 2017-06-14 00:12:00 +0530 | [diff] [blame] | 1487 | 11: andis. r0,r4,DSISR_DABRMATCH@h |
| 1488 | bne- handle_dabr_fault |
| 1489 | ld r4,_DAR(r1) |
Benjamin Herrenschmidt | a546498 | 2012-03-07 16:48:45 +1100 | [diff] [blame] | 1490 | ld r5,_DSISR(r1) |
| 1491 | addi r3,r1,STACK_FRAME_OVERHEAD |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1492 | bl do_page_fault |
Benjamin Herrenschmidt | a546498 | 2012-03-07 16:48:45 +1100 | [diff] [blame] | 1493 | cmpdi r3,0 |
| 1494 | beq+ 12f |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1495 | bl save_nvgprs |
Benjamin Herrenschmidt | a546498 | 2012-03-07 16:48:45 +1100 | [diff] [blame] | 1496 | mr r5,r3 |
| 1497 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 1498 | lwz r4,_DAR(r1) |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1499 | bl bad_page_fault |
| 1500 | b ret_from_except |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1501 | |
K.Prasad | 9c7cc23 | 2010-03-29 23:59:25 +0000 | [diff] [blame] | 1502 | /* We have a data breakpoint exception - handle it */ |
| 1503 | handle_dabr_fault: |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1504 | bl save_nvgprs |
K.Prasad | 9c7cc23 | 2010-03-29 23:59:25 +0000 | [diff] [blame] | 1505 | ld r4,_DAR(r1) |
| 1506 | ld r5,_DSISR(r1) |
| 1507 | addi r3,r1,STACK_FRAME_OVERHEAD |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1508 | bl do_break |
| 1509 | 12: b ret_from_except_lite |
K.Prasad | 9c7cc23 | 2010-03-29 23:59:25 +0000 | [diff] [blame] | 1510 | |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1511 | |
Aneesh Kumar K.V | caca285 | 2016-04-29 23:26:07 +1000 | [diff] [blame] | 1512 | #ifdef CONFIG_PPC_STD_MMU_64 |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1513 | /* We have a page fault that hash_page could handle but HV refused |
| 1514 | * the PTE insertion |
| 1515 | */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1516 | 13: bl save_nvgprs |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1517 | mr r5,r3 |
| 1518 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 1519 | ld r4,_DAR(r1) |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1520 | bl low_hash_fault |
| 1521 | b ret_from_except |
Aneesh Kumar K.V | caca285 | 2016-04-29 23:26:07 +1000 | [diff] [blame] | 1522 | #endif |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 1523 | |
Paul Mackerras | 9c1e105 | 2009-08-17 15:17:54 +1000 | [diff] [blame] | 1524 | /* |
| 1525 | * We come here as a result of a DSI at a point where we don't want |
| 1526 | * to call hash_page, such as when we are accessing memory (possibly |
| 1527 | * user memory) inside a PMU interrupt that occurred while interrupts |
| 1528 | * were soft-disabled. We want to invoke the exception handler for |
| 1529 | * the access, or panic if there isn't a handler. |
| 1530 | */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1531 | 77: bl save_nvgprs |
Paul Mackerras | 9c1e105 | 2009-08-17 15:17:54 +1000 | [diff] [blame] | 1532 | mr r4,r3 |
| 1533 | addi r3,r1,STACK_FRAME_OVERHEAD |
| 1534 | li r5,SIGSEGV |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 1535 | bl bad_page_fault |
| 1536 | b ret_from_except |
Michael Ellerman | 4e2bf01 | 2014-07-15 20:25:02 +1000 | [diff] [blame] | 1537 | |
| 1538 | /* |
| 1539 | * Here we have detected that the kernel stack pointer is bad. |
| 1540 | * R9 contains the saved CR, r13 points to the paca, |
| 1541 | * r10 contains the (bad) kernel stack pointer, |
| 1542 | * r11 and r12 contain the saved SRR0 and SRR1. |
| 1543 | * We switch to using an emergency stack, save the registers there, |
| 1544 | * and call kernel_bad_stack(), which panics. |
| 1545 | */ |
| 1546 | bad_stack: |
| 1547 | ld r1,PACAEMERGSP(r13) |
| 1548 | subi r1,r1,64+INT_FRAME_SIZE |
| 1549 | std r9,_CCR(r1) |
| 1550 | std r10,GPR1(r1) |
| 1551 | std r11,_NIP(r1) |
| 1552 | std r12,_MSR(r1) |
| 1553 | mfspr r11,SPRN_DAR |
| 1554 | mfspr r12,SPRN_DSISR |
| 1555 | std r11,_DAR(r1) |
| 1556 | std r12,_DSISR(r1) |
| 1557 | mflr r10 |
| 1558 | mfctr r11 |
| 1559 | mfxer r12 |
| 1560 | std r10,_LINK(r1) |
| 1561 | std r11,_CTR(r1) |
| 1562 | std r12,_XER(r1) |
| 1563 | SAVE_GPR(0,r1) |
| 1564 | SAVE_GPR(2,r1) |
| 1565 | ld r10,EX_R3(r3) |
| 1566 | std r10,GPR3(r1) |
| 1567 | SAVE_GPR(4,r1) |
| 1568 | SAVE_4GPRS(5,r1) |
| 1569 | ld r9,EX_R9(r3) |
| 1570 | ld r10,EX_R10(r3) |
| 1571 | SAVE_2GPRS(9,r1) |
| 1572 | ld r9,EX_R11(r3) |
| 1573 | ld r10,EX_R12(r3) |
| 1574 | ld r11,EX_R13(r3) |
| 1575 | std r9,GPR11(r1) |
| 1576 | std r10,GPR12(r1) |
| 1577 | std r11,GPR13(r1) |
| 1578 | BEGIN_FTR_SECTION |
| 1579 | ld r10,EX_CFAR(r3) |
| 1580 | std r10,ORIG_GPR3(r1) |
| 1581 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) |
| 1582 | SAVE_8GPRS(14,r1) |
| 1583 | SAVE_10GPRS(22,r1) |
| 1584 | lhz r12,PACA_TRAP_SAVE(r13) |
| 1585 | std r12,_TRAP(r1) |
| 1586 | addi r11,r1,INT_FRAME_SIZE |
| 1587 | std r11,0(r1) |
| 1588 | li r12,0 |
| 1589 | std r12,0(r11) |
| 1590 | ld r2,PACATOC(r13) |
| 1591 | ld r11,exception_marker@toc(r2) |
| 1592 | std r12,RESULT(r1) |
| 1593 | std r11,STACK_FRAME_OVERHEAD-16(r1) |
| 1594 | 1: addi r3,r1,STACK_FRAME_OVERHEAD |
| 1595 | bl kernel_bad_stack |
| 1596 | b 1b |
Nicholas Piggin | 0f0c6ca | 2016-09-21 17:44:05 +1000 | [diff] [blame] | 1597 | |
Michael Ellerman | c3b82eb | 2018-01-10 03:07:15 +1100 | [diff] [blame] | 1598 | .globl rfi_flush_fallback |
| 1599 | rfi_flush_fallback: |
| 1600 | SET_SCRATCH0(r13); |
| 1601 | GET_PACA(r13); |
| 1602 | std r9,PACA_EXRFI+EX_R9(r13) |
| 1603 | std r10,PACA_EXRFI+EX_R10(r13) |
| 1604 | std r11,PACA_EXRFI+EX_R11(r13) |
Michael Ellerman | c3b82eb | 2018-01-10 03:07:15 +1100 | [diff] [blame] | 1605 | mfctr r9 |
| 1606 | ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) |
Nicholas Piggin | ec0084d | 2018-02-22 23:35:45 +1100 | [diff] [blame] | 1607 | ld r11,PACA_L1D_FLUSH_SIZE(r13) |
| 1608 | srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ |
Michael Ellerman | c3b82eb | 2018-01-10 03:07:15 +1100 | [diff] [blame] | 1609 | mtctr r11 |
| 1610 | DCBT_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ |
| 1611 | |
| 1612 | /* order ld/st prior to dcbt stop all streams with flushing */ |
| 1613 | sync |
Nicholas Piggin | ec0084d | 2018-02-22 23:35:45 +1100 | [diff] [blame] | 1614 | |
| 1615 | /* |
| 1616 | * The load adresses are at staggered offsets within cachelines, |
| 1617 | * which suits some pipelines better (on others it should not |
| 1618 | * hurt). |
| 1619 | */ |
| 1620 | 1: |
| 1621 | ld r11,(0x80 + 8)*0(r10) |
| 1622 | ld r11,(0x80 + 8)*1(r10) |
| 1623 | ld r11,(0x80 + 8)*2(r10) |
| 1624 | ld r11,(0x80 + 8)*3(r10) |
| 1625 | ld r11,(0x80 + 8)*4(r10) |
| 1626 | ld r11,(0x80 + 8)*5(r10) |
| 1627 | ld r11,(0x80 + 8)*6(r10) |
| 1628 | ld r11,(0x80 + 8)*7(r10) |
| 1629 | addi r10,r10,0x80*8 |
Michael Ellerman | c3b82eb | 2018-01-10 03:07:15 +1100 | [diff] [blame] | 1630 | bdnz 1b |
| 1631 | |
| 1632 | mtctr r9 |
| 1633 | ld r9,PACA_EXRFI+EX_R9(r13) |
| 1634 | ld r10,PACA_EXRFI+EX_R10(r13) |
| 1635 | ld r11,PACA_EXRFI+EX_R11(r13) |
Michael Ellerman | c3b82eb | 2018-01-10 03:07:15 +1100 | [diff] [blame] | 1636 | GET_SCRATCH0(r13); |
| 1637 | rfid |
| 1638 | |
| 1639 | .globl hrfi_flush_fallback |
| 1640 | hrfi_flush_fallback: |
| 1641 | SET_SCRATCH0(r13); |
| 1642 | GET_PACA(r13); |
| 1643 | std r9,PACA_EXRFI+EX_R9(r13) |
| 1644 | std r10,PACA_EXRFI+EX_R10(r13) |
| 1645 | std r11,PACA_EXRFI+EX_R11(r13) |
Michael Ellerman | c3b82eb | 2018-01-10 03:07:15 +1100 | [diff] [blame] | 1646 | mfctr r9 |
| 1647 | ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) |
Nicholas Piggin | ec0084d | 2018-02-22 23:35:45 +1100 | [diff] [blame] | 1648 | ld r11,PACA_L1D_FLUSH_SIZE(r13) |
| 1649 | srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ |
Michael Ellerman | c3b82eb | 2018-01-10 03:07:15 +1100 | [diff] [blame] | 1650 | mtctr r11 |
| 1651 | DCBT_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ |
| 1652 | |
| 1653 | /* order ld/st prior to dcbt stop all streams with flushing */ |
| 1654 | sync |
Nicholas Piggin | ec0084d | 2018-02-22 23:35:45 +1100 | [diff] [blame] | 1655 | |
| 1656 | /* |
| 1657 | * The load adresses are at staggered offsets within cachelines, |
| 1658 | * which suits some pipelines better (on others it should not |
| 1659 | * hurt). |
| 1660 | */ |
| 1661 | 1: |
| 1662 | ld r11,(0x80 + 8)*0(r10) |
| 1663 | ld r11,(0x80 + 8)*1(r10) |
| 1664 | ld r11,(0x80 + 8)*2(r10) |
| 1665 | ld r11,(0x80 + 8)*3(r10) |
| 1666 | ld r11,(0x80 + 8)*4(r10) |
| 1667 | ld r11,(0x80 + 8)*5(r10) |
| 1668 | ld r11,(0x80 + 8)*6(r10) |
| 1669 | ld r11,(0x80 + 8)*7(r10) |
| 1670 | addi r10,r10,0x80*8 |
Michael Ellerman | c3b82eb | 2018-01-10 03:07:15 +1100 | [diff] [blame] | 1671 | bdnz 1b |
| 1672 | |
| 1673 | mtctr r9 |
| 1674 | ld r9,PACA_EXRFI+EX_R9(r13) |
| 1675 | ld r10,PACA_EXRFI+EX_R10(r13) |
| 1676 | ld r11,PACA_EXRFI+EX_R11(r13) |
Michael Ellerman | c3b82eb | 2018-01-10 03:07:15 +1100 | [diff] [blame] | 1677 | GET_SCRATCH0(r13); |
| 1678 | hrfid |
| 1679 | |
Nicholas Piggin | 0f0c6ca | 2016-09-21 17:44:05 +1000 | [diff] [blame] | 1680 | /* |
| 1681 | * Called from arch_local_irq_enable when an interrupt needs |
| 1682 | * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate |
| 1683 | * which kind of interrupt. MSR:EE is already off. We generate a |
| 1684 | * stackframe like if a real interrupt had happened. |
| 1685 | * |
| 1686 | * Note: While MSR:EE is off, we need to make sure that _MSR |
| 1687 | * in the generated frame has EE set to 1 or the exception |
| 1688 | * handler will not properly re-enable them. |
| 1689 | */ |
| 1690 | _GLOBAL(__replay_interrupt) |
| 1691 | /* We are going to jump to the exception common code which |
| 1692 | * will retrieve various register values from the PACA which |
| 1693 | * we don't give a damn about, so we don't bother storing them. |
| 1694 | */ |
| 1695 | mfmsr r12 |
| 1696 | mflr r11 |
| 1697 | mfcr r9 |
| 1698 | ori r12,r12,MSR_EE |
| 1699 | cmpwi r3,0x900 |
| 1700 | beq decrementer_common |
| 1701 | cmpwi r3,0x500 |
| 1702 | beq hardware_interrupt_common |
| 1703 | BEGIN_FTR_SECTION |
| 1704 | cmpwi r3,0xe80 |
| 1705 | beq h_doorbell_common |
| 1706 | cmpwi r3,0xea0 |
| 1707 | beq h_virt_irq_common |
| 1708 | cmpwi r3,0xe60 |
| 1709 | beq hmi_exception_common |
| 1710 | FTR_SECTION_ELSE |
| 1711 | cmpwi r3,0xa00 |
| 1712 | beq doorbell_super_common |
| 1713 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
| 1714 | blr |