Mayank Rana | 511f3b2 | 2016-08-02 12:00:11 -0700 | [diff] [blame^] | 1 | MSM SuperSpeed USB3.0 SoC controller |
| 2 | |
| 3 | Required properties : |
| 4 | - compatible : should be "qcom,dwc-usb3-msm" |
| 5 | - reg: Address and length of the register set for the device |
| 6 | Required regs are: |
| 7 | "core_base" : usb controller register set |
| 8 | - interrupts: IRQ lines used by this controller |
| 9 | - interrupt-names : Interrupt resource entries are : |
| 10 | "hs_phy_irq" : Interrupt from HS PHY for asynchronous events in LPM. |
| 11 | "pwr_event_irq" : Interrupt to controller for asynchronous events in LPM. |
| 12 | Used for SS-USB power events. |
| 13 | - clocks: a list of phandles to the controller clocks. Use as per |
| 14 | Documentation/devicetree/bindings/clock/clock-bindings.txt |
| 15 | - clock-names: Names of the clocks in 1-1 correspondence with the "clocks" |
| 16 | property. Required clocks are "xo", "iface_clk", "core_clk", "sleep_clk" |
| 17 | and "utmi_clk". |
| 18 | |
| 19 | Optional properties : |
| 20 | - reg: Additional registers |
| 21 | "tcsr_base" : top-level CSR register to be written during power-on reset |
| 22 | initialize the internal MUX that controls whether to use USB3 controller |
| 23 | with primary port. |
| 24 | "ahb2phy_base" : top-level register to configure read/write wait cycle with |
| 25 | both QMP and QUSB PHY registers. |
| 26 | - Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for |
| 27 | below optional properties: |
| 28 | - qcom,msm_bus,name |
| 29 | - qcom,msm_bus,num_cases |
| 30 | - qcom,msm_bus,num_paths |
| 31 | - qcom,msm_bus,vectors |
| 32 | - interrupt-names : Optional interrupt resource entries are: |
| 33 | "pmic_id_irq" : Interrupt from PMIC for external ID pin notification. |
| 34 | "ss_phy_irq" : Interrupt from super speed phy for wake up notification. |
| 35 | - clocks: a list of phandles to the controller clocks. Use as per |
| 36 | Documentation/devicetree/bindings/clock/clock-bindings.txt |
| 37 | - clock-names: Names of the clocks in 1-1 correspondence with the "clocks" |
| 38 | property. Optional clocks are "bus_aggr_clk" and "cfg_ahb_clk". |
| 39 | - qcom,charging-disabled: If present then battery charging using USB |
| 40 | is disabled. |
| 41 | - vbus_dwc3-supply: phandle to the 5V VBUS supply regulator used for host mode. |
| 42 | - USB3_GDSC-supply : phandle to the globally distributed switch controller |
| 43 | regulator node to the USB controller. |
| 44 | - qcom,dwc-usb3-msm-tx-fifo-size: If present, represents RAM size available for |
| 45 | TX fifo allocation in bytes |
| 46 | - qcom,usb-dbm : phandle for the DBM device |
| 47 | - qcom,lpm-to-suspend-delay-ms: Indicates timeout (in milliseconds) to release wakeup source |
| 48 | after USB is kept into LPM. |
| 49 | - qcom,ext-hub-reset-gpio: This corresponds to gpio which is used for HUB reset. |
| 50 | - qcom,disable-dev-mode-pm: If present, it disables PM runtime functionality for device mode. |
| 51 | - qcom,disable-host-mode-pm: If present, it disables XHCI PM runtime functionality when USB |
| 52 | host mode is used. |
| 53 | - extcon: phandles to external connector devices. First phandle should point to |
| 54 | external connector, which provide "USB" cable events, the second |
| 55 | should point to external connector device, which provide "USB-HOST" |
| 56 | cable events. A single phandle may be specified if a single connector |
| 57 | device provides both "USB" and "USB-HOST" events. |
| 58 | |
| 59 | Sub nodes: |
| 60 | - Sub node for "DWC3- USB3 controller". |
| 61 | This sub node is required property for device node. The properties of this subnode |
| 62 | are specified in dwc3.txt. |
| 63 | |
| 64 | Example MSM USB3.0 controller device node : |
| 65 | usb@f9200000 { |
| 66 | compatible = "qcom,dwc-usb3-msm"; |
| 67 | reg = <0xf9200000 0xfc000>, |
| 68 | <0xfd4ab000 0x4>, |
| 69 | <0xf9b3e000 0x3ff>; |
| 70 | reg-names = "core_base", |
| 71 | "tcsr_base", |
| 72 | "ahb2phy_base", |
| 73 | interrupts = <0 133 0>; |
| 74 | interrupt-names = "hs_phy_irq"; |
| 75 | vbus_dwc3-supply = <&pm8941_mvs1>; |
| 76 | USB3_GDSC-supply = <&gdsc_usb30>; |
| 77 | qcom,dwc-usb3-msm-dbm-eps = <4> |
| 78 | qcom,dwc_usb3-adc_tm = <&pm8941_adc_tm>; |
| 79 | qcom,dwc-usb3-msm-tx-fifo-size = <29696>; |
| 80 | qcom,usb-dbm = <&dbm_1p4>; |
| 81 | qcom,lpm-to-suspend-delay-ms = <2>; |
| 82 | |
| 83 | qcom,msm_bus,name = "usb3"; |
| 84 | qcom,msm_bus,num_cases = <2>; |
| 85 | qcom,msm_bus,num_paths = <1>; |
| 86 | qcom,msm_bus,vectors = |
| 87 | <61 512 0 0>, |
| 88 | <61 512 240000000 960000000>; |
| 89 | |
| 90 | clocks = <&clock_gcc clk_gcc_usb30_master_clk>, |
| 91 | <&clock_gcc clk_gcc_cfg_noc_usb3_axi_clk>, |
| 92 | <&clock_gcc clk_gcc_aggre1_usb3_axi_clk>, |
| 93 | <&clock_gcc clk_gcc_usb30_mock_utmi_clk>, |
| 94 | <&clock_gcc clk_gcc_usb30_sleep_clk>, |
| 95 | <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>, |
| 96 | <&clock_gcc clk_cxo_dwc3_clk>; |
| 97 | |
| 98 | clock-names = "core_clk", "iface_clk", "bus_aggr_clk", |
| 99 | "utmi_clk", "sleep_clk", "cfg_ahb_clk", "xo"; |
| 100 | |
| 101 | dwc3@f9200000 { |
| 102 | compatible = "synopsys,dwc3"; |
| 103 | reg = <0xf9200000 0xfc000>; |
| 104 | interrupts = <0 131 0>, <0 179 0>; |
| 105 | interrupt-names = "irq", "otg_irq"; |
| 106 | tx-fifo-resize; |
| 107 | }; |
| 108 | }; |