Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 1 | /* |
Robert Richter | 6852fd9 | 2008-07-22 21:09:08 +0200 | [diff] [blame] | 2 | * @file op_model_amd.c |
Barry Kasindorf | bd87f1f | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 3 | * athlon / K7 / K8 / Family 10h model-specific MSR operations |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * |
Robert Richter | ae735e9 | 2008-12-25 17:26:07 +0100 | [diff] [blame] | 5 | * @remark Copyright 2002-2009 OProfile authors |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * @remark Read the file COPYING |
| 7 | * |
| 8 | * @author John Levon |
| 9 | * @author Philippe Elie |
| 10 | * @author Graydon Hoare |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 11 | * @author Robert Richter <robert.richter@amd.com> |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 12 | * @author Barry Kasindorf |
Robert Richter | ae735e9 | 2008-12-25 17:26:07 +0100 | [diff] [blame] | 13 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | |
| 15 | #include <linux/oprofile.h> |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 16 | #include <linux/device.h> |
| 17 | #include <linux/pci.h> |
| 18 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 19 | #include <asm/ptrace.h> |
| 20 | #include <asm/msr.h> |
Don Zickus | 3e4ff11 | 2006-06-26 13:57:01 +0200 | [diff] [blame] | 21 | #include <asm/nmi.h> |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 22 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 23 | #include "op_x86_model.h" |
| 24 | #include "op_counter.h" |
| 25 | |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 26 | #define NUM_COUNTERS 4 |
| 27 | #define NUM_CONTROLS 4 |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 28 | #define OP_EVENT_MASK 0x0FFF |
Robert Richter | 42399ad | 2009-05-25 17:59:06 +0200 | [diff] [blame] | 29 | #define OP_CTR_OVERFLOW (1ULL<<31) |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 30 | |
| 31 | #define MSR_AMD_EVENTSEL_RESERVED ((0xFFFFFCF0ULL<<32)|(1ULL<<21)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 33 | static unsigned long reset_value[NUM_COUNTERS]; |
| 34 | |
| 35 | #ifdef CONFIG_OPROFILE_IBS |
| 36 | |
Robert Richter | 87f0bac | 2008-07-22 21:09:03 +0200 | [diff] [blame] | 37 | /* IbsFetchCtl bits/masks */ |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 38 | #define IBS_FETCH_RAND_EN (1ULL<<57) |
| 39 | #define IBS_FETCH_VAL (1ULL<<49) |
| 40 | #define IBS_FETCH_ENABLE (1ULL<<48) |
| 41 | #define IBS_FETCH_CNT_MASK 0xFFFF0000ULL |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 42 | |
Robert Richter | 87f0bac | 2008-07-22 21:09:03 +0200 | [diff] [blame] | 43 | /*IbsOpCtl bits */ |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 44 | #define IBS_OP_CNT_CTL (1ULL<<19) |
| 45 | #define IBS_OP_VAL (1ULL<<18) |
| 46 | #define IBS_OP_ENABLE (1ULL<<17) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 47 | |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 48 | #define IBS_FETCH_SIZE 6 |
| 49 | #define IBS_OP_SIZE 12 |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 50 | |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 51 | static int has_ibs; /* AMD Family10h and later */ |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 52 | |
| 53 | struct op_ibs_config { |
| 54 | unsigned long op_enabled; |
| 55 | unsigned long fetch_enabled; |
| 56 | unsigned long max_cnt_fetch; |
| 57 | unsigned long max_cnt_op; |
| 58 | unsigned long rand_en; |
| 59 | unsigned long dispatched_ops; |
| 60 | }; |
| 61 | |
| 62 | static struct op_ibs_config ibs_config; |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 63 | |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 64 | #endif |
| 65 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 66 | /* functions for op_amd_spec */ |
Robert Richter | dfa1542 | 2008-07-22 21:08:49 +0200 | [diff] [blame] | 67 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 68 | static void op_amd_fill_in_addresses(struct op_msrs * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 69 | { |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 70 | int i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 71 | |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 72 | for (i = 0; i < NUM_COUNTERS; i++) { |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 73 | if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i)) |
| 74 | msrs->counters[i].addr = MSR_K7_PERFCTR0 + i; |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 75 | else |
| 76 | msrs->counters[i].addr = 0; |
| 77 | } |
| 78 | |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 79 | for (i = 0; i < NUM_CONTROLS; i++) { |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 80 | if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) |
| 81 | msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i; |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 82 | else |
| 83 | msrs->controls[i].addr = 0; |
| 84 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 85 | } |
| 86 | |
Robert Richter | ef8828d | 2009-05-25 19:31:44 +0200 | [diff] [blame] | 87 | static void op_amd_setup_ctrs(struct op_x86_model_spec const *model, |
| 88 | struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 89 | { |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 90 | u64 val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 91 | int i; |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 92 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 93 | /* clear all counters */ |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 94 | for (i = 0 ; i < NUM_CONTROLS; ++i) { |
Robert Richter | 217d3cf | 2009-06-04 02:36:44 +0200 | [diff] [blame] | 95 | if (unlikely(!msrs->controls[i].addr)) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 96 | continue; |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 97 | rdmsrl(msrs->controls[i].addr, val); |
| 98 | val &= model->reserved; |
| 99 | wrmsrl(msrs->controls[i].addr, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 100 | } |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 101 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 102 | /* avoid a false detection of ctr overflows in NMI handler */ |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 103 | for (i = 0; i < NUM_COUNTERS; ++i) { |
Robert Richter | 217d3cf | 2009-06-04 02:36:44 +0200 | [diff] [blame] | 104 | if (unlikely(!msrs->counters[i].addr)) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 105 | continue; |
Robert Richter | bbc5986 | 2009-05-25 17:38:19 +0200 | [diff] [blame] | 106 | wrmsrl(msrs->counters[i].addr, -1LL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 107 | } |
| 108 | |
| 109 | /* enable active counters */ |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 110 | for (i = 0; i < NUM_COUNTERS; ++i) { |
Robert Richter | 217d3cf | 2009-06-04 02:36:44 +0200 | [diff] [blame] | 111 | if (counter_config[i].enabled && msrs->counters[i].addr) { |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 112 | reset_value[i] = counter_config[i].count; |
Robert Richter | bbc5986 | 2009-05-25 17:38:19 +0200 | [diff] [blame] | 113 | wrmsrl(msrs->counters[i].addr, |
| 114 | -(s64)counter_config[i].count); |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 115 | rdmsrl(msrs->controls[i].addr, val); |
| 116 | val &= model->reserved; |
| 117 | val |= op_x86_get_ctrl(model, &counter_config[i]); |
| 118 | wrmsrl(msrs->controls[i].addr, val); |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 119 | } else { |
| 120 | reset_value[i] = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 121 | } |
| 122 | } |
| 123 | } |
| 124 | |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 125 | #ifdef CONFIG_OPROFILE_IBS |
| 126 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 127 | static inline int |
| 128 | op_amd_handle_ibs(struct pt_regs * const regs, |
| 129 | struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 130 | { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 131 | u64 val, ctl; |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 132 | struct op_entry entry; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 133 | |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 134 | if (!has_ibs) |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 135 | return 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 136 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 137 | if (ibs_config.fetch_enabled) { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 138 | rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl); |
| 139 | if (ctl & IBS_FETCH_VAL) { |
| 140 | rdmsrl(MSR_AMD64_IBSFETCHLINAD, val); |
| 141 | oprofile_write_reserve(&entry, regs, val, |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 142 | IBS_FETCH_CODE, IBS_FETCH_SIZE); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame^] | 143 | oprofile_add_data64(&entry, val); |
| 144 | oprofile_add_data64(&entry, ctl); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 145 | rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame^] | 146 | oprofile_add_data64(&entry, val); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 147 | oprofile_write_commit(&entry); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 148 | |
Robert Richter | fd13f6c | 2008-10-19 21:00:09 +0200 | [diff] [blame] | 149 | /* reenable the IRQ */ |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 150 | ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT_MASK); |
| 151 | ctl |= IBS_FETCH_ENABLE; |
| 152 | wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 153 | } |
| 154 | } |
| 155 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 156 | if (ibs_config.op_enabled) { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 157 | rdmsrl(MSR_AMD64_IBSOPCTL, ctl); |
| 158 | if (ctl & IBS_OP_VAL) { |
| 159 | rdmsrl(MSR_AMD64_IBSOPRIP, val); |
| 160 | oprofile_write_reserve(&entry, regs, val, |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 161 | IBS_OP_CODE, IBS_OP_SIZE); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame^] | 162 | oprofile_add_data64(&entry, val); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 163 | rdmsrl(MSR_AMD64_IBSOPDATA, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame^] | 164 | oprofile_add_data64(&entry, val); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 165 | rdmsrl(MSR_AMD64_IBSOPDATA2, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame^] | 166 | oprofile_add_data64(&entry, val); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 167 | rdmsrl(MSR_AMD64_IBSOPDATA3, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame^] | 168 | oprofile_add_data64(&entry, val); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 169 | rdmsrl(MSR_AMD64_IBSDCLINAD, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame^] | 170 | oprofile_add_data64(&entry, val); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 171 | rdmsrl(MSR_AMD64_IBSDCPHYSAD, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame^] | 172 | oprofile_add_data64(&entry, val); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 173 | oprofile_write_commit(&entry); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 174 | |
| 175 | /* reenable the IRQ */ |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 176 | ctl &= ~IBS_OP_VAL & 0xFFFFFFFF; |
| 177 | ctl |= IBS_OP_ENABLE; |
| 178 | wrmsrl(MSR_AMD64_IBSOPCTL, ctl); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 179 | } |
| 180 | } |
| 181 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 182 | return 1; |
| 183 | } |
| 184 | |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 185 | static inline void op_amd_start_ibs(void) |
| 186 | { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 187 | u64 val; |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 188 | if (has_ibs && ibs_config.fetch_enabled) { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 189 | val = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF; |
| 190 | val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0; |
| 191 | val |= IBS_FETCH_ENABLE; |
| 192 | wrmsrl(MSR_AMD64_IBSFETCHCTL, val); |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 193 | } |
| 194 | |
| 195 | if (has_ibs && ibs_config.op_enabled) { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 196 | val = (ibs_config.max_cnt_op >> 4) & 0xFFFF; |
| 197 | val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0; |
| 198 | val |= IBS_OP_ENABLE; |
| 199 | wrmsrl(MSR_AMD64_IBSOPCTL, val); |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 200 | } |
| 201 | } |
| 202 | |
| 203 | static void op_amd_stop_ibs(void) |
| 204 | { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 205 | if (has_ibs && ibs_config.fetch_enabled) |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 206 | /* clear max count and enable */ |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 207 | wrmsrl(MSR_AMD64_IBSFETCHCTL, 0); |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 208 | |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 209 | if (has_ibs && ibs_config.op_enabled) |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 210 | /* clear max count and enable */ |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 211 | wrmsrl(MSR_AMD64_IBSOPCTL, 0); |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 212 | } |
| 213 | |
| 214 | #else |
| 215 | |
| 216 | static inline int op_amd_handle_ibs(struct pt_regs * const regs, |
| 217 | struct op_msrs const * const msrs) { } |
| 218 | static inline void op_amd_start_ibs(void) { } |
| 219 | static inline void op_amd_stop_ibs(void) { } |
| 220 | |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 221 | #endif |
| 222 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 223 | static int op_amd_check_ctrs(struct pt_regs * const regs, |
| 224 | struct op_msrs const * const msrs) |
| 225 | { |
Robert Richter | 42399ad | 2009-05-25 17:59:06 +0200 | [diff] [blame] | 226 | u64 val; |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 227 | int i; |
| 228 | |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 229 | for (i = 0 ; i < NUM_COUNTERS; ++i) { |
| 230 | if (!reset_value[i]) |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 231 | continue; |
Robert Richter | 42399ad | 2009-05-25 17:59:06 +0200 | [diff] [blame] | 232 | rdmsrl(msrs->counters[i].addr, val); |
| 233 | /* bit is clear if overflowed: */ |
| 234 | if (val & OP_CTR_OVERFLOW) |
| 235 | continue; |
| 236 | oprofile_add_sample(regs, i); |
Robert Richter | bbc5986 | 2009-05-25 17:38:19 +0200 | [diff] [blame] | 237 | wrmsrl(msrs->counters[i].addr, -(s64)reset_value[i]); |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 238 | } |
| 239 | |
| 240 | op_amd_handle_ibs(regs, msrs); |
| 241 | |
| 242 | /* See op_model_ppro.c */ |
| 243 | return 1; |
| 244 | } |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 245 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 246 | static void op_amd_start(struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 247 | { |
Robert Richter | dea3766 | 2009-05-25 18:11:52 +0200 | [diff] [blame] | 248 | u64 val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 249 | int i; |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 250 | for (i = 0 ; i < NUM_COUNTERS ; ++i) { |
| 251 | if (reset_value[i]) { |
Robert Richter | dea3766 | 2009-05-25 18:11:52 +0200 | [diff] [blame] | 252 | rdmsrl(msrs->controls[i].addr, val); |
| 253 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; |
| 254 | wrmsrl(msrs->controls[i].addr, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 255 | } |
| 256 | } |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 257 | |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 258 | op_amd_start_ibs(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 259 | } |
| 260 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 261 | static void op_amd_stop(struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 262 | { |
Robert Richter | dea3766 | 2009-05-25 18:11:52 +0200 | [diff] [blame] | 263 | u64 val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 264 | int i; |
| 265 | |
Robert Richter | fd13f6c | 2008-10-19 21:00:09 +0200 | [diff] [blame] | 266 | /* |
| 267 | * Subtle: stop on all counters to avoid race with setting our |
| 268 | * pm callback |
| 269 | */ |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 270 | for (i = 0 ; i < NUM_COUNTERS ; ++i) { |
| 271 | if (!reset_value[i]) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 272 | continue; |
Robert Richter | dea3766 | 2009-05-25 18:11:52 +0200 | [diff] [blame] | 273 | rdmsrl(msrs->controls[i].addr, val); |
| 274 | val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; |
| 275 | wrmsrl(msrs->controls[i].addr, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 276 | } |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 277 | |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 278 | op_amd_stop_ibs(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 279 | } |
| 280 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 281 | static void op_amd_shutdown(struct op_msrs const * const msrs) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 282 | { |
| 283 | int i; |
| 284 | |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 285 | for (i = 0 ; i < NUM_COUNTERS ; ++i) { |
Robert Richter | 217d3cf | 2009-06-04 02:36:44 +0200 | [diff] [blame] | 286 | if (msrs->counters[i].addr) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 287 | release_perfctr_nmi(MSR_K7_PERFCTR0 + i); |
| 288 | } |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 289 | for (i = 0 ; i < NUM_CONTROLS ; ++i) { |
Robert Richter | 217d3cf | 2009-06-04 02:36:44 +0200 | [diff] [blame] | 290 | if (msrs->controls[i].addr) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 291 | release_evntsel_nmi(MSR_K7_EVNTSEL0 + i); |
| 292 | } |
| 293 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 294 | |
Robert Richter | 9fa6812 | 2008-11-24 14:21:03 +0100 | [diff] [blame] | 295 | #ifdef CONFIG_OPROFILE_IBS |
Robert Richter | a4c408a | 2008-07-22 21:09:02 +0200 | [diff] [blame] | 296 | |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 297 | static u8 ibs_eilvt_off; |
| 298 | |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 299 | static inline void apic_init_ibs_nmi_per_cpu(void *arg) |
| 300 | { |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 301 | ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 302 | } |
| 303 | |
| 304 | static inline void apic_clear_ibs_nmi_per_cpu(void *arg) |
| 305 | { |
| 306 | setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1); |
| 307 | } |
| 308 | |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 309 | static int init_ibs_nmi(void) |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 310 | { |
| 311 | #define IBSCTL_LVTOFFSETVAL (1 << 8) |
| 312 | #define IBSCTL 0x1cc |
| 313 | struct pci_dev *cpu_cfg; |
| 314 | int nodes; |
| 315 | u32 value = 0; |
| 316 | |
| 317 | /* per CPU setup */ |
Robert Richter | ebb535d | 2008-07-22 21:08:59 +0200 | [diff] [blame] | 318 | on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1); |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 319 | |
| 320 | nodes = 0; |
| 321 | cpu_cfg = NULL; |
| 322 | do { |
| 323 | cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD, |
| 324 | PCI_DEVICE_ID_AMD_10H_NB_MISC, |
| 325 | cpu_cfg); |
| 326 | if (!cpu_cfg) |
| 327 | break; |
| 328 | ++nodes; |
| 329 | pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off |
| 330 | | IBSCTL_LVTOFFSETVAL); |
| 331 | pci_read_config_dword(cpu_cfg, IBSCTL, &value); |
| 332 | if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) { |
Robert Richter | 83bd924 | 2008-12-15 15:09:50 +0100 | [diff] [blame] | 333 | pci_dev_put(cpu_cfg); |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 334 | printk(KERN_DEBUG "Failed to setup IBS LVT offset, " |
| 335 | "IBSCTL = 0x%08x", value); |
| 336 | return 1; |
| 337 | } |
| 338 | } while (1); |
| 339 | |
| 340 | if (!nodes) { |
| 341 | printk(KERN_DEBUG "No CPU node configured for IBS"); |
| 342 | return 1; |
| 343 | } |
| 344 | |
| 345 | #ifdef CONFIG_NUMA |
| 346 | /* Sanity check */ |
| 347 | /* Works only for 64bit with proper numa implementation. */ |
| 348 | if (nodes != num_possible_nodes()) { |
| 349 | printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, " |
| 350 | "found: %d, expected %d", |
| 351 | nodes, num_possible_nodes()); |
| 352 | return 1; |
| 353 | } |
| 354 | #endif |
| 355 | return 0; |
| 356 | } |
| 357 | |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 358 | /* uninitialize the APIC for the IBS interrupts if needed */ |
| 359 | static void clear_ibs_nmi(void) |
| 360 | { |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 361 | if (has_ibs) |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 362 | on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1); |
| 363 | } |
| 364 | |
Robert Richter | fd13f6c | 2008-10-19 21:00:09 +0200 | [diff] [blame] | 365 | /* initialize the APIC for the IBS interrupts if available */ |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 366 | static void ibs_init(void) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 367 | { |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 368 | has_ibs = boot_cpu_has(X86_FEATURE_IBS); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 369 | |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 370 | if (!has_ibs) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 371 | return; |
| 372 | |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 373 | if (init_ibs_nmi()) { |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 374 | has_ibs = 0; |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 375 | return; |
| 376 | } |
| 377 | |
| 378 | printk(KERN_INFO "oprofile: AMD IBS detected\n"); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 379 | } |
| 380 | |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 381 | static void ibs_exit(void) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 382 | { |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 383 | if (!has_ibs) |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 384 | return; |
| 385 | |
| 386 | clear_ibs_nmi(); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 387 | } |
| 388 | |
Robert Richter | 25ad2913 | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 389 | static int (*create_arch_files)(struct super_block *sb, struct dentry *root); |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 390 | |
Robert Richter | 25ad2913 | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 391 | static int setup_ibs_files(struct super_block *sb, struct dentry *root) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 392 | { |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 393 | struct dentry *dir; |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 394 | int ret = 0; |
| 395 | |
| 396 | /* architecture specific files */ |
| 397 | if (create_arch_files) |
| 398 | ret = create_arch_files(sb, root); |
| 399 | |
| 400 | if (ret) |
| 401 | return ret; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 402 | |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 403 | if (!has_ibs) |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 404 | return ret; |
| 405 | |
| 406 | /* model specific files */ |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 407 | |
| 408 | /* setup some reasonable defaults */ |
| 409 | ibs_config.max_cnt_fetch = 250000; |
| 410 | ibs_config.fetch_enabled = 0; |
| 411 | ibs_config.max_cnt_op = 250000; |
| 412 | ibs_config.op_enabled = 0; |
| 413 | ibs_config.dispatched_ops = 1; |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 414 | |
| 415 | dir = oprofilefs_mkdir(sb, root, "ibs_fetch"); |
| 416 | oprofilefs_create_ulong(sb, dir, "enable", |
| 417 | &ibs_config.fetch_enabled); |
| 418 | oprofilefs_create_ulong(sb, dir, "max_count", |
| 419 | &ibs_config.max_cnt_fetch); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 420 | oprofilefs_create_ulong(sb, dir, "rand_enable", |
| 421 | &ibs_config.rand_en); |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 422 | |
Robert Richter | ccd755c | 2008-07-29 16:57:10 +0200 | [diff] [blame] | 423 | dir = oprofilefs_mkdir(sb, root, "ibs_op"); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 424 | oprofilefs_create_ulong(sb, dir, "enable", |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 425 | &ibs_config.op_enabled); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 426 | oprofilefs_create_ulong(sb, dir, "max_count", |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 427 | &ibs_config.max_cnt_op); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 428 | oprofilefs_create_ulong(sb, dir, "dispatched_ops", |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 429 | &ibs_config.dispatched_ops); |
Robert Richter | fc2bd73 | 2008-07-22 21:09:00 +0200 | [diff] [blame] | 430 | |
| 431 | return 0; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 432 | } |
| 433 | |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 434 | static int op_amd_init(struct oprofile_operations *ops) |
| 435 | { |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 436 | ibs_init(); |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 437 | create_arch_files = ops->create_files; |
| 438 | ops->create_files = setup_ibs_files; |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 439 | return 0; |
| 440 | } |
| 441 | |
| 442 | static void op_amd_exit(void) |
| 443 | { |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 444 | ibs_exit(); |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 445 | } |
| 446 | |
Robert Richter | 9fa6812 | 2008-11-24 14:21:03 +0100 | [diff] [blame] | 447 | #else |
| 448 | |
| 449 | /* no IBS support */ |
| 450 | |
| 451 | static int op_amd_init(struct oprofile_operations *ops) |
| 452 | { |
| 453 | return 0; |
| 454 | } |
| 455 | |
| 456 | static void op_amd_exit(void) {} |
| 457 | |
| 458 | #endif /* CONFIG_OPROFILE_IBS */ |
Robert Richter | a4c408a | 2008-07-22 21:09:02 +0200 | [diff] [blame] | 459 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 460 | struct op_x86_model_spec const op_amd_spec = { |
Robert Richter | c92960f | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 461 | .num_counters = NUM_COUNTERS, |
| 462 | .num_controls = NUM_CONTROLS, |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 463 | .reserved = MSR_AMD_EVENTSEL_RESERVED, |
| 464 | .event_mask = OP_EVENT_MASK, |
| 465 | .init = op_amd_init, |
| 466 | .exit = op_amd_exit, |
Robert Richter | c92960f | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 467 | .fill_in_addresses = &op_amd_fill_in_addresses, |
| 468 | .setup_ctrs = &op_amd_setup_ctrs, |
| 469 | .check_ctrs = &op_amd_check_ctrs, |
| 470 | .start = &op_amd_start, |
| 471 | .stop = &op_amd_stop, |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 472 | .shutdown = &op_amd_shutdown, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 473 | }; |