Kukjin Kim | b3ed3a1 | 2011-02-14 16:08:04 +0900 | [diff] [blame] | 1 | /* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h |
Changhwan Youn | c8bef14 | 2010-07-27 17:52:39 +0900 | [diff] [blame] | 2 | * |
Kukjin Kim | b3ed3a1 | 2011-02-14 16:08:04 +0900 | [diff] [blame] | 3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
| 4 | * http://www.samsung.com |
Changhwan Youn | c8bef14 | 2010-07-27 17:52:39 +0900 | [diff] [blame] | 5 | * |
Kukjin Kim | b3ed3a1 | 2011-02-14 16:08:04 +0900 | [diff] [blame] | 6 | * EXYNOS4 - Clock register definitions |
Changhwan Youn | c8bef14 | 2010-07-27 17:52:39 +0900 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #ifndef __ASM_ARCH_REGS_CLOCK_H |
| 14 | #define __ASM_ARCH_REGS_CLOCK_H __FILE__ |
| 15 | |
Kukjin Kim | 2bc02c0 | 2011-08-24 17:25:09 +0900 | [diff] [blame] | 16 | #include <plat/cpu.h> |
Changhwan Youn | c8bef14 | 2010-07-27 17:52:39 +0900 | [diff] [blame] | 17 | #include <mach/map.h> |
| 18 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 19 | #define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x)) |
Changhwan Youn | c8bef14 | 2010-07-27 17:52:39 +0900 | [diff] [blame] | 20 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 21 | #define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500) |
| 22 | #define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600) |
| 23 | #define EXYNOS4_CLKGATE_IP_LEFTBUS EXYNOS_CLKREG(0x04800) |
Sunyoung Kang | 7af36b9 | 2010-09-18 10:59:31 +0900 | [diff] [blame] | 24 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 25 | #define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500) |
| 26 | #define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600) |
| 27 | #define EXYNOS4_CLKGATE_IP_RIGHTBUS EXYNOS_CLKREG(0x08800) |
Sunyoung Kang | 7af36b9 | 2010-09-18 10:59:31 +0900 | [diff] [blame] | 28 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 29 | #define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010) |
| 30 | #define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020) |
Jaecheol Lee | 56c03d9 | 2011-07-18 19:25:13 +0900 | [diff] [blame] | 31 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 32 | #define EXYNOS4_EPLL_CON0 EXYNOS_CLKREG(0x0C110) |
| 33 | #define EXYNOS4_EPLL_CON1 EXYNOS_CLKREG(0x0C114) |
| 34 | #define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120) |
| 35 | #define EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124) |
Changhwan Youn | c8bef14 | 2010-07-27 17:52:39 +0900 | [diff] [blame] | 36 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 37 | #define EXYNOS4_CLKSRC_TOP0 EXYNOS_CLKREG(0x0C210) |
| 38 | #define EXYNOS4_CLKSRC_TOP1 EXYNOS_CLKREG(0x0C214) |
| 39 | #define EXYNOS4_CLKSRC_CAM EXYNOS_CLKREG(0x0C220) |
| 40 | #define EXYNOS4_CLKSRC_TV EXYNOS_CLKREG(0x0C224) |
| 41 | #define EXYNOS4_CLKSRC_MFC EXYNOS_CLKREG(0x0C228) |
| 42 | #define EXYNOS4_CLKSRC_G3D EXYNOS_CLKREG(0x0C22C) |
| 43 | #define EXYNOS4_CLKSRC_IMAGE EXYNOS_CLKREG(0x0C230) |
| 44 | #define EXYNOS4_CLKSRC_LCD0 EXYNOS_CLKREG(0x0C234) |
| 45 | #define EXYNOS4_CLKSRC_MAUDIO EXYNOS_CLKREG(0x0C23C) |
| 46 | #define EXYNOS4_CLKSRC_FSYS EXYNOS_CLKREG(0x0C240) |
| 47 | #define EXYNOS4_CLKSRC_PERIL0 EXYNOS_CLKREG(0x0C250) |
| 48 | #define EXYNOS4_CLKSRC_PERIL1 EXYNOS_CLKREG(0x0C254) |
Changhwan Youn | c8bef14 | 2010-07-27 17:52:39 +0900 | [diff] [blame] | 49 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 50 | #define EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310) |
| 51 | #define EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320) |
| 52 | #define EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324) |
| 53 | #define EXYNOS4_CLKSRC_MASK_LCD0 EXYNOS_CLKREG(0x0C334) |
| 54 | #define EXYNOS4_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x0C33C) |
| 55 | #define EXYNOS4_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x0C340) |
| 56 | #define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350) |
| 57 | #define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354) |
Kukjin Kim | 2bc02c0 | 2011-08-24 17:25:09 +0900 | [diff] [blame] | 58 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 59 | #define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510) |
| 60 | #define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520) |
| 61 | #define EXYNOS4_CLKDIV_TV EXYNOS_CLKREG(0x0C524) |
| 62 | #define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528) |
| 63 | #define EXYNOS4_CLKDIV_G3D EXYNOS_CLKREG(0x0C52C) |
| 64 | #define EXYNOS4_CLKDIV_IMAGE EXYNOS_CLKREG(0x0C530) |
| 65 | #define EXYNOS4_CLKDIV_LCD0 EXYNOS_CLKREG(0x0C534) |
| 66 | #define EXYNOS4_CLKDIV_MAUDIO EXYNOS_CLKREG(0x0C53C) |
| 67 | #define EXYNOS4_CLKDIV_FSYS0 EXYNOS_CLKREG(0x0C540) |
| 68 | #define EXYNOS4_CLKDIV_FSYS1 EXYNOS_CLKREG(0x0C544) |
| 69 | #define EXYNOS4_CLKDIV_FSYS2 EXYNOS_CLKREG(0x0C548) |
| 70 | #define EXYNOS4_CLKDIV_FSYS3 EXYNOS_CLKREG(0x0C54C) |
| 71 | #define EXYNOS4_CLKDIV_PERIL0 EXYNOS_CLKREG(0x0C550) |
| 72 | #define EXYNOS4_CLKDIV_PERIL1 EXYNOS_CLKREG(0x0C554) |
| 73 | #define EXYNOS4_CLKDIV_PERIL2 EXYNOS_CLKREG(0x0C558) |
| 74 | #define EXYNOS4_CLKDIV_PERIL3 EXYNOS_CLKREG(0x0C55C) |
| 75 | #define EXYNOS4_CLKDIV_PERIL4 EXYNOS_CLKREG(0x0C560) |
| 76 | #define EXYNOS4_CLKDIV_PERIL5 EXYNOS_CLKREG(0x0C564) |
| 77 | #define EXYNOS4_CLKDIV2_RATIO EXYNOS_CLKREG(0x0C580) |
Changhwan Youn | c8bef14 | 2010-07-27 17:52:39 +0900 | [diff] [blame] | 78 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 79 | #define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610) |
MyungJoo Ham | 44b2cef | 2011-12-14 20:12:46 +0900 | [diff] [blame] | 80 | #define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628) |
Sunyoung Kang | 7af36b9 | 2010-09-18 10:59:31 +0900 | [diff] [blame] | 81 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 82 | #define EXYNOS4_CLKGATE_SCLKCAM EXYNOS_CLKREG(0x0C820) |
| 83 | #define EXYNOS4_CLKGATE_IP_CAM EXYNOS_CLKREG(0x0C920) |
| 84 | #define EXYNOS4_CLKGATE_IP_TV EXYNOS_CLKREG(0x0C924) |
| 85 | #define EXYNOS4_CLKGATE_IP_MFC EXYNOS_CLKREG(0x0C928) |
| 86 | #define EXYNOS4_CLKGATE_IP_G3D EXYNOS_CLKREG(0x0C92C) |
| 87 | #define EXYNOS4_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \ |
| 88 | EXYNOS_CLKREG(0x0C930) : \ |
| 89 | EXYNOS_CLKREG(0x04930)) |
| 90 | #define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930) |
| 91 | #define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930) |
| 92 | #define EXYNOS4_CLKGATE_IP_LCD0 EXYNOS_CLKREG(0x0C934) |
| 93 | #define EXYNOS4_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x0C940) |
| 94 | #define EXYNOS4_CLKGATE_IP_GPS EXYNOS_CLKREG(0x0C94C) |
| 95 | #define EXYNOS4_CLKGATE_IP_PERIL EXYNOS_CLKREG(0x0C950) |
| 96 | #define EXYNOS4_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \ |
| 97 | EXYNOS_CLKREG(0x0C960) : \ |
| 98 | EXYNOS_CLKREG(0x08960)) |
| 99 | #define EXYNOS4210_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x0C960) |
| 100 | #define EXYNOS4212_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x08960) |
| 101 | #define EXYNOS4_CLKGATE_BLOCK EXYNOS_CLKREG(0x0C970) |
Changhwan Youn | c8bef14 | 2010-07-27 17:52:39 +0900 | [diff] [blame] | 102 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 103 | #define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300) |
| 104 | #define EXYNOS4_CLKSRC_DMC EXYNOS_CLKREG(0x10200) |
| 105 | #define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500) |
| 106 | #define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504) |
| 107 | #define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600) |
MyungJoo Ham | 44b2cef | 2011-12-14 20:12:46 +0900 | [diff] [blame] | 108 | #define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604) |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 109 | #define EXYNOS4_CLKGATE_IP_DMC EXYNOS_CLKREG(0x10900) |
Changhwan Youn | c8bef14 | 2010-07-27 17:52:39 +0900 | [diff] [blame] | 110 | |
MyungJoo Ham | 44b2cef | 2011-12-14 20:12:46 +0900 | [diff] [blame] | 111 | #define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094) |
| 112 | #define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0) |
| 113 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 114 | #define EXYNOS4_APLL_LOCK EXYNOS_CLKREG(0x14000) |
| 115 | #define EXYNOS4_MPLL_LOCK (soc_is_exynos4210() ? \ |
| 116 | EXYNOS_CLKREG(0x14004) : \ |
| 117 | EXYNOS_CLKREG(0x10008)) |
| 118 | #define EXYNOS4_APLL_CON0 EXYNOS_CLKREG(0x14100) |
| 119 | #define EXYNOS4_APLL_CON1 EXYNOS_CLKREG(0x14104) |
| 120 | #define EXYNOS4_MPLL_CON0 (soc_is_exynos4210() ? \ |
| 121 | EXYNOS_CLKREG(0x14108) : \ |
| 122 | EXYNOS_CLKREG(0x10108)) |
| 123 | #define EXYNOS4_MPLL_CON1 (soc_is_exynos4210() ? \ |
| 124 | EXYNOS_CLKREG(0x1410C) : \ |
| 125 | EXYNOS_CLKREG(0x1010C)) |
Changhwan Youn | c8bef14 | 2010-07-27 17:52:39 +0900 | [diff] [blame] | 126 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 127 | #define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200) |
| 128 | #define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400) |
Changhwan Youn | c8bef14 | 2010-07-27 17:52:39 +0900 | [diff] [blame] | 129 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 130 | #define EXYNOS4_CLKDIV_CPU EXYNOS_CLKREG(0x14500) |
| 131 | #define EXYNOS4_CLKDIV_CPU1 EXYNOS_CLKREG(0x14504) |
| 132 | #define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600) |
| 133 | #define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604) |
Changhwan Youn | c8bef14 | 2010-07-27 17:52:39 +0900 | [diff] [blame] | 134 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 135 | #define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800) |
| 136 | #define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900) |
Changhwan Youn | c8bef14 | 2010-07-27 17:52:39 +0900 | [diff] [blame] | 137 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 138 | #define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */ |
Sunyoung Kang | 7af36b9 | 2010-09-18 10:59:31 +0900 | [diff] [blame] | 139 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 140 | #define EXYNOS4_APLLCON0_ENABLE_SHIFT (31) |
| 141 | #define EXYNOS4_APLLCON0_LOCKED_SHIFT (29) |
| 142 | #define EXYNOS4_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) |
| 143 | #define EXYNOS4_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) |
Sunyoung Kang | 7af36b9 | 2010-09-18 10:59:31 +0900 | [diff] [blame] | 144 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 145 | #define EXYNOS4_EPLLCON0_ENABLE_SHIFT (31) |
| 146 | #define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29) |
Jaecheol Lee | 56c03d9 | 2011-07-18 19:25:13 +0900 | [diff] [blame] | 147 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 148 | #define EXYNOS4_VPLLCON0_ENABLE_SHIFT (31) |
| 149 | #define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29) |
Jaecheol Lee | 56c03d9 | 2011-07-18 19:25:13 +0900 | [diff] [blame] | 150 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 151 | #define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16) |
| 152 | #define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT) |
Sunyoung Kang | 7af36b9 | 2010-09-18 10:59:31 +0900 | [diff] [blame] | 153 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 154 | #define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT (0) |
| 155 | #define EXYNOS4_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
| 156 | #define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT (4) |
| 157 | #define EXYNOS4_CLKDIV_CPU0_COREM0_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
| 158 | #define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT (8) |
| 159 | #define EXYNOS4_CLKDIV_CPU0_COREM1_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
| 160 | #define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT (12) |
| 161 | #define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
| 162 | #define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT (16) |
| 163 | #define EXYNOS4_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
| 164 | #define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT (20) |
| 165 | #define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
| 166 | #define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24) |
| 167 | #define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT) |
Jaecheol Lee | d074de8 | 2012-02-02 12:31:01 +0900 | [diff] [blame] | 168 | #define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28 |
| 169 | #define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT) |
| 170 | |
| 171 | #define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0 |
| 172 | #define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) |
| 173 | #define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4 |
| 174 | #define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT) |
| 175 | #define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8 |
| 176 | #define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT) |
Sunyoung Kang | 7af36b9 | 2010-09-18 10:59:31 +0900 | [diff] [blame] | 177 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 178 | #define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0) |
| 179 | #define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
| 180 | #define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4) |
| 181 | #define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
| 182 | #define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8) |
| 183 | #define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
| 184 | #define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12) |
| 185 | #define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
| 186 | #define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16) |
| 187 | #define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
| 188 | #define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20) |
| 189 | #define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) |
| 190 | #define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24) |
| 191 | #define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) |
| 192 | #define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28) |
| 193 | #define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT) |
Sunyoung Kang | 7af36b9 | 2010-09-18 10:59:31 +0900 | [diff] [blame] | 194 | |
MyungJoo Ham | 44b2cef | 2011-12-14 20:12:46 +0900 | [diff] [blame] | 195 | #define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0) |
| 196 | #define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) |
| 197 | #define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4) |
| 198 | #define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) |
| 199 | #define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8) |
| 200 | #define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT) |
| 201 | #define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12) |
| 202 | #define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT) |
| 203 | #define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16) |
| 204 | #define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT) |
| 205 | #define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24) |
| 206 | #define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT) |
| 207 | |
| 208 | #define EXYNOS4_CLKDIV_MFC_SHIFT (0) |
| 209 | #define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT) |
| 210 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 211 | #define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0) |
| 212 | #define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) |
| 213 | #define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4) |
| 214 | #define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
| 215 | #define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8) |
| 216 | #define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
| 217 | #define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12) |
| 218 | #define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
| 219 | #define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16) |
| 220 | #define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT) |
MyungJoo Ham | 44b2cef | 2011-12-14 20:12:46 +0900 | [diff] [blame] | 221 | #define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20) |
| 222 | #define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) |
| 223 | #define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24) |
| 224 | #define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT) |
Sunyoung Kang | 7af36b9 | 2010-09-18 10:59:31 +0900 | [diff] [blame] | 225 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 226 | #define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0) |
| 227 | #define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
| 228 | #define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4) |
| 229 | #define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT) |
Sunyoung Kang | 7af36b9 | 2010-09-18 10:59:31 +0900 | [diff] [blame] | 230 | |
MyungJoo Ham | 44b2cef | 2011-12-14 20:12:46 +0900 | [diff] [blame] | 231 | #define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0) |
| 232 | #define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) |
| 233 | #define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4) |
| 234 | #define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) |
| 235 | #define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8) |
| 236 | #define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) |
| 237 | #define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12) |
| 238 | #define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT) |
| 239 | |
Kukjin Kim | 2bc02c0 | 2011-08-24 17:25:09 +0900 | [diff] [blame] | 240 | /* Only for EXYNOS4210 */ |
| 241 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 242 | #define EXYNOS4210_CLKSRC_LCD1 EXYNOS_CLKREG(0x0C238) |
| 243 | #define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338) |
| 244 | #define EXYNOS4210_CLKDIV_LCD1 EXYNOS_CLKREG(0x0C538) |
| 245 | #define EXYNOS4210_CLKGATE_IP_LCD1 EXYNOS_CLKREG(0x0C938) |
Kukjin Kim | 2bc02c0 | 2011-08-24 17:25:09 +0900 | [diff] [blame] | 246 | |
MyungJoo Ham | 44b2cef | 2011-12-14 20:12:46 +0900 | [diff] [blame] | 247 | /* Only for EXYNOS4212 */ |
| 248 | |
| 249 | #define EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568) |
| 250 | |
| 251 | #define EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668) |
| 252 | |
| 253 | #define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0) |
| 254 | #define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT) |
| 255 | |
Kukjin Kim | 87b3c6e | 2012-01-22 21:46:13 +0900 | [diff] [blame] | 256 | /* For EXYNOS5250 */ |
| 257 | |
| 258 | #define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100) |
| 259 | #define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200) |
| 260 | #define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500) |
| 261 | #define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100) |
| 262 | #define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204) |
| 263 | |
| 264 | #define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900) |
| 265 | |
| 266 | #define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500) |
| 267 | |
| 268 | #define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218) |
| 269 | #define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130) |
| 270 | #define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134) |
| 271 | #define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140) |
| 272 | #define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144) |
| 273 | #define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120) |
| 274 | |
| 275 | #define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210) |
| 276 | #define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C) |
| 277 | #define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220) |
| 278 | #define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C) |
| 279 | #define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244) |
| 280 | #define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250) |
| 281 | |
| 282 | #define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310) |
| 283 | #define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320) |
| 284 | #define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C) |
| 285 | #define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340) |
| 286 | #define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350) |
| 287 | |
| 288 | #define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510) |
| 289 | #define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514) |
| 290 | #define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520) |
| 291 | #define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C) |
| 292 | #define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C) |
| 293 | #define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548) |
| 294 | #define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C) |
| 295 | #define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550) |
| 296 | #define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554) |
| 297 | #define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558) |
| 298 | |
| 299 | #define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800) |
| 300 | #define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920) |
| 301 | #define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928) |
| 302 | #define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C) |
| 303 | #define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934) |
| 304 | #define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944) |
| 305 | #define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C) |
| 306 | #define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950) |
| 307 | #define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960) |
| 308 | #define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980) |
| 309 | |
| 310 | #define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110) |
| 311 | #define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200) |
| 312 | #define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500) |
| 313 | |
| 314 | #define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030) |
| 315 | |
| 316 | #define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29) |
| 317 | |
Sylwester Nawrocki | 1d45ac4 | 2011-03-10 21:53:40 +0900 | [diff] [blame] | 318 | /* Compatibility defines and inclusion */ |
| 319 | |
| 320 | #include <mach/regs-pmu.h> |
Seungwhan Youn | d4b34c6 | 2010-10-14 10:39:08 +0900 | [diff] [blame] | 321 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 322 | #define S5P_EPLL_CON EXYNOS4_EPLL_CON0 |
Seungwhan Youn | d4b34c6 | 2010-10-14 10:39:08 +0900 | [diff] [blame] | 323 | |
Changhwan Youn | c8bef14 | 2010-07-27 17:52:39 +0900 | [diff] [blame] | 324 | #endif /* __ASM_ARCH_REGS_CLOCK_H */ |