Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
Ben Skeggs | 70c0f26 | 2012-07-10 10:49:22 +1000 | [diff] [blame] | 25 | #include <subdev/bios.h> |
Martin Peres | a10220b | 2012-11-04 01:01:53 +0100 | [diff] [blame] | 26 | #include <subdev/bus.h> |
Ben Skeggs | e0996ae | 2012-07-10 12:20:17 +1000 | [diff] [blame] | 27 | #include <subdev/gpio.h> |
Ben Skeggs | 4196faa | 2012-07-10 14:36:38 +1000 | [diff] [blame] | 28 | #include <subdev/i2c.h> |
Ben Skeggs | 8aceb7d | 2012-07-10 16:45:24 +1000 | [diff] [blame] | 29 | #include <subdev/clock.h> |
Martin Peres | aa1b9b4 | 2012-09-02 02:55:58 +0200 | [diff] [blame] | 30 | #include <subdev/therm.h> |
Ben Skeggs | d38ac52 | 2012-07-22 16:41:26 +1000 | [diff] [blame] | 31 | #include <subdev/mxm.h> |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 32 | #include <subdev/devinit.h> |
Ben Skeggs | 7d9115d | 2012-07-11 15:58:56 +1000 | [diff] [blame] | 33 | #include <subdev/mc.h> |
Ben Skeggs | 5a5c743 | 2012-07-11 16:08:25 +1000 | [diff] [blame] | 34 | #include <subdev/timer.h> |
Ben Skeggs | 861d210 | 2012-07-11 19:05:01 +1000 | [diff] [blame] | 35 | #include <subdev/fb.h> |
| 36 | #include <subdev/ltcg.h> |
Ben Skeggs | 2c1a425 | 2012-08-22 23:55:42 -0400 | [diff] [blame] | 37 | #include <subdev/ibus.h> |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame] | 38 | #include <subdev/instmem.h> |
| 39 | #include <subdev/vm.h> |
| 40 | #include <subdev/bar.h> |
Ben Skeggs | ff4b42c | 2013-10-15 09:38:12 +1000 | [diff] [blame] | 41 | #include <subdev/pwr.h> |
Ben Skeggs | c9c0cca | 2013-02-08 09:34:56 +1000 | [diff] [blame] | 42 | #include <subdev/volt.h> |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 43 | |
Ben Skeggs | dded35d | 2013-04-25 17:23:43 +1000 | [diff] [blame] | 44 | #include <engine/device.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 45 | #include <engine/dmaobj.h> |
| 46 | #include <engine/fifo.h> |
| 47 | #include <engine/software.h> |
| 48 | #include <engine/graph.h> |
| 49 | #include <engine/disp.h> |
Ben Skeggs | 4f32656 | 2012-08-06 19:28:02 +1000 | [diff] [blame] | 50 | #include <engine/copy.h> |
Ben Skeggs | b2f04fc | 2012-11-22 15:42:23 +1000 | [diff] [blame] | 51 | #include <engine/bsp.h> |
Ben Skeggs | a7416d0 | 2012-11-22 15:48:41 +1000 | [diff] [blame] | 52 | #include <engine/vp.h> |
Ben Skeggs | fb9bff2 | 2012-11-23 11:14:49 +1000 | [diff] [blame] | 53 | #include <engine/ppp.h> |
Ben Skeggs | aa4d7a4 | 2013-02-13 15:29:11 +1000 | [diff] [blame] | 54 | #include <engine/perfmon.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 55 | |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 56 | int |
| 57 | nve0_identify(struct nouveau_device *device) |
| 58 | { |
| 59 | switch (device->chipset) { |
| 60 | case 0xe4: |
Ben Skeggs | 2094dd8 | 2012-07-27 08:28:20 +1000 | [diff] [blame] | 61 | device->cname = "GK104"; |
Ben Skeggs | 70c0f26 | 2012-07-10 10:49:22 +1000 | [diff] [blame] | 62 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
Ben Skeggs | fa531bc | 2013-02-13 13:34:39 +1000 | [diff] [blame] | 63 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass; |
Ben Skeggs | 7dcd060c | 2013-02-16 15:21:58 +1000 | [diff] [blame] | 64 | device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass; |
Ben Skeggs | 7c85652 | 2013-01-14 08:28:28 +1000 | [diff] [blame] | 65 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; |
Ben Skeggs | bc79202 | 2012-12-04 09:50:33 +1000 | [diff] [blame] | 66 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
Ben Skeggs | d38ac52 | 2012-07-22 16:41:26 +1000 | [diff] [blame] | 67 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
Ben Skeggs | cf33601 | 2014-01-14 15:55:38 +1000 | [diff] [blame] | 68 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
Ben Skeggs | 1b4fea0 | 2013-10-11 15:38:15 +1000 | [diff] [blame] | 69 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
Ben Skeggs | 48ae0b3 | 2013-10-24 09:39:05 +1000 | [diff] [blame] | 70 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
Ben Skeggs | 5a5c743 | 2012-07-11 16:08:25 +1000 | [diff] [blame] | 71 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
Ben Skeggs | aae95ca | 2013-03-04 15:01:37 +1000 | [diff] [blame] | 72 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; |
Ben Skeggs | f6bad8a | 2014-02-24 14:17:49 +1000 | [diff] [blame] | 73 | device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; |
Ben Skeggs | 2c1a425 | 2012-08-22 23:55:42 -0400 | [diff] [blame] | 74 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
Ben Skeggs | 24a4ae8 | 2013-12-23 00:39:47 +1000 | [diff] [blame] | 75 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame] | 76 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 77 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
Ben Skeggs | ff4b42c | 2013-10-15 09:38:12 +1000 | [diff] [blame] | 78 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; |
Ben Skeggs | c9c0cca | 2013-02-08 09:34:56 +1000 | [diff] [blame] | 79 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
Ben Skeggs | 344e107 | 2012-10-08 14:11:35 +1000 | [diff] [blame] | 80 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; |
Ben Skeggs | 16c4f22 | 2013-11-05 14:26:58 +1000 | [diff] [blame] | 81 | device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; |
Ben Skeggs | c46c3dd | 2013-10-03 07:30:11 +1000 | [diff] [blame] | 82 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
Ben Skeggs | 30f4e08 | 2013-06-09 16:08:22 +1000 | [diff] [blame] | 83 | device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; |
Ben Skeggs | a8f8b48 | 2014-02-20 21:33:34 +1000 | [diff] [blame] | 84 | device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; |
Ben Skeggs | 4f32656 | 2012-08-06 19:28:02 +1000 | [diff] [blame] | 85 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; |
| 86 | device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; |
Ben Skeggs | b0bc530 | 2013-04-29 09:31:05 +1000 | [diff] [blame] | 87 | device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; |
Ben Skeggs | b2f04fc | 2012-11-22 15:42:23 +1000 | [diff] [blame] | 88 | device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; |
Ben Skeggs | a7416d0 | 2012-11-22 15:48:41 +1000 | [diff] [blame] | 89 | device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; |
Ben Skeggs | fb9bff2 | 2012-11-23 11:14:49 +1000 | [diff] [blame] | 90 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
Ben Skeggs | aa4d7a4 | 2013-02-13 15:29:11 +1000 | [diff] [blame] | 91 | device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 92 | break; |
| 93 | case 0xe7: |
Ben Skeggs | 2094dd8 | 2012-07-27 08:28:20 +1000 | [diff] [blame] | 94 | device->cname = "GK107"; |
Ben Skeggs | 70c0f26 | 2012-07-10 10:49:22 +1000 | [diff] [blame] | 95 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
Ben Skeggs | fa531bc | 2013-02-13 13:34:39 +1000 | [diff] [blame] | 96 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass; |
Ben Skeggs | 7dcd060c | 2013-02-16 15:21:58 +1000 | [diff] [blame] | 97 | device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass; |
Ben Skeggs | 7c85652 | 2013-01-14 08:28:28 +1000 | [diff] [blame] | 98 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; |
Ben Skeggs | bc79202 | 2012-12-04 09:50:33 +1000 | [diff] [blame] | 99 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
Ben Skeggs | d38ac52 | 2012-07-22 16:41:26 +1000 | [diff] [blame] | 100 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
Ben Skeggs | cf33601 | 2014-01-14 15:55:38 +1000 | [diff] [blame] | 101 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
Ben Skeggs | 1b4fea0 | 2013-10-11 15:38:15 +1000 | [diff] [blame] | 102 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
Ben Skeggs | 48ae0b3 | 2013-10-24 09:39:05 +1000 | [diff] [blame] | 103 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
Ben Skeggs | 5a5c743 | 2012-07-11 16:08:25 +1000 | [diff] [blame] | 104 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
Ben Skeggs | aae95ca | 2013-03-04 15:01:37 +1000 | [diff] [blame] | 105 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; |
Ben Skeggs | f6bad8a | 2014-02-24 14:17:49 +1000 | [diff] [blame] | 106 | device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; |
Ben Skeggs | 2c1a425 | 2012-08-22 23:55:42 -0400 | [diff] [blame] | 107 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
Ben Skeggs | 24a4ae8 | 2013-12-23 00:39:47 +1000 | [diff] [blame] | 108 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame] | 109 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 110 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
Ben Skeggs | ff4b42c | 2013-10-15 09:38:12 +1000 | [diff] [blame] | 111 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; |
Ben Skeggs | c9c0cca | 2013-02-08 09:34:56 +1000 | [diff] [blame] | 112 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
Ben Skeggs | 344e107 | 2012-10-08 14:11:35 +1000 | [diff] [blame] | 113 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; |
Ben Skeggs | 16c4f22 | 2013-11-05 14:26:58 +1000 | [diff] [blame] | 114 | device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; |
Ben Skeggs | c46c3dd | 2013-10-03 07:30:11 +1000 | [diff] [blame] | 115 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
Ben Skeggs | 30f4e08 | 2013-06-09 16:08:22 +1000 | [diff] [blame] | 116 | device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; |
Ben Skeggs | a8f8b48 | 2014-02-20 21:33:34 +1000 | [diff] [blame] | 117 | device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; |
Ben Skeggs | 4f32656 | 2012-08-06 19:28:02 +1000 | [diff] [blame] | 118 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; |
| 119 | device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; |
Ben Skeggs | b0bc530 | 2013-04-29 09:31:05 +1000 | [diff] [blame] | 120 | device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; |
Ben Skeggs | b2f04fc | 2012-11-22 15:42:23 +1000 | [diff] [blame] | 121 | device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; |
Ben Skeggs | a7416d0 | 2012-11-22 15:48:41 +1000 | [diff] [blame] | 122 | device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; |
Ben Skeggs | fb9bff2 | 2012-11-23 11:14:49 +1000 | [diff] [blame] | 123 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
Ben Skeggs | aa4d7a4 | 2013-02-13 15:29:11 +1000 | [diff] [blame] | 124 | device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 125 | break; |
Ben Skeggs | caba557 | 2012-12-06 14:45:57 +1000 | [diff] [blame] | 126 | case 0xe6: |
| 127 | device->cname = "GK106"; |
| 128 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
Ben Skeggs | fa531bc | 2013-02-13 13:34:39 +1000 | [diff] [blame] | 129 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass; |
Ben Skeggs | 7dcd060c | 2013-02-16 15:21:58 +1000 | [diff] [blame] | 130 | device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass; |
Ben Skeggs | 7c85652 | 2013-01-14 08:28:28 +1000 | [diff] [blame] | 131 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; |
Ben Skeggs | bc79202 | 2012-12-04 09:50:33 +1000 | [diff] [blame] | 132 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
Ben Skeggs | caba557 | 2012-12-06 14:45:57 +1000 | [diff] [blame] | 133 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
Ben Skeggs | cf33601 | 2014-01-14 15:55:38 +1000 | [diff] [blame] | 134 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
Ben Skeggs | 1b4fea0 | 2013-10-11 15:38:15 +1000 | [diff] [blame] | 135 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
Ben Skeggs | 48ae0b3 | 2013-10-24 09:39:05 +1000 | [diff] [blame] | 136 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
Ben Skeggs | caba557 | 2012-12-06 14:45:57 +1000 | [diff] [blame] | 137 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
Ben Skeggs | aae95ca | 2013-03-04 15:01:37 +1000 | [diff] [blame] | 138 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; |
Ben Skeggs | f6bad8a | 2014-02-24 14:17:49 +1000 | [diff] [blame] | 139 | device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; |
Ben Skeggs | caba557 | 2012-12-06 14:45:57 +1000 | [diff] [blame] | 140 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
Ben Skeggs | 24a4ae8 | 2013-12-23 00:39:47 +1000 | [diff] [blame] | 141 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
Ben Skeggs | caba557 | 2012-12-06 14:45:57 +1000 | [diff] [blame] | 142 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 143 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
Ben Skeggs | ff4b42c | 2013-10-15 09:38:12 +1000 | [diff] [blame] | 144 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; |
Ben Skeggs | c9c0cca | 2013-02-08 09:34:56 +1000 | [diff] [blame] | 145 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
Ben Skeggs | caba557 | 2012-12-06 14:45:57 +1000 | [diff] [blame] | 146 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; |
Ben Skeggs | 16c4f22 | 2013-11-05 14:26:58 +1000 | [diff] [blame] | 147 | device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; |
Ben Skeggs | c46c3dd | 2013-10-03 07:30:11 +1000 | [diff] [blame] | 148 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
Ben Skeggs | 30f4e08 | 2013-06-09 16:08:22 +1000 | [diff] [blame] | 149 | device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; |
Ben Skeggs | a8f8b48 | 2014-02-20 21:33:34 +1000 | [diff] [blame] | 150 | device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; |
Ben Skeggs | caba557 | 2012-12-06 14:45:57 +1000 | [diff] [blame] | 151 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; |
| 152 | device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; |
Ben Skeggs | b0bc530 | 2013-04-29 09:31:05 +1000 | [diff] [blame] | 153 | device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; |
Ben Skeggs | caba557 | 2012-12-06 14:45:57 +1000 | [diff] [blame] | 154 | device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; |
| 155 | device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; |
| 156 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
Ben Skeggs | aa4d7a4 | 2013-02-13 15:29:11 +1000 | [diff] [blame] | 157 | device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; |
Ben Skeggs | caba557 | 2012-12-06 14:45:57 +1000 | [diff] [blame] | 158 | break; |
Alexandre Courbot | 52e98f1 | 2014-05-02 18:32:42 +0900 | [diff] [blame^] | 159 | case 0xea: |
| 160 | device->cname = "GK20A"; |
| 161 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
| 162 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
| 163 | device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; |
| 164 | device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass; |
| 165 | device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass; |
| 166 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 167 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 168 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 169 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; |
| 170 | device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; |
| 171 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
| 172 | device->oclass[NVDEV_ENGINE_GR ] = gk20a_graph_oclass; |
| 173 | device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; |
| 174 | device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; |
| 175 | break; |
Ben Skeggs | 7b4f638 | 2013-03-30 22:21:54 +1000 | [diff] [blame] | 176 | case 0xf0: |
| 177 | device->cname = "GK110"; |
| 178 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 179 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass; |
| 180 | device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass; |
Ben Skeggs | 7c85652 | 2013-01-14 08:28:28 +1000 | [diff] [blame] | 181 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; |
Ben Skeggs | 7b4f638 | 2013-03-30 22:21:54 +1000 | [diff] [blame] | 182 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
| 183 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
Ben Skeggs | cf33601 | 2014-01-14 15:55:38 +1000 | [diff] [blame] | 184 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
Ben Skeggs | 1b4fea0 | 2013-10-11 15:38:15 +1000 | [diff] [blame] | 185 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
Ben Skeggs | 48ae0b3 | 2013-10-24 09:39:05 +1000 | [diff] [blame] | 186 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
Ben Skeggs | 7b4f638 | 2013-03-30 22:21:54 +1000 | [diff] [blame] | 187 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
Ben Skeggs | aae95ca | 2013-03-04 15:01:37 +1000 | [diff] [blame] | 188 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; |
Ben Skeggs | f6bad8a | 2014-02-24 14:17:49 +1000 | [diff] [blame] | 189 | device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; |
Ben Skeggs | 7b4f638 | 2013-03-30 22:21:54 +1000 | [diff] [blame] | 190 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
Ben Skeggs | 24a4ae8 | 2013-12-23 00:39:47 +1000 | [diff] [blame] | 191 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
Ben Skeggs | 7b4f638 | 2013-03-30 22:21:54 +1000 | [diff] [blame] | 192 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 193 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
Ben Skeggs | ff4b42c | 2013-10-15 09:38:12 +1000 | [diff] [blame] | 194 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; |
Ben Skeggs | c9c0cca | 2013-02-08 09:34:56 +1000 | [diff] [blame] | 195 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
Ben Skeggs | 7b4f638 | 2013-03-30 22:21:54 +1000 | [diff] [blame] | 196 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; |
Ben Skeggs | 16c4f22 | 2013-11-05 14:26:58 +1000 | [diff] [blame] | 197 | device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; |
Ben Skeggs | c46c3dd | 2013-10-03 07:30:11 +1000 | [diff] [blame] | 198 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
Ben Skeggs | 30f4e08 | 2013-06-09 16:08:22 +1000 | [diff] [blame] | 199 | device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass; |
Ben Skeggs | a8f8b48 | 2014-02-20 21:33:34 +1000 | [diff] [blame] | 200 | device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; |
Ben Skeggs | 7b4f638 | 2013-03-30 22:21:54 +1000 | [diff] [blame] | 201 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; |
| 202 | device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; |
| 203 | device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; |
Ben Skeggs | 9ec2dbb | 2013-05-02 12:38:41 +1000 | [diff] [blame] | 204 | #if 0 |
Ben Skeggs | 7b4f638 | 2013-03-30 22:21:54 +1000 | [diff] [blame] | 205 | device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; |
| 206 | device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; |
| 207 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
| 208 | #endif |
Ben Skeggs | aa4d7a4 | 2013-02-13 15:29:11 +1000 | [diff] [blame] | 209 | device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass; |
Ben Skeggs | 7b4f638 | 2013-03-30 22:21:54 +1000 | [diff] [blame] | 210 | break; |
Ben Skeggs | aabf19c | 2013-11-05 13:14:25 +1000 | [diff] [blame] | 211 | case 0x108: |
| 212 | device->cname = "GK208"; |
| 213 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 214 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass; |
| 215 | device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass; |
Ben Skeggs | 7c85652 | 2013-01-14 08:28:28 +1000 | [diff] [blame] | 216 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; |
Ben Skeggs | aabf19c | 2013-11-05 13:14:25 +1000 | [diff] [blame] | 217 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
| 218 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
Ben Skeggs | cf33601 | 2014-01-14 15:55:38 +1000 | [diff] [blame] | 219 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
Ben Skeggs | aabf19c | 2013-11-05 13:14:25 +1000 | [diff] [blame] | 220 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
Ben Skeggs | 48ae0b3 | 2013-10-24 09:39:05 +1000 | [diff] [blame] | 221 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
Ben Skeggs | aabf19c | 2013-11-05 13:14:25 +1000 | [diff] [blame] | 222 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
Ben Skeggs | aae95ca | 2013-03-04 15:01:37 +1000 | [diff] [blame] | 223 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; |
Ben Skeggs | f6bad8a | 2014-02-24 14:17:49 +1000 | [diff] [blame] | 224 | device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; |
Ben Skeggs | aabf19c | 2013-11-05 13:14:25 +1000 | [diff] [blame] | 225 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
Ben Skeggs | 24a4ae8 | 2013-12-23 00:39:47 +1000 | [diff] [blame] | 226 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
Ben Skeggs | aabf19c | 2013-11-05 13:14:25 +1000 | [diff] [blame] | 227 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 228 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
Ben Skeggs | ff4b42c | 2013-10-15 09:38:12 +1000 | [diff] [blame] | 229 | device->oclass[NVDEV_SUBDEV_PWR ] = &nv108_pwr_oclass; |
Ben Skeggs | c9c0cca | 2013-02-08 09:34:56 +1000 | [diff] [blame] | 230 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
Ben Skeggs | aabf19c | 2013-11-05 13:14:25 +1000 | [diff] [blame] | 231 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; |
Ben Skeggs | a763951 | 2013-11-05 14:36:45 +1000 | [diff] [blame] | 232 | device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; |
Ben Skeggs | aabf19c | 2013-11-05 13:14:25 +1000 | [diff] [blame] | 233 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
Ben Skeggs | 96616b4 | 2013-11-05 14:49:49 +1000 | [diff] [blame] | 234 | device->oclass[NVDEV_ENGINE_GR ] = nv108_graph_oclass; |
Ben Skeggs | a8f8b48 | 2014-02-20 21:33:34 +1000 | [diff] [blame] | 235 | device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; |
Ben Skeggs | aabf19c | 2013-11-05 13:14:25 +1000 | [diff] [blame] | 236 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; |
| 237 | device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; |
| 238 | device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; |
Ben Skeggs | daa9ab5 | 2013-11-05 14:39:24 +1000 | [diff] [blame] | 239 | #if 0 |
Ben Skeggs | aabf19c | 2013-11-05 13:14:25 +1000 | [diff] [blame] | 240 | device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; |
| 241 | device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; |
| 242 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
| 243 | #endif |
| 244 | break; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 245 | default: |
| 246 | nv_fatal(device, "unknown Kepler chipset\n"); |
| 247 | return -EINVAL; |
| 248 | } |
| 249 | |
| 250 | return 0; |
| 251 | } |