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Bard Liao07cf7cba2014-06-20 14:41:13 +08001/*
2 * rt286.c -- RT286 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
Bard Liao6c67cde2014-11-06 09:59:59 +080020#include <linux/dmi.h>
Bard Liao07cf7cba2014-06-20 14:41:13 +080021#include <linux/acpi.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29#include <sound/jack.h>
30#include <linux/workqueue.h>
31#include <sound/rt286.h>
32#include <sound/hda_verbs.h>
33
34#include "rt286.h"
35
36#define RT286_VENDOR_ID 0x10ec0286
37
38struct rt286_priv {
39 struct regmap *regmap;
Bard Liao6879db72014-10-31 14:52:16 +080040 struct snd_soc_codec *codec;
Bard Liao07cf7cba2014-06-20 14:41:13 +080041 struct rt286_platform_data pdata;
42 struct i2c_client *i2c;
43 struct snd_soc_jack *jack;
44 struct delayed_work jack_detect_work;
45 int sys_clk;
Bard Liao6879db72014-10-31 14:52:16 +080046 int clk_id;
Bard Liao07cf7cba2014-06-20 14:41:13 +080047 struct reg_default *index_cache;
48};
49
50static struct reg_default rt286_index_def[] = {
51 { 0x01, 0xaaaa },
52 { 0x02, 0x8aaa },
53 { 0x03, 0x0002 },
54 { 0x04, 0xaf01 },
55 { 0x08, 0x000d },
56 { 0x09, 0xd810 },
Bard Liaob7a29762014-09-26 11:06:39 +080057 { 0x0a, 0x0120 },
Bard Liao07cf7cba2014-06-20 14:41:13 +080058 { 0x0b, 0x0000 },
Bard Liaobc6c4e42014-07-07 19:15:30 +080059 { 0x0d, 0x2800 },
Bard Liao07cf7cba2014-06-20 14:41:13 +080060 { 0x0f, 0x0000 },
61 { 0x19, 0x0a17 },
62 { 0x20, 0x0020 },
63 { 0x33, 0x0208 },
64 { 0x49, 0x0004 },
65 { 0x4f, 0x50e9 },
Bard Liaob7a29762014-09-26 11:06:39 +080066 { 0x50, 0x2000 },
Bard Liao07cf7cba2014-06-20 14:41:13 +080067 { 0x63, 0x2902 },
Bard Liaobc6c4e42014-07-07 19:15:30 +080068 { 0x67, 0x1111 },
69 { 0x68, 0x1016 },
70 { 0x69, 0x273f },
Bard Liao07cf7cba2014-06-20 14:41:13 +080071};
72#define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def)
73
74static const struct reg_default rt286_reg[] = {
75 { 0x00170500, 0x00000400 },
76 { 0x00220000, 0x00000031 },
77 { 0x00239000, 0x0000007f },
78 { 0x0023a000, 0x0000007f },
79 { 0x00270500, 0x00000400 },
80 { 0x00370500, 0x00000400 },
81 { 0x00870500, 0x00000400 },
82 { 0x00920000, 0x00000031 },
83 { 0x00935000, 0x000000c3 },
84 { 0x00936000, 0x000000c3 },
85 { 0x00970500, 0x00000400 },
86 { 0x00b37000, 0x00000097 },
87 { 0x00b37200, 0x00000097 },
88 { 0x00b37300, 0x00000097 },
89 { 0x00c37000, 0x00000000 },
90 { 0x00c37100, 0x00000080 },
91 { 0x01270500, 0x00000400 },
92 { 0x01370500, 0x00000400 },
93 { 0x01371f00, 0x411111f0 },
94 { 0x01439000, 0x00000080 },
95 { 0x0143a000, 0x00000080 },
96 { 0x01470700, 0x00000000 },
97 { 0x01470500, 0x00000400 },
98 { 0x01470c00, 0x00000000 },
99 { 0x01470100, 0x00000000 },
100 { 0x01837000, 0x00000000 },
101 { 0x01870500, 0x00000400 },
102 { 0x02050000, 0x00000000 },
103 { 0x02139000, 0x00000080 },
104 { 0x0213a000, 0x00000080 },
105 { 0x02170100, 0x00000000 },
106 { 0x02170500, 0x00000400 },
107 { 0x02170700, 0x00000000 },
108 { 0x02270100, 0x00000000 },
109 { 0x02370100, 0x00000000 },
Bard Liao07cf7cba2014-06-20 14:41:13 +0800110 { 0x01870700, 0x00000020 },
111 { 0x00830000, 0x000000c3 },
112 { 0x00930000, 0x000000c3 },
113 { 0x01270700, 0x00000000 },
114};
115
116static bool rt286_volatile_register(struct device *dev, unsigned int reg)
117{
118 switch (reg) {
119 case 0 ... 0xff:
120 case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
121 case RT286_GET_HP_SENSE:
122 case RT286_GET_MIC1_SENSE:
123 case RT286_PROC_COEF:
124 return true;
125 default:
126 return false;
127 }
128
129
130}
131
132static bool rt286_readable_register(struct device *dev, unsigned int reg)
133{
134 switch (reg) {
135 case 0 ... 0xff:
136 case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
137 case RT286_GET_HP_SENSE:
138 case RT286_GET_MIC1_SENSE:
139 case RT286_SET_AUDIO_POWER:
140 case RT286_SET_HPO_POWER:
141 case RT286_SET_SPK_POWER:
142 case RT286_SET_DMIC1_POWER:
143 case RT286_SPK_MUX:
144 case RT286_HPO_MUX:
145 case RT286_ADC0_MUX:
146 case RT286_ADC1_MUX:
147 case RT286_SET_MIC1:
148 case RT286_SET_PIN_HPO:
149 case RT286_SET_PIN_SPK:
150 case RT286_SET_PIN_DMIC1:
151 case RT286_SPK_EAPD:
152 case RT286_SET_AMP_GAIN_HPO:
153 case RT286_SET_DMIC2_DEFAULT:
154 case RT286_DACL_GAIN:
155 case RT286_DACR_GAIN:
156 case RT286_ADCL_GAIN:
157 case RT286_ADCR_GAIN:
158 case RT286_MIC_GAIN:
159 case RT286_SPOL_GAIN:
160 case RT286_SPOR_GAIN:
161 case RT286_HPOL_GAIN:
162 case RT286_HPOR_GAIN:
163 case RT286_F_DAC_SWITCH:
164 case RT286_F_RECMIX_SWITCH:
165 case RT286_REC_MIC_SWITCH:
166 case RT286_REC_I2S_SWITCH:
167 case RT286_REC_LINE_SWITCH:
168 case RT286_REC_BEEP_SWITCH:
169 case RT286_DAC_FORMAT:
170 case RT286_ADC_FORMAT:
171 case RT286_COEF_INDEX:
172 case RT286_PROC_COEF:
173 case RT286_SET_AMP_GAIN_ADC_IN1:
174 case RT286_SET_AMP_GAIN_ADC_IN2:
175 case RT286_SET_POWER(RT286_DAC_OUT1):
176 case RT286_SET_POWER(RT286_DAC_OUT2):
177 case RT286_SET_POWER(RT286_ADC_IN1):
178 case RT286_SET_POWER(RT286_ADC_IN2):
179 case RT286_SET_POWER(RT286_DMIC2):
180 case RT286_SET_POWER(RT286_MIC1):
181 return true;
182 default:
183 return false;
184 }
185}
186
187static int rt286_hw_write(void *context, unsigned int reg, unsigned int value)
188{
189 struct i2c_client *client = context;
190 struct rt286_priv *rt286 = i2c_get_clientdata(client);
191 u8 data[4];
192 int ret, i;
193
Bard Liaof8c101b2014-11-06 10:00:00 +0800194 /* handle index registers */
Bard Liao07cf7cba2014-06-20 14:41:13 +0800195 if (reg <= 0xff) {
196 rt286_hw_write(client, RT286_COEF_INDEX, reg);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800197 for (i = 0; i < INDEX_CACHE_SIZE; i++) {
198 if (reg == rt286->index_cache[i].reg) {
199 rt286->index_cache[i].def = value;
200 break;
201 }
202
203 }
Bard Liao66d627d2014-09-26 11:06:40 +0800204 reg = RT286_PROC_COEF;
Bard Liao07cf7cba2014-06-20 14:41:13 +0800205 }
206
207 data[0] = (reg >> 24) & 0xff;
208 data[1] = (reg >> 16) & 0xff;
209 /*
210 * 4 bit VID: reg should be 0
211 * 12 bit VID: value should be 0
212 * So we use an OR operator to handle it rather than use if condition.
213 */
214 data[2] = ((reg >> 8) & 0xff) | ((value >> 8) & 0xff);
215 data[3] = value & 0xff;
216
217 ret = i2c_master_send(client, data, 4);
218
219 if (ret == 4)
220 return 0;
221 else
222 pr_err("ret=%d\n", ret);
223 if (ret < 0)
224 return ret;
225 else
226 return -EIO;
227}
228
229static int rt286_hw_read(void *context, unsigned int reg, unsigned int *value)
230{
231 struct i2c_client *client = context;
232 struct i2c_msg xfer[2];
233 int ret;
234 __be32 be_reg;
235 unsigned int index, vid, buf = 0x0;
236
Bard Liaof8c101b2014-11-06 10:00:00 +0800237 /* handle index registers */
Bard Liao07cf7cba2014-06-20 14:41:13 +0800238 if (reg <= 0xff) {
239 rt286_hw_write(client, RT286_COEF_INDEX, reg);
240 reg = RT286_PROC_COEF;
241 }
242
243 reg = reg | 0x80000;
244 vid = (reg >> 8) & 0xfff;
245
246 if (AC_VERB_GET_AMP_GAIN_MUTE == (vid & 0xf00)) {
247 index = (reg >> 8) & 0xf;
248 reg = (reg & ~0xf0f) | index;
249 }
250 be_reg = cpu_to_be32(reg);
251
252 /* Write register */
253 xfer[0].addr = client->addr;
254 xfer[0].flags = 0;
255 xfer[0].len = 4;
256 xfer[0].buf = (u8 *)&be_reg;
257
258 /* Read data */
259 xfer[1].addr = client->addr;
260 xfer[1].flags = I2C_M_RD;
261 xfer[1].len = 4;
262 xfer[1].buf = (u8 *)&buf;
263
264 ret = i2c_transfer(client->adapter, xfer, 2);
265 if (ret < 0)
266 return ret;
267 else if (ret != 2)
268 return -EIO;
269
270 *value = be32_to_cpu(buf);
271
272 return 0;
273}
274
Thierry Reding81f3dfe2014-10-02 09:27:03 +0200275#ifdef CONFIG_PM
Bard Liao07cf7cba2014-06-20 14:41:13 +0800276static void rt286_index_sync(struct snd_soc_codec *codec)
277{
278 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
279 int i;
280
281 for (i = 0; i < INDEX_CACHE_SIZE; i++) {
282 snd_soc_write(codec, rt286->index_cache[i].reg,
283 rt286->index_cache[i].def);
284 }
285}
Thierry Reding81f3dfe2014-10-02 09:27:03 +0200286#endif
Bard Liao07cf7cba2014-06-20 14:41:13 +0800287
288static int rt286_support_power_controls[] = {
289 RT286_DAC_OUT1,
290 RT286_DAC_OUT2,
291 RT286_ADC_IN1,
292 RT286_ADC_IN2,
293 RT286_MIC1,
294 RT286_DMIC1,
295 RT286_DMIC2,
296 RT286_SPK_OUT,
297 RT286_HP_OUT,
298};
299#define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls)
300
Bard Liao90f601e2014-07-29 13:50:57 +0800301static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic)
Bard Liao07cf7cba2014-06-20 14:41:13 +0800302{
Bard Liao07cf7cba2014-06-20 14:41:13 +0800303 unsigned int val, buf;
Bard Liao07cf7cba2014-06-20 14:41:13 +0800304
305 *hp = false;
306 *mic = false;
307
308 if (rt286->pdata.cbj_en) {
Bard Liao90f601e2014-07-29 13:50:57 +0800309 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800310 *hp = buf & 0x80000000;
311 if (*hp) {
312 /* power on HV,VERF */
Bard Liao90f601e2014-07-29 13:50:57 +0800313 regmap_update_bits(rt286->regmap,
Bard Liao6879db72014-10-31 14:52:16 +0800314 RT286_DC_GAIN, 0x200, 0x200);
315
316 snd_soc_dapm_force_enable_pin(&rt286->codec->dapm,
317 "HV");
318 snd_soc_dapm_force_enable_pin(&rt286->codec->dapm,
319 "VREF");
Bard Liao07cf7cba2014-06-20 14:41:13 +0800320 /* power LDO1 */
Bard Liao6879db72014-10-31 14:52:16 +0800321 snd_soc_dapm_force_enable_pin(&rt286->codec->dapm,
322 "LDO1");
323 snd_soc_dapm_sync(&rt286->codec->dapm);
324
Bard Liao90f601e2014-07-29 13:50:57 +0800325 regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24);
Bard Liao6879db72014-10-31 14:52:16 +0800326 msleep(50);
327
328 regmap_update_bits(rt286->regmap,
329 RT286_CBJ_CTRL1, 0xfcc0, 0xd400);
330 msleep(300);
Bard Liao90f601e2014-07-29 13:50:57 +0800331 regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800332
Bard Liao6879db72014-10-31 14:52:16 +0800333 if (0x0070 == (val & 0x0070)) {
334 *mic = true;
335 } else {
336 regmap_update_bits(rt286->regmap,
337 RT286_CBJ_CTRL1, 0xfcc0, 0xe400);
338 msleep(300);
Bard Liao90f601e2014-07-29 13:50:57 +0800339 regmap_read(rt286->regmap,
340 RT286_CBJ_CTRL2, &val);
Bard Liao6879db72014-10-31 14:52:16 +0800341 if (0x0070 == (val & 0x0070))
342 *mic = true;
343 else
344 *mic = false;
Bard Liao07cf7cba2014-06-20 14:41:13 +0800345 }
Bard Liao90f601e2014-07-29 13:50:57 +0800346 regmap_update_bits(rt286->regmap,
Bard Liao6879db72014-10-31 14:52:16 +0800347 RT286_DC_GAIN, 0x200, 0x0);
348
Bard Liao07cf7cba2014-06-20 14:41:13 +0800349 } else {
Bard Liao07cf7cba2014-06-20 14:41:13 +0800350 *mic = false;
Bard Liao6879db72014-10-31 14:52:16 +0800351 regmap_write(rt286->regmap, RT286_SET_MIC1, 0x20);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800352 }
353 } else {
Bard Liao90f601e2014-07-29 13:50:57 +0800354 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800355 *hp = buf & 0x80000000;
Bard Liao90f601e2014-07-29 13:50:57 +0800356 regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800357 *mic = buf & 0x80000000;
358 }
359
Bard Liao6879db72014-10-31 14:52:16 +0800360 snd_soc_dapm_disable_pin(&rt286->codec->dapm, "HV");
361 snd_soc_dapm_disable_pin(&rt286->codec->dapm, "VREF");
362 if (!*hp)
363 snd_soc_dapm_disable_pin(&rt286->codec->dapm, "LDO1");
364 snd_soc_dapm_sync(&rt286->codec->dapm);
365
Bard Liao07cf7cba2014-06-20 14:41:13 +0800366 return 0;
367}
368
369static void rt286_jack_detect_work(struct work_struct *work)
370{
371 struct rt286_priv *rt286 =
372 container_of(work, struct rt286_priv, jack_detect_work.work);
373 int status = 0;
374 bool hp = false;
375 bool mic = false;
376
Bard Liao90f601e2014-07-29 13:50:57 +0800377 rt286_jack_detect(rt286, &hp, &mic);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800378
379 if (hp == true)
380 status |= SND_JACK_HEADPHONE;
381
382 if (mic == true)
383 status |= SND_JACK_MICROPHONE;
384
385 snd_soc_jack_report(rt286->jack, status,
386 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
387}
388
389int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
390{
391 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
392
393 rt286->jack = jack;
394
395 /* Send an initial empty report */
396 snd_soc_jack_report(rt286->jack, 0,
397 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
398
399 return 0;
400}
401EXPORT_SYMBOL_GPL(rt286_mic_detect);
402
Bard Liao6879db72014-10-31 14:52:16 +0800403static int is_mclk_mode(struct snd_soc_dapm_widget *source,
404 struct snd_soc_dapm_widget *sink)
405{
406 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(source->codec);
407
408 if (rt286->clk_id == RT286_SCLK_S_MCLK)
409 return 1;
410 else
411 return 0;
412}
413
Bard Liao07cf7cba2014-06-20 14:41:13 +0800414static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
415static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
416
417static const struct snd_kcontrol_new rt286_snd_controls[] = {
418 SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN,
419 RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
Bard Liao54d96a42015-01-23 14:51:09 +0800420 SOC_DOUBLE_R("ADC0 Capture Switch", RT286_ADCL_GAIN,
421 RT286_ADCR_GAIN, 7, 1, 1),
Bard Liao07cf7cba2014-06-20 14:41:13 +0800422 SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN,
423 RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
424 SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN,
425 0, 0x3, 0, mic_vol_tlv),
426 SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN,
427 RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1),
428};
429
430/* Digital Mixer */
431static const struct snd_kcontrol_new rt286_front_mix[] = {
432 SOC_DAPM_SINGLE("DAC Switch", RT286_F_DAC_SWITCH,
433 RT286_MUTE_SFT, 1, 1),
434 SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH,
435 RT286_MUTE_SFT, 1, 1),
436};
437
438/* Analog Input Mixer */
439static const struct snd_kcontrol_new rt286_rec_mix[] = {
440 SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH,
441 RT286_MUTE_SFT, 1, 1),
442 SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH,
443 RT286_MUTE_SFT, 1, 1),
444 SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH,
445 RT286_MUTE_SFT, 1, 1),
446 SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH,
447 RT286_MUTE_SFT, 1, 1),
448};
449
450static const struct snd_kcontrol_new spo_enable_control =
451 SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK,
452 RT286_SET_PIN_SFT, 1, 0);
453
454static const struct snd_kcontrol_new hpol_enable_control =
455 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN,
456 RT286_MUTE_SFT, 1, 1);
457
458static const struct snd_kcontrol_new hpor_enable_control =
459 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN,
460 RT286_MUTE_SFT, 1, 1);
461
462/* ADC0 source */
463static const char * const rt286_adc_src[] = {
464 "Mic", "RECMIX", "Dmic"
465};
466
467static const int rt286_adc_values[] = {
468 0, 4, 5,
469};
470
471static SOC_VALUE_ENUM_SINGLE_DECL(
472 rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT,
473 RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
474
475static const struct snd_kcontrol_new rt286_adc0_mux =
476 SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum);
477
478static SOC_VALUE_ENUM_SINGLE_DECL(
479 rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT,
480 RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
481
482static const struct snd_kcontrol_new rt286_adc1_mux =
483 SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum);
484
485static const char * const rt286_dac_src[] = {
486 "Front", "Surround"
487};
488/* HP-OUT source */
489static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX,
490 0, rt286_dac_src);
491
492static const struct snd_kcontrol_new rt286_hpo_mux =
493SOC_DAPM_ENUM("HPO source", rt286_hpo_enum);
494
495/* SPK-OUT source */
496static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX,
497 0, rt286_dac_src);
498
499static const struct snd_kcontrol_new rt286_spo_mux =
500SOC_DAPM_ENUM("SPO source", rt286_spo_enum);
501
502static int rt286_spk_event(struct snd_soc_dapm_widget *w,
503 struct snd_kcontrol *kcontrol, int event)
504{
505 struct snd_soc_codec *codec = w->codec;
506
507 switch (event) {
508 case SND_SOC_DAPM_POST_PMU:
509 snd_soc_write(codec,
510 RT286_SPK_EAPD, RT286_SET_EAPD_HIGH);
511 break;
512 case SND_SOC_DAPM_PRE_PMD:
513 snd_soc_write(codec,
514 RT286_SPK_EAPD, RT286_SET_EAPD_LOW);
515 break;
516
517 default:
518 return 0;
519 }
520
521 return 0;
522}
523
524static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w,
525 struct snd_kcontrol *kcontrol, int event)
526{
527 struct snd_soc_codec *codec = w->codec;
528
529 switch (event) {
530 case SND_SOC_DAPM_POST_PMU:
531 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0x20);
532 break;
533 case SND_SOC_DAPM_PRE_PMD:
534 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0);
535 break;
536 default:
537 return 0;
538 }
539
540 return 0;
541}
542
Bard Liao6879db72014-10-31 14:52:16 +0800543static int rt286_vref_event(struct snd_soc_dapm_widget *w,
544 struct snd_kcontrol *kcontrol, int event)
545{
546 struct snd_soc_codec *codec = w->codec;
547
548 switch (event) {
549 case SND_SOC_DAPM_PRE_PMU:
550 snd_soc_update_bits(codec,
551 RT286_CBJ_CTRL1, 0x0400, 0x0000);
552 mdelay(50);
553 break;
554 default:
555 return 0;
556 }
557
558 return 0;
559}
560
561static int rt286_ldo2_event(struct snd_soc_dapm_widget *w,
562 struct snd_kcontrol *kcontrol, int event)
563{
564 struct snd_soc_codec *codec = w->codec;
565
566 switch (event) {
567 case SND_SOC_DAPM_POST_PMU:
568 snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x08);
569 break;
570 case SND_SOC_DAPM_PRE_PMD:
571 snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x30);
572 break;
573 default:
574 return 0;
575 }
576
577 return 0;
578}
579
580static int rt286_mic1_event(struct snd_soc_dapm_widget *w,
581 struct snd_kcontrol *kcontrol, int event)
582{
583 struct snd_soc_codec *codec = w->codec;
584
585 switch (event) {
586 case SND_SOC_DAPM_PRE_PMU:
587 snd_soc_update_bits(codec,
588 RT286_A_BIAS_CTRL3, 0xc000, 0x8000);
589 snd_soc_update_bits(codec,
590 RT286_A_BIAS_CTRL2, 0xc000, 0x8000);
591 break;
592 case SND_SOC_DAPM_POST_PMD:
593 snd_soc_update_bits(codec,
594 RT286_A_BIAS_CTRL3, 0xc000, 0x0000);
595 snd_soc_update_bits(codec,
596 RT286_A_BIAS_CTRL2, 0xc000, 0x0000);
597 break;
598 default:
599 return 0;
600 }
601
602 return 0;
603}
604
Bard Liao07cf7cba2014-06-20 14:41:13 +0800605static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = {
Bard Liao6879db72014-10-31 14:52:16 +0800606 SND_SOC_DAPM_SUPPLY_S("HV", 1, RT286_POWER_CTRL1,
607 12, 1, NULL, 0),
608 SND_SOC_DAPM_SUPPLY("VREF", RT286_POWER_CTRL1,
609 0, 1, rt286_vref_event, SND_SOC_DAPM_PRE_PMU),
610 SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT286_POWER_CTRL2,
611 2, 0, NULL, 0),
612 SND_SOC_DAPM_SUPPLY_S("LDO2", 2, RT286_POWER_CTRL1,
613 13, 1, rt286_ldo2_event, SND_SOC_DAPM_PRE_PMD |
614 SND_SOC_DAPM_POST_PMU),
615 SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1,
616 5, 0, NULL, 0),
617 SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
618 0, 0, rt286_mic1_event, SND_SOC_DAPM_PRE_PMU |
619 SND_SOC_DAPM_POST_PMD),
620
Bard Liao07cf7cba2014-06-20 14:41:13 +0800621 /* Input Lines */
622 SND_SOC_DAPM_INPUT("DMIC1 Pin"),
623 SND_SOC_DAPM_INPUT("DMIC2 Pin"),
624 SND_SOC_DAPM_INPUT("MIC1"),
625 SND_SOC_DAPM_INPUT("LINE1"),
626 SND_SOC_DAPM_INPUT("Beep"),
627
628 /* DMIC */
629 SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1,
630 NULL, 0, rt286_set_dmic1_event,
631 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
632 SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1,
633 NULL, 0),
634 SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
635 0, 0, NULL, 0),
636
637 /* REC Mixer */
638 SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
639 rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)),
640
641 /* ADCs */
642 SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
643 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
644
645 /* ADC Mux */
Bard Liao54d96a42015-01-23 14:51:09 +0800646 SND_SOC_DAPM_MUX("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1,
647 &rt286_adc0_mux),
648 SND_SOC_DAPM_MUX("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1,
649 &rt286_adc1_mux),
Bard Liao07cf7cba2014-06-20 14:41:13 +0800650
651 /* Audio Interface */
652 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
653 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
654 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
655 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
656
657 /* Output Side */
658 /* DACs */
659 SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
660 SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
661
662 /* Output Mux */
663 SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux),
664 SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux),
665
666 SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO,
667 RT286_SET_PIN_SFT, 0, NULL, 0),
668
669 /* Output Mixer */
670 SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1,
671 rt286_front_mix, ARRAY_SIZE(rt286_front_mix)),
672 SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1,
673 NULL, 0),
674
675 /* Output Pga */
676 SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
677 &spo_enable_control, rt286_spk_event,
678 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
679 SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
680 &hpol_enable_control),
681 SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
682 &hpor_enable_control),
683
684 /* Output Lines */
685 SND_SOC_DAPM_OUTPUT("SPOL"),
686 SND_SOC_DAPM_OUTPUT("SPOR"),
687 SND_SOC_DAPM_OUTPUT("HPO Pin"),
688 SND_SOC_DAPM_OUTPUT("SPDIF"),
689};
690
691static const struct snd_soc_dapm_route rt286_dapm_routes[] = {
Bard Liao6879db72014-10-31 14:52:16 +0800692 {"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
693 {"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
694 {"Front", NULL, "MCLK MODE", is_mclk_mode},
695 {"Surround", NULL, "MCLK MODE", is_mclk_mode},
696
697 {"HP Power", NULL, "LDO1"},
698 {"HP Power", NULL, "LDO2"},
699
700 {"MIC1", NULL, "LDO1"},
701 {"MIC1", NULL, "LDO2"},
702 {"MIC1", NULL, "HV"},
703 {"MIC1", NULL, "VREF"},
704 {"MIC1", NULL, "MIC1 Input Buffer"},
705
706 {"SPO", NULL, "LDO1"},
707 {"SPO", NULL, "LDO2"},
708 {"SPO", NULL, "HV"},
709 {"SPO", NULL, "VREF"},
710
Bard Liao07cf7cba2014-06-20 14:41:13 +0800711 {"DMIC1", NULL, "DMIC1 Pin"},
712 {"DMIC2", NULL, "DMIC2 Pin"},
713 {"DMIC1", NULL, "DMIC Receiver"},
714 {"DMIC2", NULL, "DMIC Receiver"},
715
716 {"RECMIX", "Beep Switch", "Beep"},
717 {"RECMIX", "Line1 Switch", "LINE1"},
718 {"RECMIX", "Mic1 Switch", "MIC1"},
719
720 {"ADC 0 Mux", "Dmic", "DMIC1"},
721 {"ADC 0 Mux", "RECMIX", "RECMIX"},
722 {"ADC 0 Mux", "Mic", "MIC1"},
723 {"ADC 1 Mux", "Dmic", "DMIC2"},
724 {"ADC 1 Mux", "RECMIX", "RECMIX"},
725 {"ADC 1 Mux", "Mic", "MIC1"},
726
727 {"ADC 0", NULL, "ADC 0 Mux"},
728 {"ADC 1", NULL, "ADC 1 Mux"},
729
730 {"AIF1TX", NULL, "ADC 0"},
731 {"AIF2TX", NULL, "ADC 1"},
732
733 {"DAC 0", NULL, "AIF1RX"},
734 {"DAC 1", NULL, "AIF2RX"},
735
736 {"Front", "DAC Switch", "DAC 0"},
737 {"Front", "RECMIX Switch", "RECMIX"},
738
739 {"Surround", NULL, "DAC 1"},
740
741 {"SPK Mux", "Front", "Front"},
742 {"SPK Mux", "Surround", "Surround"},
743
744 {"HPO Mux", "Front", "Front"},
745 {"HPO Mux", "Surround", "Surround"},
746
747 {"SPO", "Switch", "SPK Mux"},
748 {"HPO L", "Switch", "HPO Mux"},
749 {"HPO R", "Switch", "HPO Mux"},
750 {"HPO L", NULL, "HP Power"},
751 {"HPO R", NULL, "HP Power"},
752
753 {"SPOL", NULL, "SPO"},
754 {"SPOR", NULL, "SPO"},
755 {"HPO Pin", NULL, "HPO L"},
756 {"HPO Pin", NULL, "HPO R"},
757};
758
759static int rt286_hw_params(struct snd_pcm_substream *substream,
760 struct snd_pcm_hw_params *params,
761 struct snd_soc_dai *dai)
762{
763 struct snd_soc_codec *codec = dai->codec;
764 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
765 unsigned int val = 0;
766 int d_len_code;
767
768 switch (params_rate(params)) {
769 /* bit 14 0:48K 1:44.1K */
770 case 44100:
771 val |= 0x4000;
772 break;
773 case 48000:
774 break;
775 default:
776 dev_err(codec->dev, "Unsupported sample rate %d\n",
777 params_rate(params));
778 return -EINVAL;
779 }
780 switch (rt286->sys_clk) {
781 case 12288000:
782 case 24576000:
783 if (params_rate(params) != 48000) {
784 dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
785 params_rate(params), rt286->sys_clk);
786 return -EINVAL;
787 }
788 break;
789 case 11289600:
790 case 22579200:
791 if (params_rate(params) != 44100) {
792 dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
793 params_rate(params), rt286->sys_clk);
794 return -EINVAL;
795 }
796 break;
797 }
798
799 if (params_channels(params) <= 16) {
800 /* bit 3:0 Number of Channel */
801 val |= (params_channels(params) - 1);
802 } else {
803 dev_err(codec->dev, "Unsupported channels %d\n",
804 params_channels(params));
805 return -EINVAL;
806 }
807
808 d_len_code = 0;
809 switch (params_width(params)) {
810 /* bit 6:4 Bits per Sample */
811 case 16:
812 d_len_code = 0;
813 val |= (0x1 << 4);
814 break;
815 case 32:
816 d_len_code = 2;
817 val |= (0x4 << 4);
818 break;
819 case 20:
820 d_len_code = 1;
821 val |= (0x2 << 4);
822 break;
823 case 24:
824 d_len_code = 2;
825 val |= (0x3 << 4);
826 break;
827 case 8:
828 d_len_code = 3;
829 break;
830 default:
831 return -EINVAL;
832 }
833
834 snd_soc_update_bits(codec,
835 RT286_I2S_CTRL1, 0x0018, d_len_code << 3);
836 dev_dbg(codec->dev, "format val = 0x%x\n", val);
837
Bard Liao45437fa2015-01-15 10:49:25 +0800838 snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x407f, val);
839 snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x407f, val);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800840
841 return 0;
842}
843
844static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
845{
846 struct snd_soc_codec *codec = dai->codec;
847
848 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
849 case SND_SOC_DAIFMT_CBM_CFM:
850 snd_soc_update_bits(codec,
851 RT286_I2S_CTRL1, 0x800, 0x800);
852 break;
853 case SND_SOC_DAIFMT_CBS_CFS:
854 snd_soc_update_bits(codec,
855 RT286_I2S_CTRL1, 0x800, 0x0);
856 break;
857 default:
858 return -EINVAL;
859 }
860
861 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
862 case SND_SOC_DAIFMT_I2S:
863 snd_soc_update_bits(codec,
864 RT286_I2S_CTRL1, 0x300, 0x0);
865 break;
866 case SND_SOC_DAIFMT_LEFT_J:
867 snd_soc_update_bits(codec,
868 RT286_I2S_CTRL1, 0x300, 0x1 << 8);
869 break;
870 case SND_SOC_DAIFMT_DSP_A:
871 snd_soc_update_bits(codec,
872 RT286_I2S_CTRL1, 0x300, 0x2 << 8);
873 break;
874 case SND_SOC_DAIFMT_DSP_B:
875 snd_soc_update_bits(codec,
876 RT286_I2S_CTRL1, 0x300, 0x3 << 8);
877 break;
878 default:
879 return -EINVAL;
880 }
881 /* bit 15 Stream Type 0:PCM 1:Non-PCM */
882 snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x8000, 0);
883 snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x8000, 0);
884
885 return 0;
886}
887
888static int rt286_set_dai_sysclk(struct snd_soc_dai *dai,
889 int clk_id, unsigned int freq, int dir)
890{
891 struct snd_soc_codec *codec = dai->codec;
892 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
893
894 dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq);
895
896 if (RT286_SCLK_S_MCLK == clk_id) {
897 snd_soc_update_bits(codec,
898 RT286_I2S_CTRL2, 0x0100, 0x0);
899 snd_soc_update_bits(codec,
900 RT286_PLL_CTRL1, 0x20, 0x20);
901 } else {
902 snd_soc_update_bits(codec,
903 RT286_I2S_CTRL2, 0x0100, 0x0100);
904 snd_soc_update_bits(codec,
905 RT286_PLL_CTRL, 0x4, 0x4);
906 snd_soc_update_bits(codec,
907 RT286_PLL_CTRL1, 0x20, 0x0);
908 }
909
910 switch (freq) {
911 case 19200000:
912 if (RT286_SCLK_S_MCLK == clk_id) {
913 dev_err(codec->dev, "Should not use MCLK\n");
914 return -EINVAL;
915 }
916 snd_soc_update_bits(codec,
917 RT286_I2S_CTRL2, 0x40, 0x40);
918 break;
919 case 24000000:
920 if (RT286_SCLK_S_MCLK == clk_id) {
921 dev_err(codec->dev, "Should not use MCLK\n");
922 return -EINVAL;
923 }
924 snd_soc_update_bits(codec,
925 RT286_I2S_CTRL2, 0x40, 0x0);
926 break;
927 case 12288000:
928 case 11289600:
929 snd_soc_update_bits(codec,
930 RT286_I2S_CTRL2, 0x8, 0x0);
931 snd_soc_update_bits(codec,
932 RT286_CLK_DIV, 0xfc1e, 0x0004);
933 break;
934 case 24576000:
935 case 22579200:
936 snd_soc_update_bits(codec,
937 RT286_I2S_CTRL2, 0x8, 0x8);
938 snd_soc_update_bits(codec,
939 RT286_CLK_DIV, 0xfc1e, 0x5406);
940 break;
941 default:
942 dev_err(codec->dev, "Unsupported system clock\n");
943 return -EINVAL;
944 }
945
946 rt286->sys_clk = freq;
Bard Liao6879db72014-10-31 14:52:16 +0800947 rt286->clk_id = clk_id;
Bard Liao07cf7cba2014-06-20 14:41:13 +0800948
949 return 0;
950}
951
952static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
953{
954 struct snd_soc_codec *codec = dai->codec;
955
956 dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
957 if (50 == ratio)
958 snd_soc_update_bits(codec,
959 RT286_I2S_CTRL1, 0x1000, 0x1000);
960 else
961 snd_soc_update_bits(codec,
962 RT286_I2S_CTRL1, 0x1000, 0x0);
963
964
965 return 0;
966}
967
968static int rt286_set_bias_level(struct snd_soc_codec *codec,
969 enum snd_soc_bias_level level)
970{
971 switch (level) {
972 case SND_SOC_BIAS_PREPARE:
Bard Liaobc6c4e42014-07-07 19:15:30 +0800973 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
Bard Liao07cf7cba2014-06-20 14:41:13 +0800974 snd_soc_write(codec,
975 RT286_SET_AUDIO_POWER, AC_PWRST_D0);
Bard Liaobc6c4e42014-07-07 19:15:30 +0800976 snd_soc_update_bits(codec,
977 RT286_DC_GAIN, 0x200, 0x200);
978 }
979 break;
980
981 case SND_SOC_BIAS_ON:
982 mdelay(10);
Bard Liao6879db72014-10-31 14:52:16 +0800983 snd_soc_update_bits(codec,
984 RT286_CBJ_CTRL1, 0x0400, 0x0400);
985 snd_soc_update_bits(codec,
986 RT286_DC_GAIN, 0x200, 0x0);
987
Bard Liao07cf7cba2014-06-20 14:41:13 +0800988 break;
989
990 case SND_SOC_BIAS_STANDBY:
991 snd_soc_write(codec,
992 RT286_SET_AUDIO_POWER, AC_PWRST_D3);
Bard Liaobc6c4e42014-07-07 19:15:30 +0800993 snd_soc_update_bits(codec,
Bard Liao6879db72014-10-31 14:52:16 +0800994 RT286_CBJ_CTRL1, 0x0400, 0x0000);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800995 break;
996
997 default:
998 break;
999 }
1000 codec->dapm.bias_level = level;
1001
1002 return 0;
1003}
1004
1005static irqreturn_t rt286_irq(int irq, void *data)
1006{
1007 struct rt286_priv *rt286 = data;
1008 bool hp = false;
1009 bool mic = false;
1010 int status = 0;
1011
Bard Liao90f601e2014-07-29 13:50:57 +08001012 rt286_jack_detect(rt286, &hp, &mic);
Bard Liao07cf7cba2014-06-20 14:41:13 +08001013
1014 /* Clear IRQ */
Bard Liao90f601e2014-07-29 13:50:57 +08001015 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1);
Bard Liao07cf7cba2014-06-20 14:41:13 +08001016
1017 if (hp == true)
1018 status |= SND_JACK_HEADPHONE;
1019
1020 if (mic == true)
1021 status |= SND_JACK_MICROPHONE;
1022
1023 snd_soc_jack_report(rt286->jack, status,
1024 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
1025
1026 pm_wakeup_event(&rt286->i2c->dev, 300);
1027
1028 return IRQ_HANDLED;
1029}
1030
1031static int rt286_probe(struct snd_soc_codec *codec)
1032{
1033 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
Bard Liao07cf7cba2014-06-20 14:41:13 +08001034
Bard Liao6879db72014-10-31 14:52:16 +08001035 rt286->codec = codec;
Bard Liao07cf7cba2014-06-20 14:41:13 +08001036 codec->dapm.bias_level = SND_SOC_BIAS_OFF;
Bard Liao90f601e2014-07-29 13:50:57 +08001037
1038 if (rt286->i2c->irq) {
1039 regmap_update_bits(rt286->regmap,
1040 RT286_IRQ_CTRL, 0x2, 0x2);
1041
1042 INIT_DELAYED_WORK(&rt286->jack_detect_work,
1043 rt286_jack_detect_work);
1044 schedule_delayed_work(&rt286->jack_detect_work,
1045 msecs_to_jiffies(1250));
1046 }
Bard Liao07cf7cba2014-06-20 14:41:13 +08001047
Bard Liao07cf7cba2014-06-20 14:41:13 +08001048 return 0;
1049}
1050
1051static int rt286_remove(struct snd_soc_codec *codec)
1052{
1053 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1054
1055 cancel_delayed_work_sync(&rt286->jack_detect_work);
1056
1057 return 0;
1058}
1059
1060#ifdef CONFIG_PM
1061static int rt286_suspend(struct snd_soc_codec *codec)
1062{
1063 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1064
1065 regcache_cache_only(rt286->regmap, true);
1066 regcache_mark_dirty(rt286->regmap);
1067
1068 return 0;
1069}
1070
1071static int rt286_resume(struct snd_soc_codec *codec)
1072{
1073 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1074
1075 regcache_cache_only(rt286->regmap, false);
1076 rt286_index_sync(codec);
1077 regcache_sync(rt286->regmap);
1078
1079 return 0;
1080}
1081#else
1082#define rt286_suspend NULL
1083#define rt286_resume NULL
1084#endif
1085
1086#define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1087#define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1088 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1089
1090static const struct snd_soc_dai_ops rt286_aif_dai_ops = {
1091 .hw_params = rt286_hw_params,
1092 .set_fmt = rt286_set_dai_fmt,
1093 .set_sysclk = rt286_set_dai_sysclk,
1094 .set_bclk_ratio = rt286_set_bclk_ratio,
1095};
1096
1097static struct snd_soc_dai_driver rt286_dai[] = {
1098 {
1099 .name = "rt286-aif1",
1100 .id = RT286_AIF1,
1101 .playback = {
1102 .stream_name = "AIF1 Playback",
1103 .channels_min = 1,
1104 .channels_max = 2,
1105 .rates = RT286_STEREO_RATES,
1106 .formats = RT286_FORMATS,
1107 },
1108 .capture = {
1109 .stream_name = "AIF1 Capture",
1110 .channels_min = 1,
1111 .channels_max = 2,
1112 .rates = RT286_STEREO_RATES,
1113 .formats = RT286_FORMATS,
1114 },
1115 .ops = &rt286_aif_dai_ops,
1116 .symmetric_rates = 1,
1117 },
1118 {
1119 .name = "rt286-aif2",
1120 .id = RT286_AIF2,
1121 .playback = {
1122 .stream_name = "AIF2 Playback",
1123 .channels_min = 1,
1124 .channels_max = 2,
1125 .rates = RT286_STEREO_RATES,
1126 .formats = RT286_FORMATS,
1127 },
1128 .capture = {
1129 .stream_name = "AIF2 Capture",
1130 .channels_min = 1,
1131 .channels_max = 2,
1132 .rates = RT286_STEREO_RATES,
1133 .formats = RT286_FORMATS,
1134 },
1135 .ops = &rt286_aif_dai_ops,
1136 .symmetric_rates = 1,
1137 },
1138
1139};
1140
1141static struct snd_soc_codec_driver soc_codec_dev_rt286 = {
1142 .probe = rt286_probe,
1143 .remove = rt286_remove,
1144 .suspend = rt286_suspend,
1145 .resume = rt286_resume,
1146 .set_bias_level = rt286_set_bias_level,
1147 .idle_bias_off = true,
1148 .controls = rt286_snd_controls,
1149 .num_controls = ARRAY_SIZE(rt286_snd_controls),
1150 .dapm_widgets = rt286_dapm_widgets,
1151 .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets),
1152 .dapm_routes = rt286_dapm_routes,
1153 .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes),
1154};
1155
1156static const struct regmap_config rt286_regmap = {
1157 .reg_bits = 32,
1158 .val_bits = 32,
1159 .max_register = 0x02370100,
1160 .volatile_reg = rt286_volatile_register,
1161 .readable_reg = rt286_readable_register,
1162 .reg_write = rt286_hw_write,
1163 .reg_read = rt286_hw_read,
1164 .cache_type = REGCACHE_RBTREE,
1165 .reg_defaults = rt286_reg,
1166 .num_reg_defaults = ARRAY_SIZE(rt286_reg),
1167};
1168
1169static const struct i2c_device_id rt286_i2c_id[] = {
1170 {"rt286", 0},
1171 {}
1172};
1173MODULE_DEVICE_TABLE(i2c, rt286_i2c_id);
1174
1175static const struct acpi_device_id rt286_acpi_match[] = {
1176 { "INT343A", 0 },
1177 {},
1178};
1179MODULE_DEVICE_TABLE(acpi, rt286_acpi_match);
1180
Sudip Mukherjeea5a267c2014-11-18 17:42:54 +05301181static struct dmi_system_id force_combo_jack_table[] = {
Bard Liao6c67cde2014-11-06 09:59:59 +08001182 {
1183 .ident = "Intel Wilson Beach",
1184 .matches = {
1185 DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS")
1186 }
1187 },
1188 { }
1189};
1190
Bard Liao07cf7cba2014-06-20 14:41:13 +08001191static int rt286_i2c_probe(struct i2c_client *i2c,
1192 const struct i2c_device_id *id)
1193{
1194 struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev);
1195 struct rt286_priv *rt286;
Bard Liao61a414c2014-07-07 16:48:38 +08001196 int i, ret;
Bard Liao07cf7cba2014-06-20 14:41:13 +08001197
1198 rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286),
1199 GFP_KERNEL);
1200 if (NULL == rt286)
1201 return -ENOMEM;
1202
1203 rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap);
1204 if (IS_ERR(rt286->regmap)) {
1205 ret = PTR_ERR(rt286->regmap);
1206 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1207 ret);
1208 return ret;
1209 }
1210
Bard Liao4b21768a2014-07-07 16:48:37 +08001211 regmap_read(rt286->regmap,
1212 RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &ret);
1213 if (ret != RT286_VENDOR_ID) {
1214 dev_err(&i2c->dev,
1215 "Device with ID register %x is not rt286\n", ret);
1216 return -ENODEV;
1217 }
1218
Bard Liao07cf7cba2014-06-20 14:41:13 +08001219 rt286->index_cache = rt286_index_def;
1220 rt286->i2c = i2c;
1221 i2c_set_clientdata(i2c, rt286);
1222
1223 if (pdata)
1224 rt286->pdata = *pdata;
1225
Bard Liao6c67cde2014-11-06 09:59:59 +08001226 if (dmi_check_system(force_combo_jack_table))
1227 rt286->pdata.cbj_en = true;
1228
Bard Liao61a414c2014-07-07 16:48:38 +08001229 regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3);
1230
1231 for (i = 0; i < RT286_POWER_REG_LEN; i++)
1232 regmap_write(rt286->regmap,
1233 RT286_SET_POWER(rt286_support_power_controls[i]),
1234 AC_PWRST_D1);
1235
1236 if (!rt286->pdata.cbj_en) {
1237 regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000);
1238 regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816);
Bard Liao61a414c2014-07-07 16:48:38 +08001239 regmap_update_bits(rt286->regmap,
1240 RT286_CBJ_CTRL1, 0xf000, 0xb000);
1241 } else {
1242 regmap_update_bits(rt286->regmap,
1243 RT286_CBJ_CTRL1, 0xf000, 0x5000);
1244 }
1245
1246 mdelay(10);
1247
1248 if (!rt286->pdata.gpio2_en)
1249 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x4000);
1250 else
1251 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0);
1252
1253 mdelay(10);
1254
Bard Liao6879db72014-10-31 14:52:16 +08001255 regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000);
Bard Liaof8c101b2014-11-06 10:00:00 +08001256 /* Power down LDO, VREF */
Bard Liao6879db72014-10-31 14:52:16 +08001257 regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0xc, 0x0);
1258 regmap_update_bits(rt286->regmap, RT286_POWER_CTRL1, 0x1001, 0x1001);
Bard Liao61a414c2014-07-07 16:48:38 +08001259
Bard Liaof8c101b2014-11-06 10:00:00 +08001260 /* Set depop parameter */
Bard Liaobc6c4e42014-07-07 19:15:30 +08001261 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a);
1262 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737);
1263 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
1264
Bard Liao61a414c2014-07-07 16:48:38 +08001265 if (rt286->i2c->irq) {
Bard Liao61a414c2014-07-07 16:48:38 +08001266 ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq,
1267 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286);
1268 if (ret != 0) {
1269 dev_err(&i2c->dev,
1270 "Failed to reguest IRQ: %d\n", ret);
1271 return ret;
1272 }
1273 }
1274
Bard Liao07cf7cba2014-06-20 14:41:13 +08001275 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt286,
1276 rt286_dai, ARRAY_SIZE(rt286_dai));
1277
1278 return ret;
1279}
1280
1281static int rt286_i2c_remove(struct i2c_client *i2c)
1282{
1283 struct rt286_priv *rt286 = i2c_get_clientdata(i2c);
1284
1285 if (i2c->irq)
1286 free_irq(i2c->irq, rt286);
1287 snd_soc_unregister_codec(&i2c->dev);
1288
1289 return 0;
1290}
1291
1292
Bard Liao23c4fd52014-07-14 10:18:04 +08001293static struct i2c_driver rt286_i2c_driver = {
Bard Liao07cf7cba2014-06-20 14:41:13 +08001294 .driver = {
1295 .name = "rt286",
1296 .owner = THIS_MODULE,
1297 .acpi_match_table = ACPI_PTR(rt286_acpi_match),
1298 },
1299 .probe = rt286_i2c_probe,
1300 .remove = rt286_i2c_remove,
1301 .id_table = rt286_i2c_id,
1302};
1303
1304module_i2c_driver(rt286_i2c_driver);
1305
1306MODULE_DESCRIPTION("ASoC RT286 driver");
1307MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1308MODULE_LICENSE("GPL");