Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014 Samsung Electronics Co., Ltd. |
| 3 | * Author: Chanwoo Choi <cw00.choi@samsung.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * Common Clock Framework support for Exynos5443 SoC. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/clk.h> |
| 13 | #include <linux/clkdev.h> |
| 14 | #include <linux/clk-provider.h> |
| 15 | #include <linux/of.h> |
| 16 | |
| 17 | #include <dt-bindings/clock/exynos5433.h> |
| 18 | |
| 19 | #include "clk.h" |
| 20 | #include "clk-pll.h" |
| 21 | |
| 22 | /* |
| 23 | * Register offset definitions for CMU_TOP |
| 24 | */ |
| 25 | #define ISP_PLL_LOCK 0x0000 |
| 26 | #define AUD_PLL_LOCK 0x0004 |
| 27 | #define ISP_PLL_CON0 0x0100 |
| 28 | #define ISP_PLL_CON1 0x0104 |
| 29 | #define ISP_PLL_FREQ_DET 0x0108 |
| 30 | #define AUD_PLL_CON0 0x0110 |
| 31 | #define AUD_PLL_CON1 0x0114 |
| 32 | #define AUD_PLL_CON2 0x0118 |
| 33 | #define AUD_PLL_FREQ_DET 0x011c |
| 34 | #define MUX_SEL_TOP0 0x0200 |
| 35 | #define MUX_SEL_TOP1 0x0204 |
| 36 | #define MUX_SEL_TOP2 0x0208 |
| 37 | #define MUX_SEL_TOP3 0x020c |
| 38 | #define MUX_SEL_TOP4 0x0210 |
| 39 | #define MUX_SEL_TOP_MSCL 0x0220 |
| 40 | #define MUX_SEL_TOP_CAM1 0x0224 |
| 41 | #define MUX_SEL_TOP_DISP 0x0228 |
| 42 | #define MUX_SEL_TOP_FSYS0 0x0230 |
| 43 | #define MUX_SEL_TOP_FSYS1 0x0234 |
| 44 | #define MUX_SEL_TOP_PERIC0 0x0238 |
| 45 | #define MUX_SEL_TOP_PERIC1 0x023c |
| 46 | #define MUX_ENABLE_TOP0 0x0300 |
| 47 | #define MUX_ENABLE_TOP1 0x0304 |
| 48 | #define MUX_ENABLE_TOP2 0x0308 |
| 49 | #define MUX_ENABLE_TOP3 0x030c |
| 50 | #define MUX_ENABLE_TOP4 0x0310 |
| 51 | #define MUX_ENABLE_TOP_MSCL 0x0320 |
| 52 | #define MUX_ENABLE_TOP_CAM1 0x0324 |
| 53 | #define MUX_ENABLE_TOP_DISP 0x0328 |
| 54 | #define MUX_ENABLE_TOP_FSYS0 0x0330 |
| 55 | #define MUX_ENABLE_TOP_FSYS1 0x0334 |
| 56 | #define MUX_ENABLE_TOP_PERIC0 0x0338 |
| 57 | #define MUX_ENABLE_TOP_PERIC1 0x033c |
| 58 | #define MUX_STAT_TOP0 0x0400 |
| 59 | #define MUX_STAT_TOP1 0x0404 |
| 60 | #define MUX_STAT_TOP2 0x0408 |
| 61 | #define MUX_STAT_TOP3 0x040c |
| 62 | #define MUX_STAT_TOP4 0x0410 |
| 63 | #define MUX_STAT_TOP_MSCL 0x0420 |
| 64 | #define MUX_STAT_TOP_CAM1 0x0424 |
| 65 | #define MUX_STAT_TOP_FSYS0 0x0430 |
| 66 | #define MUX_STAT_TOP_FSYS1 0x0434 |
| 67 | #define MUX_STAT_TOP_PERIC0 0x0438 |
| 68 | #define MUX_STAT_TOP_PERIC1 0x043c |
| 69 | #define DIV_TOP0 0x0600 |
| 70 | #define DIV_TOP1 0x0604 |
| 71 | #define DIV_TOP2 0x0608 |
| 72 | #define DIV_TOP3 0x060c |
| 73 | #define DIV_TOP4 0x0610 |
| 74 | #define DIV_TOP_MSCL 0x0618 |
| 75 | #define DIV_TOP_CAM10 0x061c |
| 76 | #define DIV_TOP_CAM11 0x0620 |
| 77 | #define DIV_TOP_FSYS0 0x062c |
| 78 | #define DIV_TOP_FSYS1 0x0630 |
| 79 | #define DIV_TOP_FSYS2 0x0634 |
| 80 | #define DIV_TOP_PERIC0 0x0638 |
| 81 | #define DIV_TOP_PERIC1 0x063c |
| 82 | #define DIV_TOP_PERIC2 0x0640 |
| 83 | #define DIV_TOP_PERIC3 0x0644 |
| 84 | #define DIV_TOP_PERIC4 0x0648 |
| 85 | #define DIV_TOP_PLL_FREQ_DET 0x064c |
| 86 | #define DIV_STAT_TOP0 0x0700 |
| 87 | #define DIV_STAT_TOP1 0x0704 |
| 88 | #define DIV_STAT_TOP2 0x0708 |
| 89 | #define DIV_STAT_TOP3 0x070c |
| 90 | #define DIV_STAT_TOP4 0x0710 |
| 91 | #define DIV_STAT_TOP_MSCL 0x0718 |
| 92 | #define DIV_STAT_TOP_CAM10 0x071c |
| 93 | #define DIV_STAT_TOP_CAM11 0x0720 |
| 94 | #define DIV_STAT_TOP_FSYS0 0x072c |
| 95 | #define DIV_STAT_TOP_FSYS1 0x0730 |
| 96 | #define DIV_STAT_TOP_FSYS2 0x0734 |
| 97 | #define DIV_STAT_TOP_PERIC0 0x0738 |
| 98 | #define DIV_STAT_TOP_PERIC1 0x073c |
| 99 | #define DIV_STAT_TOP_PERIC2 0x0740 |
| 100 | #define DIV_STAT_TOP_PERIC3 0x0744 |
| 101 | #define DIV_STAT_TOP_PLL_FREQ_DET 0x074c |
| 102 | #define ENABLE_ACLK_TOP 0x0800 |
| 103 | #define ENABLE_SCLK_TOP 0x0a00 |
| 104 | #define ENABLE_SCLK_TOP_MSCL 0x0a04 |
| 105 | #define ENABLE_SCLK_TOP_CAM1 0x0a08 |
| 106 | #define ENABLE_SCLK_TOP_DISP 0x0a0c |
| 107 | #define ENABLE_SCLK_TOP_FSYS 0x0a10 |
| 108 | #define ENABLE_SCLK_TOP_PERIC 0x0a14 |
| 109 | #define ENABLE_IP_TOP 0x0b00 |
| 110 | #define ENABLE_CMU_TOP 0x0c00 |
| 111 | #define ENABLE_CMU_TOP_DIV_STAT 0x0c04 |
| 112 | |
| 113 | static unsigned long top_clk_regs[] __initdata = { |
| 114 | ISP_PLL_LOCK, |
| 115 | AUD_PLL_LOCK, |
| 116 | ISP_PLL_CON0, |
| 117 | ISP_PLL_CON1, |
| 118 | ISP_PLL_FREQ_DET, |
| 119 | AUD_PLL_CON0, |
| 120 | AUD_PLL_CON1, |
| 121 | AUD_PLL_CON2, |
| 122 | AUD_PLL_FREQ_DET, |
| 123 | MUX_SEL_TOP0, |
| 124 | MUX_SEL_TOP1, |
| 125 | MUX_SEL_TOP2, |
| 126 | MUX_SEL_TOP3, |
| 127 | MUX_SEL_TOP4, |
| 128 | MUX_SEL_TOP_MSCL, |
| 129 | MUX_SEL_TOP_CAM1, |
| 130 | MUX_SEL_TOP_DISP, |
| 131 | MUX_SEL_TOP_FSYS0, |
| 132 | MUX_SEL_TOP_FSYS1, |
| 133 | MUX_SEL_TOP_PERIC0, |
| 134 | MUX_SEL_TOP_PERIC1, |
| 135 | MUX_ENABLE_TOP0, |
| 136 | MUX_ENABLE_TOP1, |
| 137 | MUX_ENABLE_TOP2, |
| 138 | MUX_ENABLE_TOP3, |
| 139 | MUX_ENABLE_TOP4, |
| 140 | MUX_ENABLE_TOP_MSCL, |
| 141 | MUX_ENABLE_TOP_CAM1, |
| 142 | MUX_ENABLE_TOP_DISP, |
| 143 | MUX_ENABLE_TOP_FSYS0, |
| 144 | MUX_ENABLE_TOP_FSYS1, |
| 145 | MUX_ENABLE_TOP_PERIC0, |
| 146 | MUX_ENABLE_TOP_PERIC1, |
| 147 | MUX_STAT_TOP0, |
| 148 | MUX_STAT_TOP1, |
| 149 | MUX_STAT_TOP2, |
| 150 | MUX_STAT_TOP3, |
| 151 | MUX_STAT_TOP4, |
| 152 | MUX_STAT_TOP_MSCL, |
| 153 | MUX_STAT_TOP_CAM1, |
| 154 | MUX_STAT_TOP_FSYS0, |
| 155 | MUX_STAT_TOP_FSYS1, |
| 156 | MUX_STAT_TOP_PERIC0, |
| 157 | MUX_STAT_TOP_PERIC1, |
| 158 | DIV_TOP0, |
| 159 | DIV_TOP1, |
| 160 | DIV_TOP2, |
| 161 | DIV_TOP3, |
| 162 | DIV_TOP4, |
| 163 | DIV_TOP_MSCL, |
| 164 | DIV_TOP_CAM10, |
| 165 | DIV_TOP_CAM11, |
| 166 | DIV_TOP_FSYS0, |
| 167 | DIV_TOP_FSYS1, |
| 168 | DIV_TOP_FSYS2, |
| 169 | DIV_TOP_PERIC0, |
| 170 | DIV_TOP_PERIC1, |
| 171 | DIV_TOP_PERIC2, |
| 172 | DIV_TOP_PERIC3, |
| 173 | DIV_TOP_PERIC4, |
| 174 | DIV_TOP_PLL_FREQ_DET, |
| 175 | DIV_STAT_TOP0, |
| 176 | DIV_STAT_TOP1, |
| 177 | DIV_STAT_TOP2, |
| 178 | DIV_STAT_TOP3, |
| 179 | DIV_STAT_TOP4, |
| 180 | DIV_STAT_TOP_MSCL, |
| 181 | DIV_STAT_TOP_CAM10, |
| 182 | DIV_STAT_TOP_CAM11, |
| 183 | DIV_STAT_TOP_FSYS0, |
| 184 | DIV_STAT_TOP_FSYS1, |
| 185 | DIV_STAT_TOP_FSYS2, |
| 186 | DIV_STAT_TOP_PERIC0, |
| 187 | DIV_STAT_TOP_PERIC1, |
| 188 | DIV_STAT_TOP_PERIC2, |
| 189 | DIV_STAT_TOP_PERIC3, |
| 190 | DIV_STAT_TOP_PLL_FREQ_DET, |
| 191 | ENABLE_ACLK_TOP, |
| 192 | ENABLE_SCLK_TOP, |
| 193 | ENABLE_SCLK_TOP_MSCL, |
| 194 | ENABLE_SCLK_TOP_CAM1, |
| 195 | ENABLE_SCLK_TOP_DISP, |
| 196 | ENABLE_SCLK_TOP_FSYS, |
| 197 | ENABLE_SCLK_TOP_PERIC, |
| 198 | ENABLE_IP_TOP, |
| 199 | ENABLE_CMU_TOP, |
| 200 | ENABLE_CMU_TOP_DIV_STAT, |
| 201 | }; |
| 202 | |
| 203 | /* list of all parent clock list */ |
| 204 | PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", }; |
| 205 | PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", }; |
| 206 | PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", }; |
| 207 | PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", }; |
| 208 | PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", }; |
| 209 | PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", }; |
| 210 | PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", }; |
Chanwoo Choi | 2323649 | 2015-02-02 23:23:57 +0900 | [diff] [blame] | 211 | PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", }; |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 212 | |
| 213 | PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",}; |
| 214 | PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",}; |
| 215 | PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a", |
| 216 | "mout_mfc_pll_user", }; |
| 217 | PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", }; |
| 218 | |
Chanwoo Choi | 2323649 | 2015-02-02 23:23:57 +0900 | [diff] [blame] | 219 | PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b", |
| 220 | "mout_mphy_pll_user", }; |
| 221 | PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a", |
| 222 | "mout_bus_pll_user", }; |
| 223 | PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", }; |
| 224 | |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 225 | PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user", |
| 226 | "mout_mphy_pll_user", }; |
| 227 | PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a", |
| 228 | "mout_mphy_pll_user", }; |
| 229 | PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a", |
| 230 | "mout_mphy_pll_user", }; |
| 231 | |
| 232 | PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",}; |
| 233 | PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", }; |
| 234 | |
| 235 | PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",}; |
| 236 | PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",}; |
| 237 | PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", }; |
| 238 | PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",}; |
| 239 | PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", }; |
| 240 | |
Chanwoo Choi | 2323649 | 2015-02-02 23:23:57 +0900 | [diff] [blame] | 241 | PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1", |
| 242 | "oscclk", "ioclk_spdif_extclk", }; |
| 243 | PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk", |
| 244 | "mout_aud_pll_user_t",}; |
| 245 | PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk", |
| 246 | "mout_aud_pll_user_t",}; |
| 247 | |
Chanwoo Choi | 2a1808a | 2015-02-02 23:24:02 +0900 | [diff] [blame] | 248 | PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", }; |
| 249 | |
Chanwoo Choi | 56bcf3f | 2015-02-02 23:23:59 +0900 | [diff] [blame] | 250 | static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = { |
| 251 | FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0), |
| 252 | }; |
| 253 | |
Chanwoo Choi | 2323649 | 2015-02-02 23:23:57 +0900 | [diff] [blame] | 254 | static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = { |
| 255 | /* Xi2s{0|1}CDCLK input clock for I2S/PCM */ |
| 256 | FRATE(0, "ioclk_audiocdclk1", NULL, CLK_IS_ROOT, 100000000), |
| 257 | FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000), |
| 258 | /* Xi2s1SDI input clock for SPDIF */ |
| 259 | FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 100000000), |
Chanwoo Choi | d0f5de6 | 2015-02-02 23:23:58 +0900 | [diff] [blame] | 260 | /* XspiCLK[4:0] input clock for SPI */ |
| 261 | FRATE(0, "ioclk_spi4_clk_in", NULL, CLK_IS_ROOT, 50000000), |
| 262 | FRATE(0, "ioclk_spi3_clk_in", NULL, CLK_IS_ROOT, 50000000), |
| 263 | FRATE(0, "ioclk_spi2_clk_in", NULL, CLK_IS_ROOT, 50000000), |
| 264 | FRATE(0, "ioclk_spi1_clk_in", NULL, CLK_IS_ROOT, 50000000), |
| 265 | FRATE(0, "ioclk_spi0_clk_in", NULL, CLK_IS_ROOT, 50000000), |
| 266 | /* Xi2s1SCLK input clock for I2S1_BCLK */ |
| 267 | FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000), |
Chanwoo Choi | 2323649 | 2015-02-02 23:23:57 +0900 | [diff] [blame] | 268 | }; |
| 269 | |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 270 | static struct samsung_mux_clock top_mux_clks[] __initdata = { |
| 271 | /* MUX_SEL_TOP0 */ |
| 272 | MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0, |
| 273 | 4, 1), |
| 274 | MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0, |
| 275 | 0, 1), |
| 276 | |
| 277 | /* MUX_SEL_TOP1 */ |
| 278 | MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t", |
| 279 | mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1), |
| 280 | MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p, |
| 281 | MUX_SEL_TOP1, 8, 1), |
| 282 | MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p, |
| 283 | MUX_SEL_TOP1, 4, 1), |
| 284 | MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p, |
| 285 | MUX_SEL_TOP1, 0, 1), |
| 286 | |
| 287 | /* MUX_SEL_TOP2 */ |
| 288 | MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400", |
| 289 | mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1), |
| 290 | MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333", |
| 291 | mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1), |
| 292 | MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b", |
| 293 | mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1), |
| 294 | MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a", |
| 295 | mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1), |
| 296 | MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400", |
| 297 | mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1), |
| 298 | MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400", |
| 299 | mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1), |
| 300 | |
| 301 | /* MUX_SEL_TOP3 */ |
| 302 | MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400", |
| 303 | mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1), |
| 304 | MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b", |
| 305 | mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1), |
| 306 | MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a", |
| 307 | mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1), |
| 308 | MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333", |
| 309 | mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1), |
| 310 | MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b", |
| 311 | mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1), |
| 312 | MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a", |
| 313 | mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1), |
| 314 | |
Chanwoo Choi | 2323649 | 2015-02-02 23:23:57 +0900 | [diff] [blame] | 315 | /* MUX_SEL_TOP4 */ |
| 316 | MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c", |
| 317 | mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1), |
| 318 | MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b", |
| 319 | mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1), |
| 320 | MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a", |
| 321 | mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1), |
| 322 | |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 323 | /* MUX_SEL_TOP_MSCL */ |
| 324 | MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p, |
| 325 | MUX_SEL_TOP_MSCL, 8, 1), |
| 326 | MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p, |
| 327 | MUX_SEL_TOP_MSCL, 4, 1), |
| 328 | MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p, |
| 329 | MUX_SEL_TOP_MSCL, 0, 1), |
| 330 | |
Chanwoo Choi | 2323649 | 2015-02-02 23:23:57 +0900 | [diff] [blame] | 331 | /* MUX_SEL_TOP_CAM1 */ |
| 332 | MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2", |
| 333 | mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1), |
| 334 | MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1", |
| 335 | mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1), |
| 336 | MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0", |
| 337 | mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1), |
| 338 | MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart", |
| 339 | mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1), |
| 340 | MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1", |
| 341 | mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1), |
| 342 | MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0", |
| 343 | mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1), |
| 344 | |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 345 | /* MUX_SEL_TOP_FSYS0 */ |
| 346 | MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p, |
| 347 | MUX_SEL_TOP_FSYS0, 28, 1), |
| 348 | MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p, |
| 349 | MUX_SEL_TOP_FSYS0, 24, 1), |
| 350 | MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p, |
| 351 | MUX_SEL_TOP_FSYS0, 20, 1), |
| 352 | MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p, |
| 353 | MUX_SEL_TOP_FSYS0, 16, 1), |
| 354 | MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p, |
| 355 | MUX_SEL_TOP_FSYS0, 12, 1), |
| 356 | MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p, |
| 357 | MUX_SEL_TOP_FSYS0, 8, 1), |
| 358 | MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p, |
| 359 | MUX_SEL_TOP_FSYS0, 4, 1), |
| 360 | MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p, |
| 361 | MUX_SEL_TOP_FSYS0, 0, 1), |
| 362 | |
Chanwoo Choi | 2323649 | 2015-02-02 23:23:57 +0900 | [diff] [blame] | 363 | /* MUX_SEL_TOP_FSYS1 */ |
| 364 | MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p, |
| 365 | MUX_SEL_TOP_FSYS1, 12, 1), |
| 366 | MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro", |
| 367 | mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1), |
| 368 | MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30", |
| 369 | mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1), |
| 370 | MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30", |
| 371 | mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1), |
| 372 | |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 373 | /* MUX_SEL_TOP_PERIC0 */ |
| 374 | MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p, |
| 375 | MUX_SEL_TOP_PERIC0, 28, 1), |
| 376 | MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p, |
| 377 | MUX_SEL_TOP_PERIC0, 24, 1), |
| 378 | MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p, |
| 379 | MUX_SEL_TOP_PERIC0, 20, 1), |
| 380 | MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p, |
| 381 | MUX_SEL_TOP_PERIC0, 16, 1), |
| 382 | MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p, |
| 383 | MUX_SEL_TOP_PERIC0, 12, 1), |
| 384 | MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p, |
| 385 | MUX_SEL_TOP_PERIC0, 8, 1), |
| 386 | MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p, |
| 387 | MUX_SEL_TOP_PERIC0, 4, 1), |
| 388 | MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p, |
| 389 | MUX_SEL_TOP_PERIC0, 0, 1), |
Chanwoo Choi | 2323649 | 2015-02-02 23:23:57 +0900 | [diff] [blame] | 390 | |
| 391 | /* MUX_SEL_TOP_PERIC1 */ |
| 392 | MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p, |
| 393 | MUX_SEL_TOP_PERIC1, 16, 1), |
| 394 | MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p, |
| 395 | MUX_SEL_TOP_PERIC1, 12, 2), |
| 396 | MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p, |
| 397 | MUX_SEL_TOP_PERIC1, 4, 2), |
| 398 | MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p, |
| 399 | MUX_SEL_TOP_PERIC1, 0, 2), |
Chanwoo Choi | 2a1808a | 2015-02-02 23:24:02 +0900 | [diff] [blame] | 400 | |
| 401 | /* MUX_SEL_TOP_DISP */ |
| 402 | MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif", |
| 403 | mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1), |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 404 | }; |
| 405 | |
| 406 | static struct samsung_div_clock top_div_clks[] __initdata = { |
Chanwoo Choi | a29308d | 2015-02-02 23:24:00 +0900 | [diff] [blame] | 407 | /* DIV_TOP1 */ |
| 408 | DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333", |
| 409 | DIV_TOP1, 28, 3), |
| 410 | DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333", |
| 411 | DIV_TOP1, 24, 3), |
| 412 | DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400", |
| 413 | DIV_TOP1, 20, 3), |
| 414 | DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c", |
| 415 | DIV_TOP1, 12, 3), |
| 416 | DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user", |
| 417 | DIV_TOP1, 8, 3), |
| 418 | DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b", |
| 419 | DIV_TOP1, 0, 3), |
| 420 | |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 421 | /* DIV_TOP2 */ |
| 422 | DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user", |
| 423 | DIV_TOP2, 0, 3), |
| 424 | |
| 425 | /* DIV_TOP3 */ |
| 426 | DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266", |
| 427 | "mout_bus_pll_user", DIV_TOP3, 24, 3), |
| 428 | DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200", |
| 429 | "mout_bus_pll_user", DIV_TOP3, 20, 3), |
| 430 | DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266", |
| 431 | "mout_bus_pll_user", DIV_TOP3, 16, 3), |
| 432 | DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b", |
| 433 | "div_aclk_peric_66_a", DIV_TOP3, 12, 3), |
| 434 | DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a", |
| 435 | "mout_bus_pll_user", DIV_TOP3, 8, 3), |
| 436 | DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b", |
| 437 | "div_aclk_peris_66_a", DIV_TOP3, 4, 3), |
| 438 | DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a", |
| 439 | "mout_bus_pll_user", DIV_TOP3, 0, 3), |
| 440 | |
Chanwoo Choi | 5785d6e | 2015-02-02 23:24:04 +0900 | [diff] [blame^] | 441 | /* DIV_TOP4 */ |
| 442 | DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user", |
| 443 | DIV_TOP4, 8, 3), |
| 444 | DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400", |
| 445 | DIV_TOP4, 4, 3), |
| 446 | DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user", |
| 447 | DIV_TOP4, 0, 3), |
| 448 | |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 449 | /* DIV_TOP_FSYS0 */ |
| 450 | DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a", |
| 451 | DIV_TOP_FSYS0, 16, 8), |
| 452 | DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b", |
| 453 | DIV_TOP_FSYS0, 12, 4), |
| 454 | DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a", |
| 455 | DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0), |
| 456 | DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d", |
| 457 | DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0), |
| 458 | |
| 459 | /* DIV_TOP_FSYS1 */ |
| 460 | DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a", |
| 461 | DIV_TOP_FSYS1, 4, 8), |
| 462 | DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b", |
| 463 | DIV_TOP_FSYS1, 0, 4), |
| 464 | |
| 465 | /* DIV_TOP_PERIC0 */ |
| 466 | DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a", |
| 467 | DIV_TOP_PERIC0, 16, 8), |
| 468 | DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1", |
| 469 | DIV_TOP_PERIC0, 12, 4), |
| 470 | DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a", |
| 471 | DIV_TOP_PERIC0, 4, 8), |
| 472 | DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0", |
| 473 | DIV_TOP_PERIC0, 0, 4), |
| 474 | |
| 475 | /* DIV_TOP_PERIC1 */ |
| 476 | DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a", |
| 477 | DIV_TOP_PERIC1, 4, 8), |
| 478 | DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2", |
| 479 | DIV_TOP_PERIC1, 0, 4), |
| 480 | |
| 481 | /* DIV_TOP_PERIC2 */ |
| 482 | DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2", |
| 483 | DIV_TOP_PERIC2, 8, 4), |
| 484 | DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0", |
| 485 | DIV_TOP_PERIC2, 4, 4), |
| 486 | DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1", |
| 487 | DIV_TOP_PERIC2, 0, 4), |
| 488 | |
Chanwoo Choi | 2323649 | 2015-02-02 23:23:57 +0900 | [diff] [blame] | 489 | /* DIV_TOP_PERIC3 */ |
| 490 | DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1", |
| 491 | DIV_TOP_PERIC3, 16, 6), |
| 492 | DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1", |
| 493 | DIV_TOP_PERIC3, 8, 8), |
| 494 | DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1", |
| 495 | DIV_TOP_PERIC3, 4, 4), |
| 496 | DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0", |
| 497 | DIV_TOP_PERIC3, 0, 4), |
| 498 | |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 499 | /* DIV_TOP_PERIC4 */ |
| 500 | DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a", |
| 501 | DIV_TOP_PERIC4, 16, 8), |
| 502 | DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4", |
| 503 | DIV_TOP_PERIC4, 12, 4), |
| 504 | DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a", |
| 505 | DIV_TOP_PERIC4, 4, 8), |
| 506 | DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3", |
| 507 | DIV_TOP_PERIC4, 0, 4), |
| 508 | }; |
| 509 | |
| 510 | static struct samsung_gate_clock top_gate_clks[] __initdata = { |
| 511 | /* ENABLE_ACLK_TOP */ |
Chanwoo Choi | 5785d6e | 2015-02-02 23:24:04 +0900 | [diff] [blame^] | 512 | GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400", |
| 513 | ENABLE_ACLK_TOP, 30, 0, 0), |
| 514 | GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266", |
| 515 | "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP, |
| 516 | 29, CLK_IGNORE_UNUSED, 0), |
| 517 | GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400", |
| 518 | ENABLE_ACLK_TOP, 26, |
| 519 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), |
| 520 | GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400", |
| 521 | ENABLE_ACLK_TOP, 25, |
| 522 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), |
| 523 | GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266", |
| 524 | ENABLE_ACLK_TOP, 24, |
| 525 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), |
| 526 | GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200", |
| 527 | ENABLE_ACLK_TOP, 23, |
| 528 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 529 | GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b", |
| 530 | ENABLE_ACLK_TOP, 22, |
| 531 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), |
| 532 | GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b", |
| 533 | ENABLE_ACLK_TOP, 21, |
| 534 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), |
| 535 | GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200", |
| 536 | ENABLE_ACLK_TOP, 18, |
| 537 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), |
Chanwoo Choi | a29308d | 2015-02-02 23:24:00 +0900 | [diff] [blame] | 538 | GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266", |
| 539 | ENABLE_ACLK_TOP, 2, |
| 540 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), |
| 541 | GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400", |
| 542 | ENABLE_ACLK_TOP, 0, |
| 543 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 544 | |
| 545 | /* ENABLE_SCLK_TOP_FSYS */ |
| 546 | GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b", |
| 547 | ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0), |
| 548 | GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b", |
| 549 | ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0), |
| 550 | GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b", |
| 551 | ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0), |
| 552 | |
| 553 | /* ENABLE_SCLK_TOP_PERIC */ |
| 554 | GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b", |
| 555 | ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0), |
| 556 | GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b", |
| 557 | ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0), |
Chanwoo Choi | 2323649 | 2015-02-02 23:23:57 +0900 | [diff] [blame] | 558 | GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif", |
| 559 | ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0), |
| 560 | GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1", |
| 561 | ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0), |
| 562 | GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1", |
| 563 | ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0), |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 564 | GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2", |
| 565 | ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT, 0), |
| 566 | GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1", |
| 567 | ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT, 0), |
| 568 | GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0", |
| 569 | ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT, 0), |
| 570 | GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b", |
| 571 | ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0), |
| 572 | GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b", |
| 573 | ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0), |
| 574 | GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b", |
| 575 | ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0), |
Chanwoo Choi | 2323649 | 2015-02-02 23:23:57 +0900 | [diff] [blame] | 576 | |
| 577 | /* MUX_ENABLE_TOP_PERIC1 */ |
| 578 | GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus", |
| 579 | MUX_ENABLE_TOP_PERIC1, 16, 0, 0), |
| 580 | GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1", |
| 581 | MUX_ENABLE_TOP_PERIC1, 4, 0, 0), |
| 582 | GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0", |
| 583 | MUX_ENABLE_TOP_PERIC1, 0, 0, 0), |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 584 | }; |
| 585 | |
| 586 | /* |
| 587 | * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL |
| 588 | * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL |
| 589 | */ |
| 590 | static struct samsung_pll_rate_table exynos5443_pll_rates[] = { |
| 591 | PLL_35XX_RATE(2500000000U, 625, 6, 0), |
| 592 | PLL_35XX_RATE(2400000000U, 500, 5, 0), |
| 593 | PLL_35XX_RATE(2300000000U, 575, 6, 0), |
| 594 | PLL_35XX_RATE(2200000000U, 550, 6, 0), |
| 595 | PLL_35XX_RATE(2100000000U, 350, 4, 0), |
| 596 | PLL_35XX_RATE(2000000000U, 500, 6, 0), |
| 597 | PLL_35XX_RATE(1900000000U, 475, 6, 0), |
| 598 | PLL_35XX_RATE(1800000000U, 375, 5, 0), |
| 599 | PLL_35XX_RATE(1700000000U, 425, 6, 0), |
| 600 | PLL_35XX_RATE(1600000000U, 400, 6, 0), |
| 601 | PLL_35XX_RATE(1500000000U, 250, 4, 0), |
| 602 | PLL_35XX_RATE(1400000000U, 350, 6, 0), |
| 603 | PLL_35XX_RATE(1332000000U, 222, 4, 0), |
| 604 | PLL_35XX_RATE(1300000000U, 325, 6, 0), |
| 605 | PLL_35XX_RATE(1200000000U, 500, 5, 1), |
| 606 | PLL_35XX_RATE(1100000000U, 550, 6, 1), |
| 607 | PLL_35XX_RATE(1086000000U, 362, 4, 1), |
| 608 | PLL_35XX_RATE(1066000000U, 533, 6, 1), |
| 609 | PLL_35XX_RATE(1000000000U, 500, 6, 1), |
| 610 | PLL_35XX_RATE(933000000U, 311, 4, 1), |
| 611 | PLL_35XX_RATE(921000000U, 307, 4, 1), |
| 612 | PLL_35XX_RATE(900000000U, 375, 5, 1), |
| 613 | PLL_35XX_RATE(825000000U, 275, 4, 1), |
| 614 | PLL_35XX_RATE(800000000U, 400, 6, 1), |
| 615 | PLL_35XX_RATE(733000000U, 733, 12, 1), |
| 616 | PLL_35XX_RATE(700000000U, 360, 6, 1), |
| 617 | PLL_35XX_RATE(667000000U, 222, 4, 1), |
| 618 | PLL_35XX_RATE(633000000U, 211, 4, 1), |
| 619 | PLL_35XX_RATE(600000000U, 500, 5, 2), |
| 620 | PLL_35XX_RATE(552000000U, 460, 5, 2), |
| 621 | PLL_35XX_RATE(550000000U, 550, 6, 2), |
| 622 | PLL_35XX_RATE(543000000U, 362, 4, 2), |
| 623 | PLL_35XX_RATE(533000000U, 533, 6, 2), |
| 624 | PLL_35XX_RATE(500000000U, 500, 6, 2), |
| 625 | PLL_35XX_RATE(444000000U, 370, 5, 2), |
| 626 | PLL_35XX_RATE(420000000U, 350, 5, 2), |
| 627 | PLL_35XX_RATE(400000000U, 400, 6, 2), |
| 628 | PLL_35XX_RATE(350000000U, 360, 6, 2), |
| 629 | PLL_35XX_RATE(333000000U, 222, 4, 2), |
| 630 | PLL_35XX_RATE(300000000U, 500, 5, 3), |
| 631 | PLL_35XX_RATE(266000000U, 532, 6, 3), |
| 632 | PLL_35XX_RATE(200000000U, 400, 6, 3), |
| 633 | PLL_35XX_RATE(166000000U, 332, 6, 3), |
| 634 | PLL_35XX_RATE(160000000U, 320, 6, 3), |
| 635 | PLL_35XX_RATE(133000000U, 552, 6, 4), |
| 636 | PLL_35XX_RATE(100000000U, 400, 6, 4), |
| 637 | { /* sentinel */ } |
| 638 | }; |
| 639 | |
| 640 | /* AUD_PLL */ |
| 641 | static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = { |
| 642 | PLL_36XX_RATE(400000000U, 200, 3, 2, 0), |
| 643 | PLL_36XX_RATE(393216000U, 197, 3, 2, -25690), |
| 644 | PLL_36XX_RATE(384000000U, 128, 2, 2, 0), |
| 645 | PLL_36XX_RATE(368640000U, 246, 4, 2, -15729), |
| 646 | PLL_36XX_RATE(361507200U, 181, 3, 2, -16148), |
| 647 | PLL_36XX_RATE(338688000U, 113, 2, 2, -6816), |
| 648 | PLL_36XX_RATE(294912000U, 98, 1, 3, 19923), |
| 649 | PLL_36XX_RATE(288000000U, 96, 1, 3, 0), |
| 650 | PLL_36XX_RATE(252000000U, 84, 1, 3, 0), |
| 651 | { /* sentinel */ } |
| 652 | }; |
| 653 | |
| 654 | static struct samsung_pll_clock top_pll_clks[] __initdata = { |
| 655 | PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk", |
| 656 | ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates), |
| 657 | PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", |
| 658 | AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates), |
| 659 | }; |
| 660 | |
| 661 | static struct samsung_cmu_info top_cmu_info __initdata = { |
| 662 | .pll_clks = top_pll_clks, |
| 663 | .nr_pll_clks = ARRAY_SIZE(top_pll_clks), |
| 664 | .mux_clks = top_mux_clks, |
| 665 | .nr_mux_clks = ARRAY_SIZE(top_mux_clks), |
| 666 | .div_clks = top_div_clks, |
| 667 | .nr_div_clks = ARRAY_SIZE(top_div_clks), |
| 668 | .gate_clks = top_gate_clks, |
| 669 | .nr_gate_clks = ARRAY_SIZE(top_gate_clks), |
Chanwoo Choi | 2323649 | 2015-02-02 23:23:57 +0900 | [diff] [blame] | 670 | .fixed_clks = top_fixed_clks, |
| 671 | .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks), |
Chanwoo Choi | 56bcf3f | 2015-02-02 23:23:59 +0900 | [diff] [blame] | 672 | .fixed_factor_clks = top_fixed_factor_clks, |
| 673 | .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks), |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 674 | .nr_clk_ids = TOP_NR_CLK, |
| 675 | .clk_regs = top_clk_regs, |
| 676 | .nr_clk_regs = ARRAY_SIZE(top_clk_regs), |
| 677 | }; |
| 678 | |
| 679 | static void __init exynos5433_cmu_top_init(struct device_node *np) |
| 680 | { |
| 681 | samsung_cmu_register_one(np, &top_cmu_info); |
| 682 | } |
| 683 | CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top", |
| 684 | exynos5433_cmu_top_init); |
| 685 | |
| 686 | /* |
| 687 | * Register offset definitions for CMU_CPIF |
| 688 | */ |
| 689 | #define MPHY_PLL_LOCK 0x0000 |
| 690 | #define MPHY_PLL_CON0 0x0100 |
| 691 | #define MPHY_PLL_CON1 0x0104 |
| 692 | #define MPHY_PLL_FREQ_DET 0x010c |
| 693 | #define MUX_SEL_CPIF0 0x0200 |
| 694 | #define DIV_CPIF 0x0600 |
| 695 | #define ENABLE_SCLK_CPIF 0x0a00 |
| 696 | |
| 697 | static unsigned long cpif_clk_regs[] __initdata = { |
| 698 | MPHY_PLL_LOCK, |
| 699 | MPHY_PLL_CON0, |
| 700 | MPHY_PLL_CON1, |
| 701 | MPHY_PLL_FREQ_DET, |
| 702 | MUX_SEL_CPIF0, |
| 703 | ENABLE_SCLK_CPIF, |
| 704 | }; |
| 705 | |
| 706 | /* list of all parent clock list */ |
| 707 | PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", }; |
| 708 | |
| 709 | static struct samsung_pll_clock cpif_pll_clks[] __initdata = { |
| 710 | PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk", |
| 711 | MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates), |
| 712 | }; |
| 713 | |
| 714 | static struct samsung_mux_clock cpif_mux_clks[] __initdata = { |
| 715 | /* MUX_SEL_CPIF0 */ |
| 716 | MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0, |
| 717 | 0, 1), |
| 718 | }; |
| 719 | |
| 720 | static struct samsung_div_clock cpif_div_clks[] __initdata = { |
| 721 | /* DIV_CPIF */ |
| 722 | DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF, |
| 723 | 0, 6), |
| 724 | }; |
| 725 | |
| 726 | static struct samsung_gate_clock cpif_gate_clks[] __initdata = { |
| 727 | /* ENABLE_SCLK_CPIF */ |
| 728 | GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll", |
| 729 | ENABLE_SCLK_CPIF, 9, 0, 0), |
| 730 | GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy", |
| 731 | ENABLE_SCLK_CPIF, 4, 0, 0), |
| 732 | }; |
| 733 | |
| 734 | static struct samsung_cmu_info cpif_cmu_info __initdata = { |
| 735 | .pll_clks = cpif_pll_clks, |
| 736 | .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks), |
| 737 | .mux_clks = cpif_mux_clks, |
| 738 | .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks), |
| 739 | .div_clks = cpif_div_clks, |
| 740 | .nr_div_clks = ARRAY_SIZE(cpif_div_clks), |
| 741 | .gate_clks = cpif_gate_clks, |
| 742 | .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks), |
| 743 | .nr_clk_ids = CPIF_NR_CLK, |
| 744 | .clk_regs = cpif_clk_regs, |
| 745 | .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs), |
| 746 | }; |
| 747 | |
| 748 | static void __init exynos5433_cmu_cpif_init(struct device_node *np) |
| 749 | { |
| 750 | samsung_cmu_register_one(np, &cpif_cmu_info); |
| 751 | } |
| 752 | CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif", |
| 753 | exynos5433_cmu_cpif_init); |
| 754 | |
| 755 | /* |
| 756 | * Register offset definitions for CMU_MIF |
| 757 | */ |
| 758 | #define MEM0_PLL_LOCK 0x0000 |
| 759 | #define MEM1_PLL_LOCK 0x0004 |
| 760 | #define BUS_PLL_LOCK 0x0008 |
| 761 | #define MFC_PLL_LOCK 0x000c |
| 762 | #define MEM0_PLL_CON0 0x0100 |
| 763 | #define MEM0_PLL_CON1 0x0104 |
| 764 | #define MEM0_PLL_FREQ_DET 0x010c |
| 765 | #define MEM1_PLL_CON0 0x0110 |
| 766 | #define MEM1_PLL_CON1 0x0114 |
| 767 | #define MEM1_PLL_FREQ_DET 0x011c |
| 768 | #define BUS_PLL_CON0 0x0120 |
| 769 | #define BUS_PLL_CON1 0x0124 |
| 770 | #define BUS_PLL_FREQ_DET 0x012c |
| 771 | #define MFC_PLL_CON0 0x0130 |
| 772 | #define MFC_PLL_CON1 0x0134 |
| 773 | #define MFC_PLL_FREQ_DET 0x013c |
Chanwoo Choi | 06d2f9d | 2015-02-02 23:24:01 +0900 | [diff] [blame] | 774 | #define MUX_SEL_MIF0 0x0200 |
| 775 | #define MUX_SEL_MIF1 0x0204 |
| 776 | #define MUX_SEL_MIF2 0x0208 |
| 777 | #define MUX_SEL_MIF3 0x020c |
| 778 | #define MUX_SEL_MIF4 0x0210 |
| 779 | #define MUX_SEL_MIF5 0x0214 |
| 780 | #define MUX_SEL_MIF6 0x0218 |
| 781 | #define MUX_SEL_MIF7 0x021c |
| 782 | #define MUX_ENABLE_MIF0 0x0300 |
| 783 | #define MUX_ENABLE_MIF1 0x0304 |
| 784 | #define MUX_ENABLE_MIF2 0x0308 |
| 785 | #define MUX_ENABLE_MIF3 0x030c |
| 786 | #define MUX_ENABLE_MIF4 0x0310 |
| 787 | #define MUX_ENABLE_MIF5 0x0314 |
| 788 | #define MUX_ENABLE_MIF6 0x0318 |
| 789 | #define MUX_ENABLE_MIF7 0x031c |
| 790 | #define MUX_STAT_MIF0 0x0400 |
| 791 | #define MUX_STAT_MIF1 0x0404 |
| 792 | #define MUX_STAT_MIF2 0x0408 |
| 793 | #define MUX_STAT_MIF3 0x040c |
| 794 | #define MUX_STAT_MIF4 0x0410 |
| 795 | #define MUX_STAT_MIF5 0x0414 |
| 796 | #define MUX_STAT_MIF6 0x0418 |
| 797 | #define MUX_STAT_MIF7 0x041c |
| 798 | #define DIV_MIF1 0x0604 |
| 799 | #define DIV_MIF2 0x0608 |
| 800 | #define DIV_MIF3 0x060c |
| 801 | #define DIV_MIF4 0x0610 |
| 802 | #define DIV_MIF5 0x0614 |
| 803 | #define DIV_MIF_PLL_FREQ_DET 0x0618 |
| 804 | #define DIV_STAT_MIF1 0x0704 |
| 805 | #define DIV_STAT_MIF2 0x0708 |
| 806 | #define DIV_STAT_MIF3 0x070c |
| 807 | #define DIV_STAT_MIF4 0x0710 |
| 808 | #define DIV_STAT_MIF5 0x0714 |
| 809 | #define DIV_STAT_MIF_PLL_FREQ_DET 0x0718 |
| 810 | #define ENABLE_ACLK_MIF0 0x0800 |
| 811 | #define ENABLE_ACLK_MIF1 0x0804 |
| 812 | #define ENABLE_ACLK_MIF2 0x0808 |
| 813 | #define ENABLE_ACLK_MIF3 0x080c |
| 814 | #define ENABLE_PCLK_MIF 0x0900 |
| 815 | #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904 |
| 816 | #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908 |
| 817 | #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c |
| 818 | #define ENABLE_PCLK_MIF_SECURE_RTC 0x0910 |
| 819 | #define ENABLE_SCLK_MIF 0x0a00 |
| 820 | #define ENABLE_IP_MIF0 0x0b00 |
| 821 | #define ENABLE_IP_MIF1 0x0b04 |
| 822 | #define ENABLE_IP_MIF2 0x0b08 |
| 823 | #define ENABLE_IP_MIF3 0x0b0c |
| 824 | #define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10 |
| 825 | #define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14 |
| 826 | #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18 |
| 827 | #define ENABLE_IP_MIF_SECURE_RTC 0x0b1c |
| 828 | #define CLKOUT_CMU_MIF 0x0c00 |
| 829 | #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04 |
| 830 | #define DREX_FREQ_CTRL0 0x1000 |
| 831 | #define DREX_FREQ_CTRL1 0x1004 |
| 832 | #define PAUSE 0x1008 |
| 833 | #define DDRPHY_LOCK_CTRL 0x100c |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 834 | |
| 835 | static unsigned long mif_clk_regs[] __initdata = { |
| 836 | MEM0_PLL_LOCK, |
| 837 | MEM1_PLL_LOCK, |
| 838 | BUS_PLL_LOCK, |
| 839 | MFC_PLL_LOCK, |
| 840 | MEM0_PLL_CON0, |
| 841 | MEM0_PLL_CON1, |
| 842 | MEM0_PLL_FREQ_DET, |
| 843 | MEM1_PLL_CON0, |
| 844 | MEM1_PLL_CON1, |
| 845 | MEM1_PLL_FREQ_DET, |
| 846 | BUS_PLL_CON0, |
| 847 | BUS_PLL_CON1, |
| 848 | BUS_PLL_FREQ_DET, |
| 849 | MFC_PLL_CON0, |
| 850 | MFC_PLL_CON1, |
| 851 | MFC_PLL_FREQ_DET, |
Chanwoo Choi | 06d2f9d | 2015-02-02 23:24:01 +0900 | [diff] [blame] | 852 | MUX_SEL_MIF0, |
| 853 | MUX_SEL_MIF1, |
| 854 | MUX_SEL_MIF2, |
| 855 | MUX_SEL_MIF3, |
| 856 | MUX_SEL_MIF4, |
| 857 | MUX_SEL_MIF5, |
| 858 | MUX_SEL_MIF6, |
| 859 | MUX_SEL_MIF7, |
| 860 | MUX_ENABLE_MIF0, |
| 861 | MUX_ENABLE_MIF1, |
| 862 | MUX_ENABLE_MIF2, |
| 863 | MUX_ENABLE_MIF3, |
| 864 | MUX_ENABLE_MIF4, |
| 865 | MUX_ENABLE_MIF5, |
| 866 | MUX_ENABLE_MIF6, |
| 867 | MUX_ENABLE_MIF7, |
| 868 | MUX_STAT_MIF0, |
| 869 | MUX_STAT_MIF1, |
| 870 | MUX_STAT_MIF2, |
| 871 | MUX_STAT_MIF3, |
| 872 | MUX_STAT_MIF4, |
| 873 | MUX_STAT_MIF5, |
| 874 | MUX_STAT_MIF6, |
| 875 | MUX_STAT_MIF7, |
| 876 | DIV_MIF1, |
| 877 | DIV_MIF2, |
| 878 | DIV_MIF3, |
| 879 | DIV_MIF4, |
| 880 | DIV_MIF5, |
| 881 | DIV_MIF_PLL_FREQ_DET, |
| 882 | DIV_STAT_MIF1, |
| 883 | DIV_STAT_MIF2, |
| 884 | DIV_STAT_MIF3, |
| 885 | DIV_STAT_MIF4, |
| 886 | DIV_STAT_MIF5, |
| 887 | DIV_STAT_MIF_PLL_FREQ_DET, |
| 888 | ENABLE_ACLK_MIF0, |
| 889 | ENABLE_ACLK_MIF1, |
| 890 | ENABLE_ACLK_MIF2, |
| 891 | ENABLE_ACLK_MIF3, |
| 892 | ENABLE_PCLK_MIF, |
| 893 | ENABLE_PCLK_MIF_SECURE_DREX0_TZ, |
| 894 | ENABLE_PCLK_MIF_SECURE_DREX1_TZ, |
| 895 | ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, |
| 896 | ENABLE_PCLK_MIF_SECURE_RTC, |
| 897 | ENABLE_SCLK_MIF, |
| 898 | ENABLE_IP_MIF0, |
| 899 | ENABLE_IP_MIF1, |
| 900 | ENABLE_IP_MIF2, |
| 901 | ENABLE_IP_MIF3, |
| 902 | ENABLE_IP_MIF_SECURE_DREX0_TZ, |
| 903 | ENABLE_IP_MIF_SECURE_DREX1_TZ, |
| 904 | ENABLE_IP_MIF_SECURE_MONOTONIC_CNT, |
| 905 | ENABLE_IP_MIF_SECURE_RTC, |
| 906 | CLKOUT_CMU_MIF, |
| 907 | CLKOUT_CMU_MIF_DIV_STAT, |
| 908 | DREX_FREQ_CTRL0, |
| 909 | DREX_FREQ_CTRL1, |
| 910 | PAUSE, |
| 911 | DDRPHY_LOCK_CTRL, |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 912 | }; |
| 913 | |
| 914 | static struct samsung_pll_clock mif_pll_clks[] __initdata = { |
| 915 | PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk", |
| 916 | MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates), |
| 917 | PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk", |
| 918 | MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates), |
| 919 | PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk", |
| 920 | BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates), |
| 921 | PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk", |
| 922 | MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates), |
| 923 | }; |
| 924 | |
Chanwoo Choi | 06d2f9d | 2015-02-02 23:24:01 +0900 | [diff] [blame] | 925 | /* list of all parent clock list */ |
| 926 | PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", }; |
| 927 | PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", }; |
| 928 | PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", }; |
| 929 | PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", }; |
| 930 | PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", }; |
| 931 | PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", }; |
| 932 | PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", }; |
| 933 | PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", }; |
| 934 | |
| 935 | PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", }; |
| 936 | PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", }; |
| 937 | PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", }; |
| 938 | PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", }; |
| 939 | |
| 940 | PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", }; |
| 941 | PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",}; |
| 942 | |
| 943 | PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a", |
| 944 | "mout_bus_pll_div2", }; |
| 945 | PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", }; |
| 946 | |
| 947 | PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b", |
| 948 | "sclk_mphy_pll", }; |
| 949 | PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a", |
| 950 | "mout_mfc_pll_div2", }; |
| 951 | PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", }; |
| 952 | PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b", |
| 953 | "sclk_mphy_pll", }; |
| 954 | PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a", |
| 955 | "mout_mfc_pll_div2", }; |
| 956 | |
| 957 | PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b", |
| 958 | "sclk_mphy_pll", }; |
| 959 | PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a", |
| 960 | "mout_mfc_pll_div2", }; |
| 961 | PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", }; |
| 962 | PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", }; |
| 963 | PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", }; |
| 964 | |
| 965 | PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", }; |
| 966 | PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" }; |
| 967 | |
| 968 | PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b", |
| 969 | "sclk_mphy_pll", }; |
| 970 | PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a", |
| 971 | "mout_mfc_pll_div2", }; |
| 972 | PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", }; |
| 973 | PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",}; |
| 974 | |
| 975 | static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = { |
| 976 | /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */ |
| 977 | FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0), |
| 978 | FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0), |
| 979 | FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0), |
| 980 | FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0), |
| 981 | }; |
| 982 | |
| 983 | static struct samsung_mux_clock mif_mux_clks[] __initdata = { |
| 984 | /* MUX_SEL_MIF0 */ |
| 985 | MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p, |
| 986 | MUX_SEL_MIF0, 28, 1), |
| 987 | MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p, |
| 988 | MUX_SEL_MIF0, 24, 1), |
| 989 | MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p, |
| 990 | MUX_SEL_MIF0, 20, 1), |
| 991 | MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p, |
| 992 | MUX_SEL_MIF0, 16, 1), |
| 993 | MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0, |
| 994 | 12, 1), |
| 995 | MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0, |
| 996 | 8, 1), |
| 997 | MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0, |
| 998 | 4, 1), |
| 999 | MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0, |
| 1000 | 0, 1), |
| 1001 | |
| 1002 | /* MUX_SEL_MIF1 */ |
| 1003 | MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p, |
| 1004 | MUX_SEL_MIF1, 24, 1), |
| 1005 | MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p, |
| 1006 | MUX_SEL_MIF1, 20, 1), |
| 1007 | MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p, |
| 1008 | MUX_SEL_MIF1, 16, 1), |
| 1009 | MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p, |
| 1010 | MUX_SEL_MIF1, 12, 1), |
| 1011 | MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p, |
| 1012 | MUX_SEL_MIF1, 8, 1), |
| 1013 | MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p, |
| 1014 | MUX_SEL_MIF1, 4, 1), |
| 1015 | |
| 1016 | /* MUX_SEL_MIF2 */ |
| 1017 | MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200", |
| 1018 | mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1), |
| 1019 | MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400", |
| 1020 | mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1), |
| 1021 | |
| 1022 | /* MUX_SEL_MIF3 */ |
| 1023 | MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b", |
| 1024 | mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1), |
| 1025 | MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a", |
| 1026 | mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1), |
| 1027 | |
| 1028 | /* MUX_SEL_MIF4 */ |
| 1029 | MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c", |
| 1030 | mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1), |
| 1031 | MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b", |
| 1032 | mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1), |
| 1033 | MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a", |
| 1034 | mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1), |
| 1035 | MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c", |
| 1036 | mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1), |
| 1037 | MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b", |
| 1038 | mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1), |
| 1039 | MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a", |
| 1040 | mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1), |
| 1041 | |
| 1042 | /* MUX_SEL_MIF5 */ |
| 1043 | MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c", |
| 1044 | mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1), |
| 1045 | MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b", |
| 1046 | mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1), |
| 1047 | MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a", |
| 1048 | mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1), |
| 1049 | MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p, |
| 1050 | MUX_SEL_MIF5, 8, 1), |
| 1051 | MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p, |
| 1052 | MUX_SEL_MIF5, 4, 1), |
| 1053 | MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p, |
| 1054 | MUX_SEL_MIF5, 0, 1), |
| 1055 | |
| 1056 | /* MUX_SEL_MIF6 */ |
| 1057 | MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p, |
| 1058 | MUX_SEL_MIF6, 8, 1), |
| 1059 | MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p, |
| 1060 | MUX_SEL_MIF6, 4, 1), |
| 1061 | MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p, |
| 1062 | MUX_SEL_MIF6, 0, 1), |
| 1063 | |
| 1064 | /* MUX_SEL_MIF7 */ |
| 1065 | MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c", |
| 1066 | mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1), |
| 1067 | MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b", |
| 1068 | mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1), |
| 1069 | MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a", |
| 1070 | mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1), |
| 1071 | MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p, |
| 1072 | MUX_SEL_MIF7, 8, 1), |
| 1073 | MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p, |
| 1074 | MUX_SEL_MIF7, 4, 1), |
| 1075 | MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p, |
| 1076 | MUX_SEL_MIF7, 0, 1), |
| 1077 | }; |
| 1078 | |
| 1079 | static struct samsung_div_clock mif_div_clks[] __initdata = { |
| 1080 | /* DIV_MIF1 */ |
| 1081 | DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy", |
| 1082 | DIV_MIF1, 16, 2), |
| 1083 | DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1, |
| 1084 | 12, 2), |
| 1085 | DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1, |
| 1086 | 8, 2), |
| 1087 | DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1, |
| 1088 | 4, 4), |
| 1089 | |
| 1090 | /* DIV_MIF2 */ |
| 1091 | DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2", |
| 1092 | DIV_MIF2, 20, 3), |
| 1093 | DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre", |
| 1094 | DIV_MIF2, 16, 4), |
| 1095 | DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre", |
| 1096 | DIV_MIF2, 12, 4), |
| 1097 | DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200", |
| 1098 | "mout_aclk_mifnm_200", DIV_MIF2, 8, 3), |
| 1099 | DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400", |
| 1100 | DIV_MIF2, 4, 2), |
| 1101 | DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400", |
| 1102 | DIV_MIF2, 0, 3), |
| 1103 | |
| 1104 | /* DIV_MIF3 */ |
| 1105 | DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre", |
| 1106 | DIV_MIF3, 16, 4), |
| 1107 | DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b", |
| 1108 | DIV_MIF3, 4, 3), |
| 1109 | DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200", |
| 1110 | DIV_MIF3, 0, 3), |
| 1111 | |
| 1112 | /* DIV_MIF4 */ |
| 1113 | DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c", |
| 1114 | DIV_MIF4, 24, 4), |
| 1115 | DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk", |
| 1116 | "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4), |
| 1117 | DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c", |
| 1118 | DIV_MIF4, 16, 4), |
| 1119 | DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c", |
| 1120 | DIV_MIF4, 12, 4), |
| 1121 | DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk", |
| 1122 | "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4), |
| 1123 | DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk", |
| 1124 | "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4), |
| 1125 | DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk", |
| 1126 | "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4), |
| 1127 | |
| 1128 | /* DIV_MIF5 */ |
| 1129 | DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5, |
| 1130 | 0, 3), |
| 1131 | }; |
| 1132 | |
| 1133 | static struct samsung_gate_clock mif_gate_clks[] __initdata = { |
| 1134 | /* ENABLE_ACLK_MIF0 */ |
| 1135 | GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0, |
| 1136 | 19, CLK_IGNORE_UNUSED, 0), |
| 1137 | GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0, |
| 1138 | 18, CLK_IGNORE_UNUSED, 0), |
| 1139 | GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0, |
| 1140 | 17, CLK_IGNORE_UNUSED, 0), |
| 1141 | GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0, |
| 1142 | 16, CLK_IGNORE_UNUSED, 0), |
| 1143 | GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0, |
| 1144 | 15, CLK_IGNORE_UNUSED, 0), |
| 1145 | GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0, |
| 1146 | 14, CLK_IGNORE_UNUSED, 0), |
| 1147 | GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1", |
| 1148 | ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0), |
| 1149 | GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0", |
| 1150 | ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0), |
| 1151 | GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1", |
| 1152 | ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0), |
| 1153 | GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0", |
| 1154 | ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0), |
| 1155 | GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1", |
| 1156 | ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0), |
| 1157 | GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0", |
| 1158 | ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0), |
| 1159 | GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1", |
| 1160 | ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0), |
| 1161 | GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0", |
| 1162 | ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0), |
| 1163 | GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1", |
| 1164 | ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0), |
| 1165 | GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0", |
| 1166 | ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0), |
| 1167 | GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1", |
| 1168 | ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0), |
| 1169 | GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0", |
| 1170 | ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0), |
| 1171 | GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1", |
| 1172 | ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0), |
| 1173 | GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0", |
| 1174 | ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0), |
| 1175 | |
| 1176 | /* ENABLE_ACLK_MIF1 */ |
| 1177 | GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem", |
| 1178 | "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28, |
| 1179 | CLK_IGNORE_UNUSED, 0), |
| 1180 | GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci", |
| 1181 | "div_aclk_mif_200", ENABLE_ACLK_MIF1, |
| 1182 | 27, CLK_IGNORE_UNUSED, 0), |
| 1183 | GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci", |
| 1184 | "div_aclk_mif_133", ENABLE_ACLK_MIF1, |
| 1185 | 26, CLK_IGNORE_UNUSED, 0), |
| 1186 | GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1", |
| 1187 | "div_aclk_mifnm_200", ENABLE_ACLK_MIF1, |
| 1188 | 25, CLK_IGNORE_UNUSED, 0), |
| 1189 | GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1", |
| 1190 | "div_aclk_drex1", ENABLE_ACLK_MIF1, |
| 1191 | 24, CLK_IGNORE_UNUSED, 0), |
| 1192 | GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0", |
| 1193 | "div_aclk_mifnm_200", ENABLE_ACLK_MIF1, |
| 1194 | 23, CLK_IGNORE_UNUSED, 0), |
| 1195 | GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0", |
| 1196 | "div_aclk_drex0", ENABLE_ACLK_MIF1, |
| 1197 | 22, CLK_IGNORE_UNUSED, 0), |
| 1198 | GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3", |
| 1199 | "div_aclk_mif_133", ENABLE_ACLK_MIF1, |
| 1200 | 21, CLK_IGNORE_UNUSED, 0), |
| 1201 | GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3", |
| 1202 | "div_aclk_drex1", ENABLE_ACLK_MIF1, |
| 1203 | 20, CLK_IGNORE_UNUSED, 0), |
| 1204 | GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1", |
| 1205 | "div_aclk_mif_133", ENABLE_ACLK_MIF1, |
| 1206 | 19, CLK_IGNORE_UNUSED, 0), |
| 1207 | GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1", |
| 1208 | "div_aclk_drex1", ENABLE_ACLK_MIF1, |
| 1209 | 18, CLK_IGNORE_UNUSED, 0), |
| 1210 | GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0", |
| 1211 | "div_aclk_mif_133", ENABLE_ACLK_MIF1, |
| 1212 | 17, CLK_IGNORE_UNUSED, 0), |
| 1213 | GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0", |
| 1214 | "div_aclk_drex1", ENABLE_ACLK_MIF1, |
| 1215 | 16, CLK_IGNORE_UNUSED, 0), |
| 1216 | GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3", |
| 1217 | "div_aclk_mif_133", ENABLE_ACLK_MIF1, |
| 1218 | 15, CLK_IGNORE_UNUSED, 0), |
| 1219 | GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3", |
| 1220 | "div_aclk_drex0", ENABLE_ACLK_MIF1, |
| 1221 | 14, CLK_IGNORE_UNUSED, 0), |
| 1222 | GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1", |
| 1223 | "div_aclk_mif_133", ENABLE_ACLK_MIF1, |
| 1224 | 13, CLK_IGNORE_UNUSED, 0), |
| 1225 | GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1", |
| 1226 | "div_aclk_drex0", ENABLE_ACLK_MIF1, |
| 1227 | 12, CLK_IGNORE_UNUSED, 0), |
| 1228 | GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0", |
| 1229 | "div_aclk_mif_133", ENABLE_ACLK_MIF1, |
| 1230 | 11, CLK_IGNORE_UNUSED, 0), |
| 1231 | GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0", |
| 1232 | "div_aclk_drex0", ENABLE_ACLK_MIF1, |
| 1233 | 10, CLK_IGNORE_UNUSED, 0), |
| 1234 | GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133", |
| 1235 | ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0), |
| 1236 | GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133", |
| 1237 | ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0), |
| 1238 | GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133", |
| 1239 | ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0), |
| 1240 | GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400", |
| 1241 | ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0), |
| 1242 | GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200", |
| 1243 | ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0), |
| 1244 | GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133", |
| 1245 | ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0), |
| 1246 | GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200", |
| 1247 | ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0), |
| 1248 | GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133", |
| 1249 | ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0), |
| 1250 | GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400", |
| 1251 | ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0), |
| 1252 | GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1, |
| 1253 | 0, CLK_IGNORE_UNUSED, 0), |
| 1254 | |
| 1255 | /* ENABLE_ACLK_MIF2 */ |
| 1256 | GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266", |
| 1257 | ENABLE_ACLK_MIF2, 20, 0, 0), |
| 1258 | GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1", |
| 1259 | ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0), |
| 1260 | GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1", |
| 1261 | ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0), |
| 1262 | GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1", |
| 1263 | ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0), |
| 1264 | GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0", |
| 1265 | ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0), |
| 1266 | GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0", |
| 1267 | ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0), |
| 1268 | GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0", |
| 1269 | ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0), |
| 1270 | GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx", |
| 1271 | "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7, |
| 1272 | CLK_IGNORE_UNUSED, 0), |
| 1273 | GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci", |
| 1274 | "div_aclk_mif_400", ENABLE_ACLK_MIF2, |
| 1275 | 5, CLK_IGNORE_UNUSED, 0), |
| 1276 | GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400", |
| 1277 | ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0), |
| 1278 | GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d", |
| 1279 | "div_aclk_mif_200", ENABLE_ACLK_MIF2, |
| 1280 | 3, CLK_IGNORE_UNUSED, 0), |
| 1281 | GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys", |
| 1282 | "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0), |
| 1283 | |
| 1284 | /* ENABLE_ACLK_MIF3 */ |
| 1285 | GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400", |
| 1286 | ENABLE_ACLK_MIF3, 4, |
| 1287 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), |
| 1288 | GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333", |
| 1289 | ENABLE_ACLK_MIF3, 1, |
| 1290 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), |
| 1291 | GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200", |
| 1292 | ENABLE_ACLK_MIF3, 0, |
| 1293 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), |
| 1294 | |
| 1295 | /* ENABLE_PCLK_MIF */ |
| 1296 | GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1", |
| 1297 | ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0), |
| 1298 | GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1", |
| 1299 | ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0), |
| 1300 | GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1", |
| 1301 | ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0), |
| 1302 | GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0", |
| 1303 | ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0), |
| 1304 | GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0", |
| 1305 | ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0), |
| 1306 | GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0", |
| 1307 | ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0), |
| 1308 | GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci", |
| 1309 | "div_aclk_mif_133", ENABLE_PCLK_MIF, 21, |
| 1310 | CLK_IGNORE_UNUSED, 0), |
| 1311 | GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133", |
| 1312 | ENABLE_PCLK_MIF, 19, 0, 0), |
| 1313 | GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133", |
| 1314 | ENABLE_PCLK_MIF, 18, 0, 0), |
| 1315 | GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3", |
| 1316 | "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0), |
| 1317 | GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1", |
| 1318 | "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0), |
| 1319 | GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0", |
| 1320 | "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0), |
| 1321 | GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3", |
| 1322 | "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0), |
| 1323 | GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1", |
| 1324 | "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0), |
| 1325 | GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0", |
| 1326 | "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0), |
| 1327 | GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133", |
| 1328 | ENABLE_PCLK_MIF, 11, 0, 0), |
| 1329 | GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133", |
| 1330 | ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0), |
| 1331 | GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133", |
| 1332 | ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0), |
| 1333 | GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133", |
| 1334 | ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0), |
| 1335 | GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133", |
| 1336 | ENABLE_PCLK_MIF, 7, 0, 0), |
| 1337 | GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133", |
| 1338 | ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0), |
| 1339 | GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133", |
| 1340 | ENABLE_PCLK_MIF, 5, 0, 0), |
| 1341 | GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133", |
| 1342 | ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0), |
| 1343 | GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133", |
| 1344 | ENABLE_PCLK_MIF, 2, 0, 0), |
| 1345 | GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133", |
| 1346 | ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), |
| 1347 | |
| 1348 | /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */ |
| 1349 | GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133", |
| 1350 | ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 0, 0), |
| 1351 | |
| 1352 | /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */ |
| 1353 | GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133", |
| 1354 | ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 0, 0), |
| 1355 | |
| 1356 | /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */ |
| 1357 | GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133", |
| 1358 | ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0), |
| 1359 | |
| 1360 | /* ENABLE_PCLK_MIF_SECURE_RTC */ |
| 1361 | GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133", |
| 1362 | ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0), |
| 1363 | |
| 1364 | /* ENABLE_SCLK_MIF */ |
| 1365 | GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1", |
| 1366 | ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0), |
| 1367 | GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp", |
| 1368 | "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF, |
| 1369 | 14, CLK_IGNORE_UNUSED, 0), |
| 1370 | GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0", |
| 1371 | ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0), |
| 1372 | GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd", |
| 1373 | ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0), |
| 1374 | GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp", |
| 1375 | "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF, |
| 1376 | 7, CLK_IGNORE_UNUSED, 0), |
| 1377 | GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp", |
| 1378 | "div_sclk_decon_vclk", ENABLE_SCLK_MIF, |
| 1379 | 6, CLK_IGNORE_UNUSED, 0), |
| 1380 | GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp", |
| 1381 | "div_sclk_decon_eclk", ENABLE_SCLK_MIF, |
| 1382 | 5, CLK_IGNORE_UNUSED, 0), |
| 1383 | GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif", |
| 1384 | ENABLE_SCLK_MIF, 4, |
| 1385 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), |
| 1386 | GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2", |
| 1387 | ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0), |
| 1388 | GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2", |
| 1389 | ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0), |
| 1390 | GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll", |
| 1391 | ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0), |
| 1392 | GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll", |
| 1393 | ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), |
Chanwoo Choi | 2a1808a | 2015-02-02 23:24:02 +0900 | [diff] [blame] | 1394 | |
| 1395 | /* ENABLE_SCLK_TOP_DISP */ |
| 1396 | GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp", |
| 1397 | "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0, |
| 1398 | CLK_IGNORE_UNUSED, 0), |
Chanwoo Choi | 06d2f9d | 2015-02-02 23:24:01 +0900 | [diff] [blame] | 1399 | }; |
| 1400 | |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 1401 | static struct samsung_cmu_info mif_cmu_info __initdata = { |
| 1402 | .pll_clks = mif_pll_clks, |
| 1403 | .nr_pll_clks = ARRAY_SIZE(mif_pll_clks), |
Chanwoo Choi | 06d2f9d | 2015-02-02 23:24:01 +0900 | [diff] [blame] | 1404 | .mux_clks = mif_mux_clks, |
| 1405 | .nr_mux_clks = ARRAY_SIZE(mif_mux_clks), |
| 1406 | .div_clks = mif_div_clks, |
| 1407 | .nr_div_clks = ARRAY_SIZE(mif_div_clks), |
| 1408 | .gate_clks = mif_gate_clks, |
| 1409 | .nr_gate_clks = ARRAY_SIZE(mif_gate_clks), |
| 1410 | .fixed_factor_clks = mif_fixed_factor_clks, |
| 1411 | .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks), |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 1412 | .nr_clk_ids = MIF_NR_CLK, |
| 1413 | .clk_regs = mif_clk_regs, |
| 1414 | .nr_clk_regs = ARRAY_SIZE(mif_clk_regs), |
| 1415 | }; |
| 1416 | |
| 1417 | static void __init exynos5433_cmu_mif_init(struct device_node *np) |
| 1418 | { |
| 1419 | samsung_cmu_register_one(np, &mif_cmu_info); |
| 1420 | } |
| 1421 | CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif", |
| 1422 | exynos5433_cmu_mif_init); |
| 1423 | |
| 1424 | /* |
| 1425 | * Register offset definitions for CMU_PERIC |
| 1426 | */ |
| 1427 | #define DIV_PERIC 0x0600 |
Chanwoo Choi | d0f5de6 | 2015-02-02 23:23:58 +0900 | [diff] [blame] | 1428 | #define DIV_STAT_PERIC 0x0700 |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 1429 | #define ENABLE_ACLK_PERIC 0x0800 |
| 1430 | #define ENABLE_PCLK_PERIC0 0x0900 |
| 1431 | #define ENABLE_PCLK_PERIC1 0x0904 |
| 1432 | #define ENABLE_SCLK_PERIC 0x0A00 |
| 1433 | #define ENABLE_IP_PERIC0 0x0B00 |
| 1434 | #define ENABLE_IP_PERIC1 0x0B04 |
| 1435 | #define ENABLE_IP_PERIC2 0x0B08 |
| 1436 | |
| 1437 | static unsigned long peric_clk_regs[] __initdata = { |
| 1438 | DIV_PERIC, |
Chanwoo Choi | d0f5de6 | 2015-02-02 23:23:58 +0900 | [diff] [blame] | 1439 | DIV_STAT_PERIC, |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 1440 | ENABLE_ACLK_PERIC, |
| 1441 | ENABLE_PCLK_PERIC0, |
| 1442 | ENABLE_PCLK_PERIC1, |
| 1443 | ENABLE_SCLK_PERIC, |
| 1444 | ENABLE_IP_PERIC0, |
| 1445 | ENABLE_IP_PERIC1, |
| 1446 | ENABLE_IP_PERIC2, |
| 1447 | }; |
| 1448 | |
Chanwoo Choi | d0f5de6 | 2015-02-02 23:23:58 +0900 | [diff] [blame] | 1449 | static struct samsung_div_clock peric_div_clks[] __initdata = { |
| 1450 | /* DIV_PERIC */ |
| 1451 | DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4), |
| 1452 | DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4), |
| 1453 | }; |
| 1454 | |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 1455 | static struct samsung_gate_clock peric_gate_clks[] __initdata = { |
Chanwoo Choi | d0f5de6 | 2015-02-02 23:23:58 +0900 | [diff] [blame] | 1456 | /* ENABLE_ACLK_PERIC */ |
| 1457 | GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66", |
| 1458 | ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0), |
| 1459 | GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66", |
| 1460 | ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0), |
| 1461 | GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66", |
| 1462 | ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0), |
| 1463 | GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66", |
| 1464 | ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0), |
| 1465 | |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 1466 | /* ENABLE_PCLK_PERIC0 */ |
Chanwoo Choi | d0f5de6 | 2015-02-02 23:23:58 +0900 | [diff] [blame] | 1467 | GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
| 1468 | 31, CLK_SET_RATE_PARENT, 0), |
| 1469 | GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66", |
| 1470 | ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0), |
| 1471 | GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66", |
| 1472 | ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0), |
| 1473 | GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
| 1474 | 28, CLK_SET_RATE_PARENT, 0), |
| 1475 | GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
| 1476 | 26, CLK_SET_RATE_PARENT, 0), |
| 1477 | GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
| 1478 | 25, CLK_SET_RATE_PARENT, 0), |
| 1479 | GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
| 1480 | 24, CLK_SET_RATE_PARENT, 0), |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 1481 | GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
| 1482 | 23, CLK_SET_RATE_PARENT, 0), |
| 1483 | GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
| 1484 | 22, CLK_SET_RATE_PARENT, 0), |
| 1485 | GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
| 1486 | 21, CLK_SET_RATE_PARENT, 0), |
Chanwoo Choi | d0f5de6 | 2015-02-02 23:23:58 +0900 | [diff] [blame] | 1487 | GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
| 1488 | 20, CLK_SET_RATE_PARENT, 0), |
| 1489 | GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66", |
| 1490 | ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0), |
| 1491 | GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66", |
| 1492 | ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0), |
| 1493 | GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66", |
| 1494 | ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0), |
| 1495 | GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66", |
| 1496 | ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0), |
| 1497 | GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66", |
| 1498 | ENABLE_PCLK_PERIC0, 15, |
| 1499 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 1500 | GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
| 1501 | 14, CLK_SET_RATE_PARENT, 0), |
| 1502 | GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
| 1503 | 13, CLK_SET_RATE_PARENT, 0), |
| 1504 | GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
| 1505 | 12, CLK_SET_RATE_PARENT, 0), |
| 1506 | GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66", |
| 1507 | ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0), |
| 1508 | GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66", |
| 1509 | ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0), |
| 1510 | GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66", |
| 1511 | ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0), |
| 1512 | GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66", |
| 1513 | ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0), |
| 1514 | GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
| 1515 | 7, CLK_SET_RATE_PARENT, 0), |
| 1516 | GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
| 1517 | 6, CLK_SET_RATE_PARENT, 0), |
| 1518 | GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
| 1519 | 5, CLK_SET_RATE_PARENT, 0), |
| 1520 | GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
| 1521 | 4, CLK_SET_RATE_PARENT, 0), |
| 1522 | GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
| 1523 | 3, CLK_SET_RATE_PARENT, 0), |
| 1524 | GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
| 1525 | 2, CLK_SET_RATE_PARENT, 0), |
| 1526 | GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
| 1527 | 1, CLK_SET_RATE_PARENT, 0), |
| 1528 | GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
| 1529 | 0, CLK_SET_RATE_PARENT, 0), |
| 1530 | |
| 1531 | /* ENABLE_PCLK_PERIC1 */ |
| 1532 | GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1, |
| 1533 | 9, CLK_SET_RATE_PARENT, 0), |
| 1534 | GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1, |
| 1535 | 8, CLK_SET_RATE_PARENT, 0), |
| 1536 | GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66", |
| 1537 | ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0), |
| 1538 | GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66", |
| 1539 | ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0), |
| 1540 | GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66", |
| 1541 | ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0), |
| 1542 | GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66", |
| 1543 | ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0), |
| 1544 | GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66", |
| 1545 | ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0), |
| 1546 | GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66", |
| 1547 | ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0), |
| 1548 | GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66", |
| 1549 | ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0), |
| 1550 | GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66", |
| 1551 | ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0), |
| 1552 | |
| 1553 | /* ENABLE_SCLK_PERIC */ |
Chanwoo Choi | d0f5de6 | 2015-02-02 23:23:58 +0900 | [diff] [blame] | 1554 | GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in", |
| 1555 | ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0), |
| 1556 | GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in", |
| 1557 | ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0), |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 1558 | GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC, |
| 1559 | 19, CLK_SET_RATE_PARENT, 0), |
| 1560 | GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC, |
| 1561 | 18, CLK_SET_RATE_PARENT, 0), |
Chanwoo Choi | d0f5de6 | 2015-02-02 23:23:58 +0900 | [diff] [blame] | 1562 | GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC, |
| 1563 | 17, 0, 0), |
| 1564 | GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC, |
| 1565 | 16, 0, 0), |
| 1566 | GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0), |
| 1567 | GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in", |
| 1568 | ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0), |
| 1569 | GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in", |
| 1570 | ENABLE_SCLK_PERIC, 12, |
| 1571 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), |
| 1572 | GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in", |
| 1573 | ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), |
| 1574 | GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk", |
| 1575 | "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10, |
| 1576 | CLK_SET_RATE_PARENT, 0), |
| 1577 | GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric", |
| 1578 | ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), |
| 1579 | GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric", |
| 1580 | ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), |
| 1581 | GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric", |
| 1582 | ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 1583 | GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC, |
| 1584 | 5, CLK_SET_RATE_PARENT, 0), |
| 1585 | GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC, |
Chanwoo Choi | d0f5de6 | 2015-02-02 23:23:58 +0900 | [diff] [blame] | 1586 | 4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 1587 | GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC, |
| 1588 | 3, CLK_SET_RATE_PARENT, 0), |
| 1589 | GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric", |
| 1590 | ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), |
| 1591 | GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric", |
| 1592 | ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), |
| 1593 | GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric", |
| 1594 | ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), |
| 1595 | }; |
| 1596 | |
| 1597 | static struct samsung_cmu_info peric_cmu_info __initdata = { |
Chanwoo Choi | d0f5de6 | 2015-02-02 23:23:58 +0900 | [diff] [blame] | 1598 | .div_clks = peric_div_clks, |
| 1599 | .nr_div_clks = ARRAY_SIZE(peric_div_clks), |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 1600 | .gate_clks = peric_gate_clks, |
| 1601 | .nr_gate_clks = ARRAY_SIZE(peric_gate_clks), |
| 1602 | .nr_clk_ids = PERIC_NR_CLK, |
| 1603 | .clk_regs = peric_clk_regs, |
| 1604 | .nr_clk_regs = ARRAY_SIZE(peric_clk_regs), |
| 1605 | }; |
| 1606 | |
| 1607 | static void __init exynos5433_cmu_peric_init(struct device_node *np) |
| 1608 | { |
| 1609 | samsung_cmu_register_one(np, &peric_cmu_info); |
| 1610 | } |
| 1611 | |
| 1612 | CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric", |
| 1613 | exynos5433_cmu_peric_init); |
| 1614 | |
| 1615 | /* |
| 1616 | * Register offset definitions for CMU_PERIS |
| 1617 | */ |
Chanwoo Choi | 56bcf3f | 2015-02-02 23:23:59 +0900 | [diff] [blame] | 1618 | #define ENABLE_ACLK_PERIS 0x0800 |
| 1619 | #define ENABLE_PCLK_PERIS 0x0900 |
| 1620 | #define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904 |
| 1621 | #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908 |
| 1622 | #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c |
| 1623 | #define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910 |
| 1624 | #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914 |
| 1625 | #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918 |
| 1626 | #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c |
| 1627 | #define ENABLE_SCLK_PERIS 0x0a00 |
| 1628 | #define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04 |
| 1629 | #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08 |
| 1630 | #define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c |
| 1631 | #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10 |
| 1632 | #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14 |
| 1633 | #define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18 |
| 1634 | #define ENABLE_IP_PERIS0 0x0b00 |
| 1635 | #define ENABLE_IP_PERIS1 0x0b04 |
| 1636 | #define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08 |
| 1637 | #define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c |
| 1638 | #define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10 |
| 1639 | #define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14 |
| 1640 | #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18 |
| 1641 | #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c |
| 1642 | #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20 |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 1643 | |
| 1644 | static unsigned long peris_clk_regs[] __initdata = { |
| 1645 | ENABLE_ACLK_PERIS, |
| 1646 | ENABLE_PCLK_PERIS, |
Chanwoo Choi | 56bcf3f | 2015-02-02 23:23:59 +0900 | [diff] [blame] | 1647 | ENABLE_PCLK_PERIS_SECURE_TZPC, |
| 1648 | ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, |
| 1649 | ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, |
| 1650 | ENABLE_PCLK_PERIS_SECURE_TOPRTC, |
| 1651 | ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, |
| 1652 | ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, |
| 1653 | ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, |
| 1654 | ENABLE_SCLK_PERIS, |
| 1655 | ENABLE_SCLK_PERIS_SECURE_SECKEY, |
| 1656 | ENABLE_SCLK_PERIS_SECURE_CHIPID, |
| 1657 | ENABLE_SCLK_PERIS_SECURE_TOPRTC, |
| 1658 | ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, |
| 1659 | ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, |
| 1660 | ENABLE_SCLK_PERIS_SECURE_OTP_CON, |
| 1661 | ENABLE_IP_PERIS0, |
| 1662 | ENABLE_IP_PERIS1, |
| 1663 | ENABLE_IP_PERIS_SECURE_TZPC, |
| 1664 | ENABLE_IP_PERIS_SECURE_SECKEY, |
| 1665 | ENABLE_IP_PERIS_SECURE_CHIPID, |
| 1666 | ENABLE_IP_PERIS_SECURE_TOPRTC, |
| 1667 | ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE, |
| 1668 | ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT, |
| 1669 | ENABLE_IP_PERIS_SECURE_OTP_CON, |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 1670 | }; |
| 1671 | |
| 1672 | static struct samsung_gate_clock peris_gate_clks[] __initdata = { |
Chanwoo Choi | 56bcf3f | 2015-02-02 23:23:59 +0900 | [diff] [blame] | 1673 | /* ENABLE_ACLK_PERIS */ |
| 1674 | GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66", |
| 1675 | ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0), |
| 1676 | GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66", |
| 1677 | ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0), |
| 1678 | GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66", |
| 1679 | ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0), |
| 1680 | |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 1681 | /* ENABLE_PCLK_PERIS */ |
| 1682 | GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66", |
| 1683 | ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0), |
| 1684 | GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66", |
| 1685 | ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0), |
| 1686 | GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66", |
| 1687 | ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0), |
| 1688 | GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66", |
| 1689 | ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0), |
| 1690 | GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66", |
| 1691 | ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0), |
| 1692 | GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66", |
| 1693 | ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0), |
| 1694 | GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66", |
| 1695 | ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0), |
| 1696 | GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66", |
| 1697 | ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0), |
| 1698 | GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66", |
| 1699 | ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0), |
| 1700 | GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66", |
| 1701 | ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0), |
Chanwoo Choi | 56bcf3f | 2015-02-02 23:23:59 +0900 | [diff] [blame] | 1702 | |
| 1703 | /* ENABLE_PCLK_PERIS_SECURE_TZPC */ |
| 1704 | GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66", |
| 1705 | ENABLE_PCLK_PERIS_SECURE_TZPC, 12, 0, 0), |
| 1706 | GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66", |
| 1707 | ENABLE_PCLK_PERIS_SECURE_TZPC, 11, 0, 0), |
| 1708 | GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66", |
| 1709 | ENABLE_PCLK_PERIS_SECURE_TZPC, 10, 0, 0), |
| 1710 | GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66", |
| 1711 | ENABLE_PCLK_PERIS_SECURE_TZPC, 9, 0, 0), |
| 1712 | GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66", |
| 1713 | ENABLE_PCLK_PERIS_SECURE_TZPC, 8, 0, 0), |
| 1714 | GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66", |
| 1715 | ENABLE_PCLK_PERIS_SECURE_TZPC, 7, 0, 0), |
| 1716 | GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66", |
| 1717 | ENABLE_PCLK_PERIS_SECURE_TZPC, 6, 0, 0), |
| 1718 | GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66", |
| 1719 | ENABLE_PCLK_PERIS_SECURE_TZPC, 5, 0, 0), |
| 1720 | GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66", |
| 1721 | ENABLE_PCLK_PERIS_SECURE_TZPC, 4, 0, 0), |
| 1722 | GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66", |
| 1723 | ENABLE_PCLK_PERIS_SECURE_TZPC, 3, 0, 0), |
| 1724 | GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66", |
| 1725 | ENABLE_PCLK_PERIS_SECURE_TZPC, 2, 0, 0), |
| 1726 | GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66", |
| 1727 | ENABLE_PCLK_PERIS_SECURE_TZPC, 1, 0, 0), |
| 1728 | GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66", |
| 1729 | ENABLE_PCLK_PERIS_SECURE_TZPC, 0, 0, 0), |
| 1730 | |
| 1731 | /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */ |
| 1732 | GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66", |
| 1733 | ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, 0, 0), |
| 1734 | |
| 1735 | /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */ |
| 1736 | GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66", |
| 1737 | ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, 0, 0), |
| 1738 | |
| 1739 | /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */ |
| 1740 | GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66", |
| 1741 | ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0), |
| 1742 | |
| 1743 | /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */ |
| 1744 | GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif", |
| 1745 | "aclk_peris_66", |
| 1746 | ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0), |
| 1747 | |
| 1748 | /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */ |
| 1749 | GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif", |
| 1750 | "aclk_peris_66", |
| 1751 | ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0), |
| 1752 | |
| 1753 | /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */ |
| 1754 | GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif", |
| 1755 | "aclk_peris_66", |
| 1756 | ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0), |
| 1757 | |
| 1758 | /* ENABLE_SCLK_PERIS */ |
| 1759 | GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common", |
| 1760 | ENABLE_SCLK_PERIS, 10, 0, 0), |
| 1761 | GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common", |
| 1762 | ENABLE_SCLK_PERIS, 4, 0, 0), |
| 1763 | GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common", |
| 1764 | ENABLE_SCLK_PERIS, 3, 0, 0), |
| 1765 | |
| 1766 | /* ENABLE_SCLK_PERIS_SECURE_SECKEY */ |
| 1767 | GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common", |
| 1768 | ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, 0, 0), |
| 1769 | |
| 1770 | /* ENABLE_SCLK_PERIS_SECURE_CHIPID */ |
| 1771 | GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common", |
| 1772 | ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0), |
| 1773 | |
| 1774 | /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */ |
| 1775 | GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common", |
| 1776 | ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0), |
| 1777 | |
| 1778 | /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */ |
| 1779 | GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common", |
| 1780 | ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0), |
| 1781 | |
| 1782 | /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */ |
| 1783 | GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common", |
| 1784 | ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0), |
| 1785 | |
| 1786 | /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */ |
| 1787 | GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common", |
| 1788 | ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0), |
Chanwoo Choi | 96bd622 | 2015-02-02 23:23:56 +0900 | [diff] [blame] | 1789 | }; |
| 1790 | |
| 1791 | static struct samsung_cmu_info peris_cmu_info __initdata = { |
| 1792 | .gate_clks = peris_gate_clks, |
| 1793 | .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), |
| 1794 | .nr_clk_ids = PERIS_NR_CLK, |
| 1795 | .clk_regs = peris_clk_regs, |
| 1796 | .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), |
| 1797 | }; |
| 1798 | |
| 1799 | static void __init exynos5433_cmu_peris_init(struct device_node *np) |
| 1800 | { |
| 1801 | samsung_cmu_register_one(np, &peris_cmu_info); |
| 1802 | } |
| 1803 | |
| 1804 | CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris", |
| 1805 | exynos5433_cmu_peris_init); |
| 1806 | |
| 1807 | /* |
| 1808 | * Register offset definitions for CMU_FSYS |
| 1809 | */ |
| 1810 | #define MUX_SEL_FSYS0 0x0200 |
| 1811 | #define MUX_SEL_FSYS1 0x0204 |
| 1812 | #define MUX_SEL_FSYS2 0x0208 |
| 1813 | #define MUX_SEL_FSYS3 0x020c |
| 1814 | #define MUX_SEL_FSYS4 0x0210 |
| 1815 | #define MUX_ENABLE_FSYS0 0x0300 |
| 1816 | #define MUX_ENABLE_FSYS1 0x0304 |
| 1817 | #define MUX_ENABLE_FSYS2 0x0308 |
| 1818 | #define MUX_ENABLE_FSYS3 0x030c |
| 1819 | #define MUX_ENABLE_FSYS4 0x0310 |
| 1820 | #define MUX_STAT_FSYS0 0x0400 |
| 1821 | #define MUX_STAT_FSYS1 0x0404 |
| 1822 | #define MUX_STAT_FSYS2 0x0408 |
| 1823 | #define MUX_STAT_FSYS3 0x040c |
| 1824 | #define MUX_STAT_FSYS4 0x0410 |
| 1825 | #define MUX_IGNORE_FSYS2 0x0508 |
| 1826 | #define MUX_IGNORE_FSYS3 0x050c |
| 1827 | #define ENABLE_ACLK_FSYS0 0x0800 |
| 1828 | #define ENABLE_ACLK_FSYS1 0x0804 |
| 1829 | #define ENABLE_PCLK_FSYS 0x0900 |
| 1830 | #define ENABLE_SCLK_FSYS 0x0a00 |
| 1831 | #define ENABLE_IP_FSYS0 0x0b00 |
| 1832 | #define ENABLE_IP_FSYS1 0x0b04 |
| 1833 | |
| 1834 | /* list of all parent clock list */ |
| 1835 | PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "div_aclk_fsys_200", }; |
| 1836 | PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", }; |
| 1837 | PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", }; |
| 1838 | PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", }; |
| 1839 | |
| 1840 | static unsigned long fsys_clk_regs[] __initdata = { |
| 1841 | MUX_SEL_FSYS0, |
| 1842 | MUX_SEL_FSYS1, |
| 1843 | MUX_SEL_FSYS2, |
| 1844 | MUX_SEL_FSYS3, |
| 1845 | MUX_SEL_FSYS4, |
| 1846 | MUX_ENABLE_FSYS0, |
| 1847 | MUX_ENABLE_FSYS1, |
| 1848 | MUX_ENABLE_FSYS2, |
| 1849 | MUX_ENABLE_FSYS3, |
| 1850 | MUX_ENABLE_FSYS4, |
| 1851 | MUX_STAT_FSYS0, |
| 1852 | MUX_STAT_FSYS1, |
| 1853 | MUX_STAT_FSYS2, |
| 1854 | MUX_STAT_FSYS3, |
| 1855 | MUX_STAT_FSYS4, |
| 1856 | MUX_IGNORE_FSYS2, |
| 1857 | MUX_IGNORE_FSYS3, |
| 1858 | ENABLE_ACLK_FSYS0, |
| 1859 | ENABLE_ACLK_FSYS1, |
| 1860 | ENABLE_PCLK_FSYS, |
| 1861 | ENABLE_SCLK_FSYS, |
| 1862 | ENABLE_IP_FSYS0, |
| 1863 | ENABLE_IP_FSYS1, |
| 1864 | }; |
| 1865 | |
| 1866 | static struct samsung_mux_clock fsys_mux_clks[] __initdata = { |
| 1867 | /* MUX_SEL_FSYS0 */ |
| 1868 | MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user", |
| 1869 | mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1), |
| 1870 | |
| 1871 | /* MUX_SEL_FSYS1 */ |
| 1872 | MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user", |
| 1873 | mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1), |
| 1874 | MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user", |
| 1875 | mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1), |
| 1876 | MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user", |
| 1877 | mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1), |
| 1878 | }; |
| 1879 | |
| 1880 | static struct samsung_gate_clock fsys_gate_clks[] __initdata = { |
| 1881 | /* ENABLE_ACLK_FSYS0 */ |
| 1882 | GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user", |
| 1883 | ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0), |
| 1884 | GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user", |
| 1885 | ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0), |
| 1886 | GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user", |
| 1887 | ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0), |
| 1888 | GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user", |
| 1889 | ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0), |
| 1890 | GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user", |
| 1891 | ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0), |
| 1892 | GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user", |
| 1893 | ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0), |
| 1894 | GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user", |
| 1895 | ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0), |
| 1896 | GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user", |
| 1897 | ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0), |
| 1898 | GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user", |
| 1899 | ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0), |
| 1900 | GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user", |
| 1901 | ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0), |
| 1902 | GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user", |
| 1903 | ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0), |
| 1904 | |
| 1905 | /* ENABLE_SCLK_FSYS */ |
| 1906 | GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user", |
| 1907 | ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0), |
| 1908 | GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user", |
| 1909 | ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0), |
| 1910 | GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user", |
| 1911 | ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), |
| 1912 | |
| 1913 | /* ENABLE_IP_FSYS0 */ |
| 1914 | GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0), |
| 1915 | GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0), |
| 1916 | }; |
| 1917 | |
| 1918 | static struct samsung_cmu_info fsys_cmu_info __initdata = { |
| 1919 | .mux_clks = fsys_mux_clks, |
| 1920 | .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), |
| 1921 | .gate_clks = fsys_gate_clks, |
| 1922 | .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), |
| 1923 | .nr_clk_ids = FSYS_NR_CLK, |
| 1924 | .clk_regs = fsys_clk_regs, |
| 1925 | .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), |
| 1926 | }; |
| 1927 | |
| 1928 | static void __init exynos5433_cmu_fsys_init(struct device_node *np) |
| 1929 | { |
| 1930 | samsung_cmu_register_one(np, &fsys_cmu_info); |
| 1931 | } |
| 1932 | |
| 1933 | CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys", |
| 1934 | exynos5433_cmu_fsys_init); |
Chanwoo Choi | a29308d | 2015-02-02 23:24:00 +0900 | [diff] [blame] | 1935 | |
| 1936 | /* |
| 1937 | * Register offset definitions for CMU_G2D |
| 1938 | */ |
| 1939 | #define MUX_SEL_G2D0 0x0200 |
| 1940 | #define MUX_SEL_ENABLE_G2D0 0x0300 |
| 1941 | #define MUX_SEL_STAT_G2D0 0x0400 |
| 1942 | #define DIV_G2D 0x0600 |
| 1943 | #define DIV_STAT_G2D 0x0700 |
| 1944 | #define DIV_ENABLE_ACLK_G2D 0x0800 |
| 1945 | #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804 |
| 1946 | #define DIV_ENABLE_PCLK_G2D 0x0900 |
| 1947 | #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904 |
| 1948 | #define DIV_ENABLE_IP_G2D0 0x0b00 |
| 1949 | #define DIV_ENABLE_IP_G2D1 0x0b04 |
| 1950 | #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08 |
| 1951 | |
| 1952 | static unsigned long g2d_clk_regs[] __initdata = { |
| 1953 | MUX_SEL_G2D0, |
| 1954 | MUX_SEL_ENABLE_G2D0, |
| 1955 | MUX_SEL_STAT_G2D0, |
| 1956 | DIV_G2D, |
| 1957 | DIV_STAT_G2D, |
| 1958 | DIV_ENABLE_ACLK_G2D, |
| 1959 | DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, |
| 1960 | DIV_ENABLE_PCLK_G2D, |
| 1961 | DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, |
| 1962 | DIV_ENABLE_IP_G2D0, |
| 1963 | DIV_ENABLE_IP_G2D1, |
| 1964 | DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D, |
| 1965 | }; |
| 1966 | |
| 1967 | /* list of all parent clock list */ |
| 1968 | PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", }; |
| 1969 | PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", }; |
| 1970 | |
| 1971 | static struct samsung_mux_clock g2d_mux_clks[] __initdata = { |
| 1972 | /* MUX_SEL_G2D0 */ |
| 1973 | MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user", |
| 1974 | mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1), |
| 1975 | MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user", |
| 1976 | mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1), |
| 1977 | }; |
| 1978 | |
| 1979 | static struct samsung_div_clock g2d_div_clks[] __initdata = { |
| 1980 | /* DIV_G2D */ |
| 1981 | DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user", |
| 1982 | DIV_G2D, 0, 2), |
| 1983 | }; |
| 1984 | |
| 1985 | static struct samsung_gate_clock g2d_gate_clks[] __initdata = { |
| 1986 | /* DIV_ENABLE_ACLK_G2D */ |
| 1987 | GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user", |
| 1988 | DIV_ENABLE_ACLK_G2D, 12, 0, 0), |
| 1989 | GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user", |
| 1990 | DIV_ENABLE_ACLK_G2D, 11, 0, 0), |
| 1991 | GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user", |
| 1992 | DIV_ENABLE_ACLK_G2D, 10, 0, 0), |
| 1993 | GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user", |
| 1994 | DIV_ENABLE_ACLK_G2D, 9, 0, 0), |
| 1995 | GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user", |
| 1996 | DIV_ENABLE_ACLK_G2D, 8, 0, 0), |
| 1997 | GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx", |
| 1998 | "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D, |
| 1999 | 7, 0, 0), |
| 2000 | GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d", |
| 2001 | DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0), |
| 2002 | GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d", |
| 2003 | DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0), |
| 2004 | GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user", |
| 2005 | DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0), |
| 2006 | GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d", |
| 2007 | DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0), |
| 2008 | GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user", |
| 2009 | DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0), |
| 2010 | GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user", |
| 2011 | DIV_ENABLE_ACLK_G2D, 1, 0, 0), |
| 2012 | GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user", |
| 2013 | DIV_ENABLE_ACLK_G2D, 0, 0, 0), |
| 2014 | |
| 2015 | /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */ |
| 2016 | GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user", |
| 2017 | DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), |
| 2018 | |
| 2019 | /* DIV_ENABLE_PCLK_G2D */ |
| 2020 | GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d", |
| 2021 | DIV_ENABLE_PCLK_G2D, 7, 0, 0), |
| 2022 | GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d", |
| 2023 | DIV_ENABLE_PCLK_G2D, 6, 0, 0), |
| 2024 | GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d", |
| 2025 | DIV_ENABLE_PCLK_G2D, 5, 0, 0), |
| 2026 | GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d", |
| 2027 | DIV_ENABLE_PCLK_G2D, 4, 0, 0), |
| 2028 | GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d", |
| 2029 | DIV_ENABLE_PCLK_G2D, 3, 0, 0), |
| 2030 | GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d", |
| 2031 | DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0), |
| 2032 | GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d", |
| 2033 | DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0), |
| 2034 | GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D, |
| 2035 | 0, 0, 0), |
| 2036 | |
| 2037 | /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */ |
| 2038 | GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d", |
| 2039 | DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), |
| 2040 | }; |
| 2041 | |
| 2042 | static struct samsung_cmu_info g2d_cmu_info __initdata = { |
| 2043 | .mux_clks = g2d_mux_clks, |
| 2044 | .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks), |
| 2045 | .div_clks = g2d_div_clks, |
| 2046 | .nr_div_clks = ARRAY_SIZE(g2d_div_clks), |
| 2047 | .gate_clks = g2d_gate_clks, |
| 2048 | .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks), |
| 2049 | .nr_clk_ids = G2D_NR_CLK, |
| 2050 | .clk_regs = g2d_clk_regs, |
| 2051 | .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs), |
| 2052 | }; |
| 2053 | |
| 2054 | static void __init exynos5433_cmu_g2d_init(struct device_node *np) |
| 2055 | { |
| 2056 | samsung_cmu_register_one(np, &g2d_cmu_info); |
| 2057 | } |
| 2058 | |
| 2059 | CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d", |
| 2060 | exynos5433_cmu_g2d_init); |
Chanwoo Choi | 2a1808a | 2015-02-02 23:24:02 +0900 | [diff] [blame] | 2061 | |
| 2062 | /* |
| 2063 | * Register offset definitions for CMU_DISP |
| 2064 | */ |
| 2065 | #define DISP_PLL_LOCK 0x0000 |
| 2066 | #define DISP_PLL_CON0 0x0100 |
| 2067 | #define DISP_PLL_CON1 0x0104 |
| 2068 | #define DISP_PLL_FREQ_DET 0x0108 |
| 2069 | #define MUX_SEL_DISP0 0x0200 |
| 2070 | #define MUX_SEL_DISP1 0x0204 |
| 2071 | #define MUX_SEL_DISP2 0x0208 |
| 2072 | #define MUX_SEL_DISP3 0x020c |
| 2073 | #define MUX_SEL_DISP4 0x0210 |
| 2074 | #define MUX_ENABLE_DISP0 0x0300 |
| 2075 | #define MUX_ENABLE_DISP1 0x0304 |
| 2076 | #define MUX_ENABLE_DISP2 0x0308 |
| 2077 | #define MUX_ENABLE_DISP3 0x030c |
| 2078 | #define MUX_ENABLE_DISP4 0x0310 |
| 2079 | #define MUX_STAT_DISP0 0x0400 |
| 2080 | #define MUX_STAT_DISP1 0x0404 |
| 2081 | #define MUX_STAT_DISP2 0x0408 |
| 2082 | #define MUX_STAT_DISP3 0x040c |
| 2083 | #define MUX_STAT_DISP4 0x0410 |
| 2084 | #define MUX_IGNORE_DISP2 0x0508 |
| 2085 | #define DIV_DISP 0x0600 |
| 2086 | #define DIV_DISP_PLL_FREQ_DET 0x0604 |
| 2087 | #define DIV_STAT_DISP 0x0700 |
| 2088 | #define DIV_STAT_DISP_PLL_FREQ_DET 0x0704 |
| 2089 | #define ENABLE_ACLK_DISP0 0x0800 |
| 2090 | #define ENABLE_ACLK_DISP1 0x0804 |
| 2091 | #define ENABLE_PCLK_DISP 0x0900 |
| 2092 | #define ENABLE_SCLK_DISP 0x0a00 |
| 2093 | #define ENABLE_IP_DISP0 0x0b00 |
| 2094 | #define ENABLE_IP_DISP1 0x0b04 |
| 2095 | #define CLKOUT_CMU_DISP 0x0c00 |
| 2096 | #define CLKOUT_CMU_DISP_DIV_STAT 0x0c04 |
| 2097 | |
| 2098 | static unsigned long disp_clk_regs[] __initdata = { |
| 2099 | DISP_PLL_LOCK, |
| 2100 | DISP_PLL_CON0, |
| 2101 | DISP_PLL_CON1, |
| 2102 | DISP_PLL_FREQ_DET, |
| 2103 | MUX_SEL_DISP0, |
| 2104 | MUX_SEL_DISP1, |
| 2105 | MUX_SEL_DISP2, |
| 2106 | MUX_SEL_DISP3, |
| 2107 | MUX_SEL_DISP4, |
| 2108 | MUX_ENABLE_DISP0, |
| 2109 | MUX_ENABLE_DISP1, |
| 2110 | MUX_ENABLE_DISP2, |
| 2111 | MUX_ENABLE_DISP3, |
| 2112 | MUX_ENABLE_DISP4, |
| 2113 | MUX_STAT_DISP0, |
| 2114 | MUX_STAT_DISP1, |
| 2115 | MUX_STAT_DISP2, |
| 2116 | MUX_STAT_DISP3, |
| 2117 | MUX_STAT_DISP4, |
| 2118 | MUX_IGNORE_DISP2, |
| 2119 | DIV_DISP, |
| 2120 | DIV_DISP_PLL_FREQ_DET, |
| 2121 | DIV_STAT_DISP, |
| 2122 | DIV_STAT_DISP_PLL_FREQ_DET, |
| 2123 | ENABLE_ACLK_DISP0, |
| 2124 | ENABLE_ACLK_DISP1, |
| 2125 | ENABLE_PCLK_DISP, |
| 2126 | ENABLE_SCLK_DISP, |
| 2127 | ENABLE_IP_DISP0, |
| 2128 | ENABLE_IP_DISP1, |
| 2129 | CLKOUT_CMU_DISP, |
| 2130 | CLKOUT_CMU_DISP_DIV_STAT, |
| 2131 | }; |
| 2132 | |
| 2133 | /* list of all parent clock list */ |
| 2134 | PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", }; |
| 2135 | PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", }; |
| 2136 | PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", }; |
| 2137 | PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", }; |
| 2138 | PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk", |
| 2139 | "sclk_decon_tv_eclk_disp", }; |
| 2140 | PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk", |
| 2141 | "sclk_decon_vclk_disp", }; |
| 2142 | PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk", |
| 2143 | "sclk_decon_eclk_disp", }; |
| 2144 | PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk", |
| 2145 | "sclk_decon_tv_vclk_disp", }; |
| 2146 | PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", }; |
| 2147 | |
| 2148 | PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk", |
| 2149 | "phyclk_mipidphy1_bitclkdiv8_phy", }; |
| 2150 | PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk", |
| 2151 | "phyclk_mipidphy1_rxclkesc0_phy", }; |
| 2152 | PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk", |
| 2153 | "phyclk_mipidphy0_bitclkdiv8_phy", }; |
| 2154 | PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk", |
| 2155 | "phyclk_mipidphy0_rxclkesc0_phy", }; |
| 2156 | PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk", |
| 2157 | "phyclk_hdmiphy_tmds_clko_phy", }; |
| 2158 | PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk", |
| 2159 | "phyclk_hdmiphy_pixel_clko_phy", }; |
| 2160 | |
| 2161 | PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll", |
| 2162 | "mout_sclk_dsim0_user", }; |
| 2163 | PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll", |
| 2164 | "mout_sclk_decon_tv_eclk_user", }; |
| 2165 | PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll", |
| 2166 | "mout_sclk_decon_vclk_user", }; |
| 2167 | PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll", |
| 2168 | "mout_sclk_decon_eclk_user", }; |
| 2169 | |
| 2170 | PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp", |
| 2171 | "mout_sclk_dsim1_user", }; |
| 2172 | PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = { |
| 2173 | "mout_phyclk_hdmiphy_pixel_clko_user", |
| 2174 | "mout_sclk_decon_tv_vclk_b_disp", }; |
| 2175 | PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp", |
| 2176 | "mout_sclk_decon_tv_vclk_user", }; |
| 2177 | |
| 2178 | static struct samsung_pll_clock disp_pll_clks[] __initdata = { |
| 2179 | PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk", |
| 2180 | DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates), |
| 2181 | }; |
| 2182 | |
| 2183 | static struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initdata = { |
| 2184 | /* |
| 2185 | * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}. |
| 2186 | * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk} |
| 2187 | * and sclk_decon_{vclk|tv_vclk}. |
| 2188 | */ |
| 2189 | FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk", |
| 2190 | 1, 2, 0), |
| 2191 | FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk", |
| 2192 | 1, 2, 0), |
| 2193 | }; |
| 2194 | |
| 2195 | static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = { |
| 2196 | /* PHY clocks from MIPI_DPHY1 */ |
| 2197 | FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, CLK_IS_ROOT, |
| 2198 | 188000000), |
| 2199 | FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, CLK_IS_ROOT, |
| 2200 | 100000000), |
| 2201 | /* PHY clocks from MIPI_DPHY0 */ |
| 2202 | FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, CLK_IS_ROOT, |
| 2203 | 188000000), |
| 2204 | FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT, |
| 2205 | 100000000), |
| 2206 | /* PHY clocks from HDMI_PHY */ |
| 2207 | FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 300000000), |
| 2208 | FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 166000000), |
| 2209 | }; |
| 2210 | |
| 2211 | static struct samsung_mux_clock disp_mux_clks[] __initdata = { |
| 2212 | /* MUX_SEL_DISP0 */ |
| 2213 | MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0, |
| 2214 | 0, 1), |
| 2215 | |
| 2216 | /* MUX_SEL_DISP1 */ |
| 2217 | MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user", |
| 2218 | mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1), |
| 2219 | MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user", |
| 2220 | mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1), |
| 2221 | MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p, |
| 2222 | MUX_SEL_DISP1, 20, 1), |
| 2223 | MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user", |
| 2224 | mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1), |
| 2225 | MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user", |
| 2226 | mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1), |
| 2227 | MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user", |
| 2228 | mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1), |
| 2229 | MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user", |
| 2230 | mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1), |
| 2231 | MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user", |
| 2232 | mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1), |
| 2233 | |
| 2234 | /* MUX_SEL_DISP2 */ |
| 2235 | MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER, |
| 2236 | "mout_phyclk_mipidphy1_bitclkdiv8_user", |
| 2237 | mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2, |
| 2238 | 20, 1), |
| 2239 | MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER, |
| 2240 | "mout_phyclk_mipidphy1_rxclkesc0_user", |
| 2241 | mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2, |
| 2242 | 16, 1), |
| 2243 | MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER, |
| 2244 | "mout_phyclk_mipidphy0_bitclkdiv8_user", |
| 2245 | mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2, |
| 2246 | 12, 1), |
| 2247 | MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER, |
| 2248 | "mout_phyclk_mipidphy0_rxclkesc0_user", |
| 2249 | mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2, |
| 2250 | 8, 1), |
| 2251 | MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER, |
| 2252 | "mout_phyclk_hdmiphy_tmds_clko_user", |
| 2253 | mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2, |
| 2254 | 4, 1), |
| 2255 | MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER, |
| 2256 | "mout_phyclk_hdmiphy_pixel_clko_user", |
| 2257 | mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2, |
| 2258 | 0, 1), |
| 2259 | |
| 2260 | /* MUX_SEL_DISP3 */ |
| 2261 | MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p, |
| 2262 | MUX_SEL_DISP3, 12, 1), |
| 2263 | MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk", |
| 2264 | mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1), |
| 2265 | MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk", |
| 2266 | mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1), |
| 2267 | MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk", |
| 2268 | mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1), |
| 2269 | |
| 2270 | /* MUX_SEL_DISP4 */ |
| 2271 | MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp", |
| 2272 | mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1), |
| 2273 | MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp", |
| 2274 | mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1), |
| 2275 | MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP, |
| 2276 | "mout_sclk_decon_tv_vclk_c_disp", |
| 2277 | mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1), |
| 2278 | MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP, |
| 2279 | "mout_sclk_decon_tv_vclk_b_disp", |
| 2280 | mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1), |
| 2281 | MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP, |
| 2282 | "mout_sclk_decon_tv_vclk_a_disp", |
| 2283 | mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1), |
| 2284 | }; |
| 2285 | |
| 2286 | static struct samsung_div_clock disp_div_clks[] __initdata = { |
| 2287 | /* DIV_DISP */ |
| 2288 | DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp", |
| 2289 | "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3), |
| 2290 | DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp", |
| 2291 | "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3), |
| 2292 | DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0", |
| 2293 | DIV_DISP, 16, 3), |
| 2294 | DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp", |
| 2295 | "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3), |
| 2296 | DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp", |
| 2297 | "mout_sclk_decon_vclk", DIV_DISP, 8, 3), |
| 2298 | DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp", |
| 2299 | "mout_sclk_decon_eclk", DIV_DISP, 4, 3), |
| 2300 | DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user", |
| 2301 | DIV_DISP, 0, 2), |
| 2302 | }; |
| 2303 | |
| 2304 | static struct samsung_gate_clock disp_gate_clks[] __initdata = { |
| 2305 | /* ENABLE_ACLK_DISP0 */ |
| 2306 | GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user", |
| 2307 | ENABLE_ACLK_DISP0, 2, 0, 0), |
| 2308 | GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user", |
| 2309 | ENABLE_ACLK_DISP0, 0, 0, 0), |
| 2310 | |
| 2311 | /* ENABLE_ACLK_DISP1 */ |
| 2312 | GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user", |
| 2313 | ENABLE_ACLK_DISP1, 25, 0, 0), |
| 2314 | GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user", |
| 2315 | ENABLE_ACLK_DISP1, 24, 0, 0), |
| 2316 | GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x", |
| 2317 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0), |
| 2318 | GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x", |
| 2319 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0), |
| 2320 | GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3", |
| 2321 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0), |
| 2322 | GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2", |
| 2323 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0), |
| 2324 | GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1", |
| 2325 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0), |
| 2326 | GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0", |
| 2327 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0), |
| 2328 | GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4", |
| 2329 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0), |
| 2330 | GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3", |
| 2331 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0), |
| 2332 | GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2", |
| 2333 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0), |
| 2334 | GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1", |
| 2335 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0), |
| 2336 | GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0", |
| 2337 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0), |
| 2338 | GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p", |
| 2339 | "div_pclk_disp", ENABLE_ACLK_DISP1, |
| 2340 | 12, CLK_IGNORE_UNUSED, 0), |
| 2341 | GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p", |
| 2342 | "div_pclk_disp", ENABLE_ACLK_DISP1, |
| 2343 | 11, CLK_IGNORE_UNUSED, 0), |
| 2344 | GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p", |
| 2345 | "div_pclk_disp", ENABLE_ACLK_DISP1, |
| 2346 | 10, CLK_IGNORE_UNUSED, 0), |
| 2347 | GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp", |
| 2348 | ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0), |
| 2349 | GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user", |
| 2350 | ENABLE_ACLK_DISP1, 7, 0, 0), |
| 2351 | GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user", |
| 2352 | ENABLE_ACLK_DISP1, 6, 0, 0), |
| 2353 | GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x", |
| 2354 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0), |
| 2355 | GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x", |
| 2356 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0), |
| 2357 | GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user", |
| 2358 | ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0), |
| 2359 | GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp", |
| 2360 | ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0), |
| 2361 | GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333", |
| 2362 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1, |
| 2363 | CLK_IGNORE_UNUSED, 0), |
| 2364 | GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333", |
| 2365 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, |
| 2366 | 0, CLK_IGNORE_UNUSED, 0), |
| 2367 | |
| 2368 | /* ENABLE_PCLK_DISP */ |
| 2369 | GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp", |
| 2370 | ENABLE_PCLK_DISP, 23, 0, 0), |
| 2371 | GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp", |
| 2372 | ENABLE_PCLK_DISP, 22, 0, 0), |
| 2373 | GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp", |
| 2374 | ENABLE_PCLK_DISP, 21, 0, 0), |
| 2375 | GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp", |
| 2376 | ENABLE_PCLK_DISP, 20, 0, 0), |
| 2377 | GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp", |
| 2378 | ENABLE_PCLK_DISP, 19, 0, 0), |
| 2379 | GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp", |
| 2380 | ENABLE_PCLK_DISP, 18, 0, 0), |
| 2381 | GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp", |
| 2382 | ENABLE_PCLK_DISP, 17, 0, 0), |
| 2383 | GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp", |
| 2384 | ENABLE_PCLK_DISP, 16, 0, 0), |
| 2385 | GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp", |
| 2386 | ENABLE_PCLK_DISP, 15, 0, 0), |
| 2387 | GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp", |
| 2388 | ENABLE_PCLK_DISP, 14, 0, 0), |
| 2389 | GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp", |
| 2390 | ENABLE_PCLK_DISP, 13, 0, 0), |
| 2391 | GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp", |
| 2392 | ENABLE_PCLK_DISP, 12, 0, 0), |
| 2393 | GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp", |
| 2394 | ENABLE_PCLK_DISP, 11, 0, 0), |
| 2395 | GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp", |
| 2396 | ENABLE_PCLK_DISP, 10, 0, 0), |
| 2397 | GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp", |
| 2398 | ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0), |
| 2399 | GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp", |
| 2400 | ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0), |
| 2401 | GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp", |
| 2402 | ENABLE_PCLK_DISP, 7, 0, 0), |
| 2403 | GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp", |
| 2404 | ENABLE_PCLK_DISP, 6, 0, 0), |
| 2405 | GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp", |
| 2406 | ENABLE_PCLK_DISP, 5, 0, 0), |
| 2407 | GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp", |
| 2408 | ENABLE_PCLK_DISP, 3, 0, 0), |
| 2409 | GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp", |
| 2410 | ENABLE_PCLK_DISP, 2, 0, 0), |
| 2411 | GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp", |
| 2412 | ENABLE_PCLK_DISP, 1, 0, 0), |
| 2413 | |
| 2414 | /* ENABLE_SCLK_DISP */ |
| 2415 | GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8", |
| 2416 | "mout_phyclk_mipidphy1_bitclkdiv8_user", |
| 2417 | ENABLE_SCLK_DISP, 26, 0, 0), |
| 2418 | GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0", |
| 2419 | "mout_phyclk_mipidphy1_rxclkesc0_user", |
| 2420 | ENABLE_SCLK_DISP, 25, 0, 0), |
| 2421 | GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1", |
| 2422 | "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0), |
| 2423 | GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1", |
| 2424 | "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0), |
| 2425 | GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp", |
| 2426 | ENABLE_SCLK_DISP, 22, 0, 0), |
| 2427 | GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk", |
| 2428 | "div_sclk_decon_tv_vclk_disp", |
| 2429 | ENABLE_SCLK_DISP, 21, 0, 0), |
| 2430 | GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8", |
| 2431 | "mout_phyclk_mipidphy0_bitclkdiv8_user", |
| 2432 | ENABLE_SCLK_DISP, 15, 0, 0), |
| 2433 | GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0", |
| 2434 | "mout_phyclk_mipidphy0_rxclkesc0_user", |
| 2435 | ENABLE_SCLK_DISP, 14, 0, 0), |
| 2436 | GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko", |
| 2437 | "mout_phyclk_hdmiphy_tmds_clko_user", |
| 2438 | ENABLE_SCLK_DISP, 13, 0, 0), |
| 2439 | GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel", |
| 2440 | "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0), |
| 2441 | GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies", |
| 2442 | "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0), |
| 2443 | GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0", |
| 2444 | "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0), |
| 2445 | GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0", |
| 2446 | "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0), |
| 2447 | GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user", |
| 2448 | ENABLE_SCLK_DISP, 7, 0, 0), |
| 2449 | GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp", |
| 2450 | ENABLE_SCLK_DISP, 6, 0, 0), |
| 2451 | GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp", |
| 2452 | ENABLE_SCLK_DISP, 5, 0, 0), |
| 2453 | GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk", |
| 2454 | "div_sclk_decon_tv_eclk_disp", |
| 2455 | ENABLE_SCLK_DISP, 4, 0, 0), |
| 2456 | GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk", |
| 2457 | "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0), |
| 2458 | GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk", |
| 2459 | "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0), |
| 2460 | }; |
| 2461 | |
| 2462 | static struct samsung_cmu_info disp_cmu_info __initdata = { |
| 2463 | .pll_clks = disp_pll_clks, |
| 2464 | .nr_pll_clks = ARRAY_SIZE(disp_pll_clks), |
| 2465 | .mux_clks = disp_mux_clks, |
| 2466 | .nr_mux_clks = ARRAY_SIZE(disp_mux_clks), |
| 2467 | .div_clks = disp_div_clks, |
| 2468 | .nr_div_clks = ARRAY_SIZE(disp_div_clks), |
| 2469 | .gate_clks = disp_gate_clks, |
| 2470 | .nr_gate_clks = ARRAY_SIZE(disp_gate_clks), |
| 2471 | .fixed_clks = disp_fixed_clks, |
| 2472 | .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks), |
| 2473 | .fixed_factor_clks = disp_fixed_factor_clks, |
| 2474 | .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks), |
| 2475 | .nr_clk_ids = DISP_NR_CLK, |
| 2476 | .clk_regs = disp_clk_regs, |
| 2477 | .nr_clk_regs = ARRAY_SIZE(disp_clk_regs), |
| 2478 | }; |
| 2479 | |
| 2480 | static void __init exynos5433_cmu_disp_init(struct device_node *np) |
| 2481 | { |
| 2482 | samsung_cmu_register_one(np, &disp_cmu_info); |
| 2483 | } |
| 2484 | |
| 2485 | CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp", |
| 2486 | exynos5433_cmu_disp_init); |
Chanwoo Choi | 2e997c0 | 2015-02-02 23:24:03 +0900 | [diff] [blame] | 2487 | |
| 2488 | /* |
| 2489 | * Register offset definitions for CMU_AUD |
| 2490 | */ |
| 2491 | #define MUX_SEL_AUD0 0x0200 |
| 2492 | #define MUX_SEL_AUD1 0x0204 |
| 2493 | #define MUX_ENABLE_AUD0 0x0300 |
| 2494 | #define MUX_ENABLE_AUD1 0x0304 |
| 2495 | #define MUX_STAT_AUD0 0x0400 |
| 2496 | #define DIV_AUD0 0x0600 |
| 2497 | #define DIV_AUD1 0x0604 |
| 2498 | #define DIV_STAT_AUD0 0x0700 |
| 2499 | #define DIV_STAT_AUD1 0x0704 |
| 2500 | #define ENABLE_ACLK_AUD 0x0800 |
| 2501 | #define ENABLE_PCLK_AUD 0x0900 |
| 2502 | #define ENABLE_SCLK_AUD0 0x0a00 |
| 2503 | #define ENABLE_SCLK_AUD1 0x0a04 |
| 2504 | #define ENABLE_IP_AUD0 0x0b00 |
| 2505 | #define ENABLE_IP_AUD1 0x0b04 |
| 2506 | |
| 2507 | static unsigned long aud_clk_regs[] __initdata = { |
| 2508 | MUX_SEL_AUD0, |
| 2509 | MUX_SEL_AUD1, |
| 2510 | MUX_ENABLE_AUD0, |
| 2511 | MUX_ENABLE_AUD1, |
| 2512 | MUX_STAT_AUD0, |
| 2513 | DIV_AUD0, |
| 2514 | DIV_AUD1, |
| 2515 | DIV_STAT_AUD0, |
| 2516 | DIV_STAT_AUD1, |
| 2517 | ENABLE_ACLK_AUD, |
| 2518 | ENABLE_PCLK_AUD, |
| 2519 | ENABLE_SCLK_AUD0, |
| 2520 | ENABLE_SCLK_AUD1, |
| 2521 | ENABLE_IP_AUD0, |
| 2522 | ENABLE_IP_AUD1, |
| 2523 | }; |
| 2524 | |
| 2525 | /* list of all parent clock list */ |
| 2526 | PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", }; |
| 2527 | PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",}; |
| 2528 | |
| 2529 | static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = { |
| 2530 | FRATE(0, "ioclk_jtag_tclk", NULL, CLK_IS_ROOT, 33000000), |
| 2531 | FRATE(0, "ioclk_slimbus_clk", NULL, CLK_IS_ROOT, 25000000), |
| 2532 | FRATE(0, "ioclk_i2s_bclk", NULL, CLK_IS_ROOT, 50000000), |
| 2533 | }; |
| 2534 | |
| 2535 | static struct samsung_mux_clock aud_mux_clks[] __initdata = { |
| 2536 | /* MUX_SEL_AUD0 */ |
| 2537 | MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user", |
| 2538 | mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1), |
| 2539 | |
| 2540 | /* MUX_SEL_AUD1 */ |
| 2541 | MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p, |
| 2542 | MUX_SEL_AUD1, 8, 1), |
| 2543 | MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p, |
| 2544 | MUX_SEL_AUD1, 0, 1), |
| 2545 | }; |
| 2546 | |
| 2547 | static struct samsung_div_clock aud_div_clks[] __initdata = { |
| 2548 | /* DIV_AUD0 */ |
| 2549 | DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0, |
| 2550 | 12, 4), |
| 2551 | DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0, |
| 2552 | 8, 4), |
| 2553 | DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0, |
| 2554 | 4, 4), |
| 2555 | DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0, |
| 2556 | 0, 4), |
| 2557 | |
| 2558 | /* DIV_AUD1 */ |
| 2559 | DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus", |
| 2560 | "mout_aud_pll_user", DIV_AUD1, 16, 5), |
| 2561 | DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user", |
| 2562 | DIV_AUD1, 12, 4), |
| 2563 | DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm", |
| 2564 | DIV_AUD1, 4, 8), |
| 2565 | DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s", |
| 2566 | DIV_AUD1, 0, 4), |
| 2567 | }; |
| 2568 | |
| 2569 | static struct samsung_gate_clock aud_gate_clks[] __initdata = { |
| 2570 | /* ENABLE_ACLK_AUD */ |
| 2571 | GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud", |
| 2572 | ENABLE_ACLK_AUD, 12, 0, 0), |
| 2573 | GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud", |
| 2574 | ENABLE_ACLK_AUD, 7, 0, 0), |
| 2575 | GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud", |
| 2576 | ENABLE_ACLK_AUD, 0, 4, 0), |
| 2577 | GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud", |
| 2578 | ENABLE_ACLK_AUD, 0, 3, 0), |
| 2579 | GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud", |
| 2580 | ENABLE_ACLK_AUD, 0, 2, 0), |
| 2581 | GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD, |
| 2582 | 0, 1, 0), |
| 2583 | GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD, |
| 2584 | 0, CLK_IGNORE_UNUSED, 0), |
| 2585 | |
| 2586 | /* ENABLE_PCLK_AUD */ |
| 2587 | GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD, |
| 2588 | 13, 0, 0), |
| 2589 | GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD, |
| 2590 | 12, 0, 0), |
| 2591 | GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD, |
| 2592 | 11, 0, 0), |
| 2593 | GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud", |
| 2594 | ENABLE_PCLK_AUD, 10, 0, 0), |
| 2595 | GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud", |
| 2596 | ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0), |
| 2597 | GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud", |
| 2598 | ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0), |
| 2599 | GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud", |
| 2600 | ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0), |
| 2601 | GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud", |
| 2602 | ENABLE_PCLK_AUD, 6, 0, 0), |
| 2603 | GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud", |
| 2604 | ENABLE_PCLK_AUD, 5, 0, 0), |
| 2605 | GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud", |
| 2606 | ENABLE_PCLK_AUD, 4, 0, 0), |
| 2607 | GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud", |
| 2608 | ENABLE_PCLK_AUD, 3, 0, 0), |
| 2609 | GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD, |
| 2610 | 2, 0, 0), |
| 2611 | GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud", |
| 2612 | ENABLE_PCLK_AUD, 0, 0, 0), |
| 2613 | |
| 2614 | /* ENABLE_SCLK_AUD0 */ |
| 2615 | GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0, |
| 2616 | 2, 0, 0), |
| 2617 | GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud", |
| 2618 | ENABLE_SCLK_AUD0, 1, 0, 0), |
| 2619 | GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0, |
| 2620 | 0, 0, 0), |
| 2621 | |
| 2622 | /* ENABLE_SCLK_AUD1 */ |
| 2623 | GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk", |
| 2624 | ENABLE_SCLK_AUD1, 6, 0, 0), |
| 2625 | GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk", |
| 2626 | ENABLE_SCLK_AUD1, 5, 0, 0), |
| 2627 | GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus", |
| 2628 | ENABLE_SCLK_AUD1, 4, 0, 0), |
| 2629 | GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart", |
| 2630 | ENABLE_SCLK_AUD1, 3, 0, 0), |
| 2631 | GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm", |
| 2632 | ENABLE_SCLK_AUD1, 2, 0, 0), |
| 2633 | GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk", |
| 2634 | ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0), |
| 2635 | GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s", |
| 2636 | ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0), |
| 2637 | }; |
| 2638 | |
| 2639 | static struct samsung_cmu_info aud_cmu_info __initdata = { |
| 2640 | .mux_clks = aud_mux_clks, |
| 2641 | .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), |
| 2642 | .div_clks = aud_div_clks, |
| 2643 | .nr_div_clks = ARRAY_SIZE(aud_div_clks), |
| 2644 | .gate_clks = aud_gate_clks, |
| 2645 | .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), |
| 2646 | .fixed_clks = aud_fixed_clks, |
| 2647 | .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks), |
| 2648 | .nr_clk_ids = AUD_NR_CLK, |
| 2649 | .clk_regs = aud_clk_regs, |
| 2650 | .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), |
| 2651 | }; |
| 2652 | |
| 2653 | static void __init exynos5433_cmu_aud_init(struct device_node *np) |
| 2654 | { |
| 2655 | samsung_cmu_register_one(np, &aud_cmu_info); |
| 2656 | } |
| 2657 | CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud", |
| 2658 | exynos5433_cmu_aud_init); |
Chanwoo Choi | 5785d6e | 2015-02-02 23:24:04 +0900 | [diff] [blame^] | 2659 | |
| 2660 | |
| 2661 | /* |
| 2662 | * Register offset definitions for CMU_BUS{0|1|2} |
| 2663 | */ |
| 2664 | #define DIV_BUS 0x0600 |
| 2665 | #define DIV_STAT_BUS 0x0700 |
| 2666 | #define ENABLE_ACLK_BUS 0x0800 |
| 2667 | #define ENABLE_PCLK_BUS 0x0900 |
| 2668 | #define ENABLE_IP_BUS0 0x0b00 |
| 2669 | #define ENABLE_IP_BUS1 0x0b04 |
| 2670 | |
| 2671 | #define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */ |
| 2672 | #define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */ |
| 2673 | #define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */ |
| 2674 | |
| 2675 | /* list of all parent clock list */ |
| 2676 | PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", }; |
| 2677 | |
| 2678 | #define CMU_BUS_COMMON_CLK_REGS \ |
| 2679 | DIV_BUS, \ |
| 2680 | DIV_STAT_BUS, \ |
| 2681 | ENABLE_ACLK_BUS, \ |
| 2682 | ENABLE_PCLK_BUS, \ |
| 2683 | ENABLE_IP_BUS0, \ |
| 2684 | ENABLE_IP_BUS1 |
| 2685 | |
| 2686 | static unsigned long bus01_clk_regs[] __initdata = { |
| 2687 | CMU_BUS_COMMON_CLK_REGS, |
| 2688 | }; |
| 2689 | |
| 2690 | static unsigned long bus2_clk_regs[] __initdata = { |
| 2691 | MUX_SEL_BUS2, |
| 2692 | MUX_ENABLE_BUS2, |
| 2693 | MUX_STAT_BUS2, |
| 2694 | CMU_BUS_COMMON_CLK_REGS, |
| 2695 | }; |
| 2696 | |
| 2697 | static struct samsung_div_clock bus0_div_clks[] __initdata = { |
| 2698 | /* DIV_BUS0 */ |
| 2699 | DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400", |
| 2700 | DIV_BUS, 0, 3), |
| 2701 | }; |
| 2702 | |
| 2703 | /* CMU_BUS0 clocks */ |
| 2704 | static struct samsung_gate_clock bus0_gate_clks[] __initdata = { |
| 2705 | /* ENABLE_ACLK_BUS0 */ |
| 2706 | GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133", |
| 2707 | ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), |
| 2708 | GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133", |
| 2709 | ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), |
| 2710 | GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400", |
| 2711 | ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0), |
| 2712 | |
| 2713 | /* ENABLE_PCLK_BUS0 */ |
| 2714 | GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133", |
| 2715 | ENABLE_PCLK_BUS, 2, 0, 0), |
| 2716 | GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133", |
| 2717 | ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), |
| 2718 | GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133", |
| 2719 | ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), |
| 2720 | }; |
| 2721 | |
| 2722 | /* CMU_BUS1 clocks */ |
| 2723 | static struct samsung_div_clock bus1_div_clks[] __initdata = { |
| 2724 | /* DIV_BUS1 */ |
| 2725 | DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400", |
| 2726 | DIV_BUS, 0, 3), |
| 2727 | }; |
| 2728 | |
| 2729 | static struct samsung_gate_clock bus1_gate_clks[] __initdata = { |
| 2730 | /* ENABLE_ACLK_BUS1 */ |
| 2731 | GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133", |
| 2732 | ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), |
| 2733 | GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133", |
| 2734 | ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), |
| 2735 | GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400", |
| 2736 | ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0), |
| 2737 | |
| 2738 | /* ENABLE_PCLK_BUS1 */ |
| 2739 | GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133", |
| 2740 | ENABLE_PCLK_BUS, 2, 0, 0), |
| 2741 | GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133", |
| 2742 | ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), |
| 2743 | GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133", |
| 2744 | ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), |
| 2745 | }; |
| 2746 | |
| 2747 | /* CMU_BUS2 clocks */ |
| 2748 | static struct samsung_mux_clock bus2_mux_clks[] __initdata = { |
| 2749 | /* MUX_SEL_BUS2 */ |
| 2750 | MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user", |
| 2751 | mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1), |
| 2752 | }; |
| 2753 | |
| 2754 | static struct samsung_div_clock bus2_div_clks[] __initdata = { |
| 2755 | /* DIV_BUS2 */ |
| 2756 | DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133", |
| 2757 | "mout_aclk_bus2_400_user", DIV_BUS, 0, 3), |
| 2758 | }; |
| 2759 | |
| 2760 | static struct samsung_gate_clock bus2_gate_clks[] __initdata = { |
| 2761 | /* ENABLE_ACLK_BUS2 */ |
| 2762 | GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133", |
| 2763 | ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0), |
| 2764 | GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133", |
| 2765 | ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), |
| 2766 | GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400", |
| 2767 | "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS, |
| 2768 | 1, CLK_IGNORE_UNUSED, 0), |
| 2769 | GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400", |
| 2770 | "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS, |
| 2771 | 0, CLK_IGNORE_UNUSED, 0), |
| 2772 | |
| 2773 | /* ENABLE_PCLK_BUS2 */ |
| 2774 | GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133", |
| 2775 | ENABLE_PCLK_BUS, 2, 0, 0), |
| 2776 | GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133", |
| 2777 | ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), |
| 2778 | GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133", |
| 2779 | ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), |
| 2780 | }; |
| 2781 | |
| 2782 | #define CMU_BUS_INFO_CLKS(id) \ |
| 2783 | .div_clks = bus##id##_div_clks, \ |
| 2784 | .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \ |
| 2785 | .gate_clks = bus##id##_gate_clks, \ |
| 2786 | .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \ |
| 2787 | .nr_clk_ids = BUSx_NR_CLK |
| 2788 | |
| 2789 | static struct samsung_cmu_info bus0_cmu_info __initdata = { |
| 2790 | CMU_BUS_INFO_CLKS(0), |
| 2791 | .clk_regs = bus01_clk_regs, |
| 2792 | .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), |
| 2793 | }; |
| 2794 | |
| 2795 | static struct samsung_cmu_info bus1_cmu_info __initdata = { |
| 2796 | CMU_BUS_INFO_CLKS(1), |
| 2797 | .clk_regs = bus01_clk_regs, |
| 2798 | .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), |
| 2799 | }; |
| 2800 | |
| 2801 | static struct samsung_cmu_info bus2_cmu_info __initdata = { |
| 2802 | CMU_BUS_INFO_CLKS(2), |
| 2803 | .mux_clks = bus2_mux_clks, |
| 2804 | .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks), |
| 2805 | .clk_regs = bus2_clk_regs, |
| 2806 | .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs), |
| 2807 | }; |
| 2808 | |
| 2809 | #define exynos5433_cmu_bus_init(id) \ |
| 2810 | static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\ |
| 2811 | { \ |
| 2812 | samsung_cmu_register_one(np, &bus##id##_cmu_info); \ |
| 2813 | } \ |
| 2814 | CLK_OF_DECLARE(exynos5433_cmu_bus##id, \ |
| 2815 | "samsung,exynos5433-cmu-bus"#id, \ |
| 2816 | exynos5433_cmu_bus##id##_init) |
| 2817 | |
| 2818 | exynos5433_cmu_bus_init(0); |
| 2819 | exynos5433_cmu_bus_init(1); |
| 2820 | exynos5433_cmu_bus_init(2); |