Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be included in |
| 13 | * all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: Dave Airlie |
| 24 | * Alex Deucher |
| 25 | */ |
| 26 | #include "drmP.h" |
| 27 | #include "radeon_drm.h" |
| 28 | #include "radeon.h" |
| 29 | |
| 30 | #include "atom.h" |
| 31 | #include "atom-bits.h" |
| 32 | #include "drm_dp_helper.h" |
| 33 | |
Alex Deucher | f92a8b6 | 2009-11-23 18:40:40 -0500 | [diff] [blame] | 34 | /* move these to drm_dp_helper.c/h */ |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 35 | #define DP_LINK_CONFIGURATION_SIZE 9 |
| 36 | #define DP_LINK_STATUS_SIZE 6 |
| 37 | #define DP_DPCD_SIZE 8 |
| 38 | |
| 39 | static char *voltage_names[] = { |
| 40 | "0.4V", "0.6V", "0.8V", "1.2V" |
| 41 | }; |
| 42 | static char *pre_emph_names[] = { |
| 43 | "0dB", "3.5dB", "6dB", "9.5dB" |
| 44 | }; |
| 45 | static char *link_train_names[] = { |
| 46 | "pattern 1", "pattern 2", "idle", "off" |
| 47 | }; |
Alex Deucher | f92a8b6 | 2009-11-23 18:40:40 -0500 | [diff] [blame] | 48 | |
| 49 | static const int dp_clocks[] = { |
| 50 | 54000, // 1 lane, 1.62 Ghz |
| 51 | 90000, // 1 lane, 2.70 Ghz |
| 52 | 108000, // 2 lane, 1.62 Ghz |
| 53 | 180000, // 2 lane, 2.70 Ghz |
| 54 | 216000, // 4 lane, 1.62 Ghz |
| 55 | 360000, // 4 lane, 2.70 Ghz |
| 56 | }; |
| 57 | |
| 58 | static const int num_dp_clocks = sizeof(dp_clocks) / sizeof(int); |
| 59 | |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 60 | /* common helper functions */ |
| 61 | static int dp_lanes_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock) |
Alex Deucher | f92a8b6 | 2009-11-23 18:40:40 -0500 | [diff] [blame] | 62 | { |
| 63 | int i; |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 64 | u8 max_link_bw; |
| 65 | u8 max_lane_count; |
| 66 | |
| 67 | if (!dpcd) |
| 68 | return 0; |
| 69 | |
| 70 | max_link_bw = dpcd[DP_MAX_LINK_RATE]; |
| 71 | max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; |
Alex Deucher | f92a8b6 | 2009-11-23 18:40:40 -0500 | [diff] [blame] | 72 | |
| 73 | switch (max_link_bw) { |
| 74 | case DP_LINK_BW_1_62: |
| 75 | default: |
| 76 | for (i = 0; i < num_dp_clocks; i++) { |
| 77 | if (i % 2) |
| 78 | continue; |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 79 | switch (max_lane_count) { |
| 80 | case 1: |
| 81 | if (i > 1) |
| 82 | return 0; |
| 83 | break; |
| 84 | case 2: |
| 85 | if (i > 3) |
| 86 | return 0; |
| 87 | break; |
| 88 | case 4: |
| 89 | default: |
| 90 | break; |
| 91 | } |
Alex Deucher | f92a8b6 | 2009-11-23 18:40:40 -0500 | [diff] [blame] | 92 | if (dp_clocks[i] > mode_clock) { |
| 93 | if (i < 2) |
| 94 | return 1; |
| 95 | else if (i < 4) |
| 96 | return 2; |
| 97 | else |
| 98 | return 4; |
| 99 | } |
| 100 | } |
| 101 | break; |
| 102 | case DP_LINK_BW_2_7: |
| 103 | for (i = 0; i < num_dp_clocks; i++) { |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 104 | switch (max_lane_count) { |
| 105 | case 1: |
| 106 | if (i > 1) |
| 107 | return 0; |
| 108 | break; |
| 109 | case 2: |
| 110 | if (i > 3) |
| 111 | return 0; |
| 112 | break; |
| 113 | case 4: |
| 114 | default: |
| 115 | break; |
| 116 | } |
Alex Deucher | f92a8b6 | 2009-11-23 18:40:40 -0500 | [diff] [blame] | 117 | if (dp_clocks[i] > mode_clock) { |
| 118 | if (i < 2) |
| 119 | return 1; |
| 120 | else if (i < 4) |
| 121 | return 2; |
| 122 | else |
| 123 | return 4; |
| 124 | } |
| 125 | } |
| 126 | break; |
| 127 | } |
| 128 | |
| 129 | return 0; |
| 130 | } |
| 131 | |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 132 | static int dp_link_clock_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock) |
Alex Deucher | f92a8b6 | 2009-11-23 18:40:40 -0500 | [diff] [blame] | 133 | { |
| 134 | int i; |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 135 | u8 max_link_bw; |
| 136 | u8 max_lane_count; |
| 137 | |
| 138 | if (!dpcd) |
| 139 | return 0; |
| 140 | |
| 141 | max_link_bw = dpcd[DP_MAX_LINK_RATE]; |
| 142 | max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; |
Alex Deucher | f92a8b6 | 2009-11-23 18:40:40 -0500 | [diff] [blame] | 143 | |
| 144 | switch (max_link_bw) { |
| 145 | case DP_LINK_BW_1_62: |
| 146 | default: |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 147 | for (i = 0; i < num_dp_clocks; i++) { |
| 148 | if (i % 2) |
| 149 | continue; |
| 150 | switch (max_lane_count) { |
| 151 | case 1: |
| 152 | if (i > 1) |
| 153 | return 0; |
| 154 | break; |
| 155 | case 2: |
| 156 | if (i > 3) |
| 157 | return 0; |
| 158 | break; |
| 159 | case 4: |
| 160 | default: |
| 161 | break; |
| 162 | } |
| 163 | if (dp_clocks[i] > mode_clock) |
| 164 | return 162000; |
| 165 | } |
Alex Deucher | f92a8b6 | 2009-11-23 18:40:40 -0500 | [diff] [blame] | 166 | break; |
| 167 | case DP_LINK_BW_2_7: |
| 168 | for (i = 0; i < num_dp_clocks; i++) { |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 169 | switch (max_lane_count) { |
| 170 | case 1: |
| 171 | if (i > 1) |
| 172 | return 0; |
| 173 | break; |
| 174 | case 2: |
| 175 | if (i > 3) |
| 176 | return 0; |
| 177 | break; |
| 178 | case 4: |
| 179 | default: |
| 180 | break; |
| 181 | } |
Alex Deucher | f92a8b6 | 2009-11-23 18:40:40 -0500 | [diff] [blame] | 182 | if (dp_clocks[i] > mode_clock) |
| 183 | return (i % 2) ? 270000 : 162000; |
| 184 | } |
| 185 | } |
| 186 | |
| 187 | return 0; |
| 188 | } |
| 189 | |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 190 | int dp_mode_valid(u8 dpcd[DP_DPCD_SIZE], int mode_clock) |
| 191 | { |
| 192 | int lanes = dp_lanes_for_mode_clock(dpcd, mode_clock); |
| 193 | int bw = dp_lanes_for_mode_clock(dpcd, mode_clock); |
| 194 | |
| 195 | if ((lanes == 0) || (bw == 0)) |
| 196 | return MODE_CLOCK_HIGH; |
| 197 | |
| 198 | return MODE_OK; |
| 199 | } |
| 200 | |
| 201 | static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r) |
| 202 | { |
| 203 | return link_status[r - DP_LANE0_1_STATUS]; |
| 204 | } |
| 205 | |
| 206 | static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE], |
| 207 | int lane) |
| 208 | { |
| 209 | int i = DP_LANE0_1_STATUS + (lane >> 1); |
| 210 | int s = (lane & 1) * 4; |
| 211 | u8 l = dp_link_status(link_status, i); |
| 212 | return (l >> s) & 0xf; |
| 213 | } |
| 214 | |
| 215 | static bool dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE], |
| 216 | int lane_count) |
| 217 | { |
| 218 | int lane; |
| 219 | u8 lane_status; |
| 220 | |
| 221 | for (lane = 0; lane < lane_count; lane++) { |
| 222 | lane_status = dp_get_lane_status(link_status, lane); |
| 223 | if ((lane_status & DP_LANE_CR_DONE) == 0) |
| 224 | return false; |
| 225 | } |
| 226 | return true; |
| 227 | } |
| 228 | |
| 229 | static bool dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE], |
| 230 | int lane_count) |
| 231 | { |
| 232 | u8 lane_align; |
| 233 | u8 lane_status; |
| 234 | int lane; |
| 235 | |
| 236 | lane_align = dp_link_status(link_status, |
| 237 | DP_LANE_ALIGN_STATUS_UPDATED); |
| 238 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) |
| 239 | return false; |
| 240 | for (lane = 0; lane < lane_count; lane++) { |
| 241 | lane_status = dp_get_lane_status(link_status, lane); |
| 242 | if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) |
| 243 | return false; |
| 244 | } |
| 245 | return true; |
| 246 | } |
| 247 | |
| 248 | static u8 dp_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], |
| 249 | int lane) |
| 250 | |
| 251 | { |
| 252 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); |
| 253 | int s = ((lane & 1) ? |
| 254 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : |
| 255 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); |
| 256 | u8 l = dp_link_status(link_status, i); |
| 257 | |
| 258 | return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; |
| 259 | } |
| 260 | |
| 261 | static u8 dp_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], |
| 262 | int lane) |
| 263 | { |
| 264 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); |
| 265 | int s = ((lane & 1) ? |
| 266 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : |
| 267 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); |
| 268 | u8 l = dp_link_status(link_status, i); |
| 269 | |
| 270 | return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; |
| 271 | } |
| 272 | |
| 273 | /* XXX fix me -- chip specific */ |
| 274 | #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 |
| 275 | static u8 dp_pre_emphasis_max(u8 voltage_swing) |
| 276 | { |
| 277 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 278 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 279 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 280 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 281 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 282 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 283 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
| 284 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 285 | default: |
| 286 | return DP_TRAIN_PRE_EMPHASIS_0; |
| 287 | } |
| 288 | } |
| 289 | |
| 290 | static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], |
| 291 | int lane_count, |
| 292 | u8 train_set[4]) |
| 293 | { |
| 294 | u8 v = 0; |
| 295 | u8 p = 0; |
| 296 | int lane; |
| 297 | |
| 298 | for (lane = 0; lane < lane_count; lane++) { |
| 299 | u8 this_v = dp_get_adjust_request_voltage(link_status, lane); |
| 300 | u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane); |
| 301 | |
| 302 | DRM_INFO("requested signal parameters: lane %d voltage %s pre_emph %s\n", |
| 303 | lane, |
| 304 | voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
| 305 | pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); |
| 306 | |
| 307 | if (this_v > v) |
| 308 | v = this_v; |
| 309 | if (this_p > p) |
| 310 | p = this_p; |
| 311 | } |
| 312 | |
| 313 | if (v >= DP_VOLTAGE_MAX) |
| 314 | v = DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; |
| 315 | |
| 316 | if (p >= dp_pre_emphasis_max(v)) |
| 317 | p = dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
| 318 | |
| 319 | DRM_INFO("using signal parameters: voltage %s pre_emph %s\n", |
| 320 | voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
| 321 | pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); |
| 322 | |
| 323 | for (lane = 0; lane < 4; lane++) |
| 324 | train_set[lane] = v | p; |
| 325 | } |
| 326 | |
| 327 | |
| 328 | /* radeon aux chan functions */ |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 329 | bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes, |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 330 | int num_bytes, u8 *read_byte, |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 331 | u8 read_buf_len, u8 delay) |
| 332 | { |
| 333 | struct drm_device *dev = chan->dev; |
| 334 | struct radeon_device *rdev = dev->dev_private; |
| 335 | PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION args; |
| 336 | int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); |
| 337 | unsigned char *base; |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 338 | |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 339 | memset(&args, 0, sizeof(args)); |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 340 | |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 341 | base = (unsigned char *)rdev->mode_info.atom_context->scratch; |
| 342 | |
| 343 | memcpy(base, req_bytes, num_bytes); |
| 344 | |
| 345 | args.lpAuxRequest = 0; |
| 346 | args.lpDataOut = 16; |
| 347 | args.ucDataOutLen = 0; |
Alex Deucher | 6a93cb2 | 2009-11-23 17:39:28 -0500 | [diff] [blame] | 348 | args.ucChannelID = chan->rec.i2c_id; |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 349 | args.ucDelay = delay / 10; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 350 | |
| 351 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 352 | |
| 353 | if (args.ucReplyStatus) { |
| 354 | DRM_ERROR("failed to get auxch %02x%02x %02x %02x 0x%02x %02x\n", |
| 355 | req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3], |
Alex Deucher | 6a93cb2 | 2009-11-23 17:39:28 -0500 | [diff] [blame] | 356 | chan->rec.i2c_id, args.ucReplyStatus); |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 357 | return false; |
| 358 | } |
| 359 | |
| 360 | if (args.ucDataOutLen && read_byte && read_buf_len) { |
| 361 | if (read_buf_len < args.ucDataOutLen) { |
| 362 | DRM_ERROR("Buffer to small for return answer %d %d\n", |
| 363 | read_buf_len, args.ucDataOutLen); |
| 364 | return false; |
| 365 | } |
| 366 | { |
| 367 | int len = min(read_buf_len, args.ucDataOutLen); |
| 368 | memcpy(read_byte, base + 16, len); |
| 369 | } |
| 370 | } |
| 371 | return true; |
| 372 | } |
| 373 | |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 374 | bool radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, uint16_t address, |
| 375 | uint8_t send_bytes, uint8_t *send) |
| 376 | { |
| 377 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
| 378 | u8 msg[20]; |
| 379 | u8 msg_len, dp_msg_len; |
| 380 | bool ret; |
| 381 | |
| 382 | dp_msg_len = 4; |
| 383 | msg[0] = address; |
| 384 | msg[1] = address >> 8; |
| 385 | msg[2] = AUX_NATIVE_WRITE << 4; |
| 386 | dp_msg_len += send_bytes; |
| 387 | msg[3] = (dp_msg_len << 4) | (send_bytes - 1); |
| 388 | |
| 389 | if (send_bytes > 16) |
| 390 | return false; |
| 391 | |
| 392 | memcpy(&msg[4], send, send_bytes); |
| 393 | msg_len = 4 + send_bytes; |
| 394 | ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, NULL, 0, 0); |
| 395 | return ret; |
| 396 | } |
| 397 | |
| 398 | bool radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, uint16_t address, |
| 399 | uint8_t delay, uint8_t expected_bytes, |
| 400 | uint8_t *read_p) |
| 401 | { |
| 402 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
| 403 | u8 msg[20]; |
| 404 | u8 msg_len, dp_msg_len; |
| 405 | bool ret = false; |
| 406 | msg_len = 4; |
| 407 | dp_msg_len = 4; |
| 408 | msg[0] = address; |
| 409 | msg[1] = address >> 8; |
| 410 | msg[2] = AUX_NATIVE_READ << 4; |
| 411 | msg[3] = (dp_msg_len) << 4; |
| 412 | msg[3] |= expected_bytes - 1; |
| 413 | |
| 414 | ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, read_p, expected_bytes, delay); |
| 415 | return ret; |
| 416 | } |
| 417 | |
| 418 | /* radeon dp functions */ |
Alex Deucher | 4143e91 | 2009-11-23 18:02:35 -0500 | [diff] [blame] | 419 | static u8 radeon_dp_encoder_service(struct radeon_device *rdev, int action, int dp_clock, |
| 420 | uint8_t ucconfig, uint8_t lane_num) |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 421 | { |
| 422 | DP_ENCODER_SERVICE_PARAMETERS args; |
| 423 | int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); |
| 424 | |
| 425 | memset(&args, 0, sizeof(args)); |
| 426 | args.ucLinkClock = dp_clock / 10; |
| 427 | args.ucConfig = ucconfig; |
| 428 | args.ucAction = action; |
| 429 | args.ucLaneNum = lane_num; |
| 430 | args.ucStatus = 0; |
| 431 | |
| 432 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 433 | return args.ucStatus; |
| 434 | } |
| 435 | |
Alex Deucher | 4143e91 | 2009-11-23 18:02:35 -0500 | [diff] [blame] | 436 | u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 437 | { |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 438 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 439 | struct drm_device *dev = radeon_connector->base.dev; |
| 440 | struct radeon_device *rdev = dev->dev_private; |
| 441 | |
| 442 | return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 443 | dig_connector->dp_i2c_bus->rec.i2c_id, 0); |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 444 | } |
| 445 | |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 446 | void radeon_dp_getdpcd(struct radeon_connector *radeon_connector) |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 447 | { |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 448 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 449 | u8 msg[25]; |
| 450 | int ret; |
| 451 | |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 452 | ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, 0, 8, msg); |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 453 | if (ret) { |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 454 | memcpy(dig_connector->dpcd, msg, 8); |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 455 | { |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 456 | int i; |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 457 | printk("DPCD: "); |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 458 | for (i = 0; i < 8; i++) |
| 459 | printk("%02x ", msg[i]); |
| 460 | printk("\n"); |
| 461 | } |
| 462 | } |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 463 | dig_connector->dpcd[0] = 0; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 464 | return; |
| 465 | } |
| 466 | |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 467 | void radeon_dp_set_link_config(struct drm_connector *connector, |
| 468 | struct drm_display_mode *mode) |
| 469 | { |
| 470 | struct radeon_connector *radeon_connector; |
| 471 | struct radeon_connector_atom_dig *dig_connector; |
| 472 | |
| 473 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) |
| 474 | return; |
| 475 | |
| 476 | radeon_connector = to_radeon_connector(connector); |
| 477 | if (!radeon_connector->con_priv) |
| 478 | return; |
| 479 | dig_connector = radeon_connector->con_priv; |
| 480 | |
| 481 | dig_connector->dp_clock = |
| 482 | dp_link_clock_for_mode_clock(dig_connector->dpcd, mode->clock); |
| 483 | dig_connector->dp_lane_count = |
| 484 | dp_lanes_for_mode_clock(dig_connector->dpcd, mode->clock); |
| 485 | } |
| 486 | |
| 487 | int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector, |
| 488 | struct drm_display_mode *mode) |
| 489 | { |
| 490 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
| 491 | |
| 492 | return dp_mode_valid(dig_connector->dpcd, mode->clock); |
| 493 | } |
| 494 | |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 495 | static bool atom_dp_get_link_status(struct radeon_connector *radeon_connector, |
| 496 | u8 link_status[DP_LINK_STATUS_SIZE]) |
| 497 | { |
| 498 | int ret; |
| 499 | ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, 100, |
| 500 | DP_LINK_STATUS_SIZE, link_status); |
| 501 | if (!ret) { |
| 502 | DRM_ERROR("displayport link status failed\n"); |
| 503 | return false; |
| 504 | } |
| 505 | |
| 506 | DRM_INFO("link status %02x %02x %02x %02x %02x %02x\n", |
| 507 | link_status[0], link_status[1], link_status[2], |
| 508 | link_status[3], link_status[4], link_status[5]); |
| 509 | return true; |
| 510 | } |
| 511 | |
| 512 | static void dp_set_power(struct radeon_connector *radeon_connector, u8 power_state) |
| 513 | { |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 514 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
| 515 | |
| 516 | if (dig_connector->dpcd[0] >= 0x11) { |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 517 | radeon_dp_aux_native_write(radeon_connector, DP_SET_POWER, 1, |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 518 | &power_state); |
| 519 | } |
| 520 | } |
| 521 | |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 522 | static void dp_set_downspread(struct radeon_connector *radeon_connector, u8 downspread) |
| 523 | { |
| 524 | radeon_dp_aux_native_write(radeon_connector, DP_DOWNSPREAD_CTRL, 1, |
| 525 | &downspread); |
| 526 | } |
| 527 | |
| 528 | static void dp_set_link_bw_lanes(struct radeon_connector *radeon_connector, |
| 529 | u8 link_configuration[DP_LINK_CONFIGURATION_SIZE]) |
| 530 | { |
| 531 | radeon_dp_aux_native_write(radeon_connector, DP_LINK_BW_SET, 2, |
| 532 | link_configuration); |
| 533 | } |
| 534 | |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 535 | static void dp_update_dpvs_emph(struct radeon_connector *radeon_connector, |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 536 | struct drm_encoder *encoder, |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 537 | u8 train_set[4]) |
| 538 | { |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 539 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
| 540 | int i; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 541 | |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 542 | for (i = 0; i < dig_connector->dp_lane_count; i++) |
| 543 | atombios_dig_transmitter_setup(encoder, |
| 544 | ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, |
| 545 | i, train_set[i]); |
| 546 | |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 547 | radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_LANE0_SET, |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 548 | dig_connector->dp_lane_count, train_set); |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 549 | } |
| 550 | |
| 551 | static void dp_set_training(struct radeon_connector *radeon_connector, |
| 552 | u8 training) |
| 553 | { |
| 554 | radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_PATTERN_SET, |
| 555 | 1, &training); |
| 556 | } |
| 557 | |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 558 | void dp_link_train(struct drm_encoder *encoder, |
| 559 | struct drm_connector *connector) |
| 560 | { |
| 561 | struct drm_device *dev = encoder->dev; |
| 562 | struct radeon_device *rdev = dev->dev_private; |
| 563 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 564 | struct radeon_encoder_atom_dig *dig; |
| 565 | struct radeon_connector *radeon_connector; |
| 566 | struct radeon_connector_atom_dig *dig_connector; |
| 567 | int enc_id = 0; |
| 568 | bool clock_recovery, channel_eq; |
| 569 | u8 link_status[DP_LINK_STATUS_SIZE]; |
| 570 | u8 link_configuration[DP_LINK_CONFIGURATION_SIZE]; |
| 571 | u8 tries, voltage; |
| 572 | u8 train_set[4]; |
| 573 | int i; |
| 574 | |
| 575 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) |
| 576 | return; |
| 577 | |
| 578 | if (!radeon_encoder->enc_priv) |
| 579 | return; |
| 580 | dig = radeon_encoder->enc_priv; |
| 581 | |
| 582 | radeon_connector = to_radeon_connector(connector); |
| 583 | if (!radeon_connector->con_priv) |
| 584 | return; |
| 585 | dig_connector = radeon_connector->con_priv; |
| 586 | |
| 587 | if (ASIC_IS_DCE32(rdev)) { |
| 588 | if (dig->dig_block) |
| 589 | enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; |
| 590 | else |
| 591 | enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; |
| 592 | if (dig_connector->linkb) |
| 593 | enc_id |= ATOM_DP_CONFIG_LINK_B; |
| 594 | else |
| 595 | enc_id |= ATOM_DP_CONFIG_LINK_A; |
| 596 | } else { |
| 597 | if (dig_connector->linkb) |
| 598 | enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER | ATOM_DP_CONFIG_LINK_B; |
| 599 | else |
| 600 | enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER | ATOM_DP_CONFIG_LINK_A; |
| 601 | } |
| 602 | |
| 603 | memset(link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
| 604 | if (dig_connector->dp_clock == 270000) |
| 605 | link_configuration[0] = DP_LINK_BW_2_7; |
| 606 | else |
| 607 | link_configuration[0] = DP_LINK_BW_1_62; |
| 608 | link_configuration[1] = dig_connector->dp_lane_count; |
| 609 | if (dig_connector->dpcd[0] >= 0x11) |
| 610 | link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
| 611 | |
| 612 | /* power up the sink */ |
| 613 | dp_set_power(radeon_connector, DP_SET_POWER_D0); |
| 614 | /* disable the training pattern on the sink */ |
| 615 | dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE); |
| 616 | /* set link bw and lanes on the sink */ |
| 617 | dp_set_link_bw_lanes(radeon_connector, link_configuration); |
| 618 | /* disable downspread on the sink */ |
| 619 | dp_set_downspread(radeon_connector, 0); |
| 620 | /* start training on the source */ |
| 621 | radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_START, |
| 622 | dig_connector->dp_clock, enc_id, 0); |
| 623 | /* set training pattern 1 on the source */ |
| 624 | radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, |
| 625 | dig_connector->dp_clock, enc_id, 0); |
| 626 | |
| 627 | /* set initial vs/emph */ |
| 628 | memset(train_set, 0, 4); |
| 629 | dp_update_dpvs_emph(radeon_connector, encoder, train_set); |
| 630 | udelay(400); |
| 631 | /* set training pattern 1 on the sink */ |
| 632 | dp_set_training(radeon_connector, DP_TRAINING_PATTERN_1); |
| 633 | |
| 634 | /* clock recovery loop */ |
| 635 | clock_recovery = false; |
| 636 | tries = 0; |
| 637 | voltage = 0xff; |
| 638 | for (;;) { |
| 639 | udelay(100); |
| 640 | if (!atom_dp_get_link_status(radeon_connector, link_status)) |
| 641 | break; |
| 642 | |
| 643 | if (dp_clock_recovery_ok(link_status, dig_connector->dp_lane_count)) { |
| 644 | clock_recovery = true; |
| 645 | break; |
| 646 | } |
| 647 | |
| 648 | for (i = 0; i < dig_connector->dp_lane_count; i++) { |
| 649 | if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
| 650 | break; |
| 651 | } |
| 652 | if (i == dig_connector->dp_lane_count) { |
| 653 | DRM_ERROR("clock recovery reached max voltage\n"); |
| 654 | break; |
| 655 | } |
| 656 | |
| 657 | if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
| 658 | ++tries; |
| 659 | if (tries == 5) { |
| 660 | DRM_ERROR("clock recovery tried 5 times\n"); |
| 661 | break; |
| 662 | } |
| 663 | } else |
| 664 | tries = 0; |
| 665 | |
| 666 | voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
| 667 | |
| 668 | /* Compute new train_set as requested by sink */ |
| 669 | dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set); |
| 670 | dp_update_dpvs_emph(radeon_connector, encoder, train_set); |
| 671 | } |
| 672 | if (!clock_recovery) |
| 673 | DRM_ERROR("clock recovery failed\n"); |
| 674 | else |
| 675 | DRM_INFO("clock recovery at voltage %d pre-emphasis %d\n", |
| 676 | train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
| 677 | (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> |
| 678 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
| 679 | |
| 680 | |
| 681 | /* set training pattern 2 on the sink */ |
| 682 | dp_set_training(radeon_connector, DP_TRAINING_PATTERN_2); |
| 683 | /* set training pattern 2 on the source */ |
| 684 | radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, |
| 685 | dig_connector->dp_clock, enc_id, 1); |
| 686 | |
| 687 | /* channel equalization loop */ |
| 688 | tries = 0; |
| 689 | channel_eq = false; |
| 690 | for (;;) { |
| 691 | udelay(400); |
| 692 | if (!atom_dp_get_link_status(radeon_connector, link_status)) |
| 693 | break; |
| 694 | |
| 695 | if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count)) { |
| 696 | channel_eq = true; |
| 697 | break; |
| 698 | } |
| 699 | |
| 700 | /* Try 5 times */ |
| 701 | if (tries > 5) { |
| 702 | DRM_ERROR("channel eq failed: 5 tries\n"); |
| 703 | break; |
| 704 | } |
| 705 | |
| 706 | /* Compute new train_set as requested by sink */ |
| 707 | dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set); |
| 708 | dp_update_dpvs_emph(radeon_connector, encoder, train_set); |
| 709 | |
| 710 | tries++; |
| 711 | } |
| 712 | |
| 713 | if (!channel_eq) |
| 714 | DRM_ERROR("channel eq failed\n"); |
| 715 | else |
| 716 | DRM_INFO("channel eq at voltage %d pre-emphasis %d\n", |
| 717 | train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
| 718 | (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) |
| 719 | >> DP_TRAIN_PRE_EMPHASIS_SHIFT); |
| 720 | |
| 721 | /* disable the training pattern on the sink */ |
| 722 | dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE); |
| 723 | |
| 724 | radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, |
| 725 | dig_connector->dp_clock, enc_id, 0); |
| 726 | } |
| 727 | |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 728 | int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
| 729 | uint8_t write_byte, uint8_t *read_byte) |
| 730 | { |
| 731 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
| 732 | struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter; |
| 733 | int ret = 0; |
| 734 | uint16_t address = algo_data->address; |
| 735 | uint8_t msg[5]; |
| 736 | uint8_t reply[2]; |
| 737 | int msg_len, dp_msg_len; |
| 738 | int reply_bytes; |
| 739 | |
| 740 | /* Set up the command byte */ |
| 741 | if (mode & MODE_I2C_READ) |
| 742 | msg[2] = AUX_I2C_READ << 4; |
| 743 | else |
| 744 | msg[2] = AUX_I2C_WRITE << 4; |
| 745 | |
| 746 | if (!(mode & MODE_I2C_STOP)) |
| 747 | msg[2] |= AUX_I2C_MOT << 4; |
| 748 | |
| 749 | msg[0] = address; |
| 750 | msg[1] = address >> 8; |
| 751 | |
| 752 | reply_bytes = 1; |
| 753 | |
| 754 | msg_len = 4; |
| 755 | dp_msg_len = 3; |
| 756 | switch (mode) { |
| 757 | case MODE_I2C_WRITE: |
| 758 | msg[4] = write_byte; |
| 759 | msg_len++; |
| 760 | dp_msg_len += 2; |
| 761 | break; |
| 762 | case MODE_I2C_READ: |
| 763 | dp_msg_len += 1; |
| 764 | break; |
| 765 | default: |
| 766 | break; |
| 767 | } |
| 768 | |
| 769 | msg[3] = (dp_msg_len) << 4; |
| 770 | ret = radeon_process_aux_ch(auxch, msg, msg_len, reply, reply_bytes, 0); |
| 771 | |
| 772 | if (ret) { |
| 773 | if (read_byte) |
| 774 | *read_byte = reply[0]; |
| 775 | return reply_bytes; |
| 776 | } |
| 777 | return -EREMOTEIO; |
| 778 | } |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame^] | 779 | |