Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Intel pinctrl/GPIO core driver. |
| 3 | * |
| 4 | * Copyright (C) 2015, Intel Corporation |
| 5 | * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> |
| 6 | * Mika Westerberg <mika.westerberg@linux.intel.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/init.h> |
Mika Westerberg | 193b40c | 2015-10-21 13:08:43 +0300 | [diff] [blame] | 15 | #include <linux/interrupt.h> |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 16 | #include <linux/acpi.h> |
| 17 | #include <linux/gpio.h> |
| 18 | #include <linux/gpio/driver.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/pm.h> |
| 21 | #include <linux/pinctrl/pinctrl.h> |
| 22 | #include <linux/pinctrl/pinmux.h> |
| 23 | #include <linux/pinctrl/pinconf.h> |
| 24 | #include <linux/pinctrl/pinconf-generic.h> |
| 25 | |
| 26 | #include "pinctrl-intel.h" |
| 27 | |
| 28 | /* Maximum number of pads in each group */ |
| 29 | #define NPADS_IN_GPP 24 |
| 30 | |
| 31 | /* Offset from regs */ |
| 32 | #define PADBAR 0x00c |
| 33 | #define GPI_IS 0x100 |
| 34 | #define GPI_GPE_STS 0x140 |
| 35 | #define GPI_GPE_EN 0x160 |
| 36 | |
| 37 | #define PADOWN_BITS 4 |
| 38 | #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) |
| 39 | #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p)) |
| 40 | |
| 41 | /* Offset from pad_regs */ |
| 42 | #define PADCFG0 0x000 |
| 43 | #define PADCFG0_RXEVCFG_SHIFT 25 |
| 44 | #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT) |
| 45 | #define PADCFG0_RXEVCFG_LEVEL 0 |
| 46 | #define PADCFG0_RXEVCFG_EDGE 1 |
| 47 | #define PADCFG0_RXEVCFG_DISABLED 2 |
| 48 | #define PADCFG0_RXEVCFG_EDGE_BOTH 3 |
| 49 | #define PADCFG0_RXINV BIT(23) |
| 50 | #define PADCFG0_GPIROUTIOXAPIC BIT(20) |
| 51 | #define PADCFG0_GPIROUTSCI BIT(19) |
| 52 | #define PADCFG0_GPIROUTSMI BIT(18) |
| 53 | #define PADCFG0_GPIROUTNMI BIT(17) |
| 54 | #define PADCFG0_PMODE_SHIFT 10 |
| 55 | #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT) |
| 56 | #define PADCFG0_GPIORXDIS BIT(9) |
| 57 | #define PADCFG0_GPIOTXDIS BIT(8) |
| 58 | #define PADCFG0_GPIORXSTATE BIT(1) |
| 59 | #define PADCFG0_GPIOTXSTATE BIT(0) |
| 60 | |
| 61 | #define PADCFG1 0x004 |
| 62 | #define PADCFG1_TERM_UP BIT(13) |
| 63 | #define PADCFG1_TERM_SHIFT 10 |
| 64 | #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT) |
| 65 | #define PADCFG1_TERM_20K 4 |
| 66 | #define PADCFG1_TERM_2K 3 |
| 67 | #define PADCFG1_TERM_5K 2 |
| 68 | #define PADCFG1_TERM_1K 1 |
| 69 | |
| 70 | struct intel_pad_context { |
| 71 | u32 padcfg0; |
| 72 | u32 padcfg1; |
| 73 | }; |
| 74 | |
| 75 | struct intel_community_context { |
| 76 | u32 *intmask; |
| 77 | }; |
| 78 | |
| 79 | struct intel_pinctrl_context { |
| 80 | struct intel_pad_context *pads; |
| 81 | struct intel_community_context *communities; |
| 82 | }; |
| 83 | |
| 84 | /** |
| 85 | * struct intel_pinctrl - Intel pinctrl private structure |
| 86 | * @dev: Pointer to the device structure |
| 87 | * @lock: Lock to serialize register access |
| 88 | * @pctldesc: Pin controller description |
| 89 | * @pctldev: Pointer to the pin controller device |
| 90 | * @chip: GPIO chip in this pin controller |
| 91 | * @soc: SoC/PCH specific pin configuration data |
| 92 | * @communities: All communities in this pin controller |
| 93 | * @ncommunities: Number of communities in this pin controller |
| 94 | * @context: Configuration saved over system sleep |
| 95 | */ |
| 96 | struct intel_pinctrl { |
| 97 | struct device *dev; |
| 98 | spinlock_t lock; |
| 99 | struct pinctrl_desc pctldesc; |
| 100 | struct pinctrl_dev *pctldev; |
| 101 | struct gpio_chip chip; |
| 102 | const struct intel_pinctrl_soc_data *soc; |
| 103 | struct intel_community *communities; |
| 104 | size_t ncommunities; |
| 105 | struct intel_pinctrl_context context; |
| 106 | }; |
| 107 | |
| 108 | #define gpiochip_to_pinctrl(c) container_of(c, struct intel_pinctrl, chip) |
| 109 | #define pin_to_padno(c, p) ((p) - (c)->pin_base) |
| 110 | |
| 111 | static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, |
| 112 | unsigned pin) |
| 113 | { |
| 114 | struct intel_community *community; |
| 115 | int i; |
| 116 | |
| 117 | for (i = 0; i < pctrl->ncommunities; i++) { |
| 118 | community = &pctrl->communities[i]; |
| 119 | if (pin >= community->pin_base && |
| 120 | pin < community->pin_base + community->npins) |
| 121 | return community; |
| 122 | } |
| 123 | |
| 124 | dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); |
| 125 | return NULL; |
| 126 | } |
| 127 | |
| 128 | static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin, |
| 129 | unsigned reg) |
| 130 | { |
| 131 | const struct intel_community *community; |
| 132 | unsigned padno; |
| 133 | |
| 134 | community = intel_get_community(pctrl, pin); |
| 135 | if (!community) |
| 136 | return NULL; |
| 137 | |
| 138 | padno = pin_to_padno(community, pin); |
| 139 | return community->pad_regs + reg + padno * 8; |
| 140 | } |
| 141 | |
| 142 | static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin) |
| 143 | { |
| 144 | const struct intel_community *community; |
| 145 | unsigned padno, gpp, gpp_offset, offset; |
| 146 | void __iomem *padown; |
| 147 | |
| 148 | community = intel_get_community(pctrl, pin); |
| 149 | if (!community) |
| 150 | return false; |
| 151 | if (!community->padown_offset) |
| 152 | return true; |
| 153 | |
| 154 | padno = pin_to_padno(community, pin); |
| 155 | gpp = padno / NPADS_IN_GPP; |
| 156 | gpp_offset = padno % NPADS_IN_GPP; |
| 157 | offset = community->padown_offset + gpp * 16 + (gpp_offset / 8) * 4; |
| 158 | padown = community->regs + offset; |
| 159 | |
| 160 | return !(readl(padown) & PADOWN_MASK(padno)); |
| 161 | } |
| 162 | |
Mika Westerberg | 4341e8a | 2015-10-21 13:08:44 +0300 | [diff] [blame] | 163 | static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin) |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 164 | { |
| 165 | const struct intel_community *community; |
| 166 | unsigned padno, gpp, offset; |
| 167 | void __iomem *hostown; |
| 168 | |
| 169 | community = intel_get_community(pctrl, pin); |
| 170 | if (!community) |
| 171 | return true; |
| 172 | if (!community->hostown_offset) |
| 173 | return false; |
| 174 | |
| 175 | padno = pin_to_padno(community, pin); |
| 176 | gpp = padno / NPADS_IN_GPP; |
| 177 | offset = community->hostown_offset + gpp * 4; |
| 178 | hostown = community->regs + offset; |
| 179 | |
| 180 | return !(readl(hostown) & BIT(padno % NPADS_IN_GPP)); |
| 181 | } |
| 182 | |
| 183 | static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) |
| 184 | { |
| 185 | struct intel_community *community; |
| 186 | unsigned padno, gpp, offset; |
| 187 | u32 value; |
| 188 | |
| 189 | community = intel_get_community(pctrl, pin); |
| 190 | if (!community) |
| 191 | return true; |
| 192 | if (!community->padcfglock_offset) |
| 193 | return false; |
| 194 | |
| 195 | padno = pin_to_padno(community, pin); |
| 196 | gpp = padno / NPADS_IN_GPP; |
| 197 | |
| 198 | /* |
| 199 | * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, |
| 200 | * the pad is considered unlocked. Any other case means that it is |
| 201 | * either fully or partially locked and we don't touch it. |
| 202 | */ |
| 203 | offset = community->padcfglock_offset + gpp * 8; |
| 204 | value = readl(community->regs + offset); |
| 205 | if (value & BIT(pin % NPADS_IN_GPP)) |
| 206 | return true; |
| 207 | |
| 208 | offset = community->padcfglock_offset + 4 + gpp * 8; |
| 209 | value = readl(community->regs + offset); |
| 210 | if (value & BIT(pin % NPADS_IN_GPP)) |
| 211 | return true; |
| 212 | |
| 213 | return false; |
| 214 | } |
| 215 | |
| 216 | static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin) |
| 217 | { |
| 218 | return intel_pad_owned_by_host(pctrl, pin) && |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 219 | !intel_pad_locked(pctrl, pin); |
| 220 | } |
| 221 | |
| 222 | static int intel_get_groups_count(struct pinctrl_dev *pctldev) |
| 223 | { |
| 224 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 225 | |
| 226 | return pctrl->soc->ngroups; |
| 227 | } |
| 228 | |
| 229 | static const char *intel_get_group_name(struct pinctrl_dev *pctldev, |
| 230 | unsigned group) |
| 231 | { |
| 232 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 233 | |
| 234 | return pctrl->soc->groups[group].name; |
| 235 | } |
| 236 | |
| 237 | static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, |
| 238 | const unsigned **pins, unsigned *npins) |
| 239 | { |
| 240 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 241 | |
| 242 | *pins = pctrl->soc->groups[group].pins; |
| 243 | *npins = pctrl->soc->groups[group].npins; |
| 244 | return 0; |
| 245 | } |
| 246 | |
| 247 | static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
| 248 | unsigned pin) |
| 249 | { |
| 250 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 251 | u32 cfg0, cfg1, mode; |
| 252 | bool locked, acpi; |
| 253 | |
| 254 | if (!intel_pad_owned_by_host(pctrl, pin)) { |
| 255 | seq_puts(s, "not available"); |
| 256 | return; |
| 257 | } |
| 258 | |
| 259 | cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); |
| 260 | cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); |
| 261 | |
| 262 | mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; |
| 263 | if (!mode) |
| 264 | seq_puts(s, "GPIO "); |
| 265 | else |
| 266 | seq_printf(s, "mode %d ", mode); |
| 267 | |
| 268 | seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); |
| 269 | |
| 270 | locked = intel_pad_locked(pctrl, pin); |
Mika Westerberg | 4341e8a | 2015-10-21 13:08:44 +0300 | [diff] [blame] | 271 | acpi = intel_pad_acpi_mode(pctrl, pin); |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 272 | |
| 273 | if (locked || acpi) { |
| 274 | seq_puts(s, " ["); |
| 275 | if (locked) { |
| 276 | seq_puts(s, "LOCKED"); |
| 277 | if (acpi) |
| 278 | seq_puts(s, ", "); |
| 279 | } |
| 280 | if (acpi) |
| 281 | seq_puts(s, "ACPI"); |
| 282 | seq_puts(s, "]"); |
| 283 | } |
| 284 | } |
| 285 | |
| 286 | static const struct pinctrl_ops intel_pinctrl_ops = { |
| 287 | .get_groups_count = intel_get_groups_count, |
| 288 | .get_group_name = intel_get_group_name, |
| 289 | .get_group_pins = intel_get_group_pins, |
| 290 | .pin_dbg_show = intel_pin_dbg_show, |
| 291 | }; |
| 292 | |
| 293 | static int intel_get_functions_count(struct pinctrl_dev *pctldev) |
| 294 | { |
| 295 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 296 | |
| 297 | return pctrl->soc->nfunctions; |
| 298 | } |
| 299 | |
| 300 | static const char *intel_get_function_name(struct pinctrl_dev *pctldev, |
| 301 | unsigned function) |
| 302 | { |
| 303 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 304 | |
| 305 | return pctrl->soc->functions[function].name; |
| 306 | } |
| 307 | |
| 308 | static int intel_get_function_groups(struct pinctrl_dev *pctldev, |
| 309 | unsigned function, |
| 310 | const char * const **groups, |
| 311 | unsigned * const ngroups) |
| 312 | { |
| 313 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 314 | |
| 315 | *groups = pctrl->soc->functions[function].groups; |
| 316 | *ngroups = pctrl->soc->functions[function].ngroups; |
| 317 | return 0; |
| 318 | } |
| 319 | |
| 320 | static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, |
| 321 | unsigned group) |
| 322 | { |
| 323 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 324 | const struct intel_pingroup *grp = &pctrl->soc->groups[group]; |
| 325 | unsigned long flags; |
| 326 | int i; |
| 327 | |
| 328 | spin_lock_irqsave(&pctrl->lock, flags); |
| 329 | |
| 330 | /* |
| 331 | * All pins in the groups needs to be accessible and writable |
| 332 | * before we can enable the mux for this group. |
| 333 | */ |
| 334 | for (i = 0; i < grp->npins; i++) { |
| 335 | if (!intel_pad_usable(pctrl, grp->pins[i])) { |
| 336 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 337 | return -EBUSY; |
| 338 | } |
| 339 | } |
| 340 | |
| 341 | /* Now enable the mux setting for each pin in the group */ |
| 342 | for (i = 0; i < grp->npins; i++) { |
| 343 | void __iomem *padcfg0; |
| 344 | u32 value; |
| 345 | |
| 346 | padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0); |
| 347 | value = readl(padcfg0); |
| 348 | |
| 349 | value &= ~PADCFG0_PMODE_MASK; |
| 350 | value |= grp->mode << PADCFG0_PMODE_SHIFT; |
| 351 | |
| 352 | writel(value, padcfg0); |
| 353 | } |
| 354 | |
| 355 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 356 | |
| 357 | return 0; |
| 358 | } |
| 359 | |
| 360 | static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, |
| 361 | struct pinctrl_gpio_range *range, |
| 362 | unsigned pin) |
| 363 | { |
| 364 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 365 | void __iomem *padcfg0; |
| 366 | unsigned long flags; |
| 367 | u32 value; |
| 368 | |
| 369 | spin_lock_irqsave(&pctrl->lock, flags); |
| 370 | |
| 371 | if (!intel_pad_usable(pctrl, pin)) { |
| 372 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 373 | return -EBUSY; |
| 374 | } |
| 375 | |
| 376 | padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); |
| 377 | /* Put the pad into GPIO mode */ |
| 378 | value = readl(padcfg0) & ~PADCFG0_PMODE_MASK; |
| 379 | /* Disable SCI/SMI/NMI generation */ |
| 380 | value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); |
| 381 | value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); |
| 382 | /* Disable TX buffer and enable RX (this will be input) */ |
| 383 | value &= ~PADCFG0_GPIORXDIS; |
| 384 | value |= PADCFG0_GPIOTXDIS; |
| 385 | writel(value, padcfg0); |
| 386 | |
| 387 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 388 | |
| 389 | return 0; |
| 390 | } |
| 391 | |
| 392 | static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, |
| 393 | struct pinctrl_gpio_range *range, |
| 394 | unsigned pin, bool input) |
| 395 | { |
| 396 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 397 | void __iomem *padcfg0; |
| 398 | unsigned long flags; |
| 399 | u32 value; |
| 400 | |
| 401 | spin_lock_irqsave(&pctrl->lock, flags); |
| 402 | |
| 403 | padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); |
| 404 | |
| 405 | value = readl(padcfg0); |
| 406 | if (input) |
| 407 | value |= PADCFG0_GPIOTXDIS; |
| 408 | else |
| 409 | value &= ~PADCFG0_GPIOTXDIS; |
| 410 | writel(value, padcfg0); |
| 411 | |
| 412 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 413 | |
| 414 | return 0; |
| 415 | } |
| 416 | |
| 417 | static const struct pinmux_ops intel_pinmux_ops = { |
| 418 | .get_functions_count = intel_get_functions_count, |
| 419 | .get_function_name = intel_get_function_name, |
| 420 | .get_function_groups = intel_get_function_groups, |
| 421 | .set_mux = intel_pinmux_set_mux, |
| 422 | .gpio_request_enable = intel_gpio_request_enable, |
| 423 | .gpio_set_direction = intel_gpio_set_direction, |
| 424 | }; |
| 425 | |
| 426 | static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin, |
| 427 | unsigned long *config) |
| 428 | { |
| 429 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 430 | enum pin_config_param param = pinconf_to_config_param(*config); |
| 431 | u32 value, term; |
| 432 | u16 arg = 0; |
| 433 | |
| 434 | if (!intel_pad_owned_by_host(pctrl, pin)) |
| 435 | return -ENOTSUPP; |
| 436 | |
| 437 | value = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); |
| 438 | term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; |
| 439 | |
| 440 | switch (param) { |
| 441 | case PIN_CONFIG_BIAS_DISABLE: |
| 442 | if (term) |
| 443 | return -EINVAL; |
| 444 | break; |
| 445 | |
| 446 | case PIN_CONFIG_BIAS_PULL_UP: |
| 447 | if (!term || !(value & PADCFG1_TERM_UP)) |
| 448 | return -EINVAL; |
| 449 | |
| 450 | switch (term) { |
| 451 | case PADCFG1_TERM_1K: |
| 452 | arg = 1000; |
| 453 | break; |
| 454 | case PADCFG1_TERM_2K: |
| 455 | arg = 2000; |
| 456 | break; |
| 457 | case PADCFG1_TERM_5K: |
| 458 | arg = 5000; |
| 459 | break; |
| 460 | case PADCFG1_TERM_20K: |
| 461 | arg = 20000; |
| 462 | break; |
| 463 | } |
| 464 | |
| 465 | break; |
| 466 | |
| 467 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 468 | if (!term || value & PADCFG1_TERM_UP) |
| 469 | return -EINVAL; |
| 470 | |
| 471 | switch (term) { |
| 472 | case PADCFG1_TERM_5K: |
| 473 | arg = 5000; |
| 474 | break; |
| 475 | case PADCFG1_TERM_20K: |
| 476 | arg = 20000; |
| 477 | break; |
| 478 | } |
| 479 | |
| 480 | break; |
| 481 | |
| 482 | default: |
| 483 | return -ENOTSUPP; |
| 484 | } |
| 485 | |
| 486 | *config = pinconf_to_config_packed(param, arg); |
| 487 | return 0; |
| 488 | } |
| 489 | |
| 490 | static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin, |
| 491 | unsigned long config) |
| 492 | { |
| 493 | unsigned param = pinconf_to_config_param(config); |
| 494 | unsigned arg = pinconf_to_config_argument(config); |
| 495 | void __iomem *padcfg1; |
| 496 | unsigned long flags; |
| 497 | int ret = 0; |
| 498 | u32 value; |
| 499 | |
| 500 | spin_lock_irqsave(&pctrl->lock, flags); |
| 501 | |
| 502 | padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); |
| 503 | value = readl(padcfg1); |
| 504 | |
| 505 | switch (param) { |
| 506 | case PIN_CONFIG_BIAS_DISABLE: |
| 507 | value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); |
| 508 | break; |
| 509 | |
| 510 | case PIN_CONFIG_BIAS_PULL_UP: |
| 511 | value &= ~PADCFG1_TERM_MASK; |
| 512 | |
| 513 | value |= PADCFG1_TERM_UP; |
| 514 | |
| 515 | switch (arg) { |
| 516 | case 20000: |
| 517 | value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; |
| 518 | break; |
| 519 | case 5000: |
| 520 | value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; |
| 521 | break; |
| 522 | case 2000: |
| 523 | value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT; |
| 524 | break; |
| 525 | case 1000: |
| 526 | value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; |
| 527 | break; |
| 528 | default: |
| 529 | ret = -EINVAL; |
| 530 | } |
| 531 | |
| 532 | break; |
| 533 | |
| 534 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 535 | value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK); |
| 536 | |
| 537 | switch (arg) { |
| 538 | case 20000: |
| 539 | value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; |
| 540 | break; |
| 541 | case 5000: |
| 542 | value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; |
| 543 | break; |
| 544 | default: |
| 545 | ret = -EINVAL; |
| 546 | } |
| 547 | |
| 548 | break; |
| 549 | } |
| 550 | |
| 551 | if (!ret) |
| 552 | writel(value, padcfg1); |
| 553 | |
| 554 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 555 | |
| 556 | return ret; |
| 557 | } |
| 558 | |
| 559 | static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin, |
| 560 | unsigned long *configs, unsigned nconfigs) |
| 561 | { |
| 562 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 563 | int i, ret; |
| 564 | |
| 565 | if (!intel_pad_usable(pctrl, pin)) |
| 566 | return -ENOTSUPP; |
| 567 | |
| 568 | for (i = 0; i < nconfigs; i++) { |
| 569 | switch (pinconf_to_config_param(configs[i])) { |
| 570 | case PIN_CONFIG_BIAS_DISABLE: |
| 571 | case PIN_CONFIG_BIAS_PULL_UP: |
| 572 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 573 | ret = intel_config_set_pull(pctrl, pin, configs[i]); |
| 574 | if (ret) |
| 575 | return ret; |
| 576 | break; |
| 577 | |
| 578 | default: |
| 579 | return -ENOTSUPP; |
| 580 | } |
| 581 | } |
| 582 | |
| 583 | return 0; |
| 584 | } |
| 585 | |
| 586 | static const struct pinconf_ops intel_pinconf_ops = { |
| 587 | .is_generic = true, |
| 588 | .pin_config_get = intel_config_get, |
| 589 | .pin_config_set = intel_config_set, |
| 590 | }; |
| 591 | |
| 592 | static const struct pinctrl_desc intel_pinctrl_desc = { |
| 593 | .pctlops = &intel_pinctrl_ops, |
| 594 | .pmxops = &intel_pinmux_ops, |
| 595 | .confops = &intel_pinconf_ops, |
| 596 | .owner = THIS_MODULE, |
| 597 | }; |
| 598 | |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 599 | static int intel_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 600 | { |
| 601 | struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(chip); |
| 602 | void __iomem *reg; |
| 603 | |
| 604 | reg = intel_get_padcfg(pctrl, offset, PADCFG0); |
| 605 | if (!reg) |
| 606 | return -EINVAL; |
| 607 | |
| 608 | return !!(readl(reg) & PADCFG0_GPIORXSTATE); |
| 609 | } |
| 610 | |
| 611 | static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 612 | { |
| 613 | struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(chip); |
| 614 | void __iomem *reg; |
| 615 | |
| 616 | reg = intel_get_padcfg(pctrl, offset, PADCFG0); |
| 617 | if (reg) { |
| 618 | unsigned long flags; |
| 619 | u32 padcfg0; |
| 620 | |
| 621 | spin_lock_irqsave(&pctrl->lock, flags); |
| 622 | padcfg0 = readl(reg); |
| 623 | if (value) |
| 624 | padcfg0 |= PADCFG0_GPIOTXSTATE; |
| 625 | else |
| 626 | padcfg0 &= ~PADCFG0_GPIOTXSTATE; |
| 627 | writel(padcfg0, reg); |
| 628 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 629 | } |
| 630 | } |
| 631 | |
| 632 | static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
| 633 | { |
| 634 | return pinctrl_gpio_direction_input(chip->base + offset); |
| 635 | } |
| 636 | |
| 637 | static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, |
| 638 | int value) |
| 639 | { |
| 640 | intel_gpio_set(chip, offset, value); |
| 641 | return pinctrl_gpio_direction_output(chip->base + offset); |
| 642 | } |
| 643 | |
| 644 | static const struct gpio_chip intel_gpio_chip = { |
| 645 | .owner = THIS_MODULE, |
Jonas Gorski | 98c85d5 | 2015-10-11 17:34:19 +0200 | [diff] [blame] | 646 | .request = gpiochip_generic_request, |
| 647 | .free = gpiochip_generic_free, |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 648 | .direction_input = intel_gpio_direction_input, |
| 649 | .direction_output = intel_gpio_direction_output, |
| 650 | .get = intel_gpio_get, |
| 651 | .set = intel_gpio_set, |
| 652 | }; |
| 653 | |
| 654 | static void intel_gpio_irq_ack(struct irq_data *d) |
| 655 | { |
| 656 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
| 657 | struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc); |
| 658 | const struct intel_community *community; |
| 659 | unsigned pin = irqd_to_hwirq(d); |
| 660 | |
| 661 | spin_lock(&pctrl->lock); |
| 662 | |
| 663 | community = intel_get_community(pctrl, pin); |
| 664 | if (community) { |
| 665 | unsigned padno = pin_to_padno(community, pin); |
| 666 | unsigned gpp_offset = padno % NPADS_IN_GPP; |
| 667 | unsigned gpp = padno / NPADS_IN_GPP; |
| 668 | |
| 669 | writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); |
| 670 | } |
| 671 | |
| 672 | spin_unlock(&pctrl->lock); |
| 673 | } |
| 674 | |
| 675 | static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) |
| 676 | { |
| 677 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
| 678 | struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc); |
| 679 | const struct intel_community *community; |
| 680 | unsigned pin = irqd_to_hwirq(d); |
| 681 | unsigned long flags; |
| 682 | |
| 683 | spin_lock_irqsave(&pctrl->lock, flags); |
| 684 | |
| 685 | community = intel_get_community(pctrl, pin); |
| 686 | if (community) { |
| 687 | unsigned padno = pin_to_padno(community, pin); |
| 688 | unsigned gpp_offset = padno % NPADS_IN_GPP; |
| 689 | unsigned gpp = padno / NPADS_IN_GPP; |
| 690 | void __iomem *reg; |
| 691 | u32 value; |
| 692 | |
| 693 | reg = community->regs + community->ie_offset + gpp * 4; |
| 694 | value = readl(reg); |
| 695 | if (mask) |
| 696 | value &= ~BIT(gpp_offset); |
| 697 | else |
| 698 | value |= BIT(gpp_offset); |
| 699 | writel(value, reg); |
| 700 | } |
| 701 | |
| 702 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 703 | } |
| 704 | |
| 705 | static void intel_gpio_irq_mask(struct irq_data *d) |
| 706 | { |
| 707 | intel_gpio_irq_mask_unmask(d, true); |
| 708 | } |
| 709 | |
| 710 | static void intel_gpio_irq_unmask(struct irq_data *d) |
| 711 | { |
| 712 | intel_gpio_irq_mask_unmask(d, false); |
| 713 | } |
| 714 | |
| 715 | static int intel_gpio_irq_type(struct irq_data *d, unsigned type) |
| 716 | { |
| 717 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
| 718 | struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc); |
| 719 | unsigned pin = irqd_to_hwirq(d); |
| 720 | unsigned long flags; |
| 721 | void __iomem *reg; |
| 722 | u32 value; |
| 723 | |
| 724 | reg = intel_get_padcfg(pctrl, pin, PADCFG0); |
| 725 | if (!reg) |
| 726 | return -EINVAL; |
| 727 | |
Mika Westerberg | 4341e8a | 2015-10-21 13:08:44 +0300 | [diff] [blame] | 728 | /* |
| 729 | * If the pin is in ACPI mode it is still usable as a GPIO but it |
| 730 | * cannot be used as IRQ because GPI_IS status bit will not be |
| 731 | * updated by the host controller hardware. |
| 732 | */ |
| 733 | if (intel_pad_acpi_mode(pctrl, pin)) { |
| 734 | dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); |
| 735 | return -EPERM; |
| 736 | } |
| 737 | |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 738 | spin_lock_irqsave(&pctrl->lock, flags); |
| 739 | |
| 740 | value = readl(reg); |
| 741 | |
| 742 | value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); |
| 743 | |
| 744 | if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { |
| 745 | value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; |
| 746 | } else if (type & IRQ_TYPE_EDGE_FALLING) { |
| 747 | value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; |
| 748 | value |= PADCFG0_RXINV; |
| 749 | } else if (type & IRQ_TYPE_EDGE_RISING) { |
| 750 | value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; |
| 751 | } else if (type & IRQ_TYPE_LEVEL_LOW) { |
| 752 | value |= PADCFG0_RXINV; |
| 753 | } else { |
| 754 | value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; |
| 755 | } |
| 756 | |
| 757 | writel(value, reg); |
| 758 | |
| 759 | if (type & IRQ_TYPE_EDGE_BOTH) |
Thomas Gleixner | fc756bc | 2015-06-23 15:52:45 +0200 | [diff] [blame] | 760 | irq_set_handler_locked(d, handle_edge_irq); |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 761 | else if (type & IRQ_TYPE_LEVEL_MASK) |
Thomas Gleixner | fc756bc | 2015-06-23 15:52:45 +0200 | [diff] [blame] | 762 | irq_set_handler_locked(d, handle_level_irq); |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 763 | |
| 764 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 765 | |
| 766 | return 0; |
| 767 | } |
| 768 | |
| 769 | static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) |
| 770 | { |
| 771 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
| 772 | struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc); |
| 773 | const struct intel_community *community; |
| 774 | unsigned pin = irqd_to_hwirq(d); |
| 775 | unsigned padno, gpp, gpp_offset; |
| 776 | u32 gpe_en; |
| 777 | |
| 778 | community = intel_get_community(pctrl, pin); |
| 779 | if (!community) |
| 780 | return -EINVAL; |
| 781 | |
| 782 | padno = pin_to_padno(community, pin); |
| 783 | gpp = padno / NPADS_IN_GPP; |
| 784 | gpp_offset = padno % NPADS_IN_GPP; |
| 785 | |
| 786 | /* Clear the existing wake status */ |
| 787 | writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4); |
| 788 | |
| 789 | /* |
| 790 | * The controller will generate wake when GPE of the corresponding |
| 791 | * pad is enabled and it is not routed to SCI (GPIROUTSCI is not |
| 792 | * set). |
| 793 | */ |
| 794 | gpe_en = readl(community->regs + GPI_GPE_EN + gpp * 4); |
| 795 | if (on) |
| 796 | gpe_en |= BIT(gpp_offset); |
| 797 | else |
| 798 | gpe_en &= ~BIT(gpp_offset); |
| 799 | writel(gpe_en, community->regs + GPI_GPE_EN + gpp * 4); |
| 800 | |
| 801 | dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); |
| 802 | return 0; |
| 803 | } |
| 804 | |
Mika Westerberg | 193b40c | 2015-10-21 13:08:43 +0300 | [diff] [blame] | 805 | static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 806 | const struct intel_community *community) |
| 807 | { |
Mika Westerberg | 193b40c | 2015-10-21 13:08:43 +0300 | [diff] [blame] | 808 | struct gpio_chip *gc = &pctrl->chip; |
| 809 | irqreturn_t ret = IRQ_NONE; |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 810 | int gpp; |
| 811 | |
| 812 | for (gpp = 0; gpp < community->ngpps; gpp++) { |
| 813 | unsigned long pending, enabled, gpp_offset; |
| 814 | |
| 815 | pending = readl(community->regs + GPI_IS + gpp * 4); |
| 816 | enabled = readl(community->regs + community->ie_offset + |
| 817 | gpp * 4); |
| 818 | |
| 819 | /* Only interrupts that are enabled */ |
| 820 | pending &= enabled; |
| 821 | |
| 822 | for_each_set_bit(gpp_offset, &pending, NPADS_IN_GPP) { |
| 823 | unsigned padno, irq; |
| 824 | |
| 825 | /* |
| 826 | * The last group in community can have less pins |
| 827 | * than NPADS_IN_GPP. |
| 828 | */ |
| 829 | padno = gpp_offset + gpp * NPADS_IN_GPP; |
| 830 | if (padno >= community->npins) |
| 831 | break; |
| 832 | |
| 833 | irq = irq_find_mapping(gc->irqdomain, |
| 834 | community->pin_base + padno); |
| 835 | generic_handle_irq(irq); |
Mika Westerberg | 193b40c | 2015-10-21 13:08:43 +0300 | [diff] [blame] | 836 | |
| 837 | ret |= IRQ_HANDLED; |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 838 | } |
| 839 | } |
Mika Westerberg | 193b40c | 2015-10-21 13:08:43 +0300 | [diff] [blame] | 840 | |
| 841 | return ret; |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 842 | } |
| 843 | |
Mika Westerberg | 193b40c | 2015-10-21 13:08:43 +0300 | [diff] [blame] | 844 | static irqreturn_t intel_gpio_irq(int irq, void *data) |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 845 | { |
Mika Westerberg | 193b40c | 2015-10-21 13:08:43 +0300 | [diff] [blame] | 846 | const struct intel_community *community; |
| 847 | struct intel_pinctrl *pctrl = data; |
| 848 | irqreturn_t ret = IRQ_NONE; |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 849 | int i; |
| 850 | |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 851 | /* Need to check all communities for pending interrupts */ |
Mika Westerberg | 193b40c | 2015-10-21 13:08:43 +0300 | [diff] [blame] | 852 | for (i = 0; i < pctrl->ncommunities; i++) { |
| 853 | community = &pctrl->communities[i]; |
| 854 | ret |= intel_gpio_community_irq_handler(pctrl, community); |
| 855 | } |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 856 | |
Mika Westerberg | 193b40c | 2015-10-21 13:08:43 +0300 | [diff] [blame] | 857 | return ret; |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 858 | } |
| 859 | |
| 860 | static struct irq_chip intel_gpio_irqchip = { |
| 861 | .name = "intel-gpio", |
| 862 | .irq_ack = intel_gpio_irq_ack, |
| 863 | .irq_mask = intel_gpio_irq_mask, |
| 864 | .irq_unmask = intel_gpio_irq_unmask, |
| 865 | .irq_set_type = intel_gpio_irq_type, |
| 866 | .irq_set_wake = intel_gpio_irq_wake, |
| 867 | }; |
| 868 | |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 869 | static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) |
| 870 | { |
| 871 | int ret; |
| 872 | |
| 873 | pctrl->chip = intel_gpio_chip; |
| 874 | |
| 875 | pctrl->chip.ngpio = pctrl->soc->npins; |
| 876 | pctrl->chip.label = dev_name(pctrl->dev); |
Linus Walleij | 58383c7 | 2015-11-04 09:56:26 +0100 | [diff] [blame^] | 877 | pctrl->chip.parent = pctrl->dev; |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 878 | pctrl->chip.base = -1; |
| 879 | |
| 880 | ret = gpiochip_add(&pctrl->chip); |
| 881 | if (ret) { |
| 882 | dev_err(pctrl->dev, "failed to register gpiochip\n"); |
| 883 | return ret; |
| 884 | } |
| 885 | |
| 886 | ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), |
| 887 | 0, 0, pctrl->soc->npins); |
| 888 | if (ret) { |
| 889 | dev_err(pctrl->dev, "failed to add GPIO pin range\n"); |
Mika Westerberg | 193b40c | 2015-10-21 13:08:43 +0300 | [diff] [blame] | 890 | goto fail; |
| 891 | } |
| 892 | |
| 893 | /* |
| 894 | * We need to request the interrupt here (instead of providing chip |
| 895 | * to the irq directly) because on some platforms several GPIO |
| 896 | * controllers share the same interrupt line. |
| 897 | */ |
| 898 | ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, IRQF_SHARED, |
| 899 | dev_name(pctrl->dev), pctrl); |
| 900 | if (ret) { |
| 901 | dev_err(pctrl->dev, "failed to request interrupt\n"); |
| 902 | goto fail; |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 903 | } |
| 904 | |
| 905 | ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0, |
| 906 | handle_simple_irq, IRQ_TYPE_NONE); |
| 907 | if (ret) { |
| 908 | dev_err(pctrl->dev, "failed to add irqchip\n"); |
Mika Westerberg | 193b40c | 2015-10-21 13:08:43 +0300 | [diff] [blame] | 909 | goto fail; |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 910 | } |
| 911 | |
| 912 | gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq, |
Mika Westerberg | 193b40c | 2015-10-21 13:08:43 +0300 | [diff] [blame] | 913 | NULL); |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 914 | return 0; |
Mika Westerberg | 193b40c | 2015-10-21 13:08:43 +0300 | [diff] [blame] | 915 | |
| 916 | fail: |
| 917 | gpiochip_remove(&pctrl->chip); |
| 918 | |
| 919 | return ret; |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 920 | } |
| 921 | |
| 922 | static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) |
| 923 | { |
| 924 | #ifdef CONFIG_PM_SLEEP |
| 925 | const struct intel_pinctrl_soc_data *soc = pctrl->soc; |
| 926 | struct intel_community_context *communities; |
| 927 | struct intel_pad_context *pads; |
| 928 | int i; |
| 929 | |
| 930 | pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); |
| 931 | if (!pads) |
| 932 | return -ENOMEM; |
| 933 | |
| 934 | communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, |
| 935 | sizeof(*communities), GFP_KERNEL); |
| 936 | if (!communities) |
| 937 | return -ENOMEM; |
| 938 | |
| 939 | |
| 940 | for (i = 0; i < pctrl->ncommunities; i++) { |
| 941 | struct intel_community *community = &pctrl->communities[i]; |
| 942 | u32 *intmask; |
| 943 | |
| 944 | intmask = devm_kcalloc(pctrl->dev, community->ngpps, |
| 945 | sizeof(*intmask), GFP_KERNEL); |
| 946 | if (!intmask) |
| 947 | return -ENOMEM; |
| 948 | |
| 949 | communities[i].intmask = intmask; |
| 950 | } |
| 951 | |
| 952 | pctrl->context.pads = pads; |
| 953 | pctrl->context.communities = communities; |
| 954 | #endif |
| 955 | |
| 956 | return 0; |
| 957 | } |
| 958 | |
| 959 | int intel_pinctrl_probe(struct platform_device *pdev, |
| 960 | const struct intel_pinctrl_soc_data *soc_data) |
| 961 | { |
| 962 | struct intel_pinctrl *pctrl; |
| 963 | int i, ret, irq; |
| 964 | |
| 965 | if (!soc_data) |
| 966 | return -EINVAL; |
| 967 | |
| 968 | pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); |
| 969 | if (!pctrl) |
| 970 | return -ENOMEM; |
| 971 | |
| 972 | pctrl->dev = &pdev->dev; |
| 973 | pctrl->soc = soc_data; |
| 974 | spin_lock_init(&pctrl->lock); |
| 975 | |
| 976 | /* |
| 977 | * Make a copy of the communities which we can use to hold pointers |
| 978 | * to the registers. |
| 979 | */ |
| 980 | pctrl->ncommunities = pctrl->soc->ncommunities; |
| 981 | pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities, |
| 982 | sizeof(*pctrl->communities), GFP_KERNEL); |
| 983 | if (!pctrl->communities) |
| 984 | return -ENOMEM; |
| 985 | |
| 986 | for (i = 0; i < pctrl->ncommunities; i++) { |
| 987 | struct intel_community *community = &pctrl->communities[i]; |
| 988 | struct resource *res; |
| 989 | void __iomem *regs; |
| 990 | u32 padbar; |
| 991 | |
| 992 | *community = pctrl->soc->communities[i]; |
| 993 | |
| 994 | res = platform_get_resource(pdev, IORESOURCE_MEM, |
| 995 | community->barno); |
| 996 | regs = devm_ioremap_resource(&pdev->dev, res); |
| 997 | if (IS_ERR(regs)) |
| 998 | return PTR_ERR(regs); |
| 999 | |
| 1000 | /* Read offset of the pad configuration registers */ |
| 1001 | padbar = readl(regs + PADBAR); |
| 1002 | |
| 1003 | community->regs = regs; |
| 1004 | community->pad_regs = regs + padbar; |
| 1005 | community->ngpps = DIV_ROUND_UP(community->npins, NPADS_IN_GPP); |
| 1006 | } |
| 1007 | |
| 1008 | irq = platform_get_irq(pdev, 0); |
| 1009 | if (irq < 0) { |
| 1010 | dev_err(&pdev->dev, "failed to get interrupt number\n"); |
| 1011 | return irq; |
| 1012 | } |
| 1013 | |
| 1014 | ret = intel_pinctrl_pm_init(pctrl); |
| 1015 | if (ret) |
| 1016 | return ret; |
| 1017 | |
| 1018 | pctrl->pctldesc = intel_pinctrl_desc; |
| 1019 | pctrl->pctldesc.name = dev_name(&pdev->dev); |
| 1020 | pctrl->pctldesc.pins = pctrl->soc->pins; |
| 1021 | pctrl->pctldesc.npins = pctrl->soc->npins; |
| 1022 | |
| 1023 | pctrl->pctldev = pinctrl_register(&pctrl->pctldesc, &pdev->dev, pctrl); |
Masahiro Yamada | 323de9e | 2015-06-09 13:01:16 +0900 | [diff] [blame] | 1024 | if (IS_ERR(pctrl->pctldev)) { |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 1025 | dev_err(&pdev->dev, "failed to register pinctrl driver\n"); |
Masahiro Yamada | 323de9e | 2015-06-09 13:01:16 +0900 | [diff] [blame] | 1026 | return PTR_ERR(pctrl->pctldev); |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 1027 | } |
| 1028 | |
| 1029 | ret = intel_gpio_probe(pctrl, irq); |
| 1030 | if (ret) { |
| 1031 | pinctrl_unregister(pctrl->pctldev); |
| 1032 | return ret; |
| 1033 | } |
| 1034 | |
| 1035 | platform_set_drvdata(pdev, pctrl); |
| 1036 | |
| 1037 | return 0; |
| 1038 | } |
| 1039 | EXPORT_SYMBOL_GPL(intel_pinctrl_probe); |
| 1040 | |
| 1041 | int intel_pinctrl_remove(struct platform_device *pdev) |
| 1042 | { |
| 1043 | struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); |
| 1044 | |
| 1045 | gpiochip_remove(&pctrl->chip); |
| 1046 | pinctrl_unregister(pctrl->pctldev); |
| 1047 | |
| 1048 | return 0; |
| 1049 | } |
| 1050 | EXPORT_SYMBOL_GPL(intel_pinctrl_remove); |
| 1051 | |
| 1052 | #ifdef CONFIG_PM_SLEEP |
| 1053 | int intel_pinctrl_suspend(struct device *dev) |
| 1054 | { |
| 1055 | struct platform_device *pdev = to_platform_device(dev); |
| 1056 | struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); |
| 1057 | struct intel_community_context *communities; |
| 1058 | struct intel_pad_context *pads; |
| 1059 | int i; |
| 1060 | |
| 1061 | pads = pctrl->context.pads; |
| 1062 | for (i = 0; i < pctrl->soc->npins; i++) { |
| 1063 | const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; |
| 1064 | u32 val; |
| 1065 | |
| 1066 | if (!intel_pad_usable(pctrl, desc->number)) |
| 1067 | continue; |
| 1068 | |
| 1069 | val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); |
| 1070 | pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; |
| 1071 | val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); |
| 1072 | pads[i].padcfg1 = val; |
| 1073 | } |
| 1074 | |
| 1075 | communities = pctrl->context.communities; |
| 1076 | for (i = 0; i < pctrl->ncommunities; i++) { |
| 1077 | struct intel_community *community = &pctrl->communities[i]; |
| 1078 | void __iomem *base; |
| 1079 | unsigned gpp; |
| 1080 | |
| 1081 | base = community->regs + community->ie_offset; |
| 1082 | for (gpp = 0; gpp < community->ngpps; gpp++) |
| 1083 | communities[i].intmask[gpp] = readl(base + gpp * 4); |
| 1084 | } |
| 1085 | |
| 1086 | return 0; |
| 1087 | } |
| 1088 | EXPORT_SYMBOL_GPL(intel_pinctrl_suspend); |
| 1089 | |
Mika Westerberg | f487bbf | 2015-10-13 17:51:25 +0300 | [diff] [blame] | 1090 | static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) |
| 1091 | { |
| 1092 | size_t i; |
| 1093 | |
| 1094 | for (i = 0; i < pctrl->ncommunities; i++) { |
| 1095 | const struct intel_community *community; |
| 1096 | void __iomem *base; |
| 1097 | unsigned gpp; |
| 1098 | |
| 1099 | community = &pctrl->communities[i]; |
| 1100 | base = community->regs; |
| 1101 | |
| 1102 | for (gpp = 0; gpp < community->ngpps; gpp++) { |
| 1103 | /* Mask and clear all interrupts */ |
| 1104 | writel(0, base + community->ie_offset + gpp * 4); |
| 1105 | writel(0xffff, base + GPI_IS + gpp * 4); |
| 1106 | } |
| 1107 | } |
| 1108 | } |
| 1109 | |
Mika Westerberg | 7981c001 | 2015-03-30 17:31:49 +0300 | [diff] [blame] | 1110 | int intel_pinctrl_resume(struct device *dev) |
| 1111 | { |
| 1112 | struct platform_device *pdev = to_platform_device(dev); |
| 1113 | struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); |
| 1114 | const struct intel_community_context *communities; |
| 1115 | const struct intel_pad_context *pads; |
| 1116 | int i; |
| 1117 | |
| 1118 | /* Mask all interrupts */ |
| 1119 | intel_gpio_irq_init(pctrl); |
| 1120 | |
| 1121 | pads = pctrl->context.pads; |
| 1122 | for (i = 0; i < pctrl->soc->npins; i++) { |
| 1123 | const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; |
| 1124 | void __iomem *padcfg; |
| 1125 | u32 val; |
| 1126 | |
| 1127 | if (!intel_pad_usable(pctrl, desc->number)) |
| 1128 | continue; |
| 1129 | |
| 1130 | padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0); |
| 1131 | val = readl(padcfg) & ~PADCFG0_GPIORXSTATE; |
| 1132 | if (val != pads[i].padcfg0) { |
| 1133 | writel(pads[i].padcfg0, padcfg); |
| 1134 | dev_dbg(dev, "restored pin %u padcfg0 %#08x\n", |
| 1135 | desc->number, readl(padcfg)); |
| 1136 | } |
| 1137 | |
| 1138 | padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1); |
| 1139 | val = readl(padcfg); |
| 1140 | if (val != pads[i].padcfg1) { |
| 1141 | writel(pads[i].padcfg1, padcfg); |
| 1142 | dev_dbg(dev, "restored pin %u padcfg1 %#08x\n", |
| 1143 | desc->number, readl(padcfg)); |
| 1144 | } |
| 1145 | } |
| 1146 | |
| 1147 | communities = pctrl->context.communities; |
| 1148 | for (i = 0; i < pctrl->ncommunities; i++) { |
| 1149 | struct intel_community *community = &pctrl->communities[i]; |
| 1150 | void __iomem *base; |
| 1151 | unsigned gpp; |
| 1152 | |
| 1153 | base = community->regs + community->ie_offset; |
| 1154 | for (gpp = 0; gpp < community->ngpps; gpp++) { |
| 1155 | writel(communities[i].intmask[gpp], base + gpp * 4); |
| 1156 | dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp, |
| 1157 | readl(base + gpp * 4)); |
| 1158 | } |
| 1159 | } |
| 1160 | |
| 1161 | return 0; |
| 1162 | } |
| 1163 | EXPORT_SYMBOL_GPL(intel_pinctrl_resume); |
| 1164 | #endif |
| 1165 | |
| 1166 | MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); |
| 1167 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); |
| 1168 | MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); |
| 1169 | MODULE_LICENSE("GPL v2"); |