blob: be7fada590d497311b812fb6b25c5735b0f7ae26 [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Jesse Barnesc1c7af62009-09-10 15:28:03 -070027#include <linux/module.h>
28#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080029#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080030#include <linux/kernel.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080031#include "drmP.h"
32#include "intel_drv.h"
33#include "i915_drm.h"
34#include "i915_drv.h"
Keith Packarda4fc5ed2009-04-07 16:16:42 -070035#include "intel_dp.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080036
37#include "drm_crtc_helper.h"
38
Zhenyu Wang32f9d652009-07-24 01:00:32 +080039#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
40
Jesse Barnes79e53942008-11-07 14:24:08 -080041bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
Shaohua Li7662c8b2009-06-26 11:23:55 +080042static void intel_update_watermarks(struct drm_device *dev);
Jesse Barnes652c3932009-08-17 13:31:43 -070043static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
Jesse Barnes79e53942008-11-07 14:24:08 -080044
45typedef struct {
46 /* given values */
47 int n;
48 int m1, m2;
49 int p1, p2;
50 /* derived values */
51 int dot;
52 int vco;
53 int m;
54 int p;
55} intel_clock_t;
56
57typedef struct {
58 int min, max;
59} intel_range_t;
60
61typedef struct {
62 int dot_limit;
63 int p2_slow, p2_fast;
64} intel_p2_t;
65
66#define INTEL_P2_NUM 2
Ma Lingd4906092009-03-18 20:13:27 +080067typedef struct intel_limit intel_limit_t;
68struct intel_limit {
Jesse Barnes79e53942008-11-07 14:24:08 -080069 intel_range_t dot, vco, n, m, m1, m2, p, p1;
70 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +080071 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
72 int, int, intel_clock_t *);
Jesse Barnes652c3932009-08-17 13:31:43 -070073 bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
74 int, int, intel_clock_t *);
Ma Lingd4906092009-03-18 20:13:27 +080075};
Jesse Barnes79e53942008-11-07 14:24:08 -080076
77#define I8XX_DOT_MIN 25000
78#define I8XX_DOT_MAX 350000
79#define I8XX_VCO_MIN 930000
80#define I8XX_VCO_MAX 1400000
81#define I8XX_N_MIN 3
82#define I8XX_N_MAX 16
83#define I8XX_M_MIN 96
84#define I8XX_M_MAX 140
85#define I8XX_M1_MIN 18
86#define I8XX_M1_MAX 26
87#define I8XX_M2_MIN 6
88#define I8XX_M2_MAX 16
89#define I8XX_P_MIN 4
90#define I8XX_P_MAX 128
91#define I8XX_P1_MIN 2
92#define I8XX_P1_MAX 33
93#define I8XX_P1_LVDS_MIN 1
94#define I8XX_P1_LVDS_MAX 6
95#define I8XX_P2_SLOW 4
96#define I8XX_P2_FAST 2
97#define I8XX_P2_LVDS_SLOW 14
ling.ma@intel.com0c2e3952009-07-17 11:44:30 +080098#define I8XX_P2_LVDS_FAST 7
Jesse Barnes79e53942008-11-07 14:24:08 -080099#define I8XX_P2_SLOW_LIMIT 165000
100
101#define I9XX_DOT_MIN 20000
102#define I9XX_DOT_MAX 400000
103#define I9XX_VCO_MIN 1400000
104#define I9XX_VCO_MAX 2800000
Shaohua Li21778322009-02-23 15:19:16 +0800105#define IGD_VCO_MIN 1700000
106#define IGD_VCO_MAX 3500000
Kristian Høgsbergf3cade52009-02-13 20:56:50 -0500107#define I9XX_N_MIN 1
108#define I9XX_N_MAX 6
Shaohua Li21778322009-02-23 15:19:16 +0800109/* IGD's Ncounter is a ring counter */
110#define IGD_N_MIN 3
111#define IGD_N_MAX 6
Jesse Barnes79e53942008-11-07 14:24:08 -0800112#define I9XX_M_MIN 70
113#define I9XX_M_MAX 120
Shaohua Li21778322009-02-23 15:19:16 +0800114#define IGD_M_MIN 2
115#define IGD_M_MAX 256
Jesse Barnes79e53942008-11-07 14:24:08 -0800116#define I9XX_M1_MIN 10
Kristian Høgsbergf3cade52009-02-13 20:56:50 -0500117#define I9XX_M1_MAX 22
Jesse Barnes79e53942008-11-07 14:24:08 -0800118#define I9XX_M2_MIN 5
119#define I9XX_M2_MAX 9
Shaohua Li21778322009-02-23 15:19:16 +0800120/* IGD M1 is reserved, and must be 0 */
121#define IGD_M1_MIN 0
122#define IGD_M1_MAX 0
123#define IGD_M2_MIN 0
124#define IGD_M2_MAX 254
Jesse Barnes79e53942008-11-07 14:24:08 -0800125#define I9XX_P_SDVO_DAC_MIN 5
126#define I9XX_P_SDVO_DAC_MAX 80
127#define I9XX_P_LVDS_MIN 7
128#define I9XX_P_LVDS_MAX 98
Shaohua Li21778322009-02-23 15:19:16 +0800129#define IGD_P_LVDS_MIN 7
130#define IGD_P_LVDS_MAX 112
Jesse Barnes79e53942008-11-07 14:24:08 -0800131#define I9XX_P1_MIN 1
132#define I9XX_P1_MAX 8
133#define I9XX_P2_SDVO_DAC_SLOW 10
134#define I9XX_P2_SDVO_DAC_FAST 5
135#define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
136#define I9XX_P2_LVDS_SLOW 14
137#define I9XX_P2_LVDS_FAST 7
138#define I9XX_P2_LVDS_SLOW_LIMIT 112000
139
Ma Ling044c7c42009-03-18 20:13:23 +0800140/*The parameter is for SDVO on G4x platform*/
141#define G4X_DOT_SDVO_MIN 25000
142#define G4X_DOT_SDVO_MAX 270000
143#define G4X_VCO_MIN 1750000
144#define G4X_VCO_MAX 3500000
145#define G4X_N_SDVO_MIN 1
146#define G4X_N_SDVO_MAX 4
147#define G4X_M_SDVO_MIN 104
148#define G4X_M_SDVO_MAX 138
149#define G4X_M1_SDVO_MIN 17
150#define G4X_M1_SDVO_MAX 23
151#define G4X_M2_SDVO_MIN 5
152#define G4X_M2_SDVO_MAX 11
153#define G4X_P_SDVO_MIN 10
154#define G4X_P_SDVO_MAX 30
155#define G4X_P1_SDVO_MIN 1
156#define G4X_P1_SDVO_MAX 3
157#define G4X_P2_SDVO_SLOW 10
158#define G4X_P2_SDVO_FAST 10
159#define G4X_P2_SDVO_LIMIT 270000
160
161/*The parameter is for HDMI_DAC on G4x platform*/
162#define G4X_DOT_HDMI_DAC_MIN 22000
163#define G4X_DOT_HDMI_DAC_MAX 400000
164#define G4X_N_HDMI_DAC_MIN 1
165#define G4X_N_HDMI_DAC_MAX 4
166#define G4X_M_HDMI_DAC_MIN 104
167#define G4X_M_HDMI_DAC_MAX 138
168#define G4X_M1_HDMI_DAC_MIN 16
169#define G4X_M1_HDMI_DAC_MAX 23
170#define G4X_M2_HDMI_DAC_MIN 5
171#define G4X_M2_HDMI_DAC_MAX 11
172#define G4X_P_HDMI_DAC_MIN 5
173#define G4X_P_HDMI_DAC_MAX 80
174#define G4X_P1_HDMI_DAC_MIN 1
175#define G4X_P1_HDMI_DAC_MAX 8
176#define G4X_P2_HDMI_DAC_SLOW 10
177#define G4X_P2_HDMI_DAC_FAST 5
178#define G4X_P2_HDMI_DAC_LIMIT 165000
179
180/*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
181#define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
182#define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
183#define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
184#define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
185#define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
186#define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
187#define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
188#define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
189#define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
190#define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
191#define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
192#define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
193#define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
194#define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
195#define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
196#define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
197#define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
198
199/*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
200#define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
201#define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
202#define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
203#define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
204#define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
205#define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
206#define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
207#define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
208#define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
209#define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
210#define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
211#define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
212#define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
213#define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
214#define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
215#define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
216#define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
217
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700218/*The parameter is for DISPLAY PORT on G4x platform*/
219#define G4X_DOT_DISPLAY_PORT_MIN 161670
220#define G4X_DOT_DISPLAY_PORT_MAX 227000
221#define G4X_N_DISPLAY_PORT_MIN 1
222#define G4X_N_DISPLAY_PORT_MAX 2
223#define G4X_M_DISPLAY_PORT_MIN 97
224#define G4X_M_DISPLAY_PORT_MAX 108
225#define G4X_M1_DISPLAY_PORT_MIN 0x10
226#define G4X_M1_DISPLAY_PORT_MAX 0x12
227#define G4X_M2_DISPLAY_PORT_MIN 0x05
228#define G4X_M2_DISPLAY_PORT_MAX 0x06
229#define G4X_P_DISPLAY_PORT_MIN 10
230#define G4X_P_DISPLAY_PORT_MAX 20
231#define G4X_P1_DISPLAY_PORT_MIN 1
232#define G4X_P1_DISPLAY_PORT_MAX 2
233#define G4X_P2_DISPLAY_PORT_SLOW 10
234#define G4X_P2_DISPLAY_PORT_FAST 10
235#define G4X_P2_DISPLAY_PORT_LIMIT 0
236
Zhenyu Wang2c072452009-06-05 15:38:42 +0800237/* IGDNG */
238/* as we calculate clock using (register_value + 2) for
239 N/M1/M2, so here the range value for them is (actual_value-2).
240 */
241#define IGDNG_DOT_MIN 25000
242#define IGDNG_DOT_MAX 350000
243#define IGDNG_VCO_MIN 1760000
244#define IGDNG_VCO_MAX 3510000
245#define IGDNG_N_MIN 1
246#define IGDNG_N_MAX 5
247#define IGDNG_M_MIN 79
248#define IGDNG_M_MAX 118
249#define IGDNG_M1_MIN 12
250#define IGDNG_M1_MAX 23
251#define IGDNG_M2_MIN 5
252#define IGDNG_M2_MAX 9
253#define IGDNG_P_SDVO_DAC_MIN 5
254#define IGDNG_P_SDVO_DAC_MAX 80
255#define IGDNG_P_LVDS_MIN 28
256#define IGDNG_P_LVDS_MAX 112
257#define IGDNG_P1_MIN 1
258#define IGDNG_P1_MAX 8
259#define IGDNG_P2_SDVO_DAC_SLOW 10
260#define IGDNG_P2_SDVO_DAC_FAST 5
261#define IGDNG_P2_LVDS_SLOW 14 /* single channel */
262#define IGDNG_P2_LVDS_FAST 7 /* double channel */
263#define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */
264
Ma Lingd4906092009-03-18 20:13:27 +0800265static bool
266intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
267 int target, int refclk, intel_clock_t *best_clock);
268static bool
Jesse Barnes652c3932009-08-17 13:31:43 -0700269intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
270 int target, int refclk, intel_clock_t *best_clock);
271static bool
Ma Lingd4906092009-03-18 20:13:27 +0800272intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
273 int target, int refclk, intel_clock_t *best_clock);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800274static bool
275intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
276 int target, int refclk, intel_clock_t *best_clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800277
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700278static bool
279intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
280 int target, int refclk, intel_clock_t *best_clock);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800281static bool
282intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
283 int target, int refclk, intel_clock_t *best_clock);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700284
Keith Packarde4b36692009-06-05 19:22:17 -0700285static const intel_limit_t intel_limits_i8xx_dvo = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800286 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
287 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
288 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
289 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
290 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
291 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
292 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
293 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
294 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
295 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800296 .find_pll = intel_find_best_PLL,
Jesse Barnes652c3932009-08-17 13:31:43 -0700297 .find_reduced_pll = intel_find_best_reduced_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700298};
299
300static const intel_limit_t intel_limits_i8xx_lvds = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800301 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
302 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
303 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
304 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
305 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
306 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
307 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
308 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
309 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
310 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800311 .find_pll = intel_find_best_PLL,
Jesse Barnes652c3932009-08-17 13:31:43 -0700312 .find_reduced_pll = intel_find_best_reduced_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700313};
314
315static const intel_limit_t intel_limits_i9xx_sdvo = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800316 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
317 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
318 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
319 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
320 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
321 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
322 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
323 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
324 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
325 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800326 .find_pll = intel_find_best_PLL,
Jesse Barnes652c3932009-08-17 13:31:43 -0700327 .find_reduced_pll = intel_find_best_reduced_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700328};
329
330static const intel_limit_t intel_limits_i9xx_lvds = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800331 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
332 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
333 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
334 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
335 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
336 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
337 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
338 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
339 /* The single-channel range is 25-112Mhz, and dual-channel
340 * is 80-224Mhz. Prefer single channel as much as possible.
341 */
342 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
343 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800344 .find_pll = intel_find_best_PLL,
Jesse Barnes652c3932009-08-17 13:31:43 -0700345 .find_reduced_pll = intel_find_best_reduced_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700346};
347
Ma Ling044c7c42009-03-18 20:13:23 +0800348 /* below parameter and function is for G4X Chipset Family*/
Keith Packarde4b36692009-06-05 19:22:17 -0700349static const intel_limit_t intel_limits_g4x_sdvo = {
Ma Ling044c7c42009-03-18 20:13:23 +0800350 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
351 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
352 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
353 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
354 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
355 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
356 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
357 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
358 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
359 .p2_slow = G4X_P2_SDVO_SLOW,
360 .p2_fast = G4X_P2_SDVO_FAST
361 },
Ma Lingd4906092009-03-18 20:13:27 +0800362 .find_pll = intel_g4x_find_best_PLL,
Jesse Barnes652c3932009-08-17 13:31:43 -0700363 .find_reduced_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700364};
365
366static const intel_limit_t intel_limits_g4x_hdmi = {
Ma Ling044c7c42009-03-18 20:13:23 +0800367 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
368 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
369 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
370 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
371 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
372 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
373 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
374 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
375 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
376 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
377 .p2_fast = G4X_P2_HDMI_DAC_FAST
378 },
Ma Lingd4906092009-03-18 20:13:27 +0800379 .find_pll = intel_g4x_find_best_PLL,
Jesse Barnes652c3932009-08-17 13:31:43 -0700380 .find_reduced_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700381};
382
383static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Ma Ling044c7c42009-03-18 20:13:23 +0800384 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
385 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
386 .vco = { .min = G4X_VCO_MIN,
387 .max = G4X_VCO_MAX },
388 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
389 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
390 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
391 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
392 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
393 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
394 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
395 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
396 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
397 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
398 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
399 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
400 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
401 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
402 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
403 },
Ma Lingd4906092009-03-18 20:13:27 +0800404 .find_pll = intel_g4x_find_best_PLL,
Jesse Barnes652c3932009-08-17 13:31:43 -0700405 .find_reduced_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700406};
407
408static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Ma Ling044c7c42009-03-18 20:13:23 +0800409 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
410 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
411 .vco = { .min = G4X_VCO_MIN,
412 .max = G4X_VCO_MAX },
413 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
414 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
415 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
416 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
417 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
418 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
419 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
420 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
421 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
422 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
423 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
424 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
425 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
426 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
427 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
428 },
Ma Lingd4906092009-03-18 20:13:27 +0800429 .find_pll = intel_g4x_find_best_PLL,
Jesse Barnes652c3932009-08-17 13:31:43 -0700430 .find_reduced_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700431};
432
433static const intel_limit_t intel_limits_g4x_display_port = {
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700434 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
435 .max = G4X_DOT_DISPLAY_PORT_MAX },
436 .vco = { .min = G4X_VCO_MIN,
437 .max = G4X_VCO_MAX},
438 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
439 .max = G4X_N_DISPLAY_PORT_MAX },
440 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
441 .max = G4X_M_DISPLAY_PORT_MAX },
442 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
443 .max = G4X_M1_DISPLAY_PORT_MAX },
444 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
445 .max = G4X_M2_DISPLAY_PORT_MAX },
446 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
447 .max = G4X_P_DISPLAY_PORT_MAX },
448 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
449 .max = G4X_P1_DISPLAY_PORT_MAX},
450 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
451 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
452 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
453 .find_pll = intel_find_pll_g4x_dp,
Keith Packarde4b36692009-06-05 19:22:17 -0700454};
455
456static const intel_limit_t intel_limits_igd_sdvo = {
Shaohua Li21778322009-02-23 15:19:16 +0800457 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
458 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
459 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
460 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
461 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
462 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
463 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
464 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
465 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
466 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
Shaohua Li61157072009-04-03 15:24:43 +0800467 .find_pll = intel_find_best_PLL,
Jesse Barnes652c3932009-08-17 13:31:43 -0700468 .find_reduced_pll = intel_find_best_reduced_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700469};
470
471static const intel_limit_t intel_limits_igd_lvds = {
Shaohua Li21778322009-02-23 15:19:16 +0800472 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
473 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
474 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
475 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
476 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
477 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
478 .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
479 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
480 /* IGD only supports single-channel mode. */
481 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
482 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
Shaohua Li61157072009-04-03 15:24:43 +0800483 .find_pll = intel_find_best_PLL,
Jesse Barnes652c3932009-08-17 13:31:43 -0700484 .find_reduced_pll = intel_find_best_reduced_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700485};
486
487static const intel_limit_t intel_limits_igdng_sdvo = {
Zhenyu Wang2c072452009-06-05 15:38:42 +0800488 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
489 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
490 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
491 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
492 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
493 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
494 .p = { .min = IGDNG_P_SDVO_DAC_MIN, .max = IGDNG_P_SDVO_DAC_MAX },
495 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
496 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
497 .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
498 .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
499 .find_pll = intel_igdng_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700500};
501
502static const intel_limit_t intel_limits_igdng_lvds = {
Zhenyu Wang2c072452009-06-05 15:38:42 +0800503 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
504 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
505 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
506 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
507 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
508 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
509 .p = { .min = IGDNG_P_LVDS_MIN, .max = IGDNG_P_LVDS_MAX },
510 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
511 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
512 .p2_slow = IGDNG_P2_LVDS_SLOW,
513 .p2_fast = IGDNG_P2_LVDS_FAST },
514 .find_pll = intel_igdng_find_best_PLL,
Jesse Barnes79e53942008-11-07 14:24:08 -0800515};
516
Zhenyu Wang2c072452009-06-05 15:38:42 +0800517static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
518{
519 const intel_limit_t *limit;
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700521 limit = &intel_limits_igdng_lvds;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800522 else
Keith Packarde4b36692009-06-05 19:22:17 -0700523 limit = &intel_limits_igdng_sdvo;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800524
525 return limit;
526}
527
Ma Ling044c7c42009-03-18 20:13:23 +0800528static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
529{
530 struct drm_device *dev = crtc->dev;
531 struct drm_i915_private *dev_priv = dev->dev_private;
532 const intel_limit_t *limit;
533
534 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
535 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
536 LVDS_CLKB_POWER_UP)
537 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700538 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800539 else
540 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700541 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800542 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
543 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700544 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800545 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700546 limit = &intel_limits_g4x_sdvo;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700547 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700548 limit = &intel_limits_g4x_display_port;
Ma Ling044c7c42009-03-18 20:13:23 +0800549 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700550 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800551
552 return limit;
553}
554
Jesse Barnes79e53942008-11-07 14:24:08 -0800555static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
556{
557 struct drm_device *dev = crtc->dev;
558 const intel_limit_t *limit;
559
Zhenyu Wang2c072452009-06-05 15:38:42 +0800560 if (IS_IGDNG(dev))
561 limit = intel_igdng_limit(crtc);
562 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800563 limit = intel_g4x_limit(crtc);
Shaohua Li21778322009-02-23 15:19:16 +0800564 } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800565 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700566 limit = &intel_limits_i9xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800567 else
Keith Packarde4b36692009-06-05 19:22:17 -0700568 limit = &intel_limits_i9xx_sdvo;
Shaohua Li21778322009-02-23 15:19:16 +0800569 } else if (IS_IGD(dev)) {
570 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700571 limit = &intel_limits_igd_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800572 else
Keith Packarde4b36692009-06-05 19:22:17 -0700573 limit = &intel_limits_igd_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800574 } else {
575 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700576 limit = &intel_limits_i8xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800577 else
Keith Packarde4b36692009-06-05 19:22:17 -0700578 limit = &intel_limits_i8xx_dvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800579 }
580 return limit;
581}
582
Shaohua Li21778322009-02-23 15:19:16 +0800583/* m1 is reserved as 0 in IGD, n is a ring counter */
584static void igd_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800585{
Shaohua Li21778322009-02-23 15:19:16 +0800586 clock->m = clock->m2 + 2;
587 clock->p = clock->p1 * clock->p2;
588 clock->vco = refclk * clock->m / clock->n;
589 clock->dot = clock->vco / clock->p;
590}
591
592static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
593{
594 if (IS_IGD(dev)) {
595 igd_clock(refclk, clock);
596 return;
597 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800598 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
599 clock->p = clock->p1 * clock->p2;
600 clock->vco = refclk * clock->m / (clock->n + 2);
601 clock->dot = clock->vco / clock->p;
602}
603
Jesse Barnes79e53942008-11-07 14:24:08 -0800604/**
605 * Returns whether any output on the specified pipe is of the specified type
606 */
607bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
608{
609 struct drm_device *dev = crtc->dev;
610 struct drm_mode_config *mode_config = &dev->mode_config;
611 struct drm_connector *l_entry;
612
613 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
614 if (l_entry->encoder &&
615 l_entry->encoder->crtc == crtc) {
616 struct intel_output *intel_output = to_intel_output(l_entry);
617 if (intel_output->type == type)
618 return true;
619 }
620 }
621 return false;
622}
623
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800624struct drm_connector *
625intel_pipe_get_output (struct drm_crtc *crtc)
626{
627 struct drm_device *dev = crtc->dev;
628 struct drm_mode_config *mode_config = &dev->mode_config;
629 struct drm_connector *l_entry, *ret = NULL;
630
631 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
632 if (l_entry->encoder &&
633 l_entry->encoder->crtc == crtc) {
634 ret = l_entry;
635 break;
636 }
637 }
638 return ret;
639}
640
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800641#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800642/**
643 * Returns whether the given set of divisors are valid for a given refclk with
644 * the given connectors.
645 */
646
647static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
648{
649 const intel_limit_t *limit = intel_limit (crtc);
Shaohua Li21778322009-02-23 15:19:16 +0800650 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800651
652 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
653 INTELPllInvalid ("p1 out of range\n");
654 if (clock->p < limit->p.min || limit->p.max < clock->p)
655 INTELPllInvalid ("p out of range\n");
656 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
657 INTELPllInvalid ("m2 out of range\n");
658 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
659 INTELPllInvalid ("m1 out of range\n");
Shaohua Li21778322009-02-23 15:19:16 +0800660 if (clock->m1 <= clock->m2 && !IS_IGD(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800661 INTELPllInvalid ("m1 <= m2\n");
662 if (clock->m < limit->m.min || limit->m.max < clock->m)
663 INTELPllInvalid ("m out of range\n");
664 if (clock->n < limit->n.min || limit->n.max < clock->n)
665 INTELPllInvalid ("n out of range\n");
666 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
667 INTELPllInvalid ("vco out of range\n");
668 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
669 * connector, etc., rather than just a single range.
670 */
671 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
672 INTELPllInvalid ("dot out of range\n");
673
674 return true;
675}
676
Ma Lingd4906092009-03-18 20:13:27 +0800677static bool
678intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
679 int target, int refclk, intel_clock_t *best_clock)
680
Jesse Barnes79e53942008-11-07 14:24:08 -0800681{
682 struct drm_device *dev = crtc->dev;
683 struct drm_i915_private *dev_priv = dev->dev_private;
684 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800685 int err = target;
686
Bruno Prémontbc5e5712009-08-08 13:01:17 +0200687 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Florian Mickler832cc282009-07-13 18:40:32 +0800688 (I915_READ(LVDS)) != 0) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800689 /*
690 * For LVDS, if the panel is on, just rely on its current
691 * settings for dual-channel. We haven't figured out how to
692 * reliably set up different single/dual channel state, if we
693 * even can.
694 */
695 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
696 LVDS_CLKB_POWER_UP)
697 clock.p2 = limit->p2.p2_fast;
698 else
699 clock.p2 = limit->p2.p2_slow;
700 } else {
701 if (target < limit->p2.dot_limit)
702 clock.p2 = limit->p2.p2_slow;
703 else
704 clock.p2 = limit->p2.p2_fast;
705 }
706
707 memset (best_clock, 0, sizeof (*best_clock));
708
Jesse Barnes652c3932009-08-17 13:31:43 -0700709 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
710 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
711 clock.m1++) {
712 for (clock.m2 = limit->m2.min;
713 clock.m2 <= limit->m2.max; clock.m2++) {
714 /* m1 is always 0 in IGD */
715 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
716 break;
717 for (clock.n = limit->n.min;
718 clock.n <= limit->n.max; clock.n++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800719 int this_err;
720
Shaohua Li21778322009-02-23 15:19:16 +0800721 intel_clock(dev, refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800722
723 if (!intel_PLL_is_valid(crtc, &clock))
724 continue;
725
726 this_err = abs(clock.dot - target);
727 if (this_err < err) {
728 *best_clock = clock;
729 err = this_err;
730 }
731 }
732 }
733 }
734 }
735
736 return (err != target);
737}
738
Jesse Barnes652c3932009-08-17 13:31:43 -0700739
740static bool
741intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
742 int target, int refclk, intel_clock_t *best_clock)
743
744{
745 struct drm_device *dev = crtc->dev;
746 intel_clock_t clock;
747 int err = target;
748 bool found = false;
749
750 memcpy(&clock, best_clock, sizeof(intel_clock_t));
751
752 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
753 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
754 /* m1 is always 0 in IGD */
755 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
756 break;
757 for (clock.n = limit->n.min; clock.n <= limit->n.max;
758 clock.n++) {
759 int this_err;
760
761 intel_clock(dev, refclk, &clock);
762
763 if (!intel_PLL_is_valid(crtc, &clock))
764 continue;
765
766 this_err = abs(clock.dot - target);
767 if (this_err < err) {
768 *best_clock = clock;
769 err = this_err;
770 found = true;
771 }
772 }
773 }
774 }
775
776 return found;
777}
778
Ma Lingd4906092009-03-18 20:13:27 +0800779static bool
780intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
781 int target, int refclk, intel_clock_t *best_clock)
782{
783 struct drm_device *dev = crtc->dev;
784 struct drm_i915_private *dev_priv = dev->dev_private;
785 intel_clock_t clock;
786 int max_n;
787 bool found;
788 /* approximately equals target * 0.00488 */
789 int err_most = (target >> 8) + (target >> 10);
790 found = false;
791
792 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
793 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
794 LVDS_CLKB_POWER_UP)
795 clock.p2 = limit->p2.p2_fast;
796 else
797 clock.p2 = limit->p2.p2_slow;
798 } else {
799 if (target < limit->p2.dot_limit)
800 clock.p2 = limit->p2.p2_slow;
801 else
802 clock.p2 = limit->p2.p2_fast;
803 }
804
805 memset(best_clock, 0, sizeof(*best_clock));
806 max_n = limit->n.max;
807 /* based on hardware requriment prefer smaller n to precision */
808 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Jesse Barnes652c3932009-08-17 13:31:43 -0700809 /* based on hardware requirment prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800810 for (clock.m1 = limit->m1.max;
811 clock.m1 >= limit->m1.min; clock.m1--) {
812 for (clock.m2 = limit->m2.max;
813 clock.m2 >= limit->m2.min; clock.m2--) {
814 for (clock.p1 = limit->p1.max;
815 clock.p1 >= limit->p1.min; clock.p1--) {
816 int this_err;
817
Shaohua Li21778322009-02-23 15:19:16 +0800818 intel_clock(dev, refclk, &clock);
Ma Lingd4906092009-03-18 20:13:27 +0800819 if (!intel_PLL_is_valid(crtc, &clock))
820 continue;
821 this_err = abs(clock.dot - target) ;
822 if (this_err < err_most) {
823 *best_clock = clock;
824 err_most = this_err;
825 max_n = clock.n;
826 found = true;
827 }
828 }
829 }
830 }
831 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800832 return found;
833}
Ma Lingd4906092009-03-18 20:13:27 +0800834
Zhenyu Wang2c072452009-06-05 15:38:42 +0800835static bool
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800836intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
837 int target, int refclk, intel_clock_t *best_clock)
838{
839 struct drm_device *dev = crtc->dev;
840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.n = 1;
843 clock.p1 = 2;
844 clock.p2 = 10;
845 clock.m1 = 12;
846 clock.m2 = 9;
847 } else {
848 clock.n = 2;
849 clock.p1 = 1;
850 clock.p2 = 10;
851 clock.m1 = 14;
852 clock.m2 = 8;
853 }
854 intel_clock(dev, refclk, &clock);
855 memcpy(best_clock, &clock, sizeof(intel_clock_t));
856 return true;
857}
858
859static bool
Zhenyu Wang2c072452009-06-05 15:38:42 +0800860intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
861 int target, int refclk, intel_clock_t *best_clock)
862{
863 struct drm_device *dev = crtc->dev;
864 struct drm_i915_private *dev_priv = dev->dev_private;
865 intel_clock_t clock;
866 int max_n;
867 bool found;
868 int err_most = 47;
869 found = false;
870
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800871 /* eDP has only 2 clock choice, no n/m/p setting */
872 if (HAS_eDP)
873 return true;
874
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800875 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
876 return intel_find_pll_igdng_dp(limit, crtc, target,
877 refclk, best_clock);
878
Zhenyu Wang2c072452009-06-05 15:38:42 +0800879 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Zhenyu Wangb09aea72009-09-19 14:54:06 +0800880 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
Zhenyu Wang2c072452009-06-05 15:38:42 +0800881 LVDS_CLKB_POWER_UP)
882 clock.p2 = limit->p2.p2_fast;
883 else
884 clock.p2 = limit->p2.p2_slow;
885 } else {
886 if (target < limit->p2.dot_limit)
887 clock.p2 = limit->p2.p2_slow;
888 else
889 clock.p2 = limit->p2.p2_fast;
890 }
891
892 memset(best_clock, 0, sizeof(*best_clock));
893 max_n = limit->n.max;
Jesse Barnes652c3932009-08-17 13:31:43 -0700894 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
895 /* based on hardware requriment prefer smaller n to precision */
896 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
897 /* based on hardware requirment prefere larger m1,m2 */
898 for (clock.m1 = limit->m1.max;
899 clock.m1 >= limit->m1.min; clock.m1--) {
900 for (clock.m2 = limit->m2.max;
901 clock.m2 >= limit->m2.min; clock.m2--) {
Zhenyu Wang2c072452009-06-05 15:38:42 +0800902 int this_err;
903
904 intel_clock(dev, refclk, &clock);
905 if (!intel_PLL_is_valid(crtc, &clock))
906 continue;
907 this_err = abs((10000 - (target*10000/clock.dot)));
908 if (this_err < err_most) {
909 *best_clock = clock;
910 err_most = this_err;
911 max_n = clock.n;
912 found = true;
913 /* found on first matching */
914 goto out;
915 }
916 }
917 }
918 }
919 }
920out:
Ma Lingd4906092009-03-18 20:13:27 +0800921 return found;
922}
923
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700924/* DisplayPort has only two frequencies, 162MHz and 270MHz */
925static bool
926intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
927 int target, int refclk, intel_clock_t *best_clock)
928{
929 intel_clock_t clock;
930 if (target < 200000) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700931 clock.p1 = 2;
932 clock.p2 = 10;
Keith Packardb3d25492009-06-24 23:09:15 -0700933 clock.n = 2;
934 clock.m1 = 23;
935 clock.m2 = 8;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700936 } else {
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700937 clock.p1 = 1;
938 clock.p2 = 10;
Keith Packardb3d25492009-06-24 23:09:15 -0700939 clock.n = 1;
940 clock.m1 = 14;
941 clock.m2 = 2;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700942 }
Keith Packardb3d25492009-06-24 23:09:15 -0700943 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
944 clock.p = (clock.p1 * clock.p2);
945 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700946 memcpy(best_clock, &clock, sizeof(intel_clock_t));
947 return true;
948}
949
Jesse Barnes79e53942008-11-07 14:24:08 -0800950void
951intel_wait_for_vblank(struct drm_device *dev)
952{
953 /* Wait for 20ms, i.e. one cycle at 50hz. */
Arjan van de Ven580982d2009-03-23 13:36:25 -0700954 mdelay(20);
Jesse Barnes79e53942008-11-07 14:24:08 -0800955}
956
Jesse Barnes80824002009-09-10 15:28:06 -0700957/* Parameters have changed, update FBC info */
958static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
959{
960 struct drm_device *dev = crtc->dev;
961 struct drm_i915_private *dev_priv = dev->dev_private;
962 struct drm_framebuffer *fb = crtc->fb;
963 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
964 struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
966 int plane, i;
967 u32 fbc_ctl, fbc_ctl2;
968
969 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
970
971 if (fb->pitch < dev_priv->cfb_pitch)
972 dev_priv->cfb_pitch = fb->pitch;
973
974 /* FBC_CTL wants 64B units */
975 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
976 dev_priv->cfb_fence = obj_priv->fence_reg;
977 dev_priv->cfb_plane = intel_crtc->plane;
978 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
979
980 /* Clear old tags */
981 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
982 I915_WRITE(FBC_TAG + (i * 4), 0);
983
984 /* Set it up... */
985 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
986 if (obj_priv->tiling_mode != I915_TILING_NONE)
987 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
988 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
989 I915_WRITE(FBC_FENCE_OFF, crtc->y);
990
991 /* enable it... */
992 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
993 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
994 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
995 if (obj_priv->tiling_mode != I915_TILING_NONE)
996 fbc_ctl |= dev_priv->cfb_fence;
997 I915_WRITE(FBC_CONTROL, fbc_ctl);
998
999 DRM_DEBUG("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1000 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1001}
1002
1003void i8xx_disable_fbc(struct drm_device *dev)
1004{
1005 struct drm_i915_private *dev_priv = dev->dev_private;
1006 u32 fbc_ctl;
1007
Jesse Barnesc1a1cdc2009-09-16 15:05:00 -07001008 if (!I915_HAS_FBC(dev))
1009 return;
1010
Jesse Barnes80824002009-09-10 15:28:06 -07001011 /* Disable compression */
1012 fbc_ctl = I915_READ(FBC_CONTROL);
1013 fbc_ctl &= ~FBC_CTL_EN;
1014 I915_WRITE(FBC_CONTROL, fbc_ctl);
1015
1016 /* Wait for compressing bit to clear */
1017 while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1018 ; /* nothing */
1019
1020 intel_wait_for_vblank(dev);
1021
1022 DRM_DEBUG("disabled FBC\n");
1023}
1024
1025static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1026{
1027 struct drm_device *dev = crtc->dev;
1028 struct drm_i915_private *dev_priv = dev->dev_private;
1029
1030 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1031}
1032
Jesse Barnes74dff282009-09-14 15:39:40 -07001033static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1034{
1035 struct drm_device *dev = crtc->dev;
1036 struct drm_i915_private *dev_priv = dev->dev_private;
1037 struct drm_framebuffer *fb = crtc->fb;
1038 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1039 struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1041 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1042 DPFC_CTL_PLANEB);
1043 unsigned long stall_watermark = 200;
1044 u32 dpfc_ctl;
1045
1046 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1047 dev_priv->cfb_fence = obj_priv->fence_reg;
1048 dev_priv->cfb_plane = intel_crtc->plane;
1049
1050 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1051 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1052 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1053 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1054 } else {
1055 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1056 }
1057
1058 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1059 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1060 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1061 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1062 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1063
1064 /* enable it... */
1065 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1066
1067 DRM_DEBUG("enabled fbc on plane %d\n", intel_crtc->plane);
1068}
1069
1070void g4x_disable_fbc(struct drm_device *dev)
1071{
1072 struct drm_i915_private *dev_priv = dev->dev_private;
1073 u32 dpfc_ctl;
1074
1075 /* Disable compression */
1076 dpfc_ctl = I915_READ(DPFC_CONTROL);
1077 dpfc_ctl &= ~DPFC_CTL_EN;
1078 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1079 intel_wait_for_vblank(dev);
1080
1081 DRM_DEBUG("disabled FBC\n");
1082}
1083
1084static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1085{
1086 struct drm_device *dev = crtc->dev;
1087 struct drm_i915_private *dev_priv = dev->dev_private;
1088
1089 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1090}
1091
Jesse Barnes80824002009-09-10 15:28:06 -07001092/**
1093 * intel_update_fbc - enable/disable FBC as needed
1094 * @crtc: CRTC to point the compressor at
1095 * @mode: mode in use
1096 *
1097 * Set up the framebuffer compression hardware at mode set time. We
1098 * enable it if possible:
1099 * - plane A only (on pre-965)
1100 * - no pixel mulitply/line duplication
1101 * - no alpha buffer discard
1102 * - no dual wide
1103 * - framebuffer <= 2048 in width, 1536 in height
1104 *
1105 * We can't assume that any compression will take place (worst case),
1106 * so the compressed buffer has to be the same size as the uncompressed
1107 * one. It also must reside (along with the line length buffer) in
1108 * stolen memory.
1109 *
1110 * We need to enable/disable FBC on a global basis.
1111 */
1112static void intel_update_fbc(struct drm_crtc *crtc,
1113 struct drm_display_mode *mode)
1114{
1115 struct drm_device *dev = crtc->dev;
1116 struct drm_i915_private *dev_priv = dev->dev_private;
1117 struct drm_framebuffer *fb = crtc->fb;
1118 struct intel_framebuffer *intel_fb;
1119 struct drm_i915_gem_object *obj_priv;
1120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1121 int plane = intel_crtc->plane;
1122
1123 if (!i915_powersave)
1124 return;
1125
Jesse Barnese70236a2009-09-21 10:42:27 -07001126 if (!dev_priv->display.fbc_enabled ||
1127 !dev_priv->display.enable_fbc ||
1128 !dev_priv->display.disable_fbc)
1129 return;
1130
Jesse Barnes80824002009-09-10 15:28:06 -07001131 if (!crtc->fb)
1132 return;
1133
1134 intel_fb = to_intel_framebuffer(fb);
1135 obj_priv = intel_fb->obj->driver_private;
1136
1137 /*
1138 * If FBC is already on, we just have to verify that we can
1139 * keep it that way...
1140 * Need to disable if:
1141 * - changing FBC params (stride, fence, mode)
1142 * - new fb is too large to fit in compressed buffer
1143 * - going to an unsupported config (interlace, pixel multiply, etc.)
1144 */
1145 if (intel_fb->obj->size > dev_priv->cfb_size) {
1146 DRM_DEBUG("framebuffer too large, disabling compression\n");
1147 goto out_disable;
1148 }
1149 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1150 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1151 DRM_DEBUG("mode incompatible with compression, disabling\n");
1152 goto out_disable;
1153 }
1154 if ((mode->hdisplay > 2048) ||
1155 (mode->vdisplay > 1536)) {
1156 DRM_DEBUG("mode too large for compression, disabling\n");
1157 goto out_disable;
1158 }
Jesse Barnes74dff282009-09-14 15:39:40 -07001159 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
Jesse Barnes80824002009-09-10 15:28:06 -07001160 DRM_DEBUG("plane not 0, disabling compression\n");
1161 goto out_disable;
1162 }
1163 if (obj_priv->tiling_mode != I915_TILING_X) {
1164 DRM_DEBUG("framebuffer not tiled, disabling compression\n");
1165 goto out_disable;
1166 }
1167
Jesse Barnese70236a2009-09-21 10:42:27 -07001168 if (dev_priv->display.fbc_enabled(crtc)) {
Jesse Barnes80824002009-09-10 15:28:06 -07001169 /* We can re-enable it in this case, but need to update pitch */
1170 if (fb->pitch > dev_priv->cfb_pitch)
Jesse Barnese70236a2009-09-21 10:42:27 -07001171 dev_priv->display.disable_fbc(dev);
Jesse Barnes80824002009-09-10 15:28:06 -07001172 if (obj_priv->fence_reg != dev_priv->cfb_fence)
Jesse Barnese70236a2009-09-21 10:42:27 -07001173 dev_priv->display.disable_fbc(dev);
Jesse Barnes80824002009-09-10 15:28:06 -07001174 if (plane != dev_priv->cfb_plane)
Jesse Barnese70236a2009-09-21 10:42:27 -07001175 dev_priv->display.disable_fbc(dev);
Jesse Barnes80824002009-09-10 15:28:06 -07001176 }
1177
Jesse Barnese70236a2009-09-21 10:42:27 -07001178 if (!dev_priv->display.fbc_enabled(crtc)) {
Jesse Barnes80824002009-09-10 15:28:06 -07001179 /* Now try to turn it back on if possible */
Jesse Barnese70236a2009-09-21 10:42:27 -07001180 dev_priv->display.enable_fbc(crtc, 500);
Jesse Barnes80824002009-09-10 15:28:06 -07001181 }
1182
1183 return;
1184
1185out_disable:
1186 DRM_DEBUG("unsupported config, disabling FBC\n");
1187 /* Multiple disables should be harmless */
Jesse Barnese70236a2009-09-21 10:42:27 -07001188 if (dev_priv->display.fbc_enabled(crtc))
1189 dev_priv->display.disable_fbc(dev);
Jesse Barnes80824002009-09-10 15:28:06 -07001190}
1191
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001192static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001193intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1194 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08001195{
1196 struct drm_device *dev = crtc->dev;
1197 struct drm_i915_private *dev_priv = dev->dev_private;
1198 struct drm_i915_master_private *master_priv;
1199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1200 struct intel_framebuffer *intel_fb;
1201 struct drm_i915_gem_object *obj_priv;
1202 struct drm_gem_object *obj;
1203 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07001204 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08001205 unsigned long Start, Offset;
Jesse Barnes80824002009-09-10 15:28:06 -07001206 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1207 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1208 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1209 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1210 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001211 u32 dspcntr, alignment;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001212 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08001213
1214 /* no fb bound */
1215 if (!crtc->fb) {
1216 DRM_DEBUG("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001217 return 0;
1218 }
1219
Jesse Barnes80824002009-09-10 15:28:06 -07001220 switch (plane) {
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001221 case 0:
1222 case 1:
1223 break;
1224 default:
Jesse Barnes80824002009-09-10 15:28:06 -07001225 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001226 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08001227 }
1228
1229 intel_fb = to_intel_framebuffer(crtc->fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08001230 obj = intel_fb->obj;
1231 obj_priv = obj->driver_private;
1232
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001233 switch (obj_priv->tiling_mode) {
1234 case I915_TILING_NONE:
1235 alignment = 64 * 1024;
1236 break;
1237 case I915_TILING_X:
Chris Wilson2ebed172009-02-11 14:26:30 +00001238 /* pin() will align the object as required by fence */
1239 alignment = 0;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001240 break;
1241 case I915_TILING_Y:
1242 /* FIXME: Is this true? */
1243 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001244 return -EINVAL;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001245 default:
1246 BUG();
1247 }
1248
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001249 mutex_lock(&dev->struct_mutex);
Chris Wilson8c4b8c32009-06-17 22:08:52 +01001250 ret = i915_gem_object_pin(obj, alignment);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001251 if (ret != 0) {
1252 mutex_unlock(&dev->struct_mutex);
1253 return ret;
1254 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001255
Chris Wilson8c4b8c32009-06-17 22:08:52 +01001256 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001257 if (ret != 0) {
Chris Wilson8c4b8c32009-06-17 22:08:52 +01001258 i915_gem_object_unpin(obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001259 mutex_unlock(&dev->struct_mutex);
1260 return ret;
1261 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001262
Chris Wilson8c4b8c32009-06-17 22:08:52 +01001263 /* Pre-i965 needs to install a fence for tiled scan-out */
1264 if (!IS_I965G(dev) &&
1265 obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1266 obj_priv->tiling_mode != I915_TILING_NONE) {
1267 ret = i915_gem_object_get_fence_reg(obj);
1268 if (ret != 0) {
1269 i915_gem_object_unpin(obj);
1270 mutex_unlock(&dev->struct_mutex);
1271 return ret;
1272 }
1273 }
1274
Jesse Barnes79e53942008-11-07 14:24:08 -08001275 dspcntr = I915_READ(dspcntr_reg);
Jesse Barnes712531b2009-01-09 13:56:14 -08001276 /* Mask out pixel format bits in case we change it */
1277 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Jesse Barnes79e53942008-11-07 14:24:08 -08001278 switch (crtc->fb->bits_per_pixel) {
1279 case 8:
1280 dspcntr |= DISPPLANE_8BPP;
1281 break;
1282 case 16:
1283 if (crtc->fb->depth == 15)
1284 dspcntr |= DISPPLANE_15_16BPP;
1285 else
1286 dspcntr |= DISPPLANE_16BPP;
1287 break;
1288 case 24:
1289 case 32:
1290 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1291 break;
1292 default:
1293 DRM_ERROR("Unknown color depth\n");
Chris Wilson8c4b8c32009-06-17 22:08:52 +01001294 i915_gem_object_unpin(obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001295 mutex_unlock(&dev->struct_mutex);
1296 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08001297 }
Jesse Barnesf5448472009-04-14 14:17:47 -07001298 if (IS_I965G(dev)) {
1299 if (obj_priv->tiling_mode != I915_TILING_NONE)
1300 dspcntr |= DISPPLANE_TILED;
1301 else
1302 dspcntr &= ~DISPPLANE_TILED;
1303 }
1304
Zhenyu Wang553bd142009-09-02 10:57:52 +08001305 if (IS_IGDNG(dev))
1306 /* must disable */
1307 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1308
Jesse Barnes79e53942008-11-07 14:24:08 -08001309 I915_WRITE(dspcntr_reg, dspcntr);
1310
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001311 Start = obj_priv->gtt_offset;
1312 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1313
Jesse Barnes79e53942008-11-07 14:24:08 -08001314 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001315 I915_WRITE(dspstride, crtc->fb->pitch);
Jesse Barnes79e53942008-11-07 14:24:08 -08001316 if (IS_I965G(dev)) {
1317 I915_WRITE(dspbase, Offset);
1318 I915_READ(dspbase);
1319 I915_WRITE(dspsurf, Start);
1320 I915_READ(dspsurf);
Jesse Barnesf5448472009-04-14 14:17:47 -07001321 I915_WRITE(dsptileoff, (y << 16) | x);
Jesse Barnes79e53942008-11-07 14:24:08 -08001322 } else {
1323 I915_WRITE(dspbase, Start + Offset);
1324 I915_READ(dspbase);
1325 }
1326
Jesse Barnes74dff282009-09-14 15:39:40 -07001327 if ((IS_I965G(dev) || plane == 0))
Jesse Barnesedb81952009-09-17 17:06:47 -07001328 intel_update_fbc(crtc, &crtc->mode);
1329
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001330 intel_wait_for_vblank(dev);
1331
1332 if (old_fb) {
1333 intel_fb = to_intel_framebuffer(old_fb);
Jesse Barnes652c3932009-08-17 13:31:43 -07001334 obj_priv = intel_fb->obj->driver_private;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001335 i915_gem_object_unpin(intel_fb->obj);
1336 }
Jesse Barnes652c3932009-08-17 13:31:43 -07001337 intel_increase_pllclock(crtc, true);
1338
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001339 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08001340
1341 if (!dev->primary->master)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001342 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08001343
1344 master_priv = dev->primary->master->driver_priv;
1345 if (!master_priv->sarea_priv)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001346 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08001347
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001348 if (pipe) {
Jesse Barnes79e53942008-11-07 14:24:08 -08001349 master_priv->sarea_priv->pipeB_x = x;
1350 master_priv->sarea_priv->pipeB_y = y;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001351 } else {
1352 master_priv->sarea_priv->pipeA_x = x;
1353 master_priv->sarea_priv->pipeA_y = y;
Jesse Barnes79e53942008-11-07 14:24:08 -08001354 }
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001355
1356 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08001357}
1358
Zhenyu Wang24f119c2009-07-24 01:00:28 +08001359/* Disable the VGA plane that we never use */
1360static void i915_disable_vga (struct drm_device *dev)
1361{
1362 struct drm_i915_private *dev_priv = dev->dev_private;
1363 u8 sr1;
1364 u32 vga_reg;
1365
1366 if (IS_IGDNG(dev))
1367 vga_reg = CPU_VGACNTRL;
1368 else
1369 vga_reg = VGACNTRL;
1370
1371 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1372 return;
1373
1374 I915_WRITE8(VGA_SR_INDEX, 1);
1375 sr1 = I915_READ8(VGA_SR_DATA);
1376 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1377 udelay(100);
1378
1379 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1380}
1381
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001382static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1383{
1384 struct drm_device *dev = crtc->dev;
1385 struct drm_i915_private *dev_priv = dev->dev_private;
1386 u32 dpa_ctl;
1387
1388 DRM_DEBUG("\n");
1389 dpa_ctl = I915_READ(DP_A);
1390 dpa_ctl &= ~DP_PLL_ENABLE;
1391 I915_WRITE(DP_A, dpa_ctl);
1392}
1393
1394static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1395{
1396 struct drm_device *dev = crtc->dev;
1397 struct drm_i915_private *dev_priv = dev->dev_private;
1398 u32 dpa_ctl;
1399
1400 dpa_ctl = I915_READ(DP_A);
1401 dpa_ctl |= DP_PLL_ENABLE;
1402 I915_WRITE(DP_A, dpa_ctl);
1403 udelay(200);
1404}
1405
1406
1407static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1408{
1409 struct drm_device *dev = crtc->dev;
1410 struct drm_i915_private *dev_priv = dev->dev_private;
1411 u32 dpa_ctl;
1412
1413 DRM_DEBUG("eDP PLL enable for clock %d\n", clock);
1414 dpa_ctl = I915_READ(DP_A);
1415 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1416
1417 if (clock < 200000) {
1418 u32 temp;
1419 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1420 /* workaround for 160Mhz:
1421 1) program 0x4600c bits 15:0 = 0x8124
1422 2) program 0x46010 bit 0 = 1
1423 3) program 0x46034 bit 24 = 1
1424 4) program 0x64000 bit 14 = 1
1425 */
1426 temp = I915_READ(0x4600c);
1427 temp &= 0xffff0000;
1428 I915_WRITE(0x4600c, temp | 0x8124);
1429
1430 temp = I915_READ(0x46010);
1431 I915_WRITE(0x46010, temp | 1);
1432
1433 temp = I915_READ(0x46034);
1434 I915_WRITE(0x46034, temp | (1 << 24));
1435 } else {
1436 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1437 }
1438 I915_WRITE(DP_A, dpa_ctl);
1439
1440 udelay(500);
1441}
1442
Zhenyu Wang2c072452009-06-05 15:38:42 +08001443static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
Jesse Barnes79e53942008-11-07 14:24:08 -08001444{
1445 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001446 struct drm_i915_private *dev_priv = dev->dev_private;
1447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1448 int pipe = intel_crtc->pipe;
Shaohua Li7662c8b2009-06-26 11:23:55 +08001449 int plane = intel_crtc->plane;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001450 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1451 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1452 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1453 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1454 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1455 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1456 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1457 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1458 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1459 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001460 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
Zhenyu Wang8dd81a32009-09-19 14:54:09 +08001461 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001462 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1463 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1464 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1465 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1466 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1467 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1468 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1469 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1470 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1471 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1472 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1473 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1474 u32 temp;
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001475 int tries = 5, j, n;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001476
1477 /* XXX: When our outputs are all unaware of DPMS modes other than off
1478 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1479 */
1480 switch (mode) {
1481 case DRM_MODE_DPMS_ON:
1482 case DRM_MODE_DPMS_STANDBY:
1483 case DRM_MODE_DPMS_SUSPEND:
1484 DRM_DEBUG("crtc %d dpms on\n", pipe);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001485 if (HAS_eDP) {
1486 /* enable eDP PLL */
1487 igdng_enable_pll_edp(crtc);
1488 } else {
1489 /* enable PCH DPLL */
1490 temp = I915_READ(pch_dpll_reg);
1491 if ((temp & DPLL_VCO_ENABLE) == 0) {
1492 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1493 I915_READ(pch_dpll_reg);
1494 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08001495
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001496 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1497 temp = I915_READ(fdi_rx_reg);
1498 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1499 FDI_SEL_PCDCLK |
1500 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1501 I915_READ(fdi_rx_reg);
1502 udelay(200);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001503
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001504 /* Enable CPU FDI TX PLL, always on for IGDNG */
1505 temp = I915_READ(fdi_tx_reg);
1506 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1507 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1508 I915_READ(fdi_tx_reg);
1509 udelay(100);
1510 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08001511 }
1512
Zhenyu Wang8dd81a32009-09-19 14:54:09 +08001513 /* Enable panel fitting for LVDS */
1514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1515 temp = I915_READ(pf_ctl_reg);
1516 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE);
1517
1518 /* currently full aspect */
1519 I915_WRITE(pf_win_pos, 0);
1520
1521 I915_WRITE(pf_win_size,
1522 (dev_priv->panel_fixed_mode->hdisplay << 16) |
1523 (dev_priv->panel_fixed_mode->vdisplay));
1524 }
1525
Zhenyu Wang2c072452009-06-05 15:38:42 +08001526 /* Enable CPU pipe */
1527 temp = I915_READ(pipeconf_reg);
1528 if ((temp & PIPEACONF_ENABLE) == 0) {
1529 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1530 I915_READ(pipeconf_reg);
1531 udelay(100);
1532 }
1533
1534 /* configure and enable CPU plane */
1535 temp = I915_READ(dspcntr_reg);
1536 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1537 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1538 /* Flush the plane changes */
1539 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1540 }
1541
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001542 if (!HAS_eDP) {
1543 /* enable CPU FDI TX and PCH FDI RX */
1544 temp = I915_READ(fdi_tx_reg);
1545 temp |= FDI_TX_ENABLE;
1546 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1547 temp &= ~FDI_LINK_TRAIN_NONE;
1548 temp |= FDI_LINK_TRAIN_PATTERN_1;
1549 I915_WRITE(fdi_tx_reg, temp);
1550 I915_READ(fdi_tx_reg);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001551
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001552 temp = I915_READ(fdi_rx_reg);
1553 temp &= ~FDI_LINK_TRAIN_NONE;
1554 temp |= FDI_LINK_TRAIN_PATTERN_1;
1555 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1556 I915_READ(fdi_rx_reg);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001557
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001558 udelay(150);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001559
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001560 /* Train FDI. */
1561 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1562 for train result */
1563 temp = I915_READ(fdi_rx_imr_reg);
1564 temp &= ~FDI_RX_SYMBOL_LOCK;
1565 temp &= ~FDI_RX_BIT_LOCK;
1566 I915_WRITE(fdi_rx_imr_reg, temp);
1567 I915_READ(fdi_rx_imr_reg);
1568 udelay(150);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001569
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001570 temp = I915_READ(fdi_rx_iir_reg);
1571 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001572
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001573 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1574 for (j = 0; j < tries; j++) {
1575 temp = I915_READ(fdi_rx_iir_reg);
1576 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1577 if (temp & FDI_RX_BIT_LOCK)
1578 break;
1579 udelay(200);
1580 }
1581 if (j != tries)
1582 I915_WRITE(fdi_rx_iir_reg,
1583 temp | FDI_RX_BIT_LOCK);
1584 else
1585 DRM_DEBUG("train 1 fail\n");
1586 } else {
Zhenyu Wang2c072452009-06-05 15:38:42 +08001587 I915_WRITE(fdi_rx_iir_reg,
1588 temp | FDI_RX_BIT_LOCK);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001589 DRM_DEBUG("train 1 ok 2!\n");
Zhenyu Wang2c072452009-06-05 15:38:42 +08001590 }
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001591 temp = I915_READ(fdi_tx_reg);
1592 temp &= ~FDI_LINK_TRAIN_NONE;
1593 temp |= FDI_LINK_TRAIN_PATTERN_2;
1594 I915_WRITE(fdi_tx_reg, temp);
1595
1596 temp = I915_READ(fdi_rx_reg);
1597 temp &= ~FDI_LINK_TRAIN_NONE;
1598 temp |= FDI_LINK_TRAIN_PATTERN_2;
1599 I915_WRITE(fdi_rx_reg, temp);
1600
1601 udelay(150);
1602
1603 temp = I915_READ(fdi_rx_iir_reg);
1604 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1605
1606 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1607 for (j = 0; j < tries; j++) {
1608 temp = I915_READ(fdi_rx_iir_reg);
1609 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1610 if (temp & FDI_RX_SYMBOL_LOCK)
1611 break;
1612 udelay(200);
1613 }
1614 if (j != tries) {
1615 I915_WRITE(fdi_rx_iir_reg,
1616 temp | FDI_RX_SYMBOL_LOCK);
1617 DRM_DEBUG("train 2 ok 1!\n");
1618 } else
1619 DRM_DEBUG("train 2 fail\n");
1620 } else {
Zhenyu Wang2c072452009-06-05 15:38:42 +08001621 I915_WRITE(fdi_rx_iir_reg,
1622 temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001623 DRM_DEBUG("train 2 ok 2!\n");
1624 }
1625 DRM_DEBUG("train done\n");
1626
1627 /* set transcoder timing */
1628 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1629 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1630 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1631
1632 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1633 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1634 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1635
1636 /* enable PCH transcoder */
1637 temp = I915_READ(transconf_reg);
1638 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1639 I915_READ(transconf_reg);
1640
1641 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1642 ;
1643
1644 /* enable normal */
1645
1646 temp = I915_READ(fdi_tx_reg);
1647 temp &= ~FDI_LINK_TRAIN_NONE;
1648 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1649 FDI_TX_ENHANCE_FRAME_ENABLE);
1650 I915_READ(fdi_tx_reg);
1651
1652 temp = I915_READ(fdi_rx_reg);
1653 temp &= ~FDI_LINK_TRAIN_NONE;
1654 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1655 FDI_RX_ENHANCE_FRAME_ENABLE);
1656 I915_READ(fdi_rx_reg);
1657
1658 /* wait one idle pattern time */
1659 udelay(100);
1660
Zhenyu Wang2c072452009-06-05 15:38:42 +08001661 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08001662
1663 intel_crtc_load_lut(crtc);
1664
1665 break;
1666 case DRM_MODE_DPMS_OFF:
1667 DRM_DEBUG("crtc %d dpms off\n", pipe);
1668
Zhenyu Wang24f119c2009-07-24 01:00:28 +08001669 i915_disable_vga(dev);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001670
1671 /* Disable display plane */
1672 temp = I915_READ(dspcntr_reg);
1673 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1674 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1675 /* Flush the plane changes */
1676 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1677 I915_READ(dspbase_reg);
1678 }
1679
1680 /* disable cpu pipe, disable after all planes disabled */
1681 temp = I915_READ(pipeconf_reg);
1682 if ((temp & PIPEACONF_ENABLE) != 0) {
1683 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1684 I915_READ(pipeconf_reg);
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001685 n = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001686 /* wait for cpu pipe off, pipe state */
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001687 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1688 n++;
1689 if (n < 60) {
1690 udelay(500);
1691 continue;
1692 } else {
1693 DRM_DEBUG("pipe %d off delay\n", pipe);
1694 break;
1695 }
1696 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08001697 } else
1698 DRM_DEBUG("crtc %d is disabled\n", pipe);
1699
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001700 if (HAS_eDP) {
1701 igdng_disable_pll_edp(crtc);
1702 }
1703
Zhenyu Wang2c072452009-06-05 15:38:42 +08001704 /* disable CPU FDI tx and PCH FDI rx */
1705 temp = I915_READ(fdi_tx_reg);
1706 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1707 I915_READ(fdi_tx_reg);
1708
1709 temp = I915_READ(fdi_rx_reg);
1710 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1711 I915_READ(fdi_rx_reg);
1712
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001713 udelay(100);
1714
Zhenyu Wang2c072452009-06-05 15:38:42 +08001715 /* still set train pattern 1 */
1716 temp = I915_READ(fdi_tx_reg);
1717 temp &= ~FDI_LINK_TRAIN_NONE;
1718 temp |= FDI_LINK_TRAIN_PATTERN_1;
1719 I915_WRITE(fdi_tx_reg, temp);
1720
1721 temp = I915_READ(fdi_rx_reg);
1722 temp &= ~FDI_LINK_TRAIN_NONE;
1723 temp |= FDI_LINK_TRAIN_PATTERN_1;
1724 I915_WRITE(fdi_rx_reg, temp);
1725
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001726 udelay(100);
1727
Zhenyu Wang2c072452009-06-05 15:38:42 +08001728 /* disable PCH transcoder */
1729 temp = I915_READ(transconf_reg);
1730 if ((temp & TRANS_ENABLE) != 0) {
1731 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1732 I915_READ(transconf_reg);
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001733 n = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001734 /* wait for PCH transcoder off, transcoder state */
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001735 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1736 n++;
1737 if (n < 60) {
1738 udelay(500);
1739 continue;
1740 } else {
1741 DRM_DEBUG("transcoder %d off delay\n", pipe);
1742 break;
1743 }
1744 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08001745 }
1746
1747 /* disable PCH DPLL */
1748 temp = I915_READ(pch_dpll_reg);
1749 if ((temp & DPLL_VCO_ENABLE) != 0) {
1750 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1751 I915_READ(pch_dpll_reg);
1752 }
1753
1754 temp = I915_READ(fdi_rx_reg);
1755 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1756 temp &= ~FDI_SEL_PCDCLK;
1757 temp &= ~FDI_RX_PLL_ENABLE;
1758 I915_WRITE(fdi_rx_reg, temp);
1759 I915_READ(fdi_rx_reg);
1760 }
1761
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001762 /* Disable CPU FDI TX PLL */
1763 temp = I915_READ(fdi_tx_reg);
1764 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1765 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1766 I915_READ(fdi_tx_reg);
1767 udelay(100);
1768 }
1769
1770 /* Disable PF */
1771 temp = I915_READ(pf_ctl_reg);
1772 if ((temp & PF_ENABLE) != 0) {
1773 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1774 I915_READ(pf_ctl_reg);
1775 }
1776 I915_WRITE(pf_win_size, 0);
1777
Zhenyu Wang2c072452009-06-05 15:38:42 +08001778 /* Wait for the clocks to turn off. */
1779 udelay(150);
1780 break;
1781 }
1782}
1783
1784static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1785{
1786 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08001787 struct drm_i915_private *dev_priv = dev->dev_private;
1788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1789 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07001790 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08001791 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
Jesse Barnes80824002009-09-10 15:28:06 -07001792 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1793 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
Jesse Barnes79e53942008-11-07 14:24:08 -08001794 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1795 u32 temp;
Jesse Barnes79e53942008-11-07 14:24:08 -08001796
1797 /* XXX: When our outputs are all unaware of DPMS modes other than off
1798 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1799 */
1800 switch (mode) {
1801 case DRM_MODE_DPMS_ON:
1802 case DRM_MODE_DPMS_STANDBY:
1803 case DRM_MODE_DPMS_SUSPEND:
1804 /* Enable the DPLL */
1805 temp = I915_READ(dpll_reg);
1806 if ((temp & DPLL_VCO_ENABLE) == 0) {
1807 I915_WRITE(dpll_reg, temp);
1808 I915_READ(dpll_reg);
1809 /* Wait for the clocks to stabilize. */
1810 udelay(150);
1811 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1812 I915_READ(dpll_reg);
1813 /* Wait for the clocks to stabilize. */
1814 udelay(150);
1815 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1816 I915_READ(dpll_reg);
1817 /* Wait for the clocks to stabilize. */
1818 udelay(150);
1819 }
1820
1821 /* Enable the pipe */
1822 temp = I915_READ(pipeconf_reg);
1823 if ((temp & PIPEACONF_ENABLE) == 0)
1824 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1825
1826 /* Enable the plane */
1827 temp = I915_READ(dspcntr_reg);
1828 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1829 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1830 /* Flush the plane changes */
1831 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1832 }
1833
1834 intel_crtc_load_lut(crtc);
1835
Jesse Barnes74dff282009-09-14 15:39:40 -07001836 if ((IS_I965G(dev) || plane == 0))
1837 intel_update_fbc(crtc, &crtc->mode);
Jesse Barnes80824002009-09-10 15:28:06 -07001838
Jesse Barnes79e53942008-11-07 14:24:08 -08001839 /* Give the overlay scaler a chance to enable if it's on this pipe */
1840 //intel_crtc_dpms_video(crtc, true); TODO
Shaohua Li7662c8b2009-06-26 11:23:55 +08001841 intel_update_watermarks(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001842 break;
1843 case DRM_MODE_DPMS_OFF:
Shaohua Li7662c8b2009-06-26 11:23:55 +08001844 intel_update_watermarks(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001845 /* Give the overlay scaler a chance to disable if it's on this pipe */
1846 //intel_crtc_dpms_video(crtc, FALSE); TODO
1847
Jesse Barnese70236a2009-09-21 10:42:27 -07001848 if (dev_priv->cfb_plane == plane &&
1849 dev_priv->display.disable_fbc)
1850 dev_priv->display.disable_fbc(dev);
Jesse Barnes80824002009-09-10 15:28:06 -07001851
Jesse Barnes79e53942008-11-07 14:24:08 -08001852 /* Disable the VGA plane that we never use */
Zhenyu Wang24f119c2009-07-24 01:00:28 +08001853 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001854
1855 /* Disable display plane */
1856 temp = I915_READ(dspcntr_reg);
1857 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1858 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1859 /* Flush the plane changes */
1860 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1861 I915_READ(dspbase_reg);
1862 }
1863
1864 if (!IS_I9XX(dev)) {
1865 /* Wait for vblank for the disable to take effect */
1866 intel_wait_for_vblank(dev);
1867 }
1868
1869 /* Next, disable display pipes */
1870 temp = I915_READ(pipeconf_reg);
1871 if ((temp & PIPEACONF_ENABLE) != 0) {
1872 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1873 I915_READ(pipeconf_reg);
1874 }
1875
1876 /* Wait for vblank for the disable to take effect. */
1877 intel_wait_for_vblank(dev);
1878
1879 temp = I915_READ(dpll_reg);
1880 if ((temp & DPLL_VCO_ENABLE) != 0) {
1881 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1882 I915_READ(dpll_reg);
1883 }
1884
1885 /* Wait for the clocks to turn off. */
1886 udelay(150);
1887 break;
1888 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08001889}
1890
1891/**
1892 * Sets the power management mode of the pipe and plane.
1893 *
1894 * This code should probably grow support for turning the cursor off and back
1895 * on appropriately at the same time as we're turning the pipe off/on.
1896 */
1897static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1898{
1899 struct drm_device *dev = crtc->dev;
Jesse Barnese70236a2009-09-21 10:42:27 -07001900 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001901 struct drm_i915_master_private *master_priv;
1902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1903 int pipe = intel_crtc->pipe;
1904 bool enabled;
1905
Jesse Barnese70236a2009-09-21 10:42:27 -07001906 dev_priv->display.dpms(crtc, mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08001907
Daniel Vetter65655d42009-08-11 16:05:31 +02001908 intel_crtc->dpms_mode = mode;
1909
Jesse Barnes79e53942008-11-07 14:24:08 -08001910 if (!dev->primary->master)
1911 return;
1912
1913 master_priv = dev->primary->master->driver_priv;
1914 if (!master_priv->sarea_priv)
1915 return;
1916
1917 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1918
1919 switch (pipe) {
1920 case 0:
1921 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1922 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1923 break;
1924 case 1:
1925 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1926 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1927 break;
1928 default:
1929 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1930 break;
1931 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001932}
1933
1934static void intel_crtc_prepare (struct drm_crtc *crtc)
1935{
1936 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1937 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1938}
1939
1940static void intel_crtc_commit (struct drm_crtc *crtc)
1941{
1942 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1943 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1944}
1945
1946void intel_encoder_prepare (struct drm_encoder *encoder)
1947{
1948 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1949 /* lvds has its own version of prepare see intel_lvds_prepare */
1950 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1951}
1952
1953void intel_encoder_commit (struct drm_encoder *encoder)
1954{
1955 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1956 /* lvds has its own version of commit see intel_lvds_commit */
1957 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1958}
1959
1960static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1961 struct drm_display_mode *mode,
1962 struct drm_display_mode *adjusted_mode)
1963{
Zhenyu Wang2c072452009-06-05 15:38:42 +08001964 struct drm_device *dev = crtc->dev;
1965 if (IS_IGDNG(dev)) {
1966 /* FDI link clock is fixed at 2.7G */
1967 if (mode->clock * 3 > 27000 * 4)
1968 return MODE_CLOCK_HIGH;
1969 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001970 return true;
1971}
1972
Jesse Barnese70236a2009-09-21 10:42:27 -07001973static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08001974{
Jesse Barnese70236a2009-09-21 10:42:27 -07001975 return 400000;
1976}
Jesse Barnes79e53942008-11-07 14:24:08 -08001977
Jesse Barnese70236a2009-09-21 10:42:27 -07001978static int i915_get_display_clock_speed(struct drm_device *dev)
1979{
1980 return 333000;
1981}
Jesse Barnes79e53942008-11-07 14:24:08 -08001982
Jesse Barnese70236a2009-09-21 10:42:27 -07001983static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
1984{
1985 return 200000;
1986}
Jesse Barnes79e53942008-11-07 14:24:08 -08001987
Jesse Barnese70236a2009-09-21 10:42:27 -07001988static int i915gm_get_display_clock_speed(struct drm_device *dev)
1989{
1990 u16 gcfgc = 0;
1991
1992 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
1993
1994 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08001995 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07001996 else {
1997 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
1998 case GC_DISPLAY_CLOCK_333_MHZ:
1999 return 333000;
2000 default:
2001 case GC_DISPLAY_CLOCK_190_200_MHZ:
2002 return 190000;
2003 }
2004 }
2005}
Jesse Barnes79e53942008-11-07 14:24:08 -08002006
Jesse Barnese70236a2009-09-21 10:42:27 -07002007static int i865_get_display_clock_speed(struct drm_device *dev)
2008{
2009 return 266000;
2010}
2011
2012static int i855_get_display_clock_speed(struct drm_device *dev)
2013{
2014 u16 hpllcc = 0;
2015 /* Assume that the hardware is in the high speed state. This
2016 * should be the default.
2017 */
2018 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2019 case GC_CLOCK_133_200:
2020 case GC_CLOCK_100_200:
2021 return 200000;
2022 case GC_CLOCK_166_250:
2023 return 250000;
2024 case GC_CLOCK_100_133:
2025 return 133000;
2026 }
2027
2028 /* Shouldn't happen */
2029 return 0;
2030}
2031
2032static int i830_get_display_clock_speed(struct drm_device *dev)
2033{
2034 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08002035}
2036
Jesse Barnes79e53942008-11-07 14:24:08 -08002037/**
2038 * Return the pipe currently connected to the panel fitter,
2039 * or -1 if the panel fitter is not present or not in use
2040 */
2041static int intel_panel_fitter_pipe (struct drm_device *dev)
2042{
2043 struct drm_i915_private *dev_priv = dev->dev_private;
2044 u32 pfit_control;
2045
2046 /* i830 doesn't have a panel fitter */
2047 if (IS_I830(dev))
2048 return -1;
2049
2050 pfit_control = I915_READ(PFIT_CONTROL);
2051
2052 /* See if the panel fitter is in use */
2053 if ((pfit_control & PFIT_ENABLE) == 0)
2054 return -1;
2055
2056 /* 965 can place panel fitter on either pipe */
2057 if (IS_I965G(dev))
2058 return (pfit_control >> 29) & 0x3;
2059
2060 /* older chips can only use pipe 1 */
2061 return 1;
2062}
2063
Zhenyu Wang2c072452009-06-05 15:38:42 +08002064struct fdi_m_n {
2065 u32 tu;
2066 u32 gmch_m;
2067 u32 gmch_n;
2068 u32 link_m;
2069 u32 link_n;
2070};
2071
2072static void
2073fdi_reduce_ratio(u32 *num, u32 *den)
2074{
2075 while (*num > 0xffffff || *den > 0xffffff) {
2076 *num >>= 1;
2077 *den >>= 1;
2078 }
2079}
2080
2081#define DATA_N 0x800000
2082#define LINK_N 0x80000
2083
2084static void
2085igdng_compute_m_n(int bytes_per_pixel, int nlanes,
2086 int pixel_clock, int link_clock,
2087 struct fdi_m_n *m_n)
2088{
2089 u64 temp;
2090
2091 m_n->tu = 64; /* default size */
2092
2093 temp = (u64) DATA_N * pixel_clock;
2094 temp = div_u64(temp, link_clock);
Andy Whitcroft956dba32009-07-01 15:20:59 +01002095 m_n->gmch_m = div_u64(temp * bytes_per_pixel, nlanes);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002096 m_n->gmch_n = DATA_N;
2097 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2098
2099 temp = (u64) LINK_N * pixel_clock;
2100 m_n->link_m = div_u64(temp, link_clock);
2101 m_n->link_n = LINK_N;
2102 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2103}
2104
2105
Shaohua Li7662c8b2009-06-26 11:23:55 +08002106struct intel_watermark_params {
2107 unsigned long fifo_size;
2108 unsigned long max_wm;
2109 unsigned long default_wm;
2110 unsigned long guard_size;
2111 unsigned long cacheline_size;
2112};
2113
2114/* IGD has different values for various configs */
2115static struct intel_watermark_params igd_display_wm = {
2116 IGD_DISPLAY_FIFO,
2117 IGD_MAX_WM,
2118 IGD_DFT_WM,
2119 IGD_GUARD_WM,
2120 IGD_FIFO_LINE_SIZE
2121};
2122static struct intel_watermark_params igd_display_hplloff_wm = {
2123 IGD_DISPLAY_FIFO,
2124 IGD_MAX_WM,
2125 IGD_DFT_HPLLOFF_WM,
2126 IGD_GUARD_WM,
2127 IGD_FIFO_LINE_SIZE
2128};
2129static struct intel_watermark_params igd_cursor_wm = {
2130 IGD_CURSOR_FIFO,
2131 IGD_CURSOR_MAX_WM,
2132 IGD_CURSOR_DFT_WM,
2133 IGD_CURSOR_GUARD_WM,
2134 IGD_FIFO_LINE_SIZE,
2135};
2136static struct intel_watermark_params igd_cursor_hplloff_wm = {
2137 IGD_CURSOR_FIFO,
2138 IGD_CURSOR_MAX_WM,
2139 IGD_CURSOR_DFT_WM,
2140 IGD_CURSOR_GUARD_WM,
2141 IGD_FIFO_LINE_SIZE
2142};
2143static struct intel_watermark_params i945_wm_info = {
Shaohua Li7662c8b2009-06-26 11:23:55 +08002144 I945_FIFO_SIZE,
2145 I915_MAX_WM,
2146 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002147 2,
2148 I915_FIFO_LINE_SIZE
2149};
2150static struct intel_watermark_params i915_wm_info = {
2151 I915_FIFO_SIZE,
2152 I915_MAX_WM,
2153 1,
2154 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08002155 I915_FIFO_LINE_SIZE
2156};
2157static struct intel_watermark_params i855_wm_info = {
2158 I855GM_FIFO_SIZE,
2159 I915_MAX_WM,
2160 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002161 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08002162 I830_FIFO_LINE_SIZE
2163};
2164static struct intel_watermark_params i830_wm_info = {
2165 I830_FIFO_SIZE,
2166 I915_MAX_WM,
2167 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002168 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08002169 I830_FIFO_LINE_SIZE
2170};
2171
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002172/**
2173 * intel_calculate_wm - calculate watermark level
2174 * @clock_in_khz: pixel clock
2175 * @wm: chip FIFO params
2176 * @pixel_size: display pixel size
2177 * @latency_ns: memory latency for the platform
2178 *
2179 * Calculate the watermark level (the level at which the display plane will
2180 * start fetching from memory again). Each chip has a different display
2181 * FIFO size and allocation, so the caller needs to figure that out and pass
2182 * in the correct intel_watermark_params structure.
2183 *
2184 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2185 * on the pixel size. When it reaches the watermark level, it'll start
2186 * fetching FIFO line sized based chunks from memory until the FIFO fills
2187 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2188 * will occur, and a display engine hang could result.
2189 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002190static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2191 struct intel_watermark_params *wm,
2192 int pixel_size,
2193 unsigned long latency_ns)
2194{
Jesse Barnes390c4dd2009-07-16 13:01:01 -07002195 long entries_required, wm_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002196
Jesse Barnesd6604672009-09-11 12:25:56 -07002197 /*
2198 * Note: we need to make sure we don't overflow for various clock &
2199 * latency values.
2200 * clocks go from a few thousand to several hundred thousand.
2201 * latency is usually a few thousand
2202 */
2203 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2204 1000;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002205 entries_required /= wm->cacheline_size;
2206
2207 DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
2208
2209 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2210
2211 DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002212
Jesse Barnes390c4dd2009-07-16 13:01:01 -07002213 /* Don't promote wm_size to unsigned... */
2214 if (wm_size > (long)wm->max_wm)
Shaohua Li7662c8b2009-06-26 11:23:55 +08002215 wm_size = wm->max_wm;
Jesse Barnes390c4dd2009-07-16 13:01:01 -07002216 if (wm_size <= 0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08002217 wm_size = wm->default_wm;
2218 return wm_size;
2219}
2220
2221struct cxsr_latency {
2222 int is_desktop;
2223 unsigned long fsb_freq;
2224 unsigned long mem_freq;
2225 unsigned long display_sr;
2226 unsigned long display_hpll_disable;
2227 unsigned long cursor_sr;
2228 unsigned long cursor_hpll_disable;
2229};
2230
2231static struct cxsr_latency cxsr_latency_table[] = {
2232 {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2233 {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2234 {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2235
2236 {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2237 {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2238 {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2239
2240 {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2241 {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2242 {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2243
2244 {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2245 {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2246 {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2247
2248 {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2249 {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2250 {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2251
2252 {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2253 {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2254 {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2255};
2256
2257static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2258 int mem)
2259{
2260 int i;
2261 struct cxsr_latency *latency;
2262
2263 if (fsb == 0 || mem == 0)
2264 return NULL;
2265
2266 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2267 latency = &cxsr_latency_table[i];
2268 if (is_desktop == latency->is_desktop &&
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05302269 fsb == latency->fsb_freq && mem == latency->mem_freq)
2270 return latency;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002271 }
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05302272
2273 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2274
2275 return NULL;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002276}
2277
2278static void igd_disable_cxsr(struct drm_device *dev)
2279{
2280 struct drm_i915_private *dev_priv = dev->dev_private;
2281 u32 reg;
2282
2283 /* deactivate cxsr */
2284 reg = I915_READ(DSPFW3);
2285 reg &= ~(IGD_SELF_REFRESH_EN);
2286 I915_WRITE(DSPFW3, reg);
2287 DRM_INFO("Big FIFO is disabled\n");
2288}
2289
2290static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2291 int pixel_size)
2292{
2293 struct drm_i915_private *dev_priv = dev->dev_private;
2294 u32 reg;
2295 unsigned long wm;
2296 struct cxsr_latency *latency;
2297
2298 latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
2299 dev_priv->mem_freq);
2300 if (!latency) {
2301 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2302 igd_disable_cxsr(dev);
2303 return;
2304 }
2305
2306 /* Display SR */
2307 wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
2308 latency->display_sr);
2309 reg = I915_READ(DSPFW1);
2310 reg &= 0x7fffff;
2311 reg |= wm << 23;
2312 I915_WRITE(DSPFW1, reg);
2313 DRM_DEBUG("DSPFW1 register is %x\n", reg);
2314
2315 /* cursor SR */
2316 wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
2317 latency->cursor_sr);
2318 reg = I915_READ(DSPFW3);
2319 reg &= ~(0x3f << 24);
2320 reg |= (wm & 0x3f) << 24;
2321 I915_WRITE(DSPFW3, reg);
2322
2323 /* Display HPLL off SR */
2324 wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
2325 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2326 reg = I915_READ(DSPFW3);
2327 reg &= 0xfffffe00;
2328 reg |= wm & 0x1ff;
2329 I915_WRITE(DSPFW3, reg);
2330
2331 /* cursor HPLL off SR */
2332 wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
2333 latency->cursor_hpll_disable);
2334 reg = I915_READ(DSPFW3);
2335 reg &= ~(0x3f << 16);
2336 reg |= (wm & 0x3f) << 16;
2337 I915_WRITE(DSPFW3, reg);
2338 DRM_DEBUG("DSPFW3 register is %x\n", reg);
2339
2340 /* activate cxsr */
2341 reg = I915_READ(DSPFW3);
2342 reg |= IGD_SELF_REFRESH_EN;
2343 I915_WRITE(DSPFW3, reg);
2344
2345 DRM_INFO("Big FIFO is enabled\n");
2346
2347 return;
2348}
2349
Jesse Barnesbcc24fb2009-08-31 10:24:31 -07002350/*
2351 * Latency for FIFO fetches is dependent on several factors:
2352 * - memory configuration (speed, channels)
2353 * - chipset
2354 * - current MCH state
2355 * It can be fairly high in some situations, so here we assume a fairly
2356 * pessimal value. It's a tradeoff between extra memory fetches (if we
2357 * set this value too high, the FIFO will fetch frequently to stay full)
2358 * and power consumption (set it too low to save power and we might see
2359 * FIFO underruns and display "flicker").
2360 *
2361 * A value of 5us seems to be a good balance; safe for very low end
2362 * platforms but not overly aggressive on lower latency configs.
2363 */
2364const static int latency_ns = 5000;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002365
Jesse Barnese70236a2009-09-21 10:42:27 -07002366static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002367{
2368 struct drm_i915_private *dev_priv = dev->dev_private;
2369 uint32_t dsparb = I915_READ(DSPARB);
2370 int size;
2371
Jesse Barnese70236a2009-09-21 10:42:27 -07002372 if (plane == 0)
Jesse Barnesf3601322009-07-22 12:54:59 -07002373 size = dsparb & 0x7f;
Jesse Barnese70236a2009-09-21 10:42:27 -07002374 else
2375 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2376 (dsparb & 0x7f);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002377
2378 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2379 size);
2380
2381 return size;
2382}
Shaohua Li7662c8b2009-06-26 11:23:55 +08002383
Jesse Barnese70236a2009-09-21 10:42:27 -07002384static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2385{
2386 struct drm_i915_private *dev_priv = dev->dev_private;
2387 uint32_t dsparb = I915_READ(DSPARB);
2388 int size;
2389
2390 if (plane == 0)
2391 size = dsparb & 0x1ff;
2392 else
2393 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2394 (dsparb & 0x1ff);
2395 size >>= 1; /* Convert to cachelines */
2396
2397 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2398 size);
2399
2400 return size;
2401}
2402
2403static int i845_get_fifo_size(struct drm_device *dev, int plane)
2404{
2405 struct drm_i915_private *dev_priv = dev->dev_private;
2406 uint32_t dsparb = I915_READ(DSPARB);
2407 int size;
2408
2409 size = dsparb & 0x7f;
2410 size >>= 2; /* Convert to cachelines */
2411
2412 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2413 size);
2414
2415 return size;
2416}
2417
2418static int i830_get_fifo_size(struct drm_device *dev, int plane)
2419{
2420 struct drm_i915_private *dev_priv = dev->dev_private;
2421 uint32_t dsparb = I915_READ(DSPARB);
2422 int size;
2423
2424 size = dsparb & 0x7f;
2425 size >>= 1; /* Convert to cachelines */
2426
2427 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2428 size);
2429
2430 return size;
2431}
2432
2433static void g4x_update_wm(struct drm_device *dev, int unused, int unused2,
2434 int unused3, int unused4)
Jesse Barnes652c3932009-08-17 13:31:43 -07002435{
2436 struct drm_i915_private *dev_priv = dev->dev_private;
2437 u32 fw_blc_self = I915_READ(FW_BLC_SELF);
2438
2439 if (i915_powersave)
2440 fw_blc_self |= FW_BLC_SELF_EN;
2441 else
2442 fw_blc_self &= ~FW_BLC_SELF_EN;
2443 I915_WRITE(FW_BLC_SELF, fw_blc_self);
2444}
2445
Jesse Barnese70236a2009-09-21 10:42:27 -07002446static void i965_update_wm(struct drm_device *dev, int unused, int unused2,
2447 int unused3, int unused4)
Shaohua Li7662c8b2009-06-26 11:23:55 +08002448{
2449 struct drm_i915_private *dev_priv = dev->dev_private;
2450
2451 DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
2452
2453 /* 965 has limitations... */
2454 I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
2455 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2456}
2457
2458static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2459 int planeb_clock, int sr_hdisplay, int pixel_size)
2460{
2461 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002462 uint32_t fwater_lo;
2463 uint32_t fwater_hi;
2464 int total_size, cacheline_size, cwm, srwm = 1;
2465 int planea_wm, planeb_wm;
2466 struct intel_watermark_params planea_params, planeb_params;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002467 unsigned long line_time_us;
2468 int sr_clock, sr_entries = 0;
2469
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002470 /* Create copies of the base settings for each pipe */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002471 if (IS_I965GM(dev) || IS_I945GM(dev))
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002472 planea_params = planeb_params = i945_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002473 else if (IS_I9XX(dev))
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002474 planea_params = planeb_params = i915_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002475 else
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002476 planea_params = planeb_params = i855_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002477
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002478 /* Grab a couple of global values before we overwrite them */
2479 total_size = planea_params.fifo_size;
2480 cacheline_size = planea_params.cacheline_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002481
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002482 /* Update per-plane FIFO sizes */
Jesse Barnese70236a2009-09-21 10:42:27 -07002483 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2484 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002485
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002486 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2487 pixel_size, latency_ns);
2488 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2489 pixel_size, latency_ns);
2490 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002491
2492 /*
2493 * Overlay gets an aggressive default since video jitter is bad.
2494 */
2495 cwm = 2;
2496
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002497 /* Calc sr entries for one plane configs */
Jesse Barnes652c3932009-08-17 13:31:43 -07002498 if (HAS_FW_BLC(dev) && sr_hdisplay &&
2499 (!planea_clock || !planeb_clock)) {
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002500 /* self-refresh has much higher latency */
2501 const static int sr_latency_ns = 6000;
2502
Shaohua Li7662c8b2009-06-26 11:23:55 +08002503 sr_clock = planea_clock ? planea_clock : planeb_clock;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002504 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2505
2506 /* Use ns/us then divide to preserve precision */
2507 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2508 pixel_size * sr_hdisplay) / 1000;
2509 sr_entries = roundup(sr_entries / cacheline_size, 1);
2510 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2511 srwm = total_size - sr_entries;
2512 if (srwm < 0)
2513 srwm = 1;
Jesse Barnes652c3932009-08-17 13:31:43 -07002514 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
Shaohua Li7662c8b2009-06-26 11:23:55 +08002515 }
2516
2517 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002518 planea_wm, planeb_wm, cwm, srwm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002519
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002520 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2521 fwater_hi = (cwm & 0x1f);
2522
2523 /* Set request length to 8 cachelines per fetch */
2524 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2525 fwater_hi = fwater_hi | (1 << 8);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002526
2527 I915_WRITE(FW_BLC, fwater_lo);
2528 I915_WRITE(FW_BLC2, fwater_hi);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002529}
2530
Jesse Barnese70236a2009-09-21 10:42:27 -07002531static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2532 int unused2, int pixel_size)
Shaohua Li7662c8b2009-06-26 11:23:55 +08002533{
2534 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf3601322009-07-22 12:54:59 -07002535 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002536 int planea_wm;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002537
Jesse Barnese70236a2009-09-21 10:42:27 -07002538 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002539
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002540 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2541 pixel_size, latency_ns);
Jesse Barnesf3601322009-07-22 12:54:59 -07002542 fwater_lo |= (3<<8) | planea_wm;
2543
2544 DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002545
2546 I915_WRITE(FW_BLC, fwater_lo);
2547}
2548
2549/**
2550 * intel_update_watermarks - update FIFO watermark values based on current modes
2551 *
2552 * Calculate watermark values for the various WM regs based on current mode
2553 * and plane configuration.
2554 *
2555 * There are several cases to deal with here:
2556 * - normal (i.e. non-self-refresh)
2557 * - self-refresh (SR) mode
2558 * - lines are large relative to FIFO size (buffer can hold up to 2)
2559 * - lines are small relative to FIFO size (buffer can hold more than 2
2560 * lines), so need to account for TLB latency
2561 *
2562 * The normal calculation is:
2563 * watermark = dotclock * bytes per pixel * latency
2564 * where latency is platform & configuration dependent (we assume pessimal
2565 * values here).
2566 *
2567 * The SR calculation is:
2568 * watermark = (trunc(latency/line time)+1) * surface width *
2569 * bytes per pixel
2570 * where
2571 * line time = htotal / dotclock
2572 * and latency is assumed to be high, as above.
2573 *
2574 * The final value programmed to the register should always be rounded up,
2575 * and include an extra 2 entries to account for clock crossings.
2576 *
2577 * We don't use the sprite, so we can ignore that. And on Crestline we have
2578 * to set the non-SR watermarks to 8.
2579 */
2580static void intel_update_watermarks(struct drm_device *dev)
2581{
Jesse Barnese70236a2009-09-21 10:42:27 -07002582 struct drm_i915_private *dev_priv = dev->dev_private;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002583 struct drm_crtc *crtc;
2584 struct intel_crtc *intel_crtc;
2585 int sr_hdisplay = 0;
2586 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2587 int enabled = 0, pixel_size = 0;
2588
Zhenyu Wangc03342f2009-09-29 11:01:23 +08002589 if (!dev_priv->display.update_wm)
2590 return;
2591
Shaohua Li7662c8b2009-06-26 11:23:55 +08002592 /* Get the clock config from both planes */
2593 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2594 intel_crtc = to_intel_crtc(crtc);
2595 if (crtc->enabled) {
2596 enabled++;
2597 if (intel_crtc->plane == 0) {
2598 DRM_DEBUG("plane A (pipe %d) clock: %d\n",
2599 intel_crtc->pipe, crtc->mode.clock);
2600 planea_clock = crtc->mode.clock;
2601 } else {
2602 DRM_DEBUG("plane B (pipe %d) clock: %d\n",
2603 intel_crtc->pipe, crtc->mode.clock);
2604 planeb_clock = crtc->mode.clock;
2605 }
2606 sr_hdisplay = crtc->mode.hdisplay;
2607 sr_clock = crtc->mode.clock;
2608 if (crtc->fb)
2609 pixel_size = crtc->fb->bits_per_pixel / 8;
2610 else
2611 pixel_size = 4; /* by default */
2612 }
2613 }
2614
2615 if (enabled <= 0)
2616 return;
2617
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002618 /* Single plane configs can enable self refresh */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002619 if (enabled == 1 && IS_IGD(dev))
2620 igd_enable_cxsr(dev, sr_clock, pixel_size);
2621 else if (IS_IGD(dev))
2622 igd_disable_cxsr(dev);
2623
Jesse Barnese70236a2009-09-21 10:42:27 -07002624 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2625 sr_hdisplay, pixel_size);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002626}
2627
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002628static int intel_crtc_mode_set(struct drm_crtc *crtc,
2629 struct drm_display_mode *mode,
2630 struct drm_display_mode *adjusted_mode,
2631 int x, int y,
2632 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002633{
2634 struct drm_device *dev = crtc->dev;
2635 struct drm_i915_private *dev_priv = dev->dev_private;
2636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2637 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07002638 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08002639 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2640 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2641 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
Jesse Barnes80824002009-09-10 15:28:06 -07002642 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
Jesse Barnes79e53942008-11-07 14:24:08 -08002643 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2644 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2645 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2646 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2647 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2648 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2649 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
Jesse Barnes80824002009-09-10 15:28:06 -07002650 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2651 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
Jesse Barnes79e53942008-11-07 14:24:08 -08002652 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
Kristian Høgsberg43565a02009-02-13 20:56:52 -05002653 int refclk, num_outputs = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07002654 intel_clock_t clock, reduced_clock;
2655 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2656 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002657 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002658 bool is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08002659 struct drm_mode_config *mode_config = &dev->mode_config;
2660 struct drm_connector *connector;
Ma Lingd4906092009-03-18 20:13:27 +08002661 const intel_limit_t *limit;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002662 int ret;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002663 struct fdi_m_n m_n = {0};
2664 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2665 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2666 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2667 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2668 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2669 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2670 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
Zhenyu Wang541998a2009-06-05 15:38:44 +08002671 int lvds_reg = LVDS;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002672 u32 temp;
2673 int sdvo_pixel_multiply;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002674 int target_clock;
Jesse Barnes79e53942008-11-07 14:24:08 -08002675
2676 drm_vblank_pre_modeset(dev, pipe);
2677
2678 list_for_each_entry(connector, &mode_config->connector_list, head) {
2679 struct intel_output *intel_output = to_intel_output(connector);
2680
2681 if (!connector->encoder || connector->encoder->crtc != crtc)
2682 continue;
2683
2684 switch (intel_output->type) {
2685 case INTEL_OUTPUT_LVDS:
2686 is_lvds = true;
2687 break;
2688 case INTEL_OUTPUT_SDVO:
Eric Anholt7d573822009-01-02 13:33:00 -08002689 case INTEL_OUTPUT_HDMI:
Jesse Barnes79e53942008-11-07 14:24:08 -08002690 is_sdvo = true;
Jesse Barnese2f0ba92009-02-02 15:11:52 -08002691 if (intel_output->needs_tv_clock)
2692 is_tv = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08002693 break;
2694 case INTEL_OUTPUT_DVO:
2695 is_dvo = true;
2696 break;
2697 case INTEL_OUTPUT_TVOUT:
2698 is_tv = true;
2699 break;
2700 case INTEL_OUTPUT_ANALOG:
2701 is_crt = true;
2702 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002703 case INTEL_OUTPUT_DISPLAYPORT:
2704 is_dp = true;
2705 break;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002706 case INTEL_OUTPUT_EDP:
2707 is_edp = true;
2708 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08002709 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05002710
2711 num_outputs++;
Jesse Barnes79e53942008-11-07 14:24:08 -08002712 }
2713
Kristian Høgsberg43565a02009-02-13 20:56:52 -05002714 if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2715 refclk = dev_priv->lvds_ssc_freq * 1000;
2716 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
2717 } else if (IS_I9XX(dev)) {
Jesse Barnes79e53942008-11-07 14:24:08 -08002718 refclk = 96000;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002719 if (IS_IGDNG(dev))
2720 refclk = 120000; /* 120Mhz refclk */
Jesse Barnes79e53942008-11-07 14:24:08 -08002721 } else {
2722 refclk = 48000;
2723 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002724
Jesse Barnes79e53942008-11-07 14:24:08 -08002725
Ma Lingd4906092009-03-18 20:13:27 +08002726 /*
2727 * Returns a set of divisors for the desired target clock with the given
2728 * refclk, or FALSE. The returned values represent the clock equation:
2729 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2730 */
2731 limit = intel_limit(crtc);
2732 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08002733 if (!ok) {
2734 DRM_ERROR("Couldn't find PLL settings for mode!\n");
Chris Wilson1f803ee2009-06-06 09:45:59 +01002735 drm_vblank_post_modeset(dev, pipe);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002736 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002737 }
2738
Jesse Barnes652c3932009-08-17 13:31:43 -07002739 if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) {
2740 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2741 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2742 (adjusted_mode->clock*3/4),
2743 refclk,
2744 &reduced_clock);
2745 }
2746
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08002747 /* SDVO TV has fixed PLL values depend on its clock range,
2748 this mirrors vbios setting. */
2749 if (is_sdvo && is_tv) {
2750 if (adjusted_mode->clock >= 100000
2751 && adjusted_mode->clock < 140500) {
2752 clock.p1 = 2;
2753 clock.p2 = 10;
2754 clock.n = 3;
2755 clock.m1 = 16;
2756 clock.m2 = 8;
2757 } else if (adjusted_mode->clock >= 140500
2758 && adjusted_mode->clock <= 200000) {
2759 clock.p1 = 1;
2760 clock.p2 = 10;
2761 clock.n = 6;
2762 clock.m1 = 12;
2763 clock.m2 = 8;
2764 }
2765 }
2766
Zhenyu Wang2c072452009-06-05 15:38:42 +08002767 /* FDI link */
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002768 if (IS_IGDNG(dev)) {
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002769 int lane, link_bw;
2770 /* eDP doesn't require FDI link, so just set DP M/N
2771 according to current link config */
2772 if (is_edp) {
2773 struct drm_connector *edp;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002774 target_clock = mode->clock;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002775 edp = intel_pipe_get_output(crtc);
2776 intel_edp_link_config(to_intel_output(edp),
2777 &lane, &link_bw);
2778 } else {
2779 /* DP over FDI requires target mode clock
2780 instead of link clock */
2781 if (is_dp)
2782 target_clock = mode->clock;
2783 else
2784 target_clock = adjusted_mode->clock;
2785 lane = 4;
2786 link_bw = 270000;
2787 }
2788 igdng_compute_m_n(3, lane, target_clock,
2789 link_bw, &m_n);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002790 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08002791
Jesse Barnes652c3932009-08-17 13:31:43 -07002792 if (IS_IGD(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +08002793 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
Jesse Barnes652c3932009-08-17 13:31:43 -07002794 if (has_reduced_clock)
2795 fp2 = (1 << reduced_clock.n) << 16 |
2796 reduced_clock.m1 << 8 | reduced_clock.m2;
2797 } else {
Shaohua Li21778322009-02-23 15:19:16 +08002798 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
Jesse Barnes652c3932009-08-17 13:31:43 -07002799 if (has_reduced_clock)
2800 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
2801 reduced_clock.m2;
2802 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002803
Zhenyu Wang2c072452009-06-05 15:38:42 +08002804 if (!IS_IGDNG(dev))
2805 dpll = DPLL_VGA_MODE_DIS;
2806
Jesse Barnes79e53942008-11-07 14:24:08 -08002807 if (IS_I9XX(dev)) {
2808 if (is_lvds)
2809 dpll |= DPLLB_MODE_LVDS;
2810 else
2811 dpll |= DPLLB_MODE_DAC_SERIAL;
2812 if (is_sdvo) {
2813 dpll |= DPLL_DVO_HIGH_SPEED;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002814 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
Sean Young942642a2009-08-06 17:35:50 +08002815 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08002816 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002817 else if (IS_IGDNG(dev))
2818 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08002819 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002820 if (is_dp)
2821 dpll |= DPLL_DVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08002822
2823 /* compute bitmask from p1 value */
Shaohua Li21778322009-02-23 15:19:16 +08002824 if (IS_IGD(dev))
2825 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002826 else {
Shaohua Li21778322009-02-23 15:19:16 +08002827 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002828 /* also FPA1 */
2829 if (IS_IGDNG(dev))
2830 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Jesse Barnes652c3932009-08-17 13:31:43 -07002831 if (IS_G4X(dev) && has_reduced_clock)
2832 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002833 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002834 switch (clock.p2) {
2835 case 5:
2836 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
2837 break;
2838 case 7:
2839 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
2840 break;
2841 case 10:
2842 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
2843 break;
2844 case 14:
2845 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
2846 break;
2847 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08002848 if (IS_I965G(dev) && !IS_IGDNG(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08002849 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2850 } else {
2851 if (is_lvds) {
2852 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2853 } else {
2854 if (clock.p1 == 2)
2855 dpll |= PLL_P1_DIVIDE_BY_TWO;
2856 else
2857 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2858 if (clock.p2 == 4)
2859 dpll |= PLL_P2_DIVIDE_BY_4;
2860 }
2861 }
2862
Kristian Høgsberg43565a02009-02-13 20:56:52 -05002863 if (is_sdvo && is_tv)
2864 dpll |= PLL_REF_INPUT_TVCLKINBC;
2865 else if (is_tv)
Jesse Barnes79e53942008-11-07 14:24:08 -08002866 /* XXX: just matching BIOS for now */
Kristian Høgsberg43565a02009-02-13 20:56:52 -05002867 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
Jesse Barnes79e53942008-11-07 14:24:08 -08002868 dpll |= 3;
Kristian Høgsberg43565a02009-02-13 20:56:52 -05002869 else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
2870 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08002871 else
2872 dpll |= PLL_REF_INPUT_DREFCLK;
2873
2874 /* setup pipeconf */
2875 pipeconf = I915_READ(pipeconf_reg);
2876
2877 /* Set up the display plane register */
2878 dspcntr = DISPPLANE_GAMMA_ENABLE;
2879
Zhenyu Wang2c072452009-06-05 15:38:42 +08002880 /* IGDNG's plane is forced to pipe, bit 24 is to
2881 enable color space conversion */
2882 if (!IS_IGDNG(dev)) {
2883 if (pipe == 0)
Jesse Barnes80824002009-09-10 15:28:06 -07002884 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002885 else
2886 dspcntr |= DISPPLANE_SEL_PIPE_B;
2887 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002888
2889 if (pipe == 0 && !IS_I965G(dev)) {
2890 /* Enable pixel doubling when the dot clock is > 90% of the (display)
2891 * core speed.
2892 *
2893 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
2894 * pipe == 0 check?
2895 */
Jesse Barnese70236a2009-09-21 10:42:27 -07002896 if (mode->clock >
2897 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
Jesse Barnes79e53942008-11-07 14:24:08 -08002898 pipeconf |= PIPEACONF_DOUBLE_WIDE;
2899 else
2900 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
2901 }
2902
2903 dspcntr |= DISPLAY_PLANE_ENABLE;
2904 pipeconf |= PIPEACONF_ENABLE;
2905 dpll |= DPLL_VCO_ENABLE;
2906
2907
2908 /* Disable the panel fitter if it was on our pipe */
Zhenyu Wang2c072452009-06-05 15:38:42 +08002909 if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08002910 I915_WRITE(PFIT_CONTROL, 0);
2911
2912 DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
2913 drm_mode_debug_printmodeline(mode);
2914
Zhenyu Wang2c072452009-06-05 15:38:42 +08002915 /* assign to IGDNG registers */
2916 if (IS_IGDNG(dev)) {
2917 fp_reg = pch_fp_reg;
2918 dpll_reg = pch_dpll_reg;
2919 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002920
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002921 if (is_edp) {
2922 igdng_disable_pll_edp(crtc);
2923 } else if ((dpll & DPLL_VCO_ENABLE)) {
Jesse Barnes79e53942008-11-07 14:24:08 -08002924 I915_WRITE(fp_reg, fp);
2925 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
2926 I915_READ(dpll_reg);
2927 udelay(150);
2928 }
2929
2930 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
2931 * This is an exception to the general rule that mode_set doesn't turn
2932 * things on.
2933 */
2934 if (is_lvds) {
Zhenyu Wang541998a2009-06-05 15:38:44 +08002935 u32 lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -08002936
Zhenyu Wang541998a2009-06-05 15:38:44 +08002937 if (IS_IGDNG(dev))
2938 lvds_reg = PCH_LVDS;
2939
2940 lvds = I915_READ(lvds_reg);
Jesse Barnes79e53942008-11-07 14:24:08 -08002941 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08002942 /* set the corresponsding LVDS_BORDER bit */
2943 lvds |= dev_priv->lvds_border_bits;
Jesse Barnes79e53942008-11-07 14:24:08 -08002944 /* Set the B0-B3 data pairs corresponding to whether we're going to
2945 * set the DPLLs for dual-channel mode or not.
2946 */
2947 if (clock.p2 == 7)
2948 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
2949 else
2950 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
2951
2952 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
2953 * appropriately here, but we need to look more thoroughly into how
2954 * panels behave in the two modes.
2955 */
2956
Zhenyu Wang541998a2009-06-05 15:38:44 +08002957 I915_WRITE(lvds_reg, lvds);
2958 I915_READ(lvds_reg);
Jesse Barnes79e53942008-11-07 14:24:08 -08002959 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002960 if (is_dp)
2961 intel_dp_set_m_n(crtc, mode, adjusted_mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08002962
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002963 if (!is_edp) {
2964 I915_WRITE(fp_reg, fp);
Jesse Barnes79e53942008-11-07 14:24:08 -08002965 I915_WRITE(dpll_reg, dpll);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002966 I915_READ(dpll_reg);
2967 /* Wait for the clocks to stabilize. */
2968 udelay(150);
2969
2970 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
Zhao Yakuibb66c512009-09-10 15:45:49 +08002971 if (is_sdvo) {
2972 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2973 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002974 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
Zhao Yakuibb66c512009-09-10 15:45:49 +08002975 } else
2976 I915_WRITE(dpll_md_reg, 0);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002977 } else {
2978 /* write it again -- the BIOS does, after all */
2979 I915_WRITE(dpll_reg, dpll);
2980 }
2981 I915_READ(dpll_reg);
2982 /* Wait for the clocks to stabilize. */
2983 udelay(150);
Jesse Barnes79e53942008-11-07 14:24:08 -08002984 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002985
Jesse Barnes652c3932009-08-17 13:31:43 -07002986 if (is_lvds && has_reduced_clock && i915_powersave) {
2987 I915_WRITE(fp_reg + 4, fp2);
2988 intel_crtc->lowfreq_avail = true;
2989 if (HAS_PIPE_CXSR(dev)) {
2990 DRM_DEBUG("enabling CxSR downclocking\n");
2991 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
2992 }
2993 } else {
2994 I915_WRITE(fp_reg + 4, fp);
2995 intel_crtc->lowfreq_avail = false;
2996 if (HAS_PIPE_CXSR(dev)) {
2997 DRM_DEBUG("disabling CxSR downclocking\n");
2998 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
2999 }
3000 }
3001
Jesse Barnes79e53942008-11-07 14:24:08 -08003002 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3003 ((adjusted_mode->crtc_htotal - 1) << 16));
3004 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3005 ((adjusted_mode->crtc_hblank_end - 1) << 16));
3006 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3007 ((adjusted_mode->crtc_hsync_end - 1) << 16));
3008 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3009 ((adjusted_mode->crtc_vtotal - 1) << 16));
3010 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3011 ((adjusted_mode->crtc_vblank_end - 1) << 16));
3012 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3013 ((adjusted_mode->crtc_vsync_end - 1) << 16));
3014 /* pipesrc and dspsize control the size that is scaled from, which should
3015 * always be the user's requested size.
3016 */
Zhenyu Wang2c072452009-06-05 15:38:42 +08003017 if (!IS_IGDNG(dev)) {
3018 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3019 (mode->hdisplay - 1));
3020 I915_WRITE(dsppos_reg, 0);
3021 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003022 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
Zhenyu Wang2c072452009-06-05 15:38:42 +08003023
3024 if (IS_IGDNG(dev)) {
3025 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3026 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3027 I915_WRITE(link_m1_reg, m_n.link_m);
3028 I915_WRITE(link_n1_reg, m_n.link_n);
3029
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003030 if (is_edp) {
3031 igdng_set_pll_edp(crtc, adjusted_mode->clock);
3032 } else {
3033 /* enable FDI RX PLL too */
3034 temp = I915_READ(fdi_rx_reg);
3035 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3036 udelay(200);
3037 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08003038 }
3039
Jesse Barnes79e53942008-11-07 14:24:08 -08003040 I915_WRITE(pipeconf_reg, pipeconf);
3041 I915_READ(pipeconf_reg);
3042
3043 intel_wait_for_vblank(dev);
3044
Zhenyu Wang553bd142009-09-02 10:57:52 +08003045 if (IS_IGDNG(dev)) {
3046 /* enable address swizzle for tiling buffer */
3047 temp = I915_READ(DISP_ARB_CTL);
3048 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3049 }
3050
Jesse Barnes79e53942008-11-07 14:24:08 -08003051 I915_WRITE(dspcntr_reg, dspcntr);
3052
3053 /* Flush the plane changes */
Chris Wilson5c3b82e2009-02-11 13:25:09 +00003054 ret = intel_pipe_set_base(crtc, x, y, old_fb);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003055
Jesse Barnes74dff282009-09-14 15:39:40 -07003056 if ((IS_I965G(dev) || plane == 0))
3057 intel_update_fbc(crtc, &crtc->mode);
Jesse Barnese70236a2009-09-21 10:42:27 -07003058
Shaohua Li7662c8b2009-06-26 11:23:55 +08003059 intel_update_watermarks(dev);
3060
Jesse Barnes79e53942008-11-07 14:24:08 -08003061 drm_vblank_post_modeset(dev, pipe);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00003062
Chris Wilson1f803ee2009-06-06 09:45:59 +01003063 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08003064}
3065
3066/** Loads the palette/gamma unit for the CRTC with the prepared values */
3067void intel_crtc_load_lut(struct drm_crtc *crtc)
3068{
3069 struct drm_device *dev = crtc->dev;
3070 struct drm_i915_private *dev_priv = dev->dev_private;
3071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3072 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3073 int i;
3074
3075 /* The clocks have to be on to load the palette. */
3076 if (!crtc->enabled)
3077 return;
3078
Zhenyu Wang2c072452009-06-05 15:38:42 +08003079 /* use legacy palette for IGDNG */
3080 if (IS_IGDNG(dev))
3081 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3082 LGC_PALETTE_B;
3083
Jesse Barnes79e53942008-11-07 14:24:08 -08003084 for (i = 0; i < 256; i++) {
3085 I915_WRITE(palreg + 4 * i,
3086 (intel_crtc->lut_r[i] << 16) |
3087 (intel_crtc->lut_g[i] << 8) |
3088 intel_crtc->lut_b[i]);
3089 }
3090}
3091
3092static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3093 struct drm_file *file_priv,
3094 uint32_t handle,
3095 uint32_t width, uint32_t height)
3096{
3097 struct drm_device *dev = crtc->dev;
3098 struct drm_i915_private *dev_priv = dev->dev_private;
3099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3100 struct drm_gem_object *bo;
3101 struct drm_i915_gem_object *obj_priv;
3102 int pipe = intel_crtc->pipe;
3103 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3104 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
Jesse Barnes14b60392009-05-20 16:47:08 -04003105 uint32_t temp = I915_READ(control);
Jesse Barnes79e53942008-11-07 14:24:08 -08003106 size_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05003107 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08003108
3109 DRM_DEBUG("\n");
3110
3111 /* if we want to turn off the cursor ignore width and height */
3112 if (!handle) {
3113 DRM_DEBUG("cursor off\n");
Jesse Barnes14b60392009-05-20 16:47:08 -04003114 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3115 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3116 temp |= CURSOR_MODE_DISABLE;
3117 } else {
3118 temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3119 }
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05003120 addr = 0;
3121 bo = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10003122 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05003123 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08003124 }
3125
3126 /* Currently we only support 64x64 cursors */
3127 if (width != 64 || height != 64) {
3128 DRM_ERROR("we currently only support 64x64 cursors\n");
3129 return -EINVAL;
3130 }
3131
3132 bo = drm_gem_object_lookup(dev, file_priv, handle);
3133 if (!bo)
3134 return -ENOENT;
3135
3136 obj_priv = bo->driver_private;
3137
3138 if (bo->size < width * height * 4) {
3139 DRM_ERROR("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10003140 ret = -ENOMEM;
3141 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08003142 }
3143
Dave Airlie71acb5e2008-12-30 20:31:46 +10003144 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05003145 mutex_lock(&dev->struct_mutex);
Dave Airlie71acb5e2008-12-30 20:31:46 +10003146 if (!dev_priv->cursor_needs_physical) {
3147 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3148 if (ret) {
3149 DRM_ERROR("failed to pin cursor bo\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05003150 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10003151 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003152 addr = obj_priv->gtt_offset;
Dave Airlie71acb5e2008-12-30 20:31:46 +10003153 } else {
3154 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3155 if (ret) {
3156 DRM_ERROR("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05003157 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10003158 }
3159 addr = obj_priv->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05003160 }
3161
Jesse Barnes14b60392009-05-20 16:47:08 -04003162 if (!IS_I9XX(dev))
3163 I915_WRITE(CURSIZE, (height << 12) | width);
3164
3165 /* Hooray for CUR*CNTR differences */
3166 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3167 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3168 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3169 temp |= (pipe << 28); /* Connect to correct pipe */
3170 } else {
3171 temp &= ~(CURSOR_FORMAT_MASK);
3172 temp |= CURSOR_ENABLE;
3173 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3174 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003175
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05003176 finish:
Jesse Barnes79e53942008-11-07 14:24:08 -08003177 I915_WRITE(control, temp);
3178 I915_WRITE(base, addr);
3179
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05003180 if (intel_crtc->cursor_bo) {
Dave Airlie71acb5e2008-12-30 20:31:46 +10003181 if (dev_priv->cursor_needs_physical) {
3182 if (intel_crtc->cursor_bo != bo)
3183 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3184 } else
3185 i915_gem_object_unpin(intel_crtc->cursor_bo);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05003186 drm_gem_object_unreference(intel_crtc->cursor_bo);
3187 }
Jesse Barnes80824002009-09-10 15:28:06 -07003188
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05003189 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05003190
3191 intel_crtc->cursor_addr = addr;
3192 intel_crtc->cursor_bo = bo;
3193
Jesse Barnes79e53942008-11-07 14:24:08 -08003194 return 0;
Dave Airlie34b8686e2009-01-15 14:03:07 +10003195fail:
3196 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05003197fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10003198 drm_gem_object_unreference(bo);
3199 mutex_unlock(&dev->struct_mutex);
3200 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08003201}
3202
3203static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3204{
3205 struct drm_device *dev = crtc->dev;
3206 struct drm_i915_private *dev_priv = dev->dev_private;
3207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07003208 struct intel_framebuffer *intel_fb;
Jesse Barnes79e53942008-11-07 14:24:08 -08003209 int pipe = intel_crtc->pipe;
3210 uint32_t temp = 0;
3211 uint32_t adder;
3212
Jesse Barnes652c3932009-08-17 13:31:43 -07003213 if (crtc->fb) {
3214 intel_fb = to_intel_framebuffer(crtc->fb);
3215 intel_mark_busy(dev, intel_fb->obj);
3216 }
3217
Jesse Barnes79e53942008-11-07 14:24:08 -08003218 if (x < 0) {
Keith Packard2245fda2009-05-30 20:42:29 -07003219 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08003220 x = -x;
3221 }
3222 if (y < 0) {
Keith Packard2245fda2009-05-30 20:42:29 -07003223 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08003224 y = -y;
3225 }
3226
Keith Packard2245fda2009-05-30 20:42:29 -07003227 temp |= x << CURSOR_X_SHIFT;
3228 temp |= y << CURSOR_Y_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08003229
3230 adder = intel_crtc->cursor_addr;
3231 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3232 I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3233
3234 return 0;
3235}
3236
3237/** Sets the color ramps on behalf of RandR */
3238void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3239 u16 blue, int regno)
3240{
3241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3242
3243 intel_crtc->lut_r[regno] = red >> 8;
3244 intel_crtc->lut_g[regno] = green >> 8;
3245 intel_crtc->lut_b[regno] = blue >> 8;
3246}
3247
Dave Airlieb8c00ac2009-10-06 13:54:01 +10003248void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3249 u16 *blue, int regno)
3250{
3251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3252
3253 *red = intel_crtc->lut_r[regno] << 8;
3254 *green = intel_crtc->lut_g[regno] << 8;
3255 *blue = intel_crtc->lut_b[regno] << 8;
3256}
3257
Jesse Barnes79e53942008-11-07 14:24:08 -08003258static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3259 u16 *blue, uint32_t size)
3260{
3261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3262 int i;
3263
3264 if (size != 256)
3265 return;
3266
3267 for (i = 0; i < 256; i++) {
3268 intel_crtc->lut_r[i] = red[i] >> 8;
3269 intel_crtc->lut_g[i] = green[i] >> 8;
3270 intel_crtc->lut_b[i] = blue[i] >> 8;
3271 }
3272
3273 intel_crtc_load_lut(crtc);
3274}
3275
3276/**
3277 * Get a pipe with a simple mode set on it for doing load-based monitor
3278 * detection.
3279 *
3280 * It will be up to the load-detect code to adjust the pipe as appropriate for
3281 * its requirements. The pipe will be connected to no other outputs.
3282 *
3283 * Currently this code will only succeed if there is a pipe with no outputs
3284 * configured for it. In the future, it could choose to temporarily disable
3285 * some outputs to free up a pipe for its use.
3286 *
3287 * \return crtc, or NULL if no pipes are available.
3288 */
3289
3290/* VESA 640x480x72Hz mode to set on the pipe */
3291static struct drm_display_mode load_detect_mode = {
3292 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3293 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3294};
3295
3296struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3297 struct drm_display_mode *mode,
3298 int *dpms_mode)
3299{
3300 struct intel_crtc *intel_crtc;
3301 struct drm_crtc *possible_crtc;
3302 struct drm_crtc *supported_crtc =NULL;
3303 struct drm_encoder *encoder = &intel_output->enc;
3304 struct drm_crtc *crtc = NULL;
3305 struct drm_device *dev = encoder->dev;
3306 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3307 struct drm_crtc_helper_funcs *crtc_funcs;
3308 int i = -1;
3309
3310 /*
3311 * Algorithm gets a little messy:
3312 * - if the connector already has an assigned crtc, use it (but make
3313 * sure it's on first)
3314 * - try to find the first unused crtc that can drive this connector,
3315 * and use that if we find one
3316 * - if there are no unused crtcs available, try to use the first
3317 * one we found that supports the connector
3318 */
3319
3320 /* See if we already have a CRTC for this connector */
3321 if (encoder->crtc) {
3322 crtc = encoder->crtc;
3323 /* Make sure the crtc and connector are running */
3324 intel_crtc = to_intel_crtc(crtc);
3325 *dpms_mode = intel_crtc->dpms_mode;
3326 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3327 crtc_funcs = crtc->helper_private;
3328 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3329 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3330 }
3331 return crtc;
3332 }
3333
3334 /* Find an unused one (if possible) */
3335 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3336 i++;
3337 if (!(encoder->possible_crtcs & (1 << i)))
3338 continue;
3339 if (!possible_crtc->enabled) {
3340 crtc = possible_crtc;
3341 break;
3342 }
3343 if (!supported_crtc)
3344 supported_crtc = possible_crtc;
3345 }
3346
3347 /*
3348 * If we didn't find an unused CRTC, don't use any.
3349 */
3350 if (!crtc) {
3351 return NULL;
3352 }
3353
3354 encoder->crtc = crtc;
Keith Packard03d60692009-06-05 18:19:56 -07003355 intel_output->base.encoder = encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08003356 intel_output->load_detect_temp = true;
3357
3358 intel_crtc = to_intel_crtc(crtc);
3359 *dpms_mode = intel_crtc->dpms_mode;
3360
3361 if (!crtc->enabled) {
3362 if (!mode)
3363 mode = &load_detect_mode;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05003364 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08003365 } else {
3366 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3367 crtc_funcs = crtc->helper_private;
3368 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3369 }
3370
3371 /* Add this connector to the crtc */
3372 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3373 encoder_funcs->commit(encoder);
3374 }
3375 /* let the connector get through one full cycle before testing */
3376 intel_wait_for_vblank(dev);
3377
3378 return crtc;
3379}
3380
3381void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3382{
3383 struct drm_encoder *encoder = &intel_output->enc;
3384 struct drm_device *dev = encoder->dev;
3385 struct drm_crtc *crtc = encoder->crtc;
3386 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3387 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3388
3389 if (intel_output->load_detect_temp) {
3390 encoder->crtc = NULL;
Keith Packard03d60692009-06-05 18:19:56 -07003391 intel_output->base.encoder = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08003392 intel_output->load_detect_temp = false;
3393 crtc->enabled = drm_helper_crtc_in_use(crtc);
3394 drm_helper_disable_unused_functions(dev);
3395 }
3396
3397 /* Switch crtc and output back off if necessary */
3398 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3399 if (encoder->crtc == crtc)
3400 encoder_funcs->dpms(encoder, dpms_mode);
3401 crtc_funcs->dpms(crtc, dpms_mode);
3402 }
3403}
3404
3405/* Returns the clock of the currently programmed mode of the given pipe. */
3406static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3407{
3408 struct drm_i915_private *dev_priv = dev->dev_private;
3409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3410 int pipe = intel_crtc->pipe;
3411 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3412 u32 fp;
3413 intel_clock_t clock;
3414
3415 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3416 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3417 else
3418 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3419
3420 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08003421 if (IS_IGD(dev)) {
3422 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3423 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
3424 } else {
3425 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3426 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3427 }
3428
Jesse Barnes79e53942008-11-07 14:24:08 -08003429 if (IS_I9XX(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +08003430 if (IS_IGD(dev))
3431 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
3432 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
3433 else
3434 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08003435 DPLL_FPA01_P1_POST_DIV_SHIFT);
3436
3437 switch (dpll & DPLL_MODE_MASK) {
3438 case DPLLB_MODE_DAC_SERIAL:
3439 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3440 5 : 10;
3441 break;
3442 case DPLLB_MODE_LVDS:
3443 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3444 7 : 14;
3445 break;
3446 default:
3447 DRM_DEBUG("Unknown DPLL mode %08x in programmed "
3448 "mode\n", (int)(dpll & DPLL_MODE_MASK));
3449 return 0;
3450 }
3451
3452 /* XXX: Handle the 100Mhz refclk */
Shaohua Li21778322009-02-23 15:19:16 +08003453 intel_clock(dev, 96000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08003454 } else {
3455 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3456
3457 if (is_lvds) {
3458 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3459 DPLL_FPA01_P1_POST_DIV_SHIFT);
3460 clock.p2 = 14;
3461
3462 if ((dpll & PLL_REF_INPUT_MASK) ==
3463 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3464 /* XXX: might not be 66MHz */
Shaohua Li21778322009-02-23 15:19:16 +08003465 intel_clock(dev, 66000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08003466 } else
Shaohua Li21778322009-02-23 15:19:16 +08003467 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08003468 } else {
3469 if (dpll & PLL_P1_DIVIDE_BY_TWO)
3470 clock.p1 = 2;
3471 else {
3472 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3473 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3474 }
3475 if (dpll & PLL_P2_DIVIDE_BY_4)
3476 clock.p2 = 4;
3477 else
3478 clock.p2 = 2;
3479
Shaohua Li21778322009-02-23 15:19:16 +08003480 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08003481 }
3482 }
3483
3484 /* XXX: It would be nice to validate the clocks, but we can't reuse
3485 * i830PllIsValid() because it relies on the xf86_config connector
3486 * configuration being accurate, which it isn't necessarily.
3487 */
3488
3489 return clock.dot;
3490}
3491
3492/** Returns the currently programmed mode of the given pipe. */
3493struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3494 struct drm_crtc *crtc)
3495{
3496 struct drm_i915_private *dev_priv = dev->dev_private;
3497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3498 int pipe = intel_crtc->pipe;
3499 struct drm_display_mode *mode;
3500 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3501 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3502 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3503 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3504
3505 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3506 if (!mode)
3507 return NULL;
3508
3509 mode->clock = intel_crtc_clock_get(dev, crtc);
3510 mode->hdisplay = (htot & 0xffff) + 1;
3511 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3512 mode->hsync_start = (hsync & 0xffff) + 1;
3513 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3514 mode->vdisplay = (vtot & 0xffff) + 1;
3515 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3516 mode->vsync_start = (vsync & 0xffff) + 1;
3517 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3518
3519 drm_mode_set_name(mode);
3520 drm_mode_set_crtcinfo(mode, 0);
3521
3522 return mode;
3523}
3524
Jesse Barnes652c3932009-08-17 13:31:43 -07003525#define GPU_IDLE_TIMEOUT 500 /* ms */
3526
3527/* When this timer fires, we've been idle for awhile */
3528static void intel_gpu_idle_timer(unsigned long arg)
3529{
3530 struct drm_device *dev = (struct drm_device *)arg;
3531 drm_i915_private_t *dev_priv = dev->dev_private;
3532
3533 DRM_DEBUG("idle timer fired, downclocking\n");
3534
3535 dev_priv->busy = false;
3536
Eric Anholt01dfba92009-09-06 15:18:53 -07003537 queue_work(dev_priv->wq, &dev_priv->idle_work);
Jesse Barnes652c3932009-08-17 13:31:43 -07003538}
3539
3540void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3541{
3542 drm_i915_private_t *dev_priv = dev->dev_private;
3543
3544 if (IS_IGDNG(dev))
3545 return;
3546
3547 if (!dev_priv->render_reclock_avail) {
Eric Anholt67cf7812009-08-31 08:52:02 -07003548 DRM_DEBUG("not reclocking render clock\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07003549 return;
3550 }
3551
3552 /* Restore render clock frequency to original value */
3553 if (IS_G4X(dev) || IS_I9XX(dev))
3554 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3555 else if (IS_I85X(dev))
3556 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3557 DRM_DEBUG("increasing render clock frequency\n");
3558
3559 /* Schedule downclock */
3560 if (schedule)
3561 mod_timer(&dev_priv->idle_timer, jiffies +
3562 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3563}
3564
3565void intel_decrease_renderclock(struct drm_device *dev)
3566{
3567 drm_i915_private_t *dev_priv = dev->dev_private;
3568
3569 if (IS_IGDNG(dev))
3570 return;
3571
3572 if (!dev_priv->render_reclock_avail) {
Eric Anholt67cf7812009-08-31 08:52:02 -07003573 DRM_DEBUG("not reclocking render clock\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07003574 return;
3575 }
3576
3577 if (IS_G4X(dev)) {
3578 u16 gcfgc;
3579
3580 /* Adjust render clock... */
3581 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3582
3583 /* Down to minimum... */
3584 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3585 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3586
3587 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3588 } else if (IS_I965G(dev)) {
3589 u16 gcfgc;
3590
3591 /* Adjust render clock... */
3592 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3593
3594 /* Down to minimum... */
3595 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3596 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3597
3598 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3599 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3600 u16 gcfgc;
3601
3602 /* Adjust render clock... */
3603 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3604
3605 /* Down to minimum... */
3606 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3607 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3608
3609 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3610 } else if (IS_I915G(dev)) {
3611 u16 gcfgc;
3612
3613 /* Adjust render clock... */
3614 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3615
3616 /* Down to minimum... */
3617 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3618 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3619
3620 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3621 } else if (IS_I85X(dev)) {
3622 u16 hpllcc;
3623
3624 /* Adjust render clock... */
3625 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3626
3627 /* Up to maximum... */
3628 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3629 hpllcc |= GC_CLOCK_133_200;
3630
3631 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3632 }
3633 DRM_DEBUG("decreasing render clock frequency\n");
3634}
3635
3636/* Note that no increase function is needed for this - increase_renderclock()
3637 * will also rewrite these bits
3638 */
3639void intel_decrease_displayclock(struct drm_device *dev)
3640{
3641 if (IS_IGDNG(dev))
3642 return;
3643
3644 if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3645 IS_I915GM(dev)) {
3646 u16 gcfgc;
3647
3648 /* Adjust render clock... */
3649 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3650
3651 /* Down to minimum... */
3652 gcfgc &= ~0xf0;
3653 gcfgc |= 0x80;
3654
3655 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3656 }
3657}
3658
3659#define CRTC_IDLE_TIMEOUT 1000 /* ms */
3660
3661static void intel_crtc_idle_timer(unsigned long arg)
3662{
3663 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3664 struct drm_crtc *crtc = &intel_crtc->base;
3665 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3666
3667 DRM_DEBUG("idle timer fired, downclocking\n");
3668
3669 intel_crtc->busy = false;
3670
Eric Anholt01dfba92009-09-06 15:18:53 -07003671 queue_work(dev_priv->wq, &dev_priv->idle_work);
Jesse Barnes652c3932009-08-17 13:31:43 -07003672}
3673
3674static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3675{
3676 struct drm_device *dev = crtc->dev;
3677 drm_i915_private_t *dev_priv = dev->dev_private;
3678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3679 int pipe = intel_crtc->pipe;
3680 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3681 int dpll = I915_READ(dpll_reg);
3682
3683 if (IS_IGDNG(dev))
3684 return;
3685
3686 if (!dev_priv->lvds_downclock_avail)
3687 return;
3688
3689 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3690 DRM_DEBUG("upclocking LVDS\n");
3691
3692 /* Unlock panel regs */
3693 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3694
3695 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3696 I915_WRITE(dpll_reg, dpll);
3697 dpll = I915_READ(dpll_reg);
3698 intel_wait_for_vblank(dev);
3699 dpll = I915_READ(dpll_reg);
3700 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3701 DRM_DEBUG("failed to upclock LVDS!\n");
3702
3703 /* ...and lock them again */
3704 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3705 }
3706
3707 /* Schedule downclock */
3708 if (schedule)
3709 mod_timer(&intel_crtc->idle_timer, jiffies +
3710 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3711}
3712
3713static void intel_decrease_pllclock(struct drm_crtc *crtc)
3714{
3715 struct drm_device *dev = crtc->dev;
3716 drm_i915_private_t *dev_priv = dev->dev_private;
3717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3718 int pipe = intel_crtc->pipe;
3719 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3720 int dpll = I915_READ(dpll_reg);
3721
3722 if (IS_IGDNG(dev))
3723 return;
3724
3725 if (!dev_priv->lvds_downclock_avail)
3726 return;
3727
3728 /*
3729 * Since this is called by a timer, we should never get here in
3730 * the manual case.
3731 */
3732 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3733 DRM_DEBUG("downclocking LVDS\n");
3734
3735 /* Unlock panel regs */
3736 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3737
3738 dpll |= DISPLAY_RATE_SELECT_FPA1;
3739 I915_WRITE(dpll_reg, dpll);
3740 dpll = I915_READ(dpll_reg);
3741 intel_wait_for_vblank(dev);
3742 dpll = I915_READ(dpll_reg);
3743 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3744 DRM_DEBUG("failed to downclock LVDS!\n");
3745
3746 /* ...and lock them again */
3747 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3748 }
3749
3750}
3751
3752/**
3753 * intel_idle_update - adjust clocks for idleness
3754 * @work: work struct
3755 *
3756 * Either the GPU or display (or both) went idle. Check the busy status
3757 * here and adjust the CRTC and GPU clocks as necessary.
3758 */
3759static void intel_idle_update(struct work_struct *work)
3760{
3761 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3762 idle_work);
3763 struct drm_device *dev = dev_priv->dev;
3764 struct drm_crtc *crtc;
3765 struct intel_crtc *intel_crtc;
3766
3767 if (!i915_powersave)
3768 return;
3769
3770 mutex_lock(&dev->struct_mutex);
3771
3772 /* GPU isn't processing, downclock it. */
3773 if (!dev_priv->busy) {
3774 intel_decrease_renderclock(dev);
3775 intel_decrease_displayclock(dev);
3776 }
3777
3778 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3779 /* Skip inactive CRTCs */
3780 if (!crtc->fb)
3781 continue;
3782
3783 intel_crtc = to_intel_crtc(crtc);
3784 if (!intel_crtc->busy)
3785 intel_decrease_pllclock(crtc);
3786 }
3787
3788 mutex_unlock(&dev->struct_mutex);
3789}
3790
3791/**
3792 * intel_mark_busy - mark the GPU and possibly the display busy
3793 * @dev: drm device
3794 * @obj: object we're operating on
3795 *
3796 * Callers can use this function to indicate that the GPU is busy processing
3797 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
3798 * buffer), we'll also mark the display as busy, so we know to increase its
3799 * clock frequency.
3800 */
3801void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3802{
3803 drm_i915_private_t *dev_priv = dev->dev_private;
3804 struct drm_crtc *crtc = NULL;
3805 struct intel_framebuffer *intel_fb;
3806 struct intel_crtc *intel_crtc;
3807
Zhenyu Wang5e17ee72009-09-03 09:30:06 +08003808 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3809 return;
3810
Jesse Barnes652c3932009-08-17 13:31:43 -07003811 dev_priv->busy = true;
3812 intel_increase_renderclock(dev, true);
3813
3814 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3815 if (!crtc->fb)
3816 continue;
3817
3818 intel_crtc = to_intel_crtc(crtc);
3819 intel_fb = to_intel_framebuffer(crtc->fb);
3820 if (intel_fb->obj == obj) {
3821 if (!intel_crtc->busy) {
3822 /* Non-busy -> busy, upclock */
3823 intel_increase_pllclock(crtc, true);
3824 intel_crtc->busy = true;
3825 } else {
3826 /* Busy -> busy, put off timer */
3827 mod_timer(&intel_crtc->idle_timer, jiffies +
3828 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3829 }
3830 }
3831 }
3832}
3833
Jesse Barnes79e53942008-11-07 14:24:08 -08003834static void intel_crtc_destroy(struct drm_crtc *crtc)
3835{
3836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3837
3838 drm_crtc_cleanup(crtc);
3839 kfree(intel_crtc);
3840}
3841
3842static const struct drm_crtc_helper_funcs intel_helper_funcs = {
3843 .dpms = intel_crtc_dpms,
3844 .mode_fixup = intel_crtc_mode_fixup,
3845 .mode_set = intel_crtc_mode_set,
3846 .mode_set_base = intel_pipe_set_base,
3847 .prepare = intel_crtc_prepare,
3848 .commit = intel_crtc_commit,
Dave Airlie068143d2009-10-05 09:58:02 +10003849 .load_lut = intel_crtc_load_lut,
Jesse Barnes79e53942008-11-07 14:24:08 -08003850};
3851
3852static const struct drm_crtc_funcs intel_crtc_funcs = {
3853 .cursor_set = intel_crtc_cursor_set,
3854 .cursor_move = intel_crtc_cursor_move,
3855 .gamma_set = intel_crtc_gamma_set,
3856 .set_config = drm_crtc_helper_set_config,
3857 .destroy = intel_crtc_destroy,
3858};
3859
3860
Hannes Ederb358d0a2008-12-18 21:18:47 +01003861static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08003862{
3863 struct intel_crtc *intel_crtc;
3864 int i;
3865
3866 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
3867 if (intel_crtc == NULL)
3868 return;
3869
3870 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
3871
3872 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
3873 intel_crtc->pipe = pipe;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003874 intel_crtc->plane = pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08003875 for (i = 0; i < 256; i++) {
3876 intel_crtc->lut_r[i] = i;
3877 intel_crtc->lut_g[i] = i;
3878 intel_crtc->lut_b[i] = i;
3879 }
3880
Jesse Barnes80824002009-09-10 15:28:06 -07003881 /* Swap pipes & planes for FBC on pre-965 */
3882 intel_crtc->pipe = pipe;
3883 intel_crtc->plane = pipe;
3884 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
3885 DRM_DEBUG("swapping pipes & planes for FBC\n");
3886 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
3887 }
3888
Jesse Barnes79e53942008-11-07 14:24:08 -08003889 intel_crtc->cursor_addr = 0;
3890 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
3891 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
3892
Jesse Barnes652c3932009-08-17 13:31:43 -07003893 intel_crtc->busy = false;
3894
3895 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
3896 (unsigned long)intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08003897}
3898
Carl Worth08d7b3d2009-04-29 14:43:54 -07003899int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
3900 struct drm_file *file_priv)
3901{
3902 drm_i915_private_t *dev_priv = dev->dev_private;
3903 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +02003904 struct drm_mode_object *drmmode_obj;
3905 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -07003906
3907 if (!dev_priv) {
3908 DRM_ERROR("called with no initialization\n");
3909 return -EINVAL;
3910 }
3911
Daniel Vetterc05422d2009-08-11 16:05:30 +02003912 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
3913 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -07003914
Daniel Vetterc05422d2009-08-11 16:05:30 +02003915 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -07003916 DRM_ERROR("no such CRTC id\n");
3917 return -EINVAL;
3918 }
3919
Daniel Vetterc05422d2009-08-11 16:05:30 +02003920 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
3921 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -07003922
Daniel Vetterc05422d2009-08-11 16:05:30 +02003923 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -07003924}
3925
Jesse Barnes79e53942008-11-07 14:24:08 -08003926struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
3927{
3928 struct drm_crtc *crtc = NULL;
3929
3930 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3932 if (intel_crtc->pipe == pipe)
3933 break;
3934 }
3935 return crtc;
3936}
3937
Hannes Ederb358d0a2008-12-18 21:18:47 +01003938static int intel_connector_clones(struct drm_device *dev, int type_mask)
Jesse Barnes79e53942008-11-07 14:24:08 -08003939{
3940 int index_mask = 0;
3941 struct drm_connector *connector;
3942 int entry = 0;
3943
3944 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3945 struct intel_output *intel_output = to_intel_output(connector);
Ma Lingf8aed702009-08-24 13:50:24 +08003946 if (type_mask & intel_output->clone_mask)
Jesse Barnes79e53942008-11-07 14:24:08 -08003947 index_mask |= (1 << entry);
3948 entry++;
3949 }
3950 return index_mask;
3951}
3952
3953
3954static void intel_setup_outputs(struct drm_device *dev)
3955{
Eric Anholt725e30a2009-01-22 13:01:02 -08003956 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08003957 struct drm_connector *connector;
3958
3959 intel_crt_init(dev);
3960
3961 /* Set up integrated LVDS */
Zhenyu Wang541998a2009-06-05 15:38:44 +08003962 if (IS_MOBILE(dev) && !IS_I830(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08003963 intel_lvds_init(dev);
3964
Zhenyu Wang2c072452009-06-05 15:38:42 +08003965 if (IS_IGDNG(dev)) {
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08003966 int found;
3967
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003968 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
3969 intel_dp_init(dev, DP_A);
3970
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08003971 if (I915_READ(HDMIB) & PORT_DETECTED) {
3972 /* check SDVOB */
3973 /* found = intel_sdvo_init(dev, HDMIB); */
3974 found = 0;
3975 if (!found)
3976 intel_hdmi_init(dev, HDMIB);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003977 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
3978 intel_dp_init(dev, PCH_DP_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08003979 }
3980
3981 if (I915_READ(HDMIC) & PORT_DETECTED)
3982 intel_hdmi_init(dev, HDMIC);
3983
3984 if (I915_READ(HDMID) & PORT_DETECTED)
3985 intel_hdmi_init(dev, HDMID);
3986
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003987 if (I915_READ(PCH_DP_C) & DP_DETECTED)
3988 intel_dp_init(dev, PCH_DP_C);
3989
3990 if (I915_READ(PCH_DP_D) & DP_DETECTED)
3991 intel_dp_init(dev, PCH_DP_D);
3992
Zhenyu Wang2c072452009-06-05 15:38:42 +08003993 } else if (IS_I9XX(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +08003994 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -08003995
Eric Anholt725e30a2009-01-22 13:01:02 -08003996 if (I915_READ(SDVOB) & SDVO_DETECTED) {
3997 found = intel_sdvo_init(dev, SDVOB);
3998 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
3999 intel_hdmi_init(dev, SDVOB);
Ma Ling27185ae2009-08-24 13:50:23 +08004000
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004001 if (!found && SUPPORTS_INTEGRATED_DP(dev))
4002 intel_dp_init(dev, DP_B);
Eric Anholt725e30a2009-01-22 13:01:02 -08004003 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -04004004
4005 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -04004006
Ma Ling27185ae2009-08-24 13:50:23 +08004007 if (I915_READ(SDVOB) & SDVO_DETECTED)
Eric Anholt725e30a2009-01-22 13:01:02 -08004008 found = intel_sdvo_init(dev, SDVOC);
Ma Ling27185ae2009-08-24 13:50:23 +08004009
4010 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4011
4012 if (SUPPORTS_INTEGRATED_HDMI(dev))
Eric Anholt725e30a2009-01-22 13:01:02 -08004013 intel_hdmi_init(dev, SDVOC);
Ma Ling27185ae2009-08-24 13:50:23 +08004014 if (SUPPORTS_INTEGRATED_DP(dev))
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004015 intel_dp_init(dev, DP_C);
Eric Anholt725e30a2009-01-22 13:01:02 -08004016 }
Ma Ling27185ae2009-08-24 13:50:23 +08004017
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004018 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
4019 intel_dp_init(dev, DP_D);
Jesse Barnes79e53942008-11-07 14:24:08 -08004020 } else
4021 intel_dvo_init(dev);
4022
Zhenyu Wang2c072452009-06-05 15:38:42 +08004023 if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08004024 intel_tv_init(dev);
4025
4026 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4027 struct intel_output *intel_output = to_intel_output(connector);
4028 struct drm_encoder *encoder = &intel_output->enc;
Jesse Barnes79e53942008-11-07 14:24:08 -08004029
Ma Lingf8aed702009-08-24 13:50:24 +08004030 encoder->possible_crtcs = intel_output->crtc_mask;
4031 encoder->possible_clones = intel_connector_clones(dev,
4032 intel_output->clone_mask);
Jesse Barnes79e53942008-11-07 14:24:08 -08004033 }
4034}
4035
4036static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4037{
4038 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4039 struct drm_device *dev = fb->dev;
4040
4041 if (fb->fbdev)
4042 intelfb_remove(dev, fb);
4043
4044 drm_framebuffer_cleanup(fb);
4045 mutex_lock(&dev->struct_mutex);
4046 drm_gem_object_unreference(intel_fb->obj);
4047 mutex_unlock(&dev->struct_mutex);
4048
4049 kfree(intel_fb);
4050}
4051
4052static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4053 struct drm_file *file_priv,
4054 unsigned int *handle)
4055{
4056 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4057 struct drm_gem_object *object = intel_fb->obj;
4058
4059 return drm_gem_handle_create(file_priv, object, handle);
4060}
4061
4062static const struct drm_framebuffer_funcs intel_fb_funcs = {
4063 .destroy = intel_user_framebuffer_destroy,
4064 .create_handle = intel_user_framebuffer_create_handle,
4065};
4066
4067int intel_framebuffer_create(struct drm_device *dev,
4068 struct drm_mode_fb_cmd *mode_cmd,
4069 struct drm_framebuffer **fb,
4070 struct drm_gem_object *obj)
4071{
4072 struct intel_framebuffer *intel_fb;
4073 int ret;
4074
4075 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4076 if (!intel_fb)
4077 return -ENOMEM;
4078
4079 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4080 if (ret) {
4081 DRM_ERROR("framebuffer init failed %d\n", ret);
4082 return ret;
4083 }
4084
4085 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4086
4087 intel_fb->obj = obj;
4088
4089 *fb = &intel_fb->base;
4090
4091 return 0;
4092}
4093
4094
4095static struct drm_framebuffer *
4096intel_user_framebuffer_create(struct drm_device *dev,
4097 struct drm_file *filp,
4098 struct drm_mode_fb_cmd *mode_cmd)
4099{
4100 struct drm_gem_object *obj;
4101 struct drm_framebuffer *fb;
4102 int ret;
4103
4104 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4105 if (!obj)
4106 return NULL;
4107
4108 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4109 if (ret) {
Jesse Barnes496818f2009-02-11 13:28:14 -08004110 mutex_lock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08004111 drm_gem_object_unreference(obj);
Jesse Barnes496818f2009-02-11 13:28:14 -08004112 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08004113 return NULL;
4114 }
4115
4116 return fb;
4117}
4118
Jesse Barnes79e53942008-11-07 14:24:08 -08004119static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -08004120 .fb_create = intel_user_framebuffer_create,
4121 .fb_changed = intelfb_probe,
4122};
4123
Jesse Barnes652c3932009-08-17 13:31:43 -07004124void intel_init_clock_gating(struct drm_device *dev)
4125{
4126 struct drm_i915_private *dev_priv = dev->dev_private;
4127
4128 /*
4129 * Disable clock gating reported to work incorrectly according to the
4130 * specs, but enable as much else as we can.
4131 */
Zhenyu Wangc03342f2009-09-29 11:01:23 +08004132 if (IS_IGDNG(dev)) {
4133 return;
4134 } else if (IS_G4X(dev)) {
Jesse Barnes652c3932009-08-17 13:31:43 -07004135 uint32_t dspclk_gate;
4136 I915_WRITE(RENCLK_GATE_D1, 0);
4137 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4138 GS_UNIT_CLOCK_GATE_DISABLE |
4139 CL_UNIT_CLOCK_GATE_DISABLE);
4140 I915_WRITE(RAMCLK_GATE_D, 0);
4141 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4142 OVRUNIT_CLOCK_GATE_DISABLE |
4143 OVCUNIT_CLOCK_GATE_DISABLE;
4144 if (IS_GM45(dev))
4145 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4146 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4147 } else if (IS_I965GM(dev)) {
4148 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4149 I915_WRITE(RENCLK_GATE_D2, 0);
4150 I915_WRITE(DSPCLK_GATE_D, 0);
4151 I915_WRITE(RAMCLK_GATE_D, 0);
4152 I915_WRITE16(DEUC, 0);
4153 } else if (IS_I965G(dev)) {
4154 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4155 I965_RCC_CLOCK_GATE_DISABLE |
4156 I965_RCPB_CLOCK_GATE_DISABLE |
4157 I965_ISC_CLOCK_GATE_DISABLE |
4158 I965_FBC_CLOCK_GATE_DISABLE);
4159 I915_WRITE(RENCLK_GATE_D2, 0);
4160 } else if (IS_I9XX(dev)) {
4161 u32 dstate = I915_READ(D_STATE);
4162
4163 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4164 DSTATE_DOT_CLOCK_GATING;
4165 I915_WRITE(D_STATE, dstate);
4166 } else if (IS_I855(dev) || IS_I865G(dev)) {
4167 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4168 } else if (IS_I830(dev)) {
4169 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4170 }
4171}
4172
Jesse Barnese70236a2009-09-21 10:42:27 -07004173/* Set up chip specific display functions */
4174static void intel_init_display(struct drm_device *dev)
4175{
4176 struct drm_i915_private *dev_priv = dev->dev_private;
4177
4178 /* We always want a DPMS function */
4179 if (IS_IGDNG(dev))
4180 dev_priv->display.dpms = igdng_crtc_dpms;
4181 else
4182 dev_priv->display.dpms = i9xx_crtc_dpms;
4183
4184 /* Only mobile has FBC, leave pointers NULL for other chips */
4185 if (IS_MOBILE(dev)) {
Jesse Barnes74dff282009-09-14 15:39:40 -07004186 if (IS_GM45(dev)) {
4187 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4188 dev_priv->display.enable_fbc = g4x_enable_fbc;
4189 dev_priv->display.disable_fbc = g4x_disable_fbc;
4190 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
Jesse Barnese70236a2009-09-21 10:42:27 -07004191 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4192 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4193 dev_priv->display.disable_fbc = i8xx_disable_fbc;
4194 }
Jesse Barnes74dff282009-09-14 15:39:40 -07004195 /* 855GM needs testing */
Jesse Barnese70236a2009-09-21 10:42:27 -07004196 }
4197
4198 /* Returns the core display clock speed */
4199 if (IS_I945G(dev))
4200 dev_priv->display.get_display_clock_speed =
4201 i945_get_display_clock_speed;
4202 else if (IS_I915G(dev))
4203 dev_priv->display.get_display_clock_speed =
4204 i915_get_display_clock_speed;
4205 else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
4206 dev_priv->display.get_display_clock_speed =
4207 i9xx_misc_get_display_clock_speed;
4208 else if (IS_I915GM(dev))
4209 dev_priv->display.get_display_clock_speed =
4210 i915gm_get_display_clock_speed;
4211 else if (IS_I865G(dev))
4212 dev_priv->display.get_display_clock_speed =
4213 i865_get_display_clock_speed;
4214 else if (IS_I855(dev))
4215 dev_priv->display.get_display_clock_speed =
4216 i855_get_display_clock_speed;
4217 else /* 852, 830 */
4218 dev_priv->display.get_display_clock_speed =
4219 i830_get_display_clock_speed;
4220
4221 /* For FIFO watermark updates */
Zhenyu Wangc03342f2009-09-29 11:01:23 +08004222 if (IS_IGDNG(dev))
4223 dev_priv->display.update_wm = NULL;
4224 else if (IS_G4X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07004225 dev_priv->display.update_wm = g4x_update_wm;
4226 else if (IS_I965G(dev))
4227 dev_priv->display.update_wm = i965_update_wm;
4228 else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4229 dev_priv->display.update_wm = i9xx_update_wm;
4230 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4231 } else {
4232 if (IS_I85X(dev))
4233 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4234 else if (IS_845G(dev))
4235 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4236 else
4237 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4238 dev_priv->display.update_wm = i830_update_wm;
4239 }
4240}
4241
Jesse Barnes79e53942008-11-07 14:24:08 -08004242void intel_modeset_init(struct drm_device *dev)
4243{
Jesse Barnes652c3932009-08-17 13:31:43 -07004244 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08004245 int num_pipe;
4246 int i;
4247
4248 drm_mode_config_init(dev);
4249
4250 dev->mode_config.min_width = 0;
4251 dev->mode_config.min_height = 0;
4252
4253 dev->mode_config.funcs = (void *)&intel_mode_funcs;
4254
Jesse Barnese70236a2009-09-21 10:42:27 -07004255 intel_init_display(dev);
4256
Jesse Barnes79e53942008-11-07 14:24:08 -08004257 if (IS_I965G(dev)) {
4258 dev->mode_config.max_width = 8192;
4259 dev->mode_config.max_height = 8192;
Keith Packard5e4d6fa2009-07-12 23:53:17 -07004260 } else if (IS_I9XX(dev)) {
4261 dev->mode_config.max_width = 4096;
4262 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -08004263 } else {
4264 dev->mode_config.max_width = 2048;
4265 dev->mode_config.max_height = 2048;
4266 }
4267
4268 /* set memory base */
4269 if (IS_I9XX(dev))
4270 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4271 else
4272 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4273
4274 if (IS_MOBILE(dev) || IS_I9XX(dev))
4275 num_pipe = 2;
4276 else
4277 num_pipe = 1;
4278 DRM_DEBUG("%d display pipe%s available.\n",
4279 num_pipe, num_pipe > 1 ? "s" : "");
4280
Jesse Barnes652c3932009-08-17 13:31:43 -07004281 if (IS_I85X(dev))
4282 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4283 else if (IS_I9XX(dev) || IS_G4X(dev))
4284 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4285
Jesse Barnes79e53942008-11-07 14:24:08 -08004286 for (i = 0; i < num_pipe; i++) {
4287 intel_crtc_init(dev, i);
4288 }
4289
4290 intel_setup_outputs(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -07004291
4292 intel_init_clock_gating(dev);
4293
4294 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4295 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4296 (unsigned long)dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08004297}
4298
4299void intel_modeset_cleanup(struct drm_device *dev)
4300{
Jesse Barnes652c3932009-08-17 13:31:43 -07004301 struct drm_i915_private *dev_priv = dev->dev_private;
4302 struct drm_crtc *crtc;
4303 struct intel_crtc *intel_crtc;
4304
4305 mutex_lock(&dev->struct_mutex);
4306
4307 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4308 /* Skip inactive CRTCs */
4309 if (!crtc->fb)
4310 continue;
4311
4312 intel_crtc = to_intel_crtc(crtc);
4313 intel_increase_pllclock(crtc, false);
4314 del_timer_sync(&intel_crtc->idle_timer);
4315 }
4316
4317 intel_increase_renderclock(dev, false);
4318 del_timer_sync(&dev_priv->idle_timer);
4319
4320 mutex_unlock(&dev->struct_mutex);
4321
Jesse Barnese70236a2009-09-21 10:42:27 -07004322 if (dev_priv->display.disable_fbc)
4323 dev_priv->display.disable_fbc(dev);
4324
Jesse Barnes79e53942008-11-07 14:24:08 -08004325 drm_mode_config_cleanup(dev);
4326}
4327
4328
4329/* current intel driver doesn't take advantage of encoders
4330 always give back the encoder for the connector
4331*/
4332struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4333{
4334 struct intel_output *intel_output = to_intel_output(connector);
4335
4336 return &intel_output->enc;
4337}
Dave Airlie28d52042009-09-21 14:33:58 +10004338
4339/*
4340 * set vga decode state - true == enable VGA decode
4341 */
4342int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4343{
4344 struct drm_i915_private *dev_priv = dev->dev_private;
4345 u16 gmch_ctrl;
4346
4347 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4348 if (state)
4349 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4350 else
4351 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4352 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4353 return 0;
4354}