blob: f0f38f5e752c8a84967fa035c7edc78aa31a2808 [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080028#include <linux/kernel.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080029#include "drmP.h"
30#include "intel_drv.h"
31#include "i915_drm.h"
32#include "i915_drv.h"
Keith Packarda4fc5ed2009-04-07 16:16:42 -070033#include "intel_dp.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080034
35#include "drm_crtc_helper.h"
36
Zhenyu Wang32f9d652009-07-24 01:00:32 +080037#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
38
Jesse Barnes79e53942008-11-07 14:24:08 -080039bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
Shaohua Li7662c8b2009-06-26 11:23:55 +080040static void intel_update_watermarks(struct drm_device *dev);
Jesse Barnes652c3932009-08-17 13:31:43 -070041static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
Jesse Barnes79e53942008-11-07 14:24:08 -080042
43typedef struct {
44 /* given values */
45 int n;
46 int m1, m2;
47 int p1, p2;
48 /* derived values */
49 int dot;
50 int vco;
51 int m;
52 int p;
53} intel_clock_t;
54
55typedef struct {
56 int min, max;
57} intel_range_t;
58
59typedef struct {
60 int dot_limit;
61 int p2_slow, p2_fast;
62} intel_p2_t;
63
64#define INTEL_P2_NUM 2
Ma Lingd4906092009-03-18 20:13:27 +080065typedef struct intel_limit intel_limit_t;
66struct intel_limit {
Jesse Barnes79e53942008-11-07 14:24:08 -080067 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +080069 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
70 int, int, intel_clock_t *);
Jesse Barnes652c3932009-08-17 13:31:43 -070071 bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
72 int, int, intel_clock_t *);
Ma Lingd4906092009-03-18 20:13:27 +080073};
Jesse Barnes79e53942008-11-07 14:24:08 -080074
75#define I8XX_DOT_MIN 25000
76#define I8XX_DOT_MAX 350000
77#define I8XX_VCO_MIN 930000
78#define I8XX_VCO_MAX 1400000
79#define I8XX_N_MIN 3
80#define I8XX_N_MAX 16
81#define I8XX_M_MIN 96
82#define I8XX_M_MAX 140
83#define I8XX_M1_MIN 18
84#define I8XX_M1_MAX 26
85#define I8XX_M2_MIN 6
86#define I8XX_M2_MAX 16
87#define I8XX_P_MIN 4
88#define I8XX_P_MAX 128
89#define I8XX_P1_MIN 2
90#define I8XX_P1_MAX 33
91#define I8XX_P1_LVDS_MIN 1
92#define I8XX_P1_LVDS_MAX 6
93#define I8XX_P2_SLOW 4
94#define I8XX_P2_FAST 2
95#define I8XX_P2_LVDS_SLOW 14
ling.ma@intel.com0c2e3952009-07-17 11:44:30 +080096#define I8XX_P2_LVDS_FAST 7
Jesse Barnes79e53942008-11-07 14:24:08 -080097#define I8XX_P2_SLOW_LIMIT 165000
98
99#define I9XX_DOT_MIN 20000
100#define I9XX_DOT_MAX 400000
101#define I9XX_VCO_MIN 1400000
102#define I9XX_VCO_MAX 2800000
Shaohua Li21778322009-02-23 15:19:16 +0800103#define IGD_VCO_MIN 1700000
104#define IGD_VCO_MAX 3500000
Kristian Høgsbergf3cade52009-02-13 20:56:50 -0500105#define I9XX_N_MIN 1
106#define I9XX_N_MAX 6
Shaohua Li21778322009-02-23 15:19:16 +0800107/* IGD's Ncounter is a ring counter */
108#define IGD_N_MIN 3
109#define IGD_N_MAX 6
Jesse Barnes79e53942008-11-07 14:24:08 -0800110#define I9XX_M_MIN 70
111#define I9XX_M_MAX 120
Shaohua Li21778322009-02-23 15:19:16 +0800112#define IGD_M_MIN 2
113#define IGD_M_MAX 256
Jesse Barnes79e53942008-11-07 14:24:08 -0800114#define I9XX_M1_MIN 10
Kristian Høgsbergf3cade52009-02-13 20:56:50 -0500115#define I9XX_M1_MAX 22
Jesse Barnes79e53942008-11-07 14:24:08 -0800116#define I9XX_M2_MIN 5
117#define I9XX_M2_MAX 9
Shaohua Li21778322009-02-23 15:19:16 +0800118/* IGD M1 is reserved, and must be 0 */
119#define IGD_M1_MIN 0
120#define IGD_M1_MAX 0
121#define IGD_M2_MIN 0
122#define IGD_M2_MAX 254
Jesse Barnes79e53942008-11-07 14:24:08 -0800123#define I9XX_P_SDVO_DAC_MIN 5
124#define I9XX_P_SDVO_DAC_MAX 80
125#define I9XX_P_LVDS_MIN 7
126#define I9XX_P_LVDS_MAX 98
Shaohua Li21778322009-02-23 15:19:16 +0800127#define IGD_P_LVDS_MIN 7
128#define IGD_P_LVDS_MAX 112
Jesse Barnes79e53942008-11-07 14:24:08 -0800129#define I9XX_P1_MIN 1
130#define I9XX_P1_MAX 8
131#define I9XX_P2_SDVO_DAC_SLOW 10
132#define I9XX_P2_SDVO_DAC_FAST 5
133#define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
134#define I9XX_P2_LVDS_SLOW 14
135#define I9XX_P2_LVDS_FAST 7
136#define I9XX_P2_LVDS_SLOW_LIMIT 112000
137
Ma Ling044c7c42009-03-18 20:13:23 +0800138/*The parameter is for SDVO on G4x platform*/
139#define G4X_DOT_SDVO_MIN 25000
140#define G4X_DOT_SDVO_MAX 270000
141#define G4X_VCO_MIN 1750000
142#define G4X_VCO_MAX 3500000
143#define G4X_N_SDVO_MIN 1
144#define G4X_N_SDVO_MAX 4
145#define G4X_M_SDVO_MIN 104
146#define G4X_M_SDVO_MAX 138
147#define G4X_M1_SDVO_MIN 17
148#define G4X_M1_SDVO_MAX 23
149#define G4X_M2_SDVO_MIN 5
150#define G4X_M2_SDVO_MAX 11
151#define G4X_P_SDVO_MIN 10
152#define G4X_P_SDVO_MAX 30
153#define G4X_P1_SDVO_MIN 1
154#define G4X_P1_SDVO_MAX 3
155#define G4X_P2_SDVO_SLOW 10
156#define G4X_P2_SDVO_FAST 10
157#define G4X_P2_SDVO_LIMIT 270000
158
159/*The parameter is for HDMI_DAC on G4x platform*/
160#define G4X_DOT_HDMI_DAC_MIN 22000
161#define G4X_DOT_HDMI_DAC_MAX 400000
162#define G4X_N_HDMI_DAC_MIN 1
163#define G4X_N_HDMI_DAC_MAX 4
164#define G4X_M_HDMI_DAC_MIN 104
165#define G4X_M_HDMI_DAC_MAX 138
166#define G4X_M1_HDMI_DAC_MIN 16
167#define G4X_M1_HDMI_DAC_MAX 23
168#define G4X_M2_HDMI_DAC_MIN 5
169#define G4X_M2_HDMI_DAC_MAX 11
170#define G4X_P_HDMI_DAC_MIN 5
171#define G4X_P_HDMI_DAC_MAX 80
172#define G4X_P1_HDMI_DAC_MIN 1
173#define G4X_P1_HDMI_DAC_MAX 8
174#define G4X_P2_HDMI_DAC_SLOW 10
175#define G4X_P2_HDMI_DAC_FAST 5
176#define G4X_P2_HDMI_DAC_LIMIT 165000
177
178/*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
179#define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
180#define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
181#define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
182#define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
183#define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
184#define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
185#define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
186#define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
187#define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
188#define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
189#define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
190#define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
191#define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
192#define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
193#define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
194#define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
195#define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
196
197/*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
198#define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
199#define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
200#define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
201#define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
202#define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
203#define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
204#define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
205#define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
206#define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
207#define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
208#define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
209#define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
210#define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
211#define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
212#define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
213#define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
214#define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
215
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700216/*The parameter is for DISPLAY PORT on G4x platform*/
217#define G4X_DOT_DISPLAY_PORT_MIN 161670
218#define G4X_DOT_DISPLAY_PORT_MAX 227000
219#define G4X_N_DISPLAY_PORT_MIN 1
220#define G4X_N_DISPLAY_PORT_MAX 2
221#define G4X_M_DISPLAY_PORT_MIN 97
222#define G4X_M_DISPLAY_PORT_MAX 108
223#define G4X_M1_DISPLAY_PORT_MIN 0x10
224#define G4X_M1_DISPLAY_PORT_MAX 0x12
225#define G4X_M2_DISPLAY_PORT_MIN 0x05
226#define G4X_M2_DISPLAY_PORT_MAX 0x06
227#define G4X_P_DISPLAY_PORT_MIN 10
228#define G4X_P_DISPLAY_PORT_MAX 20
229#define G4X_P1_DISPLAY_PORT_MIN 1
230#define G4X_P1_DISPLAY_PORT_MAX 2
231#define G4X_P2_DISPLAY_PORT_SLOW 10
232#define G4X_P2_DISPLAY_PORT_FAST 10
233#define G4X_P2_DISPLAY_PORT_LIMIT 0
234
Zhenyu Wang2c072452009-06-05 15:38:42 +0800235/* IGDNG */
236/* as we calculate clock using (register_value + 2) for
237 N/M1/M2, so here the range value for them is (actual_value-2).
238 */
239#define IGDNG_DOT_MIN 25000
240#define IGDNG_DOT_MAX 350000
241#define IGDNG_VCO_MIN 1760000
242#define IGDNG_VCO_MAX 3510000
243#define IGDNG_N_MIN 1
244#define IGDNG_N_MAX 5
245#define IGDNG_M_MIN 79
246#define IGDNG_M_MAX 118
247#define IGDNG_M1_MIN 12
248#define IGDNG_M1_MAX 23
249#define IGDNG_M2_MIN 5
250#define IGDNG_M2_MAX 9
251#define IGDNG_P_SDVO_DAC_MIN 5
252#define IGDNG_P_SDVO_DAC_MAX 80
253#define IGDNG_P_LVDS_MIN 28
254#define IGDNG_P_LVDS_MAX 112
255#define IGDNG_P1_MIN 1
256#define IGDNG_P1_MAX 8
257#define IGDNG_P2_SDVO_DAC_SLOW 10
258#define IGDNG_P2_SDVO_DAC_FAST 5
259#define IGDNG_P2_LVDS_SLOW 14 /* single channel */
260#define IGDNG_P2_LVDS_FAST 7 /* double channel */
261#define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */
262
Ma Lingd4906092009-03-18 20:13:27 +0800263static bool
264intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
265 int target, int refclk, intel_clock_t *best_clock);
266static bool
Jesse Barnes652c3932009-08-17 13:31:43 -0700267intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
268 int target, int refclk, intel_clock_t *best_clock);
269static bool
Ma Lingd4906092009-03-18 20:13:27 +0800270intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
271 int target, int refclk, intel_clock_t *best_clock);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800272static bool
273intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
274 int target, int refclk, intel_clock_t *best_clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800275
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700276static bool
277intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
278 int target, int refclk, intel_clock_t *best_clock);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800279static bool
280intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
281 int target, int refclk, intel_clock_t *best_clock);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700282
Keith Packarde4b36692009-06-05 19:22:17 -0700283static const intel_limit_t intel_limits_i8xx_dvo = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800284 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
285 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
286 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
287 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
288 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
289 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
290 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
291 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
292 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
293 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800294 .find_pll = intel_find_best_PLL,
Jesse Barnes652c3932009-08-17 13:31:43 -0700295 .find_reduced_pll = intel_find_best_reduced_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700296};
297
298static const intel_limit_t intel_limits_i8xx_lvds = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800299 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
300 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
301 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
302 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
303 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
304 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
305 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
306 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
307 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
308 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800309 .find_pll = intel_find_best_PLL,
Jesse Barnes652c3932009-08-17 13:31:43 -0700310 .find_reduced_pll = intel_find_best_reduced_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700311};
312
313static const intel_limit_t intel_limits_i9xx_sdvo = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800314 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
315 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
316 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
317 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
318 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
319 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
320 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
321 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
322 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
323 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800324 .find_pll = intel_find_best_PLL,
Jesse Barnes652c3932009-08-17 13:31:43 -0700325 .find_reduced_pll = intel_find_best_reduced_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700326};
327
328static const intel_limit_t intel_limits_i9xx_lvds = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800329 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
330 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
331 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
332 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
333 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
334 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
335 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
336 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
337 /* The single-channel range is 25-112Mhz, and dual-channel
338 * is 80-224Mhz. Prefer single channel as much as possible.
339 */
340 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
341 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800342 .find_pll = intel_find_best_PLL,
Jesse Barnes652c3932009-08-17 13:31:43 -0700343 .find_reduced_pll = intel_find_best_reduced_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700344};
345
Ma Ling044c7c42009-03-18 20:13:23 +0800346 /* below parameter and function is for G4X Chipset Family*/
Keith Packarde4b36692009-06-05 19:22:17 -0700347static const intel_limit_t intel_limits_g4x_sdvo = {
Ma Ling044c7c42009-03-18 20:13:23 +0800348 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
349 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
350 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
351 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
352 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
353 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
354 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
355 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
356 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
357 .p2_slow = G4X_P2_SDVO_SLOW,
358 .p2_fast = G4X_P2_SDVO_FAST
359 },
Ma Lingd4906092009-03-18 20:13:27 +0800360 .find_pll = intel_g4x_find_best_PLL,
Jesse Barnes652c3932009-08-17 13:31:43 -0700361 .find_reduced_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700362};
363
364static const intel_limit_t intel_limits_g4x_hdmi = {
Ma Ling044c7c42009-03-18 20:13:23 +0800365 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
366 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
367 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
368 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
369 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
370 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
371 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
372 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
373 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
374 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
375 .p2_fast = G4X_P2_HDMI_DAC_FAST
376 },
Ma Lingd4906092009-03-18 20:13:27 +0800377 .find_pll = intel_g4x_find_best_PLL,
Jesse Barnes652c3932009-08-17 13:31:43 -0700378 .find_reduced_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700379};
380
381static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Ma Ling044c7c42009-03-18 20:13:23 +0800382 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
383 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
384 .vco = { .min = G4X_VCO_MIN,
385 .max = G4X_VCO_MAX },
386 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
387 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
388 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
389 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
390 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
391 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
392 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
393 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
394 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
395 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
396 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
397 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
398 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
399 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
400 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
401 },
Ma Lingd4906092009-03-18 20:13:27 +0800402 .find_pll = intel_g4x_find_best_PLL,
Jesse Barnes652c3932009-08-17 13:31:43 -0700403 .find_reduced_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700404};
405
406static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Ma Ling044c7c42009-03-18 20:13:23 +0800407 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
408 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
409 .vco = { .min = G4X_VCO_MIN,
410 .max = G4X_VCO_MAX },
411 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
412 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
413 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
414 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
415 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
416 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
417 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
418 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
419 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
420 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
421 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
422 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
423 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
424 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
425 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
426 },
Ma Lingd4906092009-03-18 20:13:27 +0800427 .find_pll = intel_g4x_find_best_PLL,
Jesse Barnes652c3932009-08-17 13:31:43 -0700428 .find_reduced_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700429};
430
431static const intel_limit_t intel_limits_g4x_display_port = {
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700432 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
433 .max = G4X_DOT_DISPLAY_PORT_MAX },
434 .vco = { .min = G4X_VCO_MIN,
435 .max = G4X_VCO_MAX},
436 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
437 .max = G4X_N_DISPLAY_PORT_MAX },
438 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
439 .max = G4X_M_DISPLAY_PORT_MAX },
440 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
441 .max = G4X_M1_DISPLAY_PORT_MAX },
442 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
443 .max = G4X_M2_DISPLAY_PORT_MAX },
444 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
445 .max = G4X_P_DISPLAY_PORT_MAX },
446 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
447 .max = G4X_P1_DISPLAY_PORT_MAX},
448 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
449 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
450 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
451 .find_pll = intel_find_pll_g4x_dp,
Keith Packarde4b36692009-06-05 19:22:17 -0700452};
453
454static const intel_limit_t intel_limits_igd_sdvo = {
Shaohua Li21778322009-02-23 15:19:16 +0800455 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
456 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
457 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
458 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
459 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
460 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
461 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
462 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
463 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
464 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
Shaohua Li61157072009-04-03 15:24:43 +0800465 .find_pll = intel_find_best_PLL,
Jesse Barnes652c3932009-08-17 13:31:43 -0700466 .find_reduced_pll = intel_find_best_reduced_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700467};
468
469static const intel_limit_t intel_limits_igd_lvds = {
Shaohua Li21778322009-02-23 15:19:16 +0800470 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
471 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
472 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
473 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
474 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
475 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
476 .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
477 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
478 /* IGD only supports single-channel mode. */
479 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
480 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
Shaohua Li61157072009-04-03 15:24:43 +0800481 .find_pll = intel_find_best_PLL,
Jesse Barnes652c3932009-08-17 13:31:43 -0700482 .find_reduced_pll = intel_find_best_reduced_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700483};
484
485static const intel_limit_t intel_limits_igdng_sdvo = {
Zhenyu Wang2c072452009-06-05 15:38:42 +0800486 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
487 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
488 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
489 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
490 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
491 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
492 .p = { .min = IGDNG_P_SDVO_DAC_MIN, .max = IGDNG_P_SDVO_DAC_MAX },
493 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
494 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
495 .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
496 .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
497 .find_pll = intel_igdng_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700498};
499
500static const intel_limit_t intel_limits_igdng_lvds = {
Zhenyu Wang2c072452009-06-05 15:38:42 +0800501 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
502 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
503 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
504 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
505 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
506 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
507 .p = { .min = IGDNG_P_LVDS_MIN, .max = IGDNG_P_LVDS_MAX },
508 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
509 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
510 .p2_slow = IGDNG_P2_LVDS_SLOW,
511 .p2_fast = IGDNG_P2_LVDS_FAST },
512 .find_pll = intel_igdng_find_best_PLL,
Jesse Barnes79e53942008-11-07 14:24:08 -0800513};
514
Zhenyu Wang2c072452009-06-05 15:38:42 +0800515static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
516{
517 const intel_limit_t *limit;
518 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700519 limit = &intel_limits_igdng_lvds;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800520 else
Keith Packarde4b36692009-06-05 19:22:17 -0700521 limit = &intel_limits_igdng_sdvo;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800522
523 return limit;
524}
525
Ma Ling044c7c42009-03-18 20:13:23 +0800526static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
527{
528 struct drm_device *dev = crtc->dev;
529 struct drm_i915_private *dev_priv = dev->dev_private;
530 const intel_limit_t *limit;
531
532 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
533 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
534 LVDS_CLKB_POWER_UP)
535 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700536 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800537 else
538 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700539 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800540 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
541 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700542 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800543 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700544 limit = &intel_limits_g4x_sdvo;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700545 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700546 limit = &intel_limits_g4x_display_port;
Ma Ling044c7c42009-03-18 20:13:23 +0800547 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700548 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800549
550 return limit;
551}
552
Jesse Barnes79e53942008-11-07 14:24:08 -0800553static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
554{
555 struct drm_device *dev = crtc->dev;
556 const intel_limit_t *limit;
557
Zhenyu Wang2c072452009-06-05 15:38:42 +0800558 if (IS_IGDNG(dev))
559 limit = intel_igdng_limit(crtc);
560 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800561 limit = intel_g4x_limit(crtc);
Shaohua Li21778322009-02-23 15:19:16 +0800562 } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800563 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700564 limit = &intel_limits_i9xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800565 else
Keith Packarde4b36692009-06-05 19:22:17 -0700566 limit = &intel_limits_i9xx_sdvo;
Shaohua Li21778322009-02-23 15:19:16 +0800567 } else if (IS_IGD(dev)) {
568 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700569 limit = &intel_limits_igd_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800570 else
Keith Packarde4b36692009-06-05 19:22:17 -0700571 limit = &intel_limits_igd_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800572 } else {
573 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700574 limit = &intel_limits_i8xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800575 else
Keith Packarde4b36692009-06-05 19:22:17 -0700576 limit = &intel_limits_i8xx_dvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800577 }
578 return limit;
579}
580
Shaohua Li21778322009-02-23 15:19:16 +0800581/* m1 is reserved as 0 in IGD, n is a ring counter */
582static void igd_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800583{
Shaohua Li21778322009-02-23 15:19:16 +0800584 clock->m = clock->m2 + 2;
585 clock->p = clock->p1 * clock->p2;
586 clock->vco = refclk * clock->m / clock->n;
587 clock->dot = clock->vco / clock->p;
588}
589
590static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
591{
592 if (IS_IGD(dev)) {
593 igd_clock(refclk, clock);
594 return;
595 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800596 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
597 clock->p = clock->p1 * clock->p2;
598 clock->vco = refclk * clock->m / (clock->n + 2);
599 clock->dot = clock->vco / clock->p;
600}
601
Jesse Barnes79e53942008-11-07 14:24:08 -0800602/**
603 * Returns whether any output on the specified pipe is of the specified type
604 */
605bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
606{
607 struct drm_device *dev = crtc->dev;
608 struct drm_mode_config *mode_config = &dev->mode_config;
609 struct drm_connector *l_entry;
610
611 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
612 if (l_entry->encoder &&
613 l_entry->encoder->crtc == crtc) {
614 struct intel_output *intel_output = to_intel_output(l_entry);
615 if (intel_output->type == type)
616 return true;
617 }
618 }
619 return false;
620}
621
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800622struct drm_connector *
623intel_pipe_get_output (struct drm_crtc *crtc)
624{
625 struct drm_device *dev = crtc->dev;
626 struct drm_mode_config *mode_config = &dev->mode_config;
627 struct drm_connector *l_entry, *ret = NULL;
628
629 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
630 if (l_entry->encoder &&
631 l_entry->encoder->crtc == crtc) {
632 ret = l_entry;
633 break;
634 }
635 }
636 return ret;
637}
638
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800639#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800640/**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
645static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
646{
647 const intel_limit_t *limit = intel_limit (crtc);
Shaohua Li21778322009-02-23 15:19:16 +0800648 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800649
650 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
651 INTELPllInvalid ("p1 out of range\n");
652 if (clock->p < limit->p.min || limit->p.max < clock->p)
653 INTELPllInvalid ("p out of range\n");
654 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
655 INTELPllInvalid ("m2 out of range\n");
656 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
657 INTELPllInvalid ("m1 out of range\n");
Shaohua Li21778322009-02-23 15:19:16 +0800658 if (clock->m1 <= clock->m2 && !IS_IGD(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800659 INTELPllInvalid ("m1 <= m2\n");
660 if (clock->m < limit->m.min || limit->m.max < clock->m)
661 INTELPllInvalid ("m out of range\n");
662 if (clock->n < limit->n.min || limit->n.max < clock->n)
663 INTELPllInvalid ("n out of range\n");
664 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
665 INTELPllInvalid ("vco out of range\n");
666 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
667 * connector, etc., rather than just a single range.
668 */
669 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
670 INTELPllInvalid ("dot out of range\n");
671
672 return true;
673}
674
Ma Lingd4906092009-03-18 20:13:27 +0800675static bool
676intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
677 int target, int refclk, intel_clock_t *best_clock)
678
Jesse Barnes79e53942008-11-07 14:24:08 -0800679{
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800683 int err = target;
684
Bruno Prémontbc5e5712009-08-08 13:01:17 +0200685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Florian Mickler832cc282009-07-13 18:40:32 +0800686 (I915_READ(LVDS)) != 0) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
693 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
694 LVDS_CLKB_POWER_UP)
695 clock.p2 = limit->p2.p2_fast;
696 else
697 clock.p2 = limit->p2.p2_slow;
698 } else {
699 if (target < limit->p2.dot_limit)
700 clock.p2 = limit->p2.p2_slow;
701 else
702 clock.p2 = limit->p2.p2_fast;
703 }
704
705 memset (best_clock, 0, sizeof (*best_clock));
706
Jesse Barnes652c3932009-08-17 13:31:43 -0700707 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
708 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
709 clock.m1++) {
710 for (clock.m2 = limit->m2.min;
711 clock.m2 <= limit->m2.max; clock.m2++) {
712 /* m1 is always 0 in IGD */
713 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
714 break;
715 for (clock.n = limit->n.min;
716 clock.n <= limit->n.max; clock.n++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800717 int this_err;
718
Shaohua Li21778322009-02-23 15:19:16 +0800719 intel_clock(dev, refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800720
721 if (!intel_PLL_is_valid(crtc, &clock))
722 continue;
723
724 this_err = abs(clock.dot - target);
725 if (this_err < err) {
726 *best_clock = clock;
727 err = this_err;
728 }
729 }
730 }
731 }
732 }
733
734 return (err != target);
735}
736
Jesse Barnes652c3932009-08-17 13:31:43 -0700737
738static bool
739intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
740 int target, int refclk, intel_clock_t *best_clock)
741
742{
743 struct drm_device *dev = crtc->dev;
744 intel_clock_t clock;
745 int err = target;
746 bool found = false;
747
748 memcpy(&clock, best_clock, sizeof(intel_clock_t));
749
750 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
751 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
752 /* m1 is always 0 in IGD */
753 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
754 break;
755 for (clock.n = limit->n.min; clock.n <= limit->n.max;
756 clock.n++) {
757 int this_err;
758
759 intel_clock(dev, refclk, &clock);
760
761 if (!intel_PLL_is_valid(crtc, &clock))
762 continue;
763
764 this_err = abs(clock.dot - target);
765 if (this_err < err) {
766 *best_clock = clock;
767 err = this_err;
768 found = true;
769 }
770 }
771 }
772 }
773
774 return found;
775}
776
Ma Lingd4906092009-03-18 20:13:27 +0800777static bool
778intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
779 int target, int refclk, intel_clock_t *best_clock)
780{
781 struct drm_device *dev = crtc->dev;
782 struct drm_i915_private *dev_priv = dev->dev_private;
783 intel_clock_t clock;
784 int max_n;
785 bool found;
786 /* approximately equals target * 0.00488 */
787 int err_most = (target >> 8) + (target >> 10);
788 found = false;
789
790 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
791 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
792 LVDS_CLKB_POWER_UP)
793 clock.p2 = limit->p2.p2_fast;
794 else
795 clock.p2 = limit->p2.p2_slow;
796 } else {
797 if (target < limit->p2.dot_limit)
798 clock.p2 = limit->p2.p2_slow;
799 else
800 clock.p2 = limit->p2.p2_fast;
801 }
802
803 memset(best_clock, 0, sizeof(*best_clock));
804 max_n = limit->n.max;
805 /* based on hardware requriment prefer smaller n to precision */
806 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Jesse Barnes652c3932009-08-17 13:31:43 -0700807 /* based on hardware requirment prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800808 for (clock.m1 = limit->m1.max;
809 clock.m1 >= limit->m1.min; clock.m1--) {
810 for (clock.m2 = limit->m2.max;
811 clock.m2 >= limit->m2.min; clock.m2--) {
812 for (clock.p1 = limit->p1.max;
813 clock.p1 >= limit->p1.min; clock.p1--) {
814 int this_err;
815
Shaohua Li21778322009-02-23 15:19:16 +0800816 intel_clock(dev, refclk, &clock);
Ma Lingd4906092009-03-18 20:13:27 +0800817 if (!intel_PLL_is_valid(crtc, &clock))
818 continue;
819 this_err = abs(clock.dot - target) ;
820 if (this_err < err_most) {
821 *best_clock = clock;
822 err_most = this_err;
823 max_n = clock.n;
824 found = true;
825 }
826 }
827 }
828 }
829 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800830 return found;
831}
Ma Lingd4906092009-03-18 20:13:27 +0800832
Zhenyu Wang2c072452009-06-05 15:38:42 +0800833static bool
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800834intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
835 int target, int refclk, intel_clock_t *best_clock)
836{
837 struct drm_device *dev = crtc->dev;
838 intel_clock_t clock;
839 if (target < 200000) {
840 clock.n = 1;
841 clock.p1 = 2;
842 clock.p2 = 10;
843 clock.m1 = 12;
844 clock.m2 = 9;
845 } else {
846 clock.n = 2;
847 clock.p1 = 1;
848 clock.p2 = 10;
849 clock.m1 = 14;
850 clock.m2 = 8;
851 }
852 intel_clock(dev, refclk, &clock);
853 memcpy(best_clock, &clock, sizeof(intel_clock_t));
854 return true;
855}
856
857static bool
Zhenyu Wang2c072452009-06-05 15:38:42 +0800858intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
859 int target, int refclk, intel_clock_t *best_clock)
860{
861 struct drm_device *dev = crtc->dev;
862 struct drm_i915_private *dev_priv = dev->dev_private;
863 intel_clock_t clock;
864 int max_n;
865 bool found;
866 int err_most = 47;
867 found = false;
868
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800869 /* eDP has only 2 clock choice, no n/m/p setting */
870 if (HAS_eDP)
871 return true;
872
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800873 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
874 return intel_find_pll_igdng_dp(limit, crtc, target,
875 refclk, best_clock);
876
Zhenyu Wang2c072452009-06-05 15:38:42 +0800877 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
878 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
879 LVDS_CLKB_POWER_UP)
880 clock.p2 = limit->p2.p2_fast;
881 else
882 clock.p2 = limit->p2.p2_slow;
883 } else {
884 if (target < limit->p2.dot_limit)
885 clock.p2 = limit->p2.p2_slow;
886 else
887 clock.p2 = limit->p2.p2_fast;
888 }
889
890 memset(best_clock, 0, sizeof(*best_clock));
891 max_n = limit->n.max;
Jesse Barnes652c3932009-08-17 13:31:43 -0700892 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
893 /* based on hardware requriment prefer smaller n to precision */
894 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
895 /* based on hardware requirment prefere larger m1,m2 */
896 for (clock.m1 = limit->m1.max;
897 clock.m1 >= limit->m1.min; clock.m1--) {
898 for (clock.m2 = limit->m2.max;
899 clock.m2 >= limit->m2.min; clock.m2--) {
Zhenyu Wang2c072452009-06-05 15:38:42 +0800900 int this_err;
901
902 intel_clock(dev, refclk, &clock);
903 if (!intel_PLL_is_valid(crtc, &clock))
904 continue;
905 this_err = abs((10000 - (target*10000/clock.dot)));
906 if (this_err < err_most) {
907 *best_clock = clock;
908 err_most = this_err;
909 max_n = clock.n;
910 found = true;
911 /* found on first matching */
912 goto out;
913 }
914 }
915 }
916 }
917 }
918out:
Ma Lingd4906092009-03-18 20:13:27 +0800919 return found;
920}
921
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700922/* DisplayPort has only two frequencies, 162MHz and 270MHz */
923static bool
924intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
925 int target, int refclk, intel_clock_t *best_clock)
926{
927 intel_clock_t clock;
928 if (target < 200000) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700929 clock.p1 = 2;
930 clock.p2 = 10;
Keith Packardb3d25492009-06-24 23:09:15 -0700931 clock.n = 2;
932 clock.m1 = 23;
933 clock.m2 = 8;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700934 } else {
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700935 clock.p1 = 1;
936 clock.p2 = 10;
Keith Packardb3d25492009-06-24 23:09:15 -0700937 clock.n = 1;
938 clock.m1 = 14;
939 clock.m2 = 2;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700940 }
Keith Packardb3d25492009-06-24 23:09:15 -0700941 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
942 clock.p = (clock.p1 * clock.p2);
943 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700944 memcpy(best_clock, &clock, sizeof(intel_clock_t));
945 return true;
946}
947
Jesse Barnes79e53942008-11-07 14:24:08 -0800948void
949intel_wait_for_vblank(struct drm_device *dev)
950{
951 /* Wait for 20ms, i.e. one cycle at 50hz. */
Arjan van de Ven580982d2009-03-23 13:36:25 -0700952 mdelay(20);
Jesse Barnes79e53942008-11-07 14:24:08 -0800953}
954
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000955static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -0500956intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
957 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -0800958{
959 struct drm_device *dev = crtc->dev;
960 struct drm_i915_private *dev_priv = dev->dev_private;
961 struct drm_i915_master_private *master_priv;
962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
963 struct intel_framebuffer *intel_fb;
964 struct drm_i915_gem_object *obj_priv;
965 struct drm_gem_object *obj;
966 int pipe = intel_crtc->pipe;
967 unsigned long Start, Offset;
968 int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
969 int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
970 int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
Jesse Barnesf5448472009-04-14 14:17:47 -0700971 int dsptileoff = (pipe == 0 ? DSPATILEOFF : DSPBTILEOFF);
Jesse Barnes79e53942008-11-07 14:24:08 -0800972 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -0500973 u32 dspcntr, alignment;
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000974 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -0800975
976 /* no fb bound */
977 if (!crtc->fb) {
978 DRM_DEBUG("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000979 return 0;
980 }
981
982 switch (pipe) {
983 case 0:
984 case 1:
985 break;
986 default:
987 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
988 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -0800989 }
990
991 intel_fb = to_intel_framebuffer(crtc->fb);
Jesse Barnes79e53942008-11-07 14:24:08 -0800992 obj = intel_fb->obj;
993 obj_priv = obj->driver_private;
994
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -0500995 switch (obj_priv->tiling_mode) {
996 case I915_TILING_NONE:
997 alignment = 64 * 1024;
998 break;
999 case I915_TILING_X:
Chris Wilson2ebed172009-02-11 14:26:30 +00001000 /* pin() will align the object as required by fence */
1001 alignment = 0;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001002 break;
1003 case I915_TILING_Y:
1004 /* FIXME: Is this true? */
1005 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001006 return -EINVAL;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001007 default:
1008 BUG();
1009 }
1010
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001011 mutex_lock(&dev->struct_mutex);
Chris Wilson8c4b8c32009-06-17 22:08:52 +01001012 ret = i915_gem_object_pin(obj, alignment);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001013 if (ret != 0) {
1014 mutex_unlock(&dev->struct_mutex);
1015 return ret;
1016 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001017
Chris Wilson8c4b8c32009-06-17 22:08:52 +01001018 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001019 if (ret != 0) {
Chris Wilson8c4b8c32009-06-17 22:08:52 +01001020 i915_gem_object_unpin(obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001021 mutex_unlock(&dev->struct_mutex);
1022 return ret;
1023 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001024
Chris Wilson8c4b8c32009-06-17 22:08:52 +01001025 /* Pre-i965 needs to install a fence for tiled scan-out */
1026 if (!IS_I965G(dev) &&
1027 obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1028 obj_priv->tiling_mode != I915_TILING_NONE) {
1029 ret = i915_gem_object_get_fence_reg(obj);
1030 if (ret != 0) {
1031 i915_gem_object_unpin(obj);
1032 mutex_unlock(&dev->struct_mutex);
1033 return ret;
1034 }
1035 }
1036
Jesse Barnes79e53942008-11-07 14:24:08 -08001037 dspcntr = I915_READ(dspcntr_reg);
Jesse Barnes712531b2009-01-09 13:56:14 -08001038 /* Mask out pixel format bits in case we change it */
1039 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Jesse Barnes79e53942008-11-07 14:24:08 -08001040 switch (crtc->fb->bits_per_pixel) {
1041 case 8:
1042 dspcntr |= DISPPLANE_8BPP;
1043 break;
1044 case 16:
1045 if (crtc->fb->depth == 15)
1046 dspcntr |= DISPPLANE_15_16BPP;
1047 else
1048 dspcntr |= DISPPLANE_16BPP;
1049 break;
1050 case 24:
1051 case 32:
1052 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1053 break;
1054 default:
1055 DRM_ERROR("Unknown color depth\n");
Chris Wilson8c4b8c32009-06-17 22:08:52 +01001056 i915_gem_object_unpin(obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001057 mutex_unlock(&dev->struct_mutex);
1058 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08001059 }
Jesse Barnesf5448472009-04-14 14:17:47 -07001060 if (IS_I965G(dev)) {
1061 if (obj_priv->tiling_mode != I915_TILING_NONE)
1062 dspcntr |= DISPPLANE_TILED;
1063 else
1064 dspcntr &= ~DISPPLANE_TILED;
1065 }
1066
Jesse Barnes79e53942008-11-07 14:24:08 -08001067 I915_WRITE(dspcntr_reg, dspcntr);
1068
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001069 Start = obj_priv->gtt_offset;
1070 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1071
Jesse Barnes79e53942008-11-07 14:24:08 -08001072 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001073 I915_WRITE(dspstride, crtc->fb->pitch);
Jesse Barnes79e53942008-11-07 14:24:08 -08001074 if (IS_I965G(dev)) {
1075 I915_WRITE(dspbase, Offset);
1076 I915_READ(dspbase);
1077 I915_WRITE(dspsurf, Start);
1078 I915_READ(dspsurf);
Jesse Barnesf5448472009-04-14 14:17:47 -07001079 I915_WRITE(dsptileoff, (y << 16) | x);
Jesse Barnes79e53942008-11-07 14:24:08 -08001080 } else {
1081 I915_WRITE(dspbase, Start + Offset);
1082 I915_READ(dspbase);
1083 }
1084
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001085 intel_wait_for_vblank(dev);
1086
1087 if (old_fb) {
1088 intel_fb = to_intel_framebuffer(old_fb);
Jesse Barnes652c3932009-08-17 13:31:43 -07001089 obj_priv = intel_fb->obj->driver_private;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001090 i915_gem_object_unpin(intel_fb->obj);
1091 }
Jesse Barnes652c3932009-08-17 13:31:43 -07001092 intel_increase_pllclock(crtc, true);
1093
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001094 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08001095
1096 if (!dev->primary->master)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001097 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08001098
1099 master_priv = dev->primary->master->driver_priv;
1100 if (!master_priv->sarea_priv)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001101 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08001102
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001103 if (pipe) {
Jesse Barnes79e53942008-11-07 14:24:08 -08001104 master_priv->sarea_priv->pipeB_x = x;
1105 master_priv->sarea_priv->pipeB_y = y;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001106 } else {
1107 master_priv->sarea_priv->pipeA_x = x;
1108 master_priv->sarea_priv->pipeA_y = y;
Jesse Barnes79e53942008-11-07 14:24:08 -08001109 }
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001110
1111 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08001112}
1113
Zhenyu Wang24f119c2009-07-24 01:00:28 +08001114/* Disable the VGA plane that we never use */
1115static void i915_disable_vga (struct drm_device *dev)
1116{
1117 struct drm_i915_private *dev_priv = dev->dev_private;
1118 u8 sr1;
1119 u32 vga_reg;
1120
1121 if (IS_IGDNG(dev))
1122 vga_reg = CPU_VGACNTRL;
1123 else
1124 vga_reg = VGACNTRL;
1125
1126 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1127 return;
1128
1129 I915_WRITE8(VGA_SR_INDEX, 1);
1130 sr1 = I915_READ8(VGA_SR_DATA);
1131 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1132 udelay(100);
1133
1134 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1135}
1136
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001137static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1138{
1139 struct drm_device *dev = crtc->dev;
1140 struct drm_i915_private *dev_priv = dev->dev_private;
1141 u32 dpa_ctl;
1142
1143 DRM_DEBUG("\n");
1144 dpa_ctl = I915_READ(DP_A);
1145 dpa_ctl &= ~DP_PLL_ENABLE;
1146 I915_WRITE(DP_A, dpa_ctl);
1147}
1148
1149static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1150{
1151 struct drm_device *dev = crtc->dev;
1152 struct drm_i915_private *dev_priv = dev->dev_private;
1153 u32 dpa_ctl;
1154
1155 dpa_ctl = I915_READ(DP_A);
1156 dpa_ctl |= DP_PLL_ENABLE;
1157 I915_WRITE(DP_A, dpa_ctl);
1158 udelay(200);
1159}
1160
1161
1162static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1163{
1164 struct drm_device *dev = crtc->dev;
1165 struct drm_i915_private *dev_priv = dev->dev_private;
1166 u32 dpa_ctl;
1167
1168 DRM_DEBUG("eDP PLL enable for clock %d\n", clock);
1169 dpa_ctl = I915_READ(DP_A);
1170 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1171
1172 if (clock < 200000) {
1173 u32 temp;
1174 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1175 /* workaround for 160Mhz:
1176 1) program 0x4600c bits 15:0 = 0x8124
1177 2) program 0x46010 bit 0 = 1
1178 3) program 0x46034 bit 24 = 1
1179 4) program 0x64000 bit 14 = 1
1180 */
1181 temp = I915_READ(0x4600c);
1182 temp &= 0xffff0000;
1183 I915_WRITE(0x4600c, temp | 0x8124);
1184
1185 temp = I915_READ(0x46010);
1186 I915_WRITE(0x46010, temp | 1);
1187
1188 temp = I915_READ(0x46034);
1189 I915_WRITE(0x46034, temp | (1 << 24));
1190 } else {
1191 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1192 }
1193 I915_WRITE(DP_A, dpa_ctl);
1194
1195 udelay(500);
1196}
1197
Zhenyu Wang2c072452009-06-05 15:38:42 +08001198static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
Jesse Barnes79e53942008-11-07 14:24:08 -08001199{
1200 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001201 struct drm_i915_private *dev_priv = dev->dev_private;
1202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1203 int pipe = intel_crtc->pipe;
Shaohua Li7662c8b2009-06-26 11:23:55 +08001204 int plane = intel_crtc->plane;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001205 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1206 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1207 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1208 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1209 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1210 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1211 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1212 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1213 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1214 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001215 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001216 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1217 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1218 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1219 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1220 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1221 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1222 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1223 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1224 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1225 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1226 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1227 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1228 u32 temp;
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001229 int tries = 5, j, n;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001230
1231 /* XXX: When our outputs are all unaware of DPMS modes other than off
1232 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1233 */
1234 switch (mode) {
1235 case DRM_MODE_DPMS_ON:
1236 case DRM_MODE_DPMS_STANDBY:
1237 case DRM_MODE_DPMS_SUSPEND:
1238 DRM_DEBUG("crtc %d dpms on\n", pipe);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001239 if (HAS_eDP) {
1240 /* enable eDP PLL */
1241 igdng_enable_pll_edp(crtc);
1242 } else {
1243 /* enable PCH DPLL */
1244 temp = I915_READ(pch_dpll_reg);
1245 if ((temp & DPLL_VCO_ENABLE) == 0) {
1246 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1247 I915_READ(pch_dpll_reg);
1248 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08001249
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001250 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1251 temp = I915_READ(fdi_rx_reg);
1252 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1253 FDI_SEL_PCDCLK |
1254 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1255 I915_READ(fdi_rx_reg);
1256 udelay(200);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001257
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001258 /* Enable CPU FDI TX PLL, always on for IGDNG */
1259 temp = I915_READ(fdi_tx_reg);
1260 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1261 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1262 I915_READ(fdi_tx_reg);
1263 udelay(100);
1264 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08001265 }
1266
1267 /* Enable CPU pipe */
1268 temp = I915_READ(pipeconf_reg);
1269 if ((temp & PIPEACONF_ENABLE) == 0) {
1270 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1271 I915_READ(pipeconf_reg);
1272 udelay(100);
1273 }
1274
1275 /* configure and enable CPU plane */
1276 temp = I915_READ(dspcntr_reg);
1277 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1278 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1279 /* Flush the plane changes */
1280 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1281 }
1282
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001283 if (!HAS_eDP) {
1284 /* enable CPU FDI TX and PCH FDI RX */
1285 temp = I915_READ(fdi_tx_reg);
1286 temp |= FDI_TX_ENABLE;
1287 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1288 temp &= ~FDI_LINK_TRAIN_NONE;
1289 temp |= FDI_LINK_TRAIN_PATTERN_1;
1290 I915_WRITE(fdi_tx_reg, temp);
1291 I915_READ(fdi_tx_reg);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001292
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001293 temp = I915_READ(fdi_rx_reg);
1294 temp &= ~FDI_LINK_TRAIN_NONE;
1295 temp |= FDI_LINK_TRAIN_PATTERN_1;
1296 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1297 I915_READ(fdi_rx_reg);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001298
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001299 udelay(150);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001300
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001301 /* Train FDI. */
1302 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1303 for train result */
1304 temp = I915_READ(fdi_rx_imr_reg);
1305 temp &= ~FDI_RX_SYMBOL_LOCK;
1306 temp &= ~FDI_RX_BIT_LOCK;
1307 I915_WRITE(fdi_rx_imr_reg, temp);
1308 I915_READ(fdi_rx_imr_reg);
1309 udelay(150);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001310
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001311 temp = I915_READ(fdi_rx_iir_reg);
1312 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001313
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001314 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1315 for (j = 0; j < tries; j++) {
1316 temp = I915_READ(fdi_rx_iir_reg);
1317 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1318 if (temp & FDI_RX_BIT_LOCK)
1319 break;
1320 udelay(200);
1321 }
1322 if (j != tries)
1323 I915_WRITE(fdi_rx_iir_reg,
1324 temp | FDI_RX_BIT_LOCK);
1325 else
1326 DRM_DEBUG("train 1 fail\n");
1327 } else {
Zhenyu Wang2c072452009-06-05 15:38:42 +08001328 I915_WRITE(fdi_rx_iir_reg,
1329 temp | FDI_RX_BIT_LOCK);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001330 DRM_DEBUG("train 1 ok 2!\n");
Zhenyu Wang2c072452009-06-05 15:38:42 +08001331 }
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001332 temp = I915_READ(fdi_tx_reg);
1333 temp &= ~FDI_LINK_TRAIN_NONE;
1334 temp |= FDI_LINK_TRAIN_PATTERN_2;
1335 I915_WRITE(fdi_tx_reg, temp);
1336
1337 temp = I915_READ(fdi_rx_reg);
1338 temp &= ~FDI_LINK_TRAIN_NONE;
1339 temp |= FDI_LINK_TRAIN_PATTERN_2;
1340 I915_WRITE(fdi_rx_reg, temp);
1341
1342 udelay(150);
1343
1344 temp = I915_READ(fdi_rx_iir_reg);
1345 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1346
1347 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1348 for (j = 0; j < tries; j++) {
1349 temp = I915_READ(fdi_rx_iir_reg);
1350 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1351 if (temp & FDI_RX_SYMBOL_LOCK)
1352 break;
1353 udelay(200);
1354 }
1355 if (j != tries) {
1356 I915_WRITE(fdi_rx_iir_reg,
1357 temp | FDI_RX_SYMBOL_LOCK);
1358 DRM_DEBUG("train 2 ok 1!\n");
1359 } else
1360 DRM_DEBUG("train 2 fail\n");
1361 } else {
Zhenyu Wang2c072452009-06-05 15:38:42 +08001362 I915_WRITE(fdi_rx_iir_reg,
1363 temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001364 DRM_DEBUG("train 2 ok 2!\n");
1365 }
1366 DRM_DEBUG("train done\n");
1367
1368 /* set transcoder timing */
1369 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1370 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1371 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1372
1373 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1374 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1375 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1376
1377 /* enable PCH transcoder */
1378 temp = I915_READ(transconf_reg);
1379 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1380 I915_READ(transconf_reg);
1381
1382 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1383 ;
1384
1385 /* enable normal */
1386
1387 temp = I915_READ(fdi_tx_reg);
1388 temp &= ~FDI_LINK_TRAIN_NONE;
1389 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1390 FDI_TX_ENHANCE_FRAME_ENABLE);
1391 I915_READ(fdi_tx_reg);
1392
1393 temp = I915_READ(fdi_rx_reg);
1394 temp &= ~FDI_LINK_TRAIN_NONE;
1395 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1396 FDI_RX_ENHANCE_FRAME_ENABLE);
1397 I915_READ(fdi_rx_reg);
1398
1399 /* wait one idle pattern time */
1400 udelay(100);
1401
Zhenyu Wang2c072452009-06-05 15:38:42 +08001402 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08001403
1404 intel_crtc_load_lut(crtc);
1405
1406 break;
1407 case DRM_MODE_DPMS_OFF:
1408 DRM_DEBUG("crtc %d dpms off\n", pipe);
1409
Zhenyu Wang24f119c2009-07-24 01:00:28 +08001410 i915_disable_vga(dev);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001411
1412 /* Disable display plane */
1413 temp = I915_READ(dspcntr_reg);
1414 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1415 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1416 /* Flush the plane changes */
1417 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1418 I915_READ(dspbase_reg);
1419 }
1420
1421 /* disable cpu pipe, disable after all planes disabled */
1422 temp = I915_READ(pipeconf_reg);
1423 if ((temp & PIPEACONF_ENABLE) != 0) {
1424 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1425 I915_READ(pipeconf_reg);
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001426 n = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001427 /* wait for cpu pipe off, pipe state */
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001428 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1429 n++;
1430 if (n < 60) {
1431 udelay(500);
1432 continue;
1433 } else {
1434 DRM_DEBUG("pipe %d off delay\n", pipe);
1435 break;
1436 }
1437 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08001438 } else
1439 DRM_DEBUG("crtc %d is disabled\n", pipe);
1440
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001441 if (HAS_eDP) {
1442 igdng_disable_pll_edp(crtc);
1443 }
1444
Zhenyu Wang2c072452009-06-05 15:38:42 +08001445 /* disable CPU FDI tx and PCH FDI rx */
1446 temp = I915_READ(fdi_tx_reg);
1447 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1448 I915_READ(fdi_tx_reg);
1449
1450 temp = I915_READ(fdi_rx_reg);
1451 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1452 I915_READ(fdi_rx_reg);
1453
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001454 udelay(100);
1455
Zhenyu Wang2c072452009-06-05 15:38:42 +08001456 /* still set train pattern 1 */
1457 temp = I915_READ(fdi_tx_reg);
1458 temp &= ~FDI_LINK_TRAIN_NONE;
1459 temp |= FDI_LINK_TRAIN_PATTERN_1;
1460 I915_WRITE(fdi_tx_reg, temp);
1461
1462 temp = I915_READ(fdi_rx_reg);
1463 temp &= ~FDI_LINK_TRAIN_NONE;
1464 temp |= FDI_LINK_TRAIN_PATTERN_1;
1465 I915_WRITE(fdi_rx_reg, temp);
1466
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001467 udelay(100);
1468
Zhenyu Wang2c072452009-06-05 15:38:42 +08001469 /* disable PCH transcoder */
1470 temp = I915_READ(transconf_reg);
1471 if ((temp & TRANS_ENABLE) != 0) {
1472 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1473 I915_READ(transconf_reg);
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001474 n = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001475 /* wait for PCH transcoder off, transcoder state */
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001476 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1477 n++;
1478 if (n < 60) {
1479 udelay(500);
1480 continue;
1481 } else {
1482 DRM_DEBUG("transcoder %d off delay\n", pipe);
1483 break;
1484 }
1485 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08001486 }
1487
1488 /* disable PCH DPLL */
1489 temp = I915_READ(pch_dpll_reg);
1490 if ((temp & DPLL_VCO_ENABLE) != 0) {
1491 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1492 I915_READ(pch_dpll_reg);
1493 }
1494
1495 temp = I915_READ(fdi_rx_reg);
1496 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1497 temp &= ~FDI_SEL_PCDCLK;
1498 temp &= ~FDI_RX_PLL_ENABLE;
1499 I915_WRITE(fdi_rx_reg, temp);
1500 I915_READ(fdi_rx_reg);
1501 }
1502
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001503 /* Disable CPU FDI TX PLL */
1504 temp = I915_READ(fdi_tx_reg);
1505 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1506 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1507 I915_READ(fdi_tx_reg);
1508 udelay(100);
1509 }
1510
1511 /* Disable PF */
1512 temp = I915_READ(pf_ctl_reg);
1513 if ((temp & PF_ENABLE) != 0) {
1514 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1515 I915_READ(pf_ctl_reg);
1516 }
1517 I915_WRITE(pf_win_size, 0);
1518
Zhenyu Wang2c072452009-06-05 15:38:42 +08001519 /* Wait for the clocks to turn off. */
1520 udelay(150);
1521 break;
1522 }
1523}
1524
1525static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1526{
1527 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08001528 struct drm_i915_private *dev_priv = dev->dev_private;
1529 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1530 int pipe = intel_crtc->pipe;
1531 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1532 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
1533 int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
1534 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1535 u32 temp;
Jesse Barnes79e53942008-11-07 14:24:08 -08001536
1537 /* XXX: When our outputs are all unaware of DPMS modes other than off
1538 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1539 */
1540 switch (mode) {
1541 case DRM_MODE_DPMS_ON:
1542 case DRM_MODE_DPMS_STANDBY:
1543 case DRM_MODE_DPMS_SUSPEND:
1544 /* Enable the DPLL */
1545 temp = I915_READ(dpll_reg);
1546 if ((temp & DPLL_VCO_ENABLE) == 0) {
1547 I915_WRITE(dpll_reg, temp);
1548 I915_READ(dpll_reg);
1549 /* Wait for the clocks to stabilize. */
1550 udelay(150);
1551 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1552 I915_READ(dpll_reg);
1553 /* Wait for the clocks to stabilize. */
1554 udelay(150);
1555 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1556 I915_READ(dpll_reg);
1557 /* Wait for the clocks to stabilize. */
1558 udelay(150);
1559 }
1560
1561 /* Enable the pipe */
1562 temp = I915_READ(pipeconf_reg);
1563 if ((temp & PIPEACONF_ENABLE) == 0)
1564 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1565
1566 /* Enable the plane */
1567 temp = I915_READ(dspcntr_reg);
1568 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1569 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1570 /* Flush the plane changes */
1571 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1572 }
1573
1574 intel_crtc_load_lut(crtc);
1575
1576 /* Give the overlay scaler a chance to enable if it's on this pipe */
1577 //intel_crtc_dpms_video(crtc, true); TODO
Shaohua Li7662c8b2009-06-26 11:23:55 +08001578 intel_update_watermarks(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001579 break;
1580 case DRM_MODE_DPMS_OFF:
Shaohua Li7662c8b2009-06-26 11:23:55 +08001581 intel_update_watermarks(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001582 /* Give the overlay scaler a chance to disable if it's on this pipe */
1583 //intel_crtc_dpms_video(crtc, FALSE); TODO
1584
1585 /* Disable the VGA plane that we never use */
Zhenyu Wang24f119c2009-07-24 01:00:28 +08001586 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001587
1588 /* Disable display plane */
1589 temp = I915_READ(dspcntr_reg);
1590 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1591 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1592 /* Flush the plane changes */
1593 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1594 I915_READ(dspbase_reg);
1595 }
1596
1597 if (!IS_I9XX(dev)) {
1598 /* Wait for vblank for the disable to take effect */
1599 intel_wait_for_vblank(dev);
1600 }
1601
1602 /* Next, disable display pipes */
1603 temp = I915_READ(pipeconf_reg);
1604 if ((temp & PIPEACONF_ENABLE) != 0) {
1605 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1606 I915_READ(pipeconf_reg);
1607 }
1608
1609 /* Wait for vblank for the disable to take effect. */
1610 intel_wait_for_vblank(dev);
1611
1612 temp = I915_READ(dpll_reg);
1613 if ((temp & DPLL_VCO_ENABLE) != 0) {
1614 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1615 I915_READ(dpll_reg);
1616 }
1617
1618 /* Wait for the clocks to turn off. */
1619 udelay(150);
1620 break;
1621 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08001622}
1623
1624/**
1625 * Sets the power management mode of the pipe and plane.
1626 *
1627 * This code should probably grow support for turning the cursor off and back
1628 * on appropriately at the same time as we're turning the pipe off/on.
1629 */
1630static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1631{
1632 struct drm_device *dev = crtc->dev;
1633 struct drm_i915_master_private *master_priv;
1634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1635 int pipe = intel_crtc->pipe;
1636 bool enabled;
1637
1638 if (IS_IGDNG(dev))
1639 igdng_crtc_dpms(crtc, mode);
1640 else
1641 i9xx_crtc_dpms(crtc, mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08001642
1643 if (!dev->primary->master)
1644 return;
1645
1646 master_priv = dev->primary->master->driver_priv;
1647 if (!master_priv->sarea_priv)
1648 return;
1649
1650 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1651
1652 switch (pipe) {
1653 case 0:
1654 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1655 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1656 break;
1657 case 1:
1658 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1659 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1660 break;
1661 default:
1662 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1663 break;
1664 }
1665
1666 intel_crtc->dpms_mode = mode;
1667}
1668
1669static void intel_crtc_prepare (struct drm_crtc *crtc)
1670{
1671 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1672 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1673}
1674
1675static void intel_crtc_commit (struct drm_crtc *crtc)
1676{
1677 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1678 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1679}
1680
1681void intel_encoder_prepare (struct drm_encoder *encoder)
1682{
1683 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1684 /* lvds has its own version of prepare see intel_lvds_prepare */
1685 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1686}
1687
1688void intel_encoder_commit (struct drm_encoder *encoder)
1689{
1690 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1691 /* lvds has its own version of commit see intel_lvds_commit */
1692 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1693}
1694
1695static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1696 struct drm_display_mode *mode,
1697 struct drm_display_mode *adjusted_mode)
1698{
Zhenyu Wang2c072452009-06-05 15:38:42 +08001699 struct drm_device *dev = crtc->dev;
1700 if (IS_IGDNG(dev)) {
1701 /* FDI link clock is fixed at 2.7G */
1702 if (mode->clock * 3 > 27000 * 4)
1703 return MODE_CLOCK_HIGH;
1704 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001705 return true;
1706}
1707
1708
1709/** Returns the core display clock speed for i830 - i945 */
1710static int intel_get_core_clock_speed(struct drm_device *dev)
1711{
1712
1713 /* Core clock values taken from the published datasheets.
1714 * The 830 may go up to 166 Mhz, which we should check.
1715 */
1716 if (IS_I945G(dev))
1717 return 400000;
1718 else if (IS_I915G(dev))
1719 return 333000;
Shaohua Li21778322009-02-23 15:19:16 +08001720 else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08001721 return 200000;
1722 else if (IS_I915GM(dev)) {
1723 u16 gcfgc = 0;
1724
1725 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
1726
1727 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
1728 return 133000;
1729 else {
1730 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
1731 case GC_DISPLAY_CLOCK_333_MHZ:
1732 return 333000;
1733 default:
1734 case GC_DISPLAY_CLOCK_190_200_MHZ:
1735 return 190000;
1736 }
1737 }
1738 } else if (IS_I865G(dev))
1739 return 266000;
1740 else if (IS_I855(dev)) {
1741 u16 hpllcc = 0;
1742 /* Assume that the hardware is in the high speed state. This
1743 * should be the default.
1744 */
1745 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
1746 case GC_CLOCK_133_200:
1747 case GC_CLOCK_100_200:
1748 return 200000;
1749 case GC_CLOCK_166_250:
1750 return 250000;
1751 case GC_CLOCK_100_133:
1752 return 133000;
1753 }
1754 } else /* 852, 830 */
1755 return 133000;
1756
1757 return 0; /* Silence gcc warning */
1758}
1759
Jesse Barnes79e53942008-11-07 14:24:08 -08001760/**
1761 * Return the pipe currently connected to the panel fitter,
1762 * or -1 if the panel fitter is not present or not in use
1763 */
1764static int intel_panel_fitter_pipe (struct drm_device *dev)
1765{
1766 struct drm_i915_private *dev_priv = dev->dev_private;
1767 u32 pfit_control;
1768
1769 /* i830 doesn't have a panel fitter */
1770 if (IS_I830(dev))
1771 return -1;
1772
1773 pfit_control = I915_READ(PFIT_CONTROL);
1774
1775 /* See if the panel fitter is in use */
1776 if ((pfit_control & PFIT_ENABLE) == 0)
1777 return -1;
1778
1779 /* 965 can place panel fitter on either pipe */
1780 if (IS_I965G(dev))
1781 return (pfit_control >> 29) & 0x3;
1782
1783 /* older chips can only use pipe 1 */
1784 return 1;
1785}
1786
Zhenyu Wang2c072452009-06-05 15:38:42 +08001787struct fdi_m_n {
1788 u32 tu;
1789 u32 gmch_m;
1790 u32 gmch_n;
1791 u32 link_m;
1792 u32 link_n;
1793};
1794
1795static void
1796fdi_reduce_ratio(u32 *num, u32 *den)
1797{
1798 while (*num > 0xffffff || *den > 0xffffff) {
1799 *num >>= 1;
1800 *den >>= 1;
1801 }
1802}
1803
1804#define DATA_N 0x800000
1805#define LINK_N 0x80000
1806
1807static void
1808igdng_compute_m_n(int bytes_per_pixel, int nlanes,
1809 int pixel_clock, int link_clock,
1810 struct fdi_m_n *m_n)
1811{
1812 u64 temp;
1813
1814 m_n->tu = 64; /* default size */
1815
1816 temp = (u64) DATA_N * pixel_clock;
1817 temp = div_u64(temp, link_clock);
Andy Whitcroft956dba32009-07-01 15:20:59 +01001818 m_n->gmch_m = div_u64(temp * bytes_per_pixel, nlanes);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001819 m_n->gmch_n = DATA_N;
1820 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
1821
1822 temp = (u64) LINK_N * pixel_clock;
1823 m_n->link_m = div_u64(temp, link_clock);
1824 m_n->link_n = LINK_N;
1825 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
1826}
1827
1828
Shaohua Li7662c8b2009-06-26 11:23:55 +08001829struct intel_watermark_params {
1830 unsigned long fifo_size;
1831 unsigned long max_wm;
1832 unsigned long default_wm;
1833 unsigned long guard_size;
1834 unsigned long cacheline_size;
1835};
1836
1837/* IGD has different values for various configs */
1838static struct intel_watermark_params igd_display_wm = {
1839 IGD_DISPLAY_FIFO,
1840 IGD_MAX_WM,
1841 IGD_DFT_WM,
1842 IGD_GUARD_WM,
1843 IGD_FIFO_LINE_SIZE
1844};
1845static struct intel_watermark_params igd_display_hplloff_wm = {
1846 IGD_DISPLAY_FIFO,
1847 IGD_MAX_WM,
1848 IGD_DFT_HPLLOFF_WM,
1849 IGD_GUARD_WM,
1850 IGD_FIFO_LINE_SIZE
1851};
1852static struct intel_watermark_params igd_cursor_wm = {
1853 IGD_CURSOR_FIFO,
1854 IGD_CURSOR_MAX_WM,
1855 IGD_CURSOR_DFT_WM,
1856 IGD_CURSOR_GUARD_WM,
1857 IGD_FIFO_LINE_SIZE,
1858};
1859static struct intel_watermark_params igd_cursor_hplloff_wm = {
1860 IGD_CURSOR_FIFO,
1861 IGD_CURSOR_MAX_WM,
1862 IGD_CURSOR_DFT_WM,
1863 IGD_CURSOR_GUARD_WM,
1864 IGD_FIFO_LINE_SIZE
1865};
1866static struct intel_watermark_params i945_wm_info = {
Shaohua Li7662c8b2009-06-26 11:23:55 +08001867 I945_FIFO_SIZE,
1868 I915_MAX_WM,
1869 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07001870 2,
1871 I915_FIFO_LINE_SIZE
1872};
1873static struct intel_watermark_params i915_wm_info = {
1874 I915_FIFO_SIZE,
1875 I915_MAX_WM,
1876 1,
1877 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08001878 I915_FIFO_LINE_SIZE
1879};
1880static struct intel_watermark_params i855_wm_info = {
1881 I855GM_FIFO_SIZE,
1882 I915_MAX_WM,
1883 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07001884 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08001885 I830_FIFO_LINE_SIZE
1886};
1887static struct intel_watermark_params i830_wm_info = {
1888 I830_FIFO_SIZE,
1889 I915_MAX_WM,
1890 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07001891 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08001892 I830_FIFO_LINE_SIZE
1893};
1894
Jesse Barnesdff33cf2009-07-14 10:15:56 -07001895/**
1896 * intel_calculate_wm - calculate watermark level
1897 * @clock_in_khz: pixel clock
1898 * @wm: chip FIFO params
1899 * @pixel_size: display pixel size
1900 * @latency_ns: memory latency for the platform
1901 *
1902 * Calculate the watermark level (the level at which the display plane will
1903 * start fetching from memory again). Each chip has a different display
1904 * FIFO size and allocation, so the caller needs to figure that out and pass
1905 * in the correct intel_watermark_params structure.
1906 *
1907 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1908 * on the pixel size. When it reaches the watermark level, it'll start
1909 * fetching FIFO line sized based chunks from memory until the FIFO fills
1910 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1911 * will occur, and a display engine hang could result.
1912 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08001913static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1914 struct intel_watermark_params *wm,
1915 int pixel_size,
1916 unsigned long latency_ns)
1917{
Jesse Barnes390c4dd2009-07-16 13:01:01 -07001918 long entries_required, wm_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08001919
Jesse Barnesdff33cf2009-07-14 10:15:56 -07001920 entries_required = (clock_in_khz * pixel_size * latency_ns) / 1000000;
1921 entries_required /= wm->cacheline_size;
1922
1923 DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
1924
1925 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
1926
1927 DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
Shaohua Li7662c8b2009-06-26 11:23:55 +08001928
Jesse Barnes390c4dd2009-07-16 13:01:01 -07001929 /* Don't promote wm_size to unsigned... */
1930 if (wm_size > (long)wm->max_wm)
Shaohua Li7662c8b2009-06-26 11:23:55 +08001931 wm_size = wm->max_wm;
Jesse Barnes390c4dd2009-07-16 13:01:01 -07001932 if (wm_size <= 0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08001933 wm_size = wm->default_wm;
1934 return wm_size;
1935}
1936
1937struct cxsr_latency {
1938 int is_desktop;
1939 unsigned long fsb_freq;
1940 unsigned long mem_freq;
1941 unsigned long display_sr;
1942 unsigned long display_hpll_disable;
1943 unsigned long cursor_sr;
1944 unsigned long cursor_hpll_disable;
1945};
1946
1947static struct cxsr_latency cxsr_latency_table[] = {
1948 {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
1949 {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
1950 {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
1951
1952 {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
1953 {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
1954 {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
1955
1956 {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
1957 {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
1958 {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
1959
1960 {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
1961 {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
1962 {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
1963
1964 {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
1965 {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
1966 {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
1967
1968 {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
1969 {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
1970 {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
1971};
1972
1973static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
1974 int mem)
1975{
1976 int i;
1977 struct cxsr_latency *latency;
1978
1979 if (fsb == 0 || mem == 0)
1980 return NULL;
1981
1982 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
1983 latency = &cxsr_latency_table[i];
1984 if (is_desktop == latency->is_desktop &&
1985 fsb == latency->fsb_freq && mem == latency->mem_freq)
1986 break;
1987 }
1988 if (i >= ARRAY_SIZE(cxsr_latency_table)) {
1989 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
1990 return NULL;
1991 }
1992 return latency;
1993}
1994
1995static void igd_disable_cxsr(struct drm_device *dev)
1996{
1997 struct drm_i915_private *dev_priv = dev->dev_private;
1998 u32 reg;
1999
2000 /* deactivate cxsr */
2001 reg = I915_READ(DSPFW3);
2002 reg &= ~(IGD_SELF_REFRESH_EN);
2003 I915_WRITE(DSPFW3, reg);
2004 DRM_INFO("Big FIFO is disabled\n");
2005}
2006
2007static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2008 int pixel_size)
2009{
2010 struct drm_i915_private *dev_priv = dev->dev_private;
2011 u32 reg;
2012 unsigned long wm;
2013 struct cxsr_latency *latency;
2014
2015 latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
2016 dev_priv->mem_freq);
2017 if (!latency) {
2018 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2019 igd_disable_cxsr(dev);
2020 return;
2021 }
2022
2023 /* Display SR */
2024 wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
2025 latency->display_sr);
2026 reg = I915_READ(DSPFW1);
2027 reg &= 0x7fffff;
2028 reg |= wm << 23;
2029 I915_WRITE(DSPFW1, reg);
2030 DRM_DEBUG("DSPFW1 register is %x\n", reg);
2031
2032 /* cursor SR */
2033 wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
2034 latency->cursor_sr);
2035 reg = I915_READ(DSPFW3);
2036 reg &= ~(0x3f << 24);
2037 reg |= (wm & 0x3f) << 24;
2038 I915_WRITE(DSPFW3, reg);
2039
2040 /* Display HPLL off SR */
2041 wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
2042 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2043 reg = I915_READ(DSPFW3);
2044 reg &= 0xfffffe00;
2045 reg |= wm & 0x1ff;
2046 I915_WRITE(DSPFW3, reg);
2047
2048 /* cursor HPLL off SR */
2049 wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
2050 latency->cursor_hpll_disable);
2051 reg = I915_READ(DSPFW3);
2052 reg &= ~(0x3f << 16);
2053 reg |= (wm & 0x3f) << 16;
2054 I915_WRITE(DSPFW3, reg);
2055 DRM_DEBUG("DSPFW3 register is %x\n", reg);
2056
2057 /* activate cxsr */
2058 reg = I915_READ(DSPFW3);
2059 reg |= IGD_SELF_REFRESH_EN;
2060 I915_WRITE(DSPFW3, reg);
2061
2062 DRM_INFO("Big FIFO is enabled\n");
2063
2064 return;
2065}
2066
Jesse Barnesbcc24fb2009-08-31 10:24:31 -07002067/*
2068 * Latency for FIFO fetches is dependent on several factors:
2069 * - memory configuration (speed, channels)
2070 * - chipset
2071 * - current MCH state
2072 * It can be fairly high in some situations, so here we assume a fairly
2073 * pessimal value. It's a tradeoff between extra memory fetches (if we
2074 * set this value too high, the FIFO will fetch frequently to stay full)
2075 * and power consumption (set it too low to save power and we might see
2076 * FIFO underruns and display "flicker").
2077 *
2078 * A value of 5us seems to be a good balance; safe for very low end
2079 * platforms but not overly aggressive on lower latency configs.
2080 */
2081const static int latency_ns = 5000;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002082
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002083static int intel_get_fifo_size(struct drm_device *dev, int plane)
2084{
2085 struct drm_i915_private *dev_priv = dev->dev_private;
2086 uint32_t dsparb = I915_READ(DSPARB);
2087 int size;
2088
2089 if (IS_I9XX(dev)) {
2090 if (plane == 0)
2091 size = dsparb & 0x7f;
2092 else
2093 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2094 (dsparb & 0x7f);
2095 } else if (IS_I85X(dev)) {
2096 if (plane == 0)
2097 size = dsparb & 0x1ff;
2098 else
2099 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2100 (dsparb & 0x1ff);
2101 size >>= 1; /* Convert to cachelines */
Jesse Barnesf3601322009-07-22 12:54:59 -07002102 } else if (IS_845G(dev)) {
2103 size = dsparb & 0x7f;
2104 size >>= 2; /* Convert to cachelines */
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002105 } else {
2106 size = dsparb & 0x7f;
2107 size >>= 1; /* Convert to cachelines */
2108 }
2109
2110 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2111 size);
2112
2113 return size;
2114}
Shaohua Li7662c8b2009-06-26 11:23:55 +08002115
Jesse Barnes652c3932009-08-17 13:31:43 -07002116static void g4x_update_wm(struct drm_device *dev)
2117{
2118 struct drm_i915_private *dev_priv = dev->dev_private;
2119 u32 fw_blc_self = I915_READ(FW_BLC_SELF);
2120
2121 if (i915_powersave)
2122 fw_blc_self |= FW_BLC_SELF_EN;
2123 else
2124 fw_blc_self &= ~FW_BLC_SELF_EN;
2125 I915_WRITE(FW_BLC_SELF, fw_blc_self);
2126}
2127
Shaohua Li7662c8b2009-06-26 11:23:55 +08002128static void i965_update_wm(struct drm_device *dev)
2129{
2130 struct drm_i915_private *dev_priv = dev->dev_private;
2131
2132 DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
2133
2134 /* 965 has limitations... */
2135 I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
2136 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2137}
2138
2139static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2140 int planeb_clock, int sr_hdisplay, int pixel_size)
2141{
2142 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002143 uint32_t fwater_lo;
2144 uint32_t fwater_hi;
2145 int total_size, cacheline_size, cwm, srwm = 1;
2146 int planea_wm, planeb_wm;
2147 struct intel_watermark_params planea_params, planeb_params;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002148 unsigned long line_time_us;
2149 int sr_clock, sr_entries = 0;
2150
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002151 /* Create copies of the base settings for each pipe */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002152 if (IS_I965GM(dev) || IS_I945GM(dev))
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002153 planea_params = planeb_params = i945_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002154 else if (IS_I9XX(dev))
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002155 planea_params = planeb_params = i915_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002156 else
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002157 planea_params = planeb_params = i855_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002158
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002159 /* Grab a couple of global values before we overwrite them */
2160 total_size = planea_params.fifo_size;
2161 cacheline_size = planea_params.cacheline_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002162
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002163 /* Update per-plane FIFO sizes */
2164 planea_params.fifo_size = intel_get_fifo_size(dev, 0);
2165 planeb_params.fifo_size = intel_get_fifo_size(dev, 1);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002166
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002167 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2168 pixel_size, latency_ns);
2169 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2170 pixel_size, latency_ns);
2171 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002172
2173 /*
2174 * Overlay gets an aggressive default since video jitter is bad.
2175 */
2176 cwm = 2;
2177
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002178 /* Calc sr entries for one plane configs */
Jesse Barnes652c3932009-08-17 13:31:43 -07002179 if (HAS_FW_BLC(dev) && sr_hdisplay &&
2180 (!planea_clock || !planeb_clock)) {
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002181 /* self-refresh has much higher latency */
2182 const static int sr_latency_ns = 6000;
2183
Shaohua Li7662c8b2009-06-26 11:23:55 +08002184 sr_clock = planea_clock ? planea_clock : planeb_clock;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002185 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2186
2187 /* Use ns/us then divide to preserve precision */
2188 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2189 pixel_size * sr_hdisplay) / 1000;
2190 sr_entries = roundup(sr_entries / cacheline_size, 1);
2191 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2192 srwm = total_size - sr_entries;
2193 if (srwm < 0)
2194 srwm = 1;
Jesse Barnes652c3932009-08-17 13:31:43 -07002195 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
Shaohua Li7662c8b2009-06-26 11:23:55 +08002196 }
2197
2198 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002199 planea_wm, planeb_wm, cwm, srwm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002200
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002201 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2202 fwater_hi = (cwm & 0x1f);
2203
2204 /* Set request length to 8 cachelines per fetch */
2205 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2206 fwater_hi = fwater_hi | (1 << 8);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002207
2208 I915_WRITE(FW_BLC, fwater_lo);
2209 I915_WRITE(FW_BLC2, fwater_hi);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002210}
2211
2212static void i830_update_wm(struct drm_device *dev, int planea_clock,
2213 int pixel_size)
2214{
2215 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf3601322009-07-22 12:54:59 -07002216 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002217 int planea_wm;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002218
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002219 i830_wm_info.fifo_size = intel_get_fifo_size(dev, 0);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002220
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002221 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2222 pixel_size, latency_ns);
Jesse Barnesf3601322009-07-22 12:54:59 -07002223 fwater_lo |= (3<<8) | planea_wm;
2224
2225 DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002226
2227 I915_WRITE(FW_BLC, fwater_lo);
2228}
2229
2230/**
2231 * intel_update_watermarks - update FIFO watermark values based on current modes
2232 *
2233 * Calculate watermark values for the various WM regs based on current mode
2234 * and plane configuration.
2235 *
2236 * There are several cases to deal with here:
2237 * - normal (i.e. non-self-refresh)
2238 * - self-refresh (SR) mode
2239 * - lines are large relative to FIFO size (buffer can hold up to 2)
2240 * - lines are small relative to FIFO size (buffer can hold more than 2
2241 * lines), so need to account for TLB latency
2242 *
2243 * The normal calculation is:
2244 * watermark = dotclock * bytes per pixel * latency
2245 * where latency is platform & configuration dependent (we assume pessimal
2246 * values here).
2247 *
2248 * The SR calculation is:
2249 * watermark = (trunc(latency/line time)+1) * surface width *
2250 * bytes per pixel
2251 * where
2252 * line time = htotal / dotclock
2253 * and latency is assumed to be high, as above.
2254 *
2255 * The final value programmed to the register should always be rounded up,
2256 * and include an extra 2 entries to account for clock crossings.
2257 *
2258 * We don't use the sprite, so we can ignore that. And on Crestline we have
2259 * to set the non-SR watermarks to 8.
2260 */
2261static void intel_update_watermarks(struct drm_device *dev)
2262{
2263 struct drm_crtc *crtc;
2264 struct intel_crtc *intel_crtc;
2265 int sr_hdisplay = 0;
2266 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2267 int enabled = 0, pixel_size = 0;
2268
Shaohua Li7662c8b2009-06-26 11:23:55 +08002269 /* Get the clock config from both planes */
2270 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2271 intel_crtc = to_intel_crtc(crtc);
2272 if (crtc->enabled) {
2273 enabled++;
2274 if (intel_crtc->plane == 0) {
2275 DRM_DEBUG("plane A (pipe %d) clock: %d\n",
2276 intel_crtc->pipe, crtc->mode.clock);
2277 planea_clock = crtc->mode.clock;
2278 } else {
2279 DRM_DEBUG("plane B (pipe %d) clock: %d\n",
2280 intel_crtc->pipe, crtc->mode.clock);
2281 planeb_clock = crtc->mode.clock;
2282 }
2283 sr_hdisplay = crtc->mode.hdisplay;
2284 sr_clock = crtc->mode.clock;
2285 if (crtc->fb)
2286 pixel_size = crtc->fb->bits_per_pixel / 8;
2287 else
2288 pixel_size = 4; /* by default */
2289 }
2290 }
2291
2292 if (enabled <= 0)
2293 return;
2294
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002295 /* Single plane configs can enable self refresh */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002296 if (enabled == 1 && IS_IGD(dev))
2297 igd_enable_cxsr(dev, sr_clock, pixel_size);
2298 else if (IS_IGD(dev))
2299 igd_disable_cxsr(dev);
2300
Jesse Barnes652c3932009-08-17 13:31:43 -07002301 if (IS_G4X(dev))
2302 g4x_update_wm(dev);
2303 else if (IS_I965G(dev))
Shaohua Li7662c8b2009-06-26 11:23:55 +08002304 i965_update_wm(dev);
2305 else if (IS_I9XX(dev) || IS_MOBILE(dev))
2306 i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay,
2307 pixel_size);
2308 else
2309 i830_update_wm(dev, planea_clock, pixel_size);
2310}
2311
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002312static int intel_crtc_mode_set(struct drm_crtc *crtc,
2313 struct drm_display_mode *mode,
2314 struct drm_display_mode *adjusted_mode,
2315 int x, int y,
2316 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002317{
2318 struct drm_device *dev = crtc->dev;
2319 struct drm_i915_private *dev_priv = dev->dev_private;
2320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2321 int pipe = intel_crtc->pipe;
2322 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2323 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2324 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2325 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
2326 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2327 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2328 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2329 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2330 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2331 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2332 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2333 int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
2334 int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
2335 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
Kristian Høgsberg43565a02009-02-13 20:56:52 -05002336 int refclk, num_outputs = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07002337 intel_clock_t clock, reduced_clock;
2338 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2339 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002340 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002341 bool is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08002342 struct drm_mode_config *mode_config = &dev->mode_config;
2343 struct drm_connector *connector;
Ma Lingd4906092009-03-18 20:13:27 +08002344 const intel_limit_t *limit;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002345 int ret;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002346 struct fdi_m_n m_n = {0};
2347 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2348 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2349 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2350 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2351 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2352 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2353 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
Zhenyu Wang541998a2009-06-05 15:38:44 +08002354 int lvds_reg = LVDS;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002355 u32 temp;
2356 int sdvo_pixel_multiply;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002357 int target_clock;
Jesse Barnes79e53942008-11-07 14:24:08 -08002358
2359 drm_vblank_pre_modeset(dev, pipe);
2360
2361 list_for_each_entry(connector, &mode_config->connector_list, head) {
2362 struct intel_output *intel_output = to_intel_output(connector);
2363
2364 if (!connector->encoder || connector->encoder->crtc != crtc)
2365 continue;
2366
2367 switch (intel_output->type) {
2368 case INTEL_OUTPUT_LVDS:
2369 is_lvds = true;
2370 break;
2371 case INTEL_OUTPUT_SDVO:
Eric Anholt7d573822009-01-02 13:33:00 -08002372 case INTEL_OUTPUT_HDMI:
Jesse Barnes79e53942008-11-07 14:24:08 -08002373 is_sdvo = true;
Jesse Barnese2f0ba92009-02-02 15:11:52 -08002374 if (intel_output->needs_tv_clock)
2375 is_tv = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08002376 break;
2377 case INTEL_OUTPUT_DVO:
2378 is_dvo = true;
2379 break;
2380 case INTEL_OUTPUT_TVOUT:
2381 is_tv = true;
2382 break;
2383 case INTEL_OUTPUT_ANALOG:
2384 is_crt = true;
2385 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002386 case INTEL_OUTPUT_DISPLAYPORT:
2387 is_dp = true;
2388 break;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002389 case INTEL_OUTPUT_EDP:
2390 is_edp = true;
2391 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08002392 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05002393
2394 num_outputs++;
Jesse Barnes79e53942008-11-07 14:24:08 -08002395 }
2396
Kristian Høgsberg43565a02009-02-13 20:56:52 -05002397 if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2398 refclk = dev_priv->lvds_ssc_freq * 1000;
2399 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
2400 } else if (IS_I9XX(dev)) {
Jesse Barnes79e53942008-11-07 14:24:08 -08002401 refclk = 96000;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002402 if (IS_IGDNG(dev))
2403 refclk = 120000; /* 120Mhz refclk */
Jesse Barnes79e53942008-11-07 14:24:08 -08002404 } else {
2405 refclk = 48000;
2406 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002407
Jesse Barnes79e53942008-11-07 14:24:08 -08002408
Ma Lingd4906092009-03-18 20:13:27 +08002409 /*
2410 * Returns a set of divisors for the desired target clock with the given
2411 * refclk, or FALSE. The returned values represent the clock equation:
2412 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2413 */
2414 limit = intel_limit(crtc);
2415 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08002416 if (!ok) {
2417 DRM_ERROR("Couldn't find PLL settings for mode!\n");
Chris Wilson1f803ee2009-06-06 09:45:59 +01002418 drm_vblank_post_modeset(dev, pipe);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002419 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002420 }
2421
Jesse Barnes652c3932009-08-17 13:31:43 -07002422 if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) {
2423 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2424 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2425 (adjusted_mode->clock*3/4),
2426 refclk,
2427 &reduced_clock);
2428 }
2429
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08002430 /* SDVO TV has fixed PLL values depend on its clock range,
2431 this mirrors vbios setting. */
2432 if (is_sdvo && is_tv) {
2433 if (adjusted_mode->clock >= 100000
2434 && adjusted_mode->clock < 140500) {
2435 clock.p1 = 2;
2436 clock.p2 = 10;
2437 clock.n = 3;
2438 clock.m1 = 16;
2439 clock.m2 = 8;
2440 } else if (adjusted_mode->clock >= 140500
2441 && adjusted_mode->clock <= 200000) {
2442 clock.p1 = 1;
2443 clock.p2 = 10;
2444 clock.n = 6;
2445 clock.m1 = 12;
2446 clock.m2 = 8;
2447 }
2448 }
2449
Zhenyu Wang2c072452009-06-05 15:38:42 +08002450 /* FDI link */
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002451 if (IS_IGDNG(dev)) {
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002452 int lane, link_bw;
2453 /* eDP doesn't require FDI link, so just set DP M/N
2454 according to current link config */
2455 if (is_edp) {
2456 struct drm_connector *edp;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002457 target_clock = mode->clock;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002458 edp = intel_pipe_get_output(crtc);
2459 intel_edp_link_config(to_intel_output(edp),
2460 &lane, &link_bw);
2461 } else {
2462 /* DP over FDI requires target mode clock
2463 instead of link clock */
2464 if (is_dp)
2465 target_clock = mode->clock;
2466 else
2467 target_clock = adjusted_mode->clock;
2468 lane = 4;
2469 link_bw = 270000;
2470 }
2471 igdng_compute_m_n(3, lane, target_clock,
2472 link_bw, &m_n);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002473 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08002474
Jesse Barnes652c3932009-08-17 13:31:43 -07002475 if (IS_IGD(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +08002476 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
Jesse Barnes652c3932009-08-17 13:31:43 -07002477 if (has_reduced_clock)
2478 fp2 = (1 << reduced_clock.n) << 16 |
2479 reduced_clock.m1 << 8 | reduced_clock.m2;
2480 } else {
Shaohua Li21778322009-02-23 15:19:16 +08002481 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
Jesse Barnes652c3932009-08-17 13:31:43 -07002482 if (has_reduced_clock)
2483 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
2484 reduced_clock.m2;
2485 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002486
Zhenyu Wang2c072452009-06-05 15:38:42 +08002487 if (!IS_IGDNG(dev))
2488 dpll = DPLL_VGA_MODE_DIS;
2489
Jesse Barnes79e53942008-11-07 14:24:08 -08002490 if (IS_I9XX(dev)) {
2491 if (is_lvds)
2492 dpll |= DPLLB_MODE_LVDS;
2493 else
2494 dpll |= DPLLB_MODE_DAC_SERIAL;
2495 if (is_sdvo) {
2496 dpll |= DPLL_DVO_HIGH_SPEED;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002497 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
Sean Young942642a2009-08-06 17:35:50 +08002498 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08002499 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002500 else if (IS_IGDNG(dev))
2501 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08002502 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002503 if (is_dp)
2504 dpll |= DPLL_DVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08002505
2506 /* compute bitmask from p1 value */
Shaohua Li21778322009-02-23 15:19:16 +08002507 if (IS_IGD(dev))
2508 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002509 else {
Shaohua Li21778322009-02-23 15:19:16 +08002510 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002511 /* also FPA1 */
2512 if (IS_IGDNG(dev))
2513 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Jesse Barnes652c3932009-08-17 13:31:43 -07002514 if (IS_G4X(dev) && has_reduced_clock)
2515 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002516 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002517 switch (clock.p2) {
2518 case 5:
2519 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
2520 break;
2521 case 7:
2522 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
2523 break;
2524 case 10:
2525 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
2526 break;
2527 case 14:
2528 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
2529 break;
2530 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08002531 if (IS_I965G(dev) && !IS_IGDNG(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08002532 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2533 } else {
2534 if (is_lvds) {
2535 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2536 } else {
2537 if (clock.p1 == 2)
2538 dpll |= PLL_P1_DIVIDE_BY_TWO;
2539 else
2540 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2541 if (clock.p2 == 4)
2542 dpll |= PLL_P2_DIVIDE_BY_4;
2543 }
2544 }
2545
Kristian Høgsberg43565a02009-02-13 20:56:52 -05002546 if (is_sdvo && is_tv)
2547 dpll |= PLL_REF_INPUT_TVCLKINBC;
2548 else if (is_tv)
Jesse Barnes79e53942008-11-07 14:24:08 -08002549 /* XXX: just matching BIOS for now */
Kristian Høgsberg43565a02009-02-13 20:56:52 -05002550 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
Jesse Barnes79e53942008-11-07 14:24:08 -08002551 dpll |= 3;
Kristian Høgsberg43565a02009-02-13 20:56:52 -05002552 else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
2553 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08002554 else
2555 dpll |= PLL_REF_INPUT_DREFCLK;
2556
2557 /* setup pipeconf */
2558 pipeconf = I915_READ(pipeconf_reg);
2559
2560 /* Set up the display plane register */
2561 dspcntr = DISPPLANE_GAMMA_ENABLE;
2562
Zhenyu Wang2c072452009-06-05 15:38:42 +08002563 /* IGDNG's plane is forced to pipe, bit 24 is to
2564 enable color space conversion */
2565 if (!IS_IGDNG(dev)) {
2566 if (pipe == 0)
2567 dspcntr |= DISPPLANE_SEL_PIPE_A;
2568 else
2569 dspcntr |= DISPPLANE_SEL_PIPE_B;
2570 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002571
2572 if (pipe == 0 && !IS_I965G(dev)) {
2573 /* Enable pixel doubling when the dot clock is > 90% of the (display)
2574 * core speed.
2575 *
2576 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
2577 * pipe == 0 check?
2578 */
2579 if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
2580 pipeconf |= PIPEACONF_DOUBLE_WIDE;
2581 else
2582 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
2583 }
2584
2585 dspcntr |= DISPLAY_PLANE_ENABLE;
2586 pipeconf |= PIPEACONF_ENABLE;
2587 dpll |= DPLL_VCO_ENABLE;
2588
2589
2590 /* Disable the panel fitter if it was on our pipe */
Zhenyu Wang2c072452009-06-05 15:38:42 +08002591 if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08002592 I915_WRITE(PFIT_CONTROL, 0);
2593
2594 DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
2595 drm_mode_debug_printmodeline(mode);
2596
Zhenyu Wang2c072452009-06-05 15:38:42 +08002597 /* assign to IGDNG registers */
2598 if (IS_IGDNG(dev)) {
2599 fp_reg = pch_fp_reg;
2600 dpll_reg = pch_dpll_reg;
2601 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002602
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002603 if (is_edp) {
2604 igdng_disable_pll_edp(crtc);
2605 } else if ((dpll & DPLL_VCO_ENABLE)) {
Jesse Barnes79e53942008-11-07 14:24:08 -08002606 I915_WRITE(fp_reg, fp);
2607 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
2608 I915_READ(dpll_reg);
2609 udelay(150);
2610 }
2611
2612 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
2613 * This is an exception to the general rule that mode_set doesn't turn
2614 * things on.
2615 */
2616 if (is_lvds) {
Zhenyu Wang541998a2009-06-05 15:38:44 +08002617 u32 lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -08002618
Zhenyu Wang541998a2009-06-05 15:38:44 +08002619 if (IS_IGDNG(dev))
2620 lvds_reg = PCH_LVDS;
2621
2622 lvds = I915_READ(lvds_reg);
Jesse Barnes79e53942008-11-07 14:24:08 -08002623 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
2624 /* Set the B0-B3 data pairs corresponding to whether we're going to
2625 * set the DPLLs for dual-channel mode or not.
2626 */
2627 if (clock.p2 == 7)
2628 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
2629 else
2630 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
2631
2632 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
2633 * appropriately here, but we need to look more thoroughly into how
2634 * panels behave in the two modes.
2635 */
2636
Zhenyu Wang541998a2009-06-05 15:38:44 +08002637 I915_WRITE(lvds_reg, lvds);
2638 I915_READ(lvds_reg);
Jesse Barnes79e53942008-11-07 14:24:08 -08002639 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002640 if (is_dp)
2641 intel_dp_set_m_n(crtc, mode, adjusted_mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08002642
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002643 if (!is_edp) {
2644 I915_WRITE(fp_reg, fp);
Jesse Barnes79e53942008-11-07 14:24:08 -08002645 I915_WRITE(dpll_reg, dpll);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002646 I915_READ(dpll_reg);
2647 /* Wait for the clocks to stabilize. */
2648 udelay(150);
2649
2650 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
2651 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2652 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
2653 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
2654 } else {
2655 /* write it again -- the BIOS does, after all */
2656 I915_WRITE(dpll_reg, dpll);
2657 }
2658 I915_READ(dpll_reg);
2659 /* Wait for the clocks to stabilize. */
2660 udelay(150);
Jesse Barnes79e53942008-11-07 14:24:08 -08002661 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002662
Jesse Barnes652c3932009-08-17 13:31:43 -07002663 if (is_lvds && has_reduced_clock && i915_powersave) {
2664 I915_WRITE(fp_reg + 4, fp2);
2665 intel_crtc->lowfreq_avail = true;
2666 if (HAS_PIPE_CXSR(dev)) {
2667 DRM_DEBUG("enabling CxSR downclocking\n");
2668 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
2669 }
2670 } else {
2671 I915_WRITE(fp_reg + 4, fp);
2672 intel_crtc->lowfreq_avail = false;
2673 if (HAS_PIPE_CXSR(dev)) {
2674 DRM_DEBUG("disabling CxSR downclocking\n");
2675 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
2676 }
2677 }
2678
Jesse Barnes79e53942008-11-07 14:24:08 -08002679 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
2680 ((adjusted_mode->crtc_htotal - 1) << 16));
2681 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
2682 ((adjusted_mode->crtc_hblank_end - 1) << 16));
2683 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
2684 ((adjusted_mode->crtc_hsync_end - 1) << 16));
2685 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
2686 ((adjusted_mode->crtc_vtotal - 1) << 16));
2687 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
2688 ((adjusted_mode->crtc_vblank_end - 1) << 16));
2689 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
2690 ((adjusted_mode->crtc_vsync_end - 1) << 16));
2691 /* pipesrc and dspsize control the size that is scaled from, which should
2692 * always be the user's requested size.
2693 */
Zhenyu Wang2c072452009-06-05 15:38:42 +08002694 if (!IS_IGDNG(dev)) {
2695 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
2696 (mode->hdisplay - 1));
2697 I915_WRITE(dsppos_reg, 0);
2698 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002699 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
Zhenyu Wang2c072452009-06-05 15:38:42 +08002700
2701 if (IS_IGDNG(dev)) {
2702 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
2703 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
2704 I915_WRITE(link_m1_reg, m_n.link_m);
2705 I915_WRITE(link_n1_reg, m_n.link_n);
2706
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002707 if (is_edp) {
2708 igdng_set_pll_edp(crtc, adjusted_mode->clock);
2709 } else {
2710 /* enable FDI RX PLL too */
2711 temp = I915_READ(fdi_rx_reg);
2712 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
2713 udelay(200);
2714 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08002715 }
2716
Jesse Barnes79e53942008-11-07 14:24:08 -08002717 I915_WRITE(pipeconf_reg, pipeconf);
2718 I915_READ(pipeconf_reg);
2719
2720 intel_wait_for_vblank(dev);
2721
2722 I915_WRITE(dspcntr_reg, dspcntr);
2723
2724 /* Flush the plane changes */
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002725 ret = intel_pipe_set_base(crtc, x, y, old_fb);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002726
2727 intel_update_watermarks(dev);
2728
Jesse Barnes79e53942008-11-07 14:24:08 -08002729 drm_vblank_post_modeset(dev, pipe);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002730
Chris Wilson1f803ee2009-06-06 09:45:59 +01002731 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002732}
2733
2734/** Loads the palette/gamma unit for the CRTC with the prepared values */
2735void intel_crtc_load_lut(struct drm_crtc *crtc)
2736{
2737 struct drm_device *dev = crtc->dev;
2738 struct drm_i915_private *dev_priv = dev->dev_private;
2739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2740 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
2741 int i;
2742
2743 /* The clocks have to be on to load the palette. */
2744 if (!crtc->enabled)
2745 return;
2746
Zhenyu Wang2c072452009-06-05 15:38:42 +08002747 /* use legacy palette for IGDNG */
2748 if (IS_IGDNG(dev))
2749 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
2750 LGC_PALETTE_B;
2751
Jesse Barnes79e53942008-11-07 14:24:08 -08002752 for (i = 0; i < 256; i++) {
2753 I915_WRITE(palreg + 4 * i,
2754 (intel_crtc->lut_r[i] << 16) |
2755 (intel_crtc->lut_g[i] << 8) |
2756 intel_crtc->lut_b[i]);
2757 }
2758}
2759
2760static int intel_crtc_cursor_set(struct drm_crtc *crtc,
2761 struct drm_file *file_priv,
2762 uint32_t handle,
2763 uint32_t width, uint32_t height)
2764{
2765 struct drm_device *dev = crtc->dev;
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2768 struct drm_gem_object *bo;
2769 struct drm_i915_gem_object *obj_priv;
2770 int pipe = intel_crtc->pipe;
2771 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
2772 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
Jesse Barnes14b60392009-05-20 16:47:08 -04002773 uint32_t temp = I915_READ(control);
Jesse Barnes79e53942008-11-07 14:24:08 -08002774 size_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05002775 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002776
2777 DRM_DEBUG("\n");
2778
2779 /* if we want to turn off the cursor ignore width and height */
2780 if (!handle) {
2781 DRM_DEBUG("cursor off\n");
Jesse Barnes14b60392009-05-20 16:47:08 -04002782 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
2783 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
2784 temp |= CURSOR_MODE_DISABLE;
2785 } else {
2786 temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
2787 }
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05002788 addr = 0;
2789 bo = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10002790 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05002791 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08002792 }
2793
2794 /* Currently we only support 64x64 cursors */
2795 if (width != 64 || height != 64) {
2796 DRM_ERROR("we currently only support 64x64 cursors\n");
2797 return -EINVAL;
2798 }
2799
2800 bo = drm_gem_object_lookup(dev, file_priv, handle);
2801 if (!bo)
2802 return -ENOENT;
2803
2804 obj_priv = bo->driver_private;
2805
2806 if (bo->size < width * height * 4) {
2807 DRM_ERROR("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10002808 ret = -ENOMEM;
2809 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08002810 }
2811
Dave Airlie71acb5e2008-12-30 20:31:46 +10002812 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05002813 mutex_lock(&dev->struct_mutex);
Dave Airlie71acb5e2008-12-30 20:31:46 +10002814 if (!dev_priv->cursor_needs_physical) {
2815 ret = i915_gem_object_pin(bo, PAGE_SIZE);
2816 if (ret) {
2817 DRM_ERROR("failed to pin cursor bo\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05002818 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10002819 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002820 addr = obj_priv->gtt_offset;
Dave Airlie71acb5e2008-12-30 20:31:46 +10002821 } else {
2822 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
2823 if (ret) {
2824 DRM_ERROR("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05002825 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10002826 }
2827 addr = obj_priv->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05002828 }
2829
Jesse Barnes14b60392009-05-20 16:47:08 -04002830 if (!IS_I9XX(dev))
2831 I915_WRITE(CURSIZE, (height << 12) | width);
2832
2833 /* Hooray for CUR*CNTR differences */
2834 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
2835 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
2836 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
2837 temp |= (pipe << 28); /* Connect to correct pipe */
2838 } else {
2839 temp &= ~(CURSOR_FORMAT_MASK);
2840 temp |= CURSOR_ENABLE;
2841 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
2842 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002843
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05002844 finish:
Jesse Barnes79e53942008-11-07 14:24:08 -08002845 I915_WRITE(control, temp);
2846 I915_WRITE(base, addr);
2847
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05002848 if (intel_crtc->cursor_bo) {
Dave Airlie71acb5e2008-12-30 20:31:46 +10002849 if (dev_priv->cursor_needs_physical) {
2850 if (intel_crtc->cursor_bo != bo)
2851 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
2852 } else
2853 i915_gem_object_unpin(intel_crtc->cursor_bo);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05002854 drm_gem_object_unreference(intel_crtc->cursor_bo);
2855 }
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05002856 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05002857
2858 intel_crtc->cursor_addr = addr;
2859 intel_crtc->cursor_bo = bo;
2860
Jesse Barnes79e53942008-11-07 14:24:08 -08002861 return 0;
Dave Airlie34b8686e2009-01-15 14:03:07 +10002862fail:
2863 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05002864fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10002865 drm_gem_object_unreference(bo);
2866 mutex_unlock(&dev->struct_mutex);
2867 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002868}
2869
2870static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
2871{
2872 struct drm_device *dev = crtc->dev;
2873 struct drm_i915_private *dev_priv = dev->dev_private;
2874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07002875 struct intel_framebuffer *intel_fb;
Jesse Barnes79e53942008-11-07 14:24:08 -08002876 int pipe = intel_crtc->pipe;
2877 uint32_t temp = 0;
2878 uint32_t adder;
2879
Jesse Barnes652c3932009-08-17 13:31:43 -07002880 if (crtc->fb) {
2881 intel_fb = to_intel_framebuffer(crtc->fb);
2882 intel_mark_busy(dev, intel_fb->obj);
2883 }
2884
Jesse Barnes79e53942008-11-07 14:24:08 -08002885 if (x < 0) {
Keith Packard2245fda2009-05-30 20:42:29 -07002886 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08002887 x = -x;
2888 }
2889 if (y < 0) {
Keith Packard2245fda2009-05-30 20:42:29 -07002890 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08002891 y = -y;
2892 }
2893
Keith Packard2245fda2009-05-30 20:42:29 -07002894 temp |= x << CURSOR_X_SHIFT;
2895 temp |= y << CURSOR_Y_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08002896
2897 adder = intel_crtc->cursor_addr;
2898 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
2899 I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
2900
2901 return 0;
2902}
2903
2904/** Sets the color ramps on behalf of RandR */
2905void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
2906 u16 blue, int regno)
2907{
2908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2909
2910 intel_crtc->lut_r[regno] = red >> 8;
2911 intel_crtc->lut_g[regno] = green >> 8;
2912 intel_crtc->lut_b[regno] = blue >> 8;
2913}
2914
2915static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2916 u16 *blue, uint32_t size)
2917{
2918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2919 int i;
2920
2921 if (size != 256)
2922 return;
2923
2924 for (i = 0; i < 256; i++) {
2925 intel_crtc->lut_r[i] = red[i] >> 8;
2926 intel_crtc->lut_g[i] = green[i] >> 8;
2927 intel_crtc->lut_b[i] = blue[i] >> 8;
2928 }
2929
2930 intel_crtc_load_lut(crtc);
2931}
2932
2933/**
2934 * Get a pipe with a simple mode set on it for doing load-based monitor
2935 * detection.
2936 *
2937 * It will be up to the load-detect code to adjust the pipe as appropriate for
2938 * its requirements. The pipe will be connected to no other outputs.
2939 *
2940 * Currently this code will only succeed if there is a pipe with no outputs
2941 * configured for it. In the future, it could choose to temporarily disable
2942 * some outputs to free up a pipe for its use.
2943 *
2944 * \return crtc, or NULL if no pipes are available.
2945 */
2946
2947/* VESA 640x480x72Hz mode to set on the pipe */
2948static struct drm_display_mode load_detect_mode = {
2949 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
2950 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
2951};
2952
2953struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
2954 struct drm_display_mode *mode,
2955 int *dpms_mode)
2956{
2957 struct intel_crtc *intel_crtc;
2958 struct drm_crtc *possible_crtc;
2959 struct drm_crtc *supported_crtc =NULL;
2960 struct drm_encoder *encoder = &intel_output->enc;
2961 struct drm_crtc *crtc = NULL;
2962 struct drm_device *dev = encoder->dev;
2963 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2964 struct drm_crtc_helper_funcs *crtc_funcs;
2965 int i = -1;
2966
2967 /*
2968 * Algorithm gets a little messy:
2969 * - if the connector already has an assigned crtc, use it (but make
2970 * sure it's on first)
2971 * - try to find the first unused crtc that can drive this connector,
2972 * and use that if we find one
2973 * - if there are no unused crtcs available, try to use the first
2974 * one we found that supports the connector
2975 */
2976
2977 /* See if we already have a CRTC for this connector */
2978 if (encoder->crtc) {
2979 crtc = encoder->crtc;
2980 /* Make sure the crtc and connector are running */
2981 intel_crtc = to_intel_crtc(crtc);
2982 *dpms_mode = intel_crtc->dpms_mode;
2983 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
2984 crtc_funcs = crtc->helper_private;
2985 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2986 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2987 }
2988 return crtc;
2989 }
2990
2991 /* Find an unused one (if possible) */
2992 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
2993 i++;
2994 if (!(encoder->possible_crtcs & (1 << i)))
2995 continue;
2996 if (!possible_crtc->enabled) {
2997 crtc = possible_crtc;
2998 break;
2999 }
3000 if (!supported_crtc)
3001 supported_crtc = possible_crtc;
3002 }
3003
3004 /*
3005 * If we didn't find an unused CRTC, don't use any.
3006 */
3007 if (!crtc) {
3008 return NULL;
3009 }
3010
3011 encoder->crtc = crtc;
Keith Packard03d60692009-06-05 18:19:56 -07003012 intel_output->base.encoder = encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08003013 intel_output->load_detect_temp = true;
3014
3015 intel_crtc = to_intel_crtc(crtc);
3016 *dpms_mode = intel_crtc->dpms_mode;
3017
3018 if (!crtc->enabled) {
3019 if (!mode)
3020 mode = &load_detect_mode;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05003021 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08003022 } else {
3023 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3024 crtc_funcs = crtc->helper_private;
3025 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3026 }
3027
3028 /* Add this connector to the crtc */
3029 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3030 encoder_funcs->commit(encoder);
3031 }
3032 /* let the connector get through one full cycle before testing */
3033 intel_wait_for_vblank(dev);
3034
3035 return crtc;
3036}
3037
3038void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3039{
3040 struct drm_encoder *encoder = &intel_output->enc;
3041 struct drm_device *dev = encoder->dev;
3042 struct drm_crtc *crtc = encoder->crtc;
3043 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3044 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3045
3046 if (intel_output->load_detect_temp) {
3047 encoder->crtc = NULL;
Keith Packard03d60692009-06-05 18:19:56 -07003048 intel_output->base.encoder = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08003049 intel_output->load_detect_temp = false;
3050 crtc->enabled = drm_helper_crtc_in_use(crtc);
3051 drm_helper_disable_unused_functions(dev);
3052 }
3053
3054 /* Switch crtc and output back off if necessary */
3055 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3056 if (encoder->crtc == crtc)
3057 encoder_funcs->dpms(encoder, dpms_mode);
3058 crtc_funcs->dpms(crtc, dpms_mode);
3059 }
3060}
3061
3062/* Returns the clock of the currently programmed mode of the given pipe. */
3063static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3064{
3065 struct drm_i915_private *dev_priv = dev->dev_private;
3066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3067 int pipe = intel_crtc->pipe;
3068 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3069 u32 fp;
3070 intel_clock_t clock;
3071
3072 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3073 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3074 else
3075 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3076
3077 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08003078 if (IS_IGD(dev)) {
3079 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3080 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
3081 } else {
3082 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3083 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3084 }
3085
Jesse Barnes79e53942008-11-07 14:24:08 -08003086 if (IS_I9XX(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +08003087 if (IS_IGD(dev))
3088 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
3089 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
3090 else
3091 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08003092 DPLL_FPA01_P1_POST_DIV_SHIFT);
3093
3094 switch (dpll & DPLL_MODE_MASK) {
3095 case DPLLB_MODE_DAC_SERIAL:
3096 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3097 5 : 10;
3098 break;
3099 case DPLLB_MODE_LVDS:
3100 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3101 7 : 14;
3102 break;
3103 default:
3104 DRM_DEBUG("Unknown DPLL mode %08x in programmed "
3105 "mode\n", (int)(dpll & DPLL_MODE_MASK));
3106 return 0;
3107 }
3108
3109 /* XXX: Handle the 100Mhz refclk */
Shaohua Li21778322009-02-23 15:19:16 +08003110 intel_clock(dev, 96000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08003111 } else {
3112 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3113
3114 if (is_lvds) {
3115 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3116 DPLL_FPA01_P1_POST_DIV_SHIFT);
3117 clock.p2 = 14;
3118
3119 if ((dpll & PLL_REF_INPUT_MASK) ==
3120 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3121 /* XXX: might not be 66MHz */
Shaohua Li21778322009-02-23 15:19:16 +08003122 intel_clock(dev, 66000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08003123 } else
Shaohua Li21778322009-02-23 15:19:16 +08003124 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08003125 } else {
3126 if (dpll & PLL_P1_DIVIDE_BY_TWO)
3127 clock.p1 = 2;
3128 else {
3129 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3130 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3131 }
3132 if (dpll & PLL_P2_DIVIDE_BY_4)
3133 clock.p2 = 4;
3134 else
3135 clock.p2 = 2;
3136
Shaohua Li21778322009-02-23 15:19:16 +08003137 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08003138 }
3139 }
3140
3141 /* XXX: It would be nice to validate the clocks, but we can't reuse
3142 * i830PllIsValid() because it relies on the xf86_config connector
3143 * configuration being accurate, which it isn't necessarily.
3144 */
3145
3146 return clock.dot;
3147}
3148
3149/** Returns the currently programmed mode of the given pipe. */
3150struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3151 struct drm_crtc *crtc)
3152{
3153 struct drm_i915_private *dev_priv = dev->dev_private;
3154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3155 int pipe = intel_crtc->pipe;
3156 struct drm_display_mode *mode;
3157 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3158 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3159 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3160 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3161
3162 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3163 if (!mode)
3164 return NULL;
3165
3166 mode->clock = intel_crtc_clock_get(dev, crtc);
3167 mode->hdisplay = (htot & 0xffff) + 1;
3168 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3169 mode->hsync_start = (hsync & 0xffff) + 1;
3170 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3171 mode->vdisplay = (vtot & 0xffff) + 1;
3172 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3173 mode->vsync_start = (vsync & 0xffff) + 1;
3174 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3175
3176 drm_mode_set_name(mode);
3177 drm_mode_set_crtcinfo(mode, 0);
3178
3179 return mode;
3180}
3181
Jesse Barnes652c3932009-08-17 13:31:43 -07003182#define GPU_IDLE_TIMEOUT 500 /* ms */
3183
3184/* When this timer fires, we've been idle for awhile */
3185static void intel_gpu_idle_timer(unsigned long arg)
3186{
3187 struct drm_device *dev = (struct drm_device *)arg;
3188 drm_i915_private_t *dev_priv = dev->dev_private;
3189
3190 DRM_DEBUG("idle timer fired, downclocking\n");
3191
3192 dev_priv->busy = false;
3193
3194 schedule_work(&dev_priv->idle_work);
3195}
3196
3197void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3198{
3199 drm_i915_private_t *dev_priv = dev->dev_private;
3200
3201 if (IS_IGDNG(dev))
3202 return;
3203
3204 if (!dev_priv->render_reclock_avail) {
Eric Anholt67cf7812009-08-31 08:52:02 -07003205 DRM_DEBUG("not reclocking render clock\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07003206 return;
3207 }
3208
3209 /* Restore render clock frequency to original value */
3210 if (IS_G4X(dev) || IS_I9XX(dev))
3211 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3212 else if (IS_I85X(dev))
3213 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3214 DRM_DEBUG("increasing render clock frequency\n");
3215
3216 /* Schedule downclock */
3217 if (schedule)
3218 mod_timer(&dev_priv->idle_timer, jiffies +
3219 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3220}
3221
3222void intel_decrease_renderclock(struct drm_device *dev)
3223{
3224 drm_i915_private_t *dev_priv = dev->dev_private;
3225
3226 if (IS_IGDNG(dev))
3227 return;
3228
3229 if (!dev_priv->render_reclock_avail) {
Eric Anholt67cf7812009-08-31 08:52:02 -07003230 DRM_DEBUG("not reclocking render clock\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07003231 return;
3232 }
3233
3234 if (IS_G4X(dev)) {
3235 u16 gcfgc;
3236
3237 /* Adjust render clock... */
3238 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3239
3240 /* Down to minimum... */
3241 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3242 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3243
3244 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3245 } else if (IS_I965G(dev)) {
3246 u16 gcfgc;
3247
3248 /* Adjust render clock... */
3249 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3250
3251 /* Down to minimum... */
3252 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3253 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3254
3255 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3256 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3257 u16 gcfgc;
3258
3259 /* Adjust render clock... */
3260 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3261
3262 /* Down to minimum... */
3263 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3264 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3265
3266 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3267 } else if (IS_I915G(dev)) {
3268 u16 gcfgc;
3269
3270 /* Adjust render clock... */
3271 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3272
3273 /* Down to minimum... */
3274 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3275 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3276
3277 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3278 } else if (IS_I85X(dev)) {
3279 u16 hpllcc;
3280
3281 /* Adjust render clock... */
3282 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3283
3284 /* Up to maximum... */
3285 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3286 hpllcc |= GC_CLOCK_133_200;
3287
3288 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3289 }
3290 DRM_DEBUG("decreasing render clock frequency\n");
3291}
3292
3293/* Note that no increase function is needed for this - increase_renderclock()
3294 * will also rewrite these bits
3295 */
3296void intel_decrease_displayclock(struct drm_device *dev)
3297{
3298 if (IS_IGDNG(dev))
3299 return;
3300
3301 if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3302 IS_I915GM(dev)) {
3303 u16 gcfgc;
3304
3305 /* Adjust render clock... */
3306 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3307
3308 /* Down to minimum... */
3309 gcfgc &= ~0xf0;
3310 gcfgc |= 0x80;
3311
3312 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3313 }
3314}
3315
3316#define CRTC_IDLE_TIMEOUT 1000 /* ms */
3317
3318static void intel_crtc_idle_timer(unsigned long arg)
3319{
3320 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3321 struct drm_crtc *crtc = &intel_crtc->base;
3322 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3323
3324 DRM_DEBUG("idle timer fired, downclocking\n");
3325
3326 intel_crtc->busy = false;
3327
3328 schedule_work(&dev_priv->idle_work);
3329}
3330
3331static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3332{
3333 struct drm_device *dev = crtc->dev;
3334 drm_i915_private_t *dev_priv = dev->dev_private;
3335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3336 int pipe = intel_crtc->pipe;
3337 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3338 int dpll = I915_READ(dpll_reg);
3339
3340 if (IS_IGDNG(dev))
3341 return;
3342
3343 if (!dev_priv->lvds_downclock_avail)
3344 return;
3345
3346 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3347 DRM_DEBUG("upclocking LVDS\n");
3348
3349 /* Unlock panel regs */
3350 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3351
3352 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3353 I915_WRITE(dpll_reg, dpll);
3354 dpll = I915_READ(dpll_reg);
3355 intel_wait_for_vblank(dev);
3356 dpll = I915_READ(dpll_reg);
3357 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3358 DRM_DEBUG("failed to upclock LVDS!\n");
3359
3360 /* ...and lock them again */
3361 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3362 }
3363
3364 /* Schedule downclock */
3365 if (schedule)
3366 mod_timer(&intel_crtc->idle_timer, jiffies +
3367 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3368}
3369
3370static void intel_decrease_pllclock(struct drm_crtc *crtc)
3371{
3372 struct drm_device *dev = crtc->dev;
3373 drm_i915_private_t *dev_priv = dev->dev_private;
3374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3375 int pipe = intel_crtc->pipe;
3376 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3377 int dpll = I915_READ(dpll_reg);
3378
3379 if (IS_IGDNG(dev))
3380 return;
3381
3382 if (!dev_priv->lvds_downclock_avail)
3383 return;
3384
3385 /*
3386 * Since this is called by a timer, we should never get here in
3387 * the manual case.
3388 */
3389 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3390 DRM_DEBUG("downclocking LVDS\n");
3391
3392 /* Unlock panel regs */
3393 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3394
3395 dpll |= DISPLAY_RATE_SELECT_FPA1;
3396 I915_WRITE(dpll_reg, dpll);
3397 dpll = I915_READ(dpll_reg);
3398 intel_wait_for_vblank(dev);
3399 dpll = I915_READ(dpll_reg);
3400 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3401 DRM_DEBUG("failed to downclock LVDS!\n");
3402
3403 /* ...and lock them again */
3404 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3405 }
3406
3407}
3408
3409/**
3410 * intel_idle_update - adjust clocks for idleness
3411 * @work: work struct
3412 *
3413 * Either the GPU or display (or both) went idle. Check the busy status
3414 * here and adjust the CRTC and GPU clocks as necessary.
3415 */
3416static void intel_idle_update(struct work_struct *work)
3417{
3418 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3419 idle_work);
3420 struct drm_device *dev = dev_priv->dev;
3421 struct drm_crtc *crtc;
3422 struct intel_crtc *intel_crtc;
3423
3424 if (!i915_powersave)
3425 return;
3426
3427 mutex_lock(&dev->struct_mutex);
3428
3429 /* GPU isn't processing, downclock it. */
3430 if (!dev_priv->busy) {
3431 intel_decrease_renderclock(dev);
3432 intel_decrease_displayclock(dev);
3433 }
3434
3435 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3436 /* Skip inactive CRTCs */
3437 if (!crtc->fb)
3438 continue;
3439
3440 intel_crtc = to_intel_crtc(crtc);
3441 if (!intel_crtc->busy)
3442 intel_decrease_pllclock(crtc);
3443 }
3444
3445 mutex_unlock(&dev->struct_mutex);
3446}
3447
3448/**
3449 * intel_mark_busy - mark the GPU and possibly the display busy
3450 * @dev: drm device
3451 * @obj: object we're operating on
3452 *
3453 * Callers can use this function to indicate that the GPU is busy processing
3454 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
3455 * buffer), we'll also mark the display as busy, so we know to increase its
3456 * clock frequency.
3457 */
3458void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3459{
3460 drm_i915_private_t *dev_priv = dev->dev_private;
3461 struct drm_crtc *crtc = NULL;
3462 struct intel_framebuffer *intel_fb;
3463 struct intel_crtc *intel_crtc;
3464
3465 dev_priv->busy = true;
3466 intel_increase_renderclock(dev, true);
3467
3468 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3469 if (!crtc->fb)
3470 continue;
3471
3472 intel_crtc = to_intel_crtc(crtc);
3473 intel_fb = to_intel_framebuffer(crtc->fb);
3474 if (intel_fb->obj == obj) {
3475 if (!intel_crtc->busy) {
3476 /* Non-busy -> busy, upclock */
3477 intel_increase_pllclock(crtc, true);
3478 intel_crtc->busy = true;
3479 } else {
3480 /* Busy -> busy, put off timer */
3481 mod_timer(&intel_crtc->idle_timer, jiffies +
3482 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3483 }
3484 }
3485 }
3486}
3487
Jesse Barnes79e53942008-11-07 14:24:08 -08003488static void intel_crtc_destroy(struct drm_crtc *crtc)
3489{
3490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3491
Dave Airlie7ff14552009-04-22 18:52:14 +10003492 if (intel_crtc->mode_set.mode)
3493 drm_mode_destroy(crtc->dev, intel_crtc->mode_set.mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08003494 drm_crtc_cleanup(crtc);
3495 kfree(intel_crtc);
3496}
3497
3498static const struct drm_crtc_helper_funcs intel_helper_funcs = {
3499 .dpms = intel_crtc_dpms,
3500 .mode_fixup = intel_crtc_mode_fixup,
3501 .mode_set = intel_crtc_mode_set,
3502 .mode_set_base = intel_pipe_set_base,
3503 .prepare = intel_crtc_prepare,
3504 .commit = intel_crtc_commit,
3505};
3506
3507static const struct drm_crtc_funcs intel_crtc_funcs = {
3508 .cursor_set = intel_crtc_cursor_set,
3509 .cursor_move = intel_crtc_cursor_move,
3510 .gamma_set = intel_crtc_gamma_set,
3511 .set_config = drm_crtc_helper_set_config,
3512 .destroy = intel_crtc_destroy,
3513};
3514
3515
Hannes Ederb358d0a2008-12-18 21:18:47 +01003516static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08003517{
3518 struct intel_crtc *intel_crtc;
3519 int i;
3520
3521 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
3522 if (intel_crtc == NULL)
3523 return;
3524
3525 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
3526
3527 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
3528 intel_crtc->pipe = pipe;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003529 intel_crtc->plane = pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08003530 for (i = 0; i < 256; i++) {
3531 intel_crtc->lut_r[i] = i;
3532 intel_crtc->lut_g[i] = i;
3533 intel_crtc->lut_b[i] = i;
3534 }
3535
3536 intel_crtc->cursor_addr = 0;
3537 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
3538 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
3539
3540 intel_crtc->mode_set.crtc = &intel_crtc->base;
3541 intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
3542 intel_crtc->mode_set.num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07003543 intel_crtc->busy = false;
3544
3545 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
3546 (unsigned long)intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08003547
3548 if (i915_fbpercrtc) {
3549
3550
3551
3552 }
3553}
3554
Carl Worth08d7b3d2009-04-29 14:43:54 -07003555int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
3556 struct drm_file *file_priv)
3557{
3558 drm_i915_private_t *dev_priv = dev->dev_private;
3559 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +02003560 struct drm_mode_object *drmmode_obj;
3561 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -07003562
3563 if (!dev_priv) {
3564 DRM_ERROR("called with no initialization\n");
3565 return -EINVAL;
3566 }
3567
Daniel Vetterc05422d2009-08-11 16:05:30 +02003568 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
3569 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -07003570
Daniel Vetterc05422d2009-08-11 16:05:30 +02003571 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -07003572 DRM_ERROR("no such CRTC id\n");
3573 return -EINVAL;
3574 }
3575
Daniel Vetterc05422d2009-08-11 16:05:30 +02003576 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
3577 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -07003578
Daniel Vetterc05422d2009-08-11 16:05:30 +02003579 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -07003580}
3581
Jesse Barnes79e53942008-11-07 14:24:08 -08003582struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
3583{
3584 struct drm_crtc *crtc = NULL;
3585
3586 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3588 if (intel_crtc->pipe == pipe)
3589 break;
3590 }
3591 return crtc;
3592}
3593
Hannes Ederb358d0a2008-12-18 21:18:47 +01003594static int intel_connector_clones(struct drm_device *dev, int type_mask)
Jesse Barnes79e53942008-11-07 14:24:08 -08003595{
3596 int index_mask = 0;
3597 struct drm_connector *connector;
3598 int entry = 0;
3599
3600 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3601 struct intel_output *intel_output = to_intel_output(connector);
Ma Lingf8aed702009-08-24 13:50:24 +08003602 if (type_mask & intel_output->clone_mask)
Jesse Barnes79e53942008-11-07 14:24:08 -08003603 index_mask |= (1 << entry);
3604 entry++;
3605 }
3606 return index_mask;
3607}
3608
3609
3610static void intel_setup_outputs(struct drm_device *dev)
3611{
Eric Anholt725e30a2009-01-22 13:01:02 -08003612 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08003613 struct drm_connector *connector;
3614
3615 intel_crt_init(dev);
3616
3617 /* Set up integrated LVDS */
Zhenyu Wang541998a2009-06-05 15:38:44 +08003618 if (IS_MOBILE(dev) && !IS_I830(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08003619 intel_lvds_init(dev);
3620
Zhenyu Wang2c072452009-06-05 15:38:42 +08003621 if (IS_IGDNG(dev)) {
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08003622 int found;
3623
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003624 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
3625 intel_dp_init(dev, DP_A);
3626
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08003627 if (I915_READ(HDMIB) & PORT_DETECTED) {
3628 /* check SDVOB */
3629 /* found = intel_sdvo_init(dev, HDMIB); */
3630 found = 0;
3631 if (!found)
3632 intel_hdmi_init(dev, HDMIB);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003633 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
3634 intel_dp_init(dev, PCH_DP_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08003635 }
3636
3637 if (I915_READ(HDMIC) & PORT_DETECTED)
3638 intel_hdmi_init(dev, HDMIC);
3639
3640 if (I915_READ(HDMID) & PORT_DETECTED)
3641 intel_hdmi_init(dev, HDMID);
3642
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003643 if (I915_READ(PCH_DP_C) & DP_DETECTED)
3644 intel_dp_init(dev, PCH_DP_C);
3645
3646 if (I915_READ(PCH_DP_D) & DP_DETECTED)
3647 intel_dp_init(dev, PCH_DP_D);
3648
Zhenyu Wang2c072452009-06-05 15:38:42 +08003649 } else if (IS_I9XX(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +08003650 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -08003651
Eric Anholt725e30a2009-01-22 13:01:02 -08003652 if (I915_READ(SDVOB) & SDVO_DETECTED) {
3653 found = intel_sdvo_init(dev, SDVOB);
3654 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
3655 intel_hdmi_init(dev, SDVOB);
Ma Ling27185ae2009-08-24 13:50:23 +08003656
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003657 if (!found && SUPPORTS_INTEGRATED_DP(dev))
3658 intel_dp_init(dev, DP_B);
Eric Anholt725e30a2009-01-22 13:01:02 -08003659 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -04003660
3661 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -04003662
Ma Ling27185ae2009-08-24 13:50:23 +08003663 if (I915_READ(SDVOB) & SDVO_DETECTED)
Eric Anholt725e30a2009-01-22 13:01:02 -08003664 found = intel_sdvo_init(dev, SDVOC);
Ma Ling27185ae2009-08-24 13:50:23 +08003665
3666 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
3667
3668 if (SUPPORTS_INTEGRATED_HDMI(dev))
Eric Anholt725e30a2009-01-22 13:01:02 -08003669 intel_hdmi_init(dev, SDVOC);
Ma Ling27185ae2009-08-24 13:50:23 +08003670 if (SUPPORTS_INTEGRATED_DP(dev))
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003671 intel_dp_init(dev, DP_C);
Eric Anholt725e30a2009-01-22 13:01:02 -08003672 }
Ma Ling27185ae2009-08-24 13:50:23 +08003673
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003674 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
3675 intel_dp_init(dev, DP_D);
Jesse Barnes79e53942008-11-07 14:24:08 -08003676 } else
3677 intel_dvo_init(dev);
3678
Zhenyu Wang2c072452009-06-05 15:38:42 +08003679 if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08003680 intel_tv_init(dev);
3681
3682 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3683 struct intel_output *intel_output = to_intel_output(connector);
3684 struct drm_encoder *encoder = &intel_output->enc;
Jesse Barnes79e53942008-11-07 14:24:08 -08003685
Ma Lingf8aed702009-08-24 13:50:24 +08003686 encoder->possible_crtcs = intel_output->crtc_mask;
3687 encoder->possible_clones = intel_connector_clones(dev,
3688 intel_output->clone_mask);
Jesse Barnes79e53942008-11-07 14:24:08 -08003689 }
3690}
3691
3692static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
3693{
3694 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3695 struct drm_device *dev = fb->dev;
3696
3697 if (fb->fbdev)
3698 intelfb_remove(dev, fb);
3699
3700 drm_framebuffer_cleanup(fb);
3701 mutex_lock(&dev->struct_mutex);
3702 drm_gem_object_unreference(intel_fb->obj);
3703 mutex_unlock(&dev->struct_mutex);
3704
3705 kfree(intel_fb);
3706}
3707
3708static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
3709 struct drm_file *file_priv,
3710 unsigned int *handle)
3711{
3712 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3713 struct drm_gem_object *object = intel_fb->obj;
3714
3715 return drm_gem_handle_create(file_priv, object, handle);
3716}
3717
3718static const struct drm_framebuffer_funcs intel_fb_funcs = {
3719 .destroy = intel_user_framebuffer_destroy,
3720 .create_handle = intel_user_framebuffer_create_handle,
3721};
3722
3723int intel_framebuffer_create(struct drm_device *dev,
3724 struct drm_mode_fb_cmd *mode_cmd,
3725 struct drm_framebuffer **fb,
3726 struct drm_gem_object *obj)
3727{
3728 struct intel_framebuffer *intel_fb;
3729 int ret;
3730
3731 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
3732 if (!intel_fb)
3733 return -ENOMEM;
3734
3735 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
3736 if (ret) {
3737 DRM_ERROR("framebuffer init failed %d\n", ret);
3738 return ret;
3739 }
3740
3741 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
3742
3743 intel_fb->obj = obj;
3744
3745 *fb = &intel_fb->base;
3746
3747 return 0;
3748}
3749
3750
3751static struct drm_framebuffer *
3752intel_user_framebuffer_create(struct drm_device *dev,
3753 struct drm_file *filp,
3754 struct drm_mode_fb_cmd *mode_cmd)
3755{
3756 struct drm_gem_object *obj;
3757 struct drm_framebuffer *fb;
3758 int ret;
3759
3760 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
3761 if (!obj)
3762 return NULL;
3763
3764 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
3765 if (ret) {
Jesse Barnes496818f2009-02-11 13:28:14 -08003766 mutex_lock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08003767 drm_gem_object_unreference(obj);
Jesse Barnes496818f2009-02-11 13:28:14 -08003768 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08003769 return NULL;
3770 }
3771
3772 return fb;
3773}
3774
Jesse Barnes79e53942008-11-07 14:24:08 -08003775static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -08003776 .fb_create = intel_user_framebuffer_create,
3777 .fb_changed = intelfb_probe,
3778};
3779
Jesse Barnes652c3932009-08-17 13:31:43 -07003780void intel_init_clock_gating(struct drm_device *dev)
3781{
3782 struct drm_i915_private *dev_priv = dev->dev_private;
3783
3784 /*
3785 * Disable clock gating reported to work incorrectly according to the
3786 * specs, but enable as much else as we can.
3787 */
3788 if (IS_G4X(dev)) {
3789 uint32_t dspclk_gate;
3790 I915_WRITE(RENCLK_GATE_D1, 0);
3791 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
3792 GS_UNIT_CLOCK_GATE_DISABLE |
3793 CL_UNIT_CLOCK_GATE_DISABLE);
3794 I915_WRITE(RAMCLK_GATE_D, 0);
3795 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
3796 OVRUNIT_CLOCK_GATE_DISABLE |
3797 OVCUNIT_CLOCK_GATE_DISABLE;
3798 if (IS_GM45(dev))
3799 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
3800 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
3801 } else if (IS_I965GM(dev)) {
3802 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
3803 I915_WRITE(RENCLK_GATE_D2, 0);
3804 I915_WRITE(DSPCLK_GATE_D, 0);
3805 I915_WRITE(RAMCLK_GATE_D, 0);
3806 I915_WRITE16(DEUC, 0);
3807 } else if (IS_I965G(dev)) {
3808 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
3809 I965_RCC_CLOCK_GATE_DISABLE |
3810 I965_RCPB_CLOCK_GATE_DISABLE |
3811 I965_ISC_CLOCK_GATE_DISABLE |
3812 I965_FBC_CLOCK_GATE_DISABLE);
3813 I915_WRITE(RENCLK_GATE_D2, 0);
3814 } else if (IS_I9XX(dev)) {
3815 u32 dstate = I915_READ(D_STATE);
3816
3817 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
3818 DSTATE_DOT_CLOCK_GATING;
3819 I915_WRITE(D_STATE, dstate);
3820 } else if (IS_I855(dev) || IS_I865G(dev)) {
3821 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
3822 } else if (IS_I830(dev)) {
3823 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
3824 }
3825}
3826
Jesse Barnes79e53942008-11-07 14:24:08 -08003827void intel_modeset_init(struct drm_device *dev)
3828{
Jesse Barnes652c3932009-08-17 13:31:43 -07003829 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08003830 int num_pipe;
3831 int i;
3832
3833 drm_mode_config_init(dev);
3834
3835 dev->mode_config.min_width = 0;
3836 dev->mode_config.min_height = 0;
3837
3838 dev->mode_config.funcs = (void *)&intel_mode_funcs;
3839
3840 if (IS_I965G(dev)) {
3841 dev->mode_config.max_width = 8192;
3842 dev->mode_config.max_height = 8192;
Keith Packard5e4d6fa2009-07-12 23:53:17 -07003843 } else if (IS_I9XX(dev)) {
3844 dev->mode_config.max_width = 4096;
3845 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -08003846 } else {
3847 dev->mode_config.max_width = 2048;
3848 dev->mode_config.max_height = 2048;
3849 }
3850
3851 /* set memory base */
3852 if (IS_I9XX(dev))
3853 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
3854 else
3855 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
3856
3857 if (IS_MOBILE(dev) || IS_I9XX(dev))
3858 num_pipe = 2;
3859 else
3860 num_pipe = 1;
3861 DRM_DEBUG("%d display pipe%s available.\n",
3862 num_pipe, num_pipe > 1 ? "s" : "");
3863
Jesse Barnes652c3932009-08-17 13:31:43 -07003864 if (IS_I85X(dev))
3865 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
3866 else if (IS_I9XX(dev) || IS_G4X(dev))
3867 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
3868
Jesse Barnes79e53942008-11-07 14:24:08 -08003869 for (i = 0; i < num_pipe; i++) {
3870 intel_crtc_init(dev, i);
3871 }
3872
3873 intel_setup_outputs(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -07003874
3875 intel_init_clock_gating(dev);
3876
3877 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
3878 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
3879 (unsigned long)dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08003880}
3881
3882void intel_modeset_cleanup(struct drm_device *dev)
3883{
Jesse Barnes652c3932009-08-17 13:31:43 -07003884 struct drm_i915_private *dev_priv = dev->dev_private;
3885 struct drm_crtc *crtc;
3886 struct intel_crtc *intel_crtc;
3887
3888 mutex_lock(&dev->struct_mutex);
3889
3890 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3891 /* Skip inactive CRTCs */
3892 if (!crtc->fb)
3893 continue;
3894
3895 intel_crtc = to_intel_crtc(crtc);
3896 intel_increase_pllclock(crtc, false);
3897 del_timer_sync(&intel_crtc->idle_timer);
3898 }
3899
3900 intel_increase_renderclock(dev, false);
3901 del_timer_sync(&dev_priv->idle_timer);
3902
3903 mutex_unlock(&dev->struct_mutex);
3904
Jesse Barnes79e53942008-11-07 14:24:08 -08003905 drm_mode_config_cleanup(dev);
3906}
3907
3908
3909/* current intel driver doesn't take advantage of encoders
3910 always give back the encoder for the connector
3911*/
3912struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
3913{
3914 struct intel_output *intel_output = to_intel_output(connector);
3915
3916 return &intel_output->enc;
3917}