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gerrit-public.fairphone.software / kernel / msm-4.9 / 5932f74a116cf14b69b9b3e23dcaf8698151976e / . / drivers / irqchip / Kconfig
blob: b21f12f1766dea301c7b6749d0e77bc6bfaa3ebd [file] [log] [blame]
Thomas Petazzonif6e916b2012-11-20 23:00:52 +0100[diff] [blame]1config IRQCHIP
2 def_bool y
3 depends on OF_IRQ
4
Rob Herring81243e42012-11-20 21:21:40 -0600[diff] [blame]5config ARM_GIC
6 bool
7 select IRQ_DOMAIN
8 select MULTI_IRQ_HANDLER
9
10config GIC_NON_BANKED
11 bool
12
Marc Zyngier021f6532014-06-30 16:01:31 +0100[diff] [blame]13config ARM_GIC_V3
14 bool
15 select IRQ_DOMAIN
16 select MULTI_IRQ_HANDLER
17
Uwe Kleine-König292ec082013-06-26 09:18:48 +0200[diff] [blame]18config ARM_NVIC
19 bool
20 select IRQ_DOMAIN
21 select GENERIC_IRQ_CHIP
22
Rob Herring44430ec2012-10-27 17:25:26 -0500[diff] [blame]23config ARM_VIC
24 bool
25 select IRQ_DOMAIN
26 select MULTI_IRQ_HANDLER
27
28config ARM_VIC_NR
29 int
30 default 4 if ARCH_S5PV210
Rob Herring44430ec2012-10-27 17:25:26 -0500[diff] [blame]31 default 2
32 depends on ARM_VIC
33 help
34 The maximum number of VICs available in the system, for
35 power management.
36
Boris BREZILLONb1479eb2014-07-10 19:14:18 +0200[diff] [blame]37config ATMEL_AIC_IRQ
38 bool
39 select GENERIC_IRQ_CHIP
40 select IRQ_DOMAIN
41 select MULTI_IRQ_HANDLER
42 select SPARSE_IRQ
43
44config ATMEL_AIC5_IRQ
45 bool
46 select GENERIC_IRQ_CHIP
47 select IRQ_DOMAIN
48 select MULTI_IRQ_HANDLER
49 select SPARSE_IRQ
50
Florian Fainelli7f646e92014-05-23 17:40:53 -0700[diff] [blame]51config BRCMSTB_L2_IRQ
52 bool
53 depends on ARM
54 select GENERIC_IRQ_CHIP
55 select IRQ_DOMAIN
56
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200[diff] [blame]57config DW_APB_ICTL
58 bool
59 select IRQ_DOMAIN
60
James Hoganb6ef9162013-04-22 15:43:50 +0100[diff] [blame]61config IMGPDC_IRQ
62 bool
63 select GENERIC_IRQ_CHIP
64 select IRQ_DOMAIN
65
Alexander Shiyanafc98d92014-02-02 12:07:46 +0400[diff] [blame]66config CLPS711X_IRQCHIP
67 bool
68 depends on ARCH_CLPS711X
69 select IRQ_DOMAIN
70 select MULTI_IRQ_HANDLER
71 select SPARSE_IRQ
72 default y
73
Stefan Kristiansson4db8e6d2014-05-26 23:31:42 +0300[diff] [blame]74config OR1K_PIC
75 bool
76 select IRQ_DOMAIN
77
Felipe Balbi85980662014-09-15 16:15:02 -0500[diff] [blame]78config OMAP_IRQCHIP
79 bool
80 select GENERIC_IRQ_CHIP
81 select IRQ_DOMAIN
82
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200[diff] [blame]83config ORION_IRQCHIP
84 bool
85 select IRQ_DOMAIN
86 select MULTI_IRQ_HANDLER
87
Magnus Damm44358042013-02-18 23:28:34 +0900[diff] [blame]88config RENESAS_INTC_IRQPIN
89 bool
90 select IRQ_DOMAIN
91
Magnus Dammfbc83b72013-02-27 17:15:01 +0900[diff] [blame]92config RENESAS_IRQC
93 bool
94 select IRQ_DOMAIN
95
Christian Ruppertb06eb012013-06-25 18:29:57 +0200[diff] [blame]96config TB10X_IRQC
97 bool
98 select IRQ_DOMAIN
99 select GENERIC_IRQ_CHIP
100
Linus Walleij2389d502012-10-31 22:04:31 +0100[diff] [blame]101config VERSATILE_FPGA_IRQ
102 bool
103 select IRQ_DOMAIN
104
105config VERSATILE_FPGA_IRQ_NR
106 int
107 default 4
108 depends on VERSATILE_FPGA_IRQ
Max Filippov26a8e962013-12-01 12:04:57 +0400[diff] [blame]109
110config XTENSA_MX
111 bool
112 select IRQ_DOMAIN
Sricharan R96ca8482013-12-03 15:57:23 +0530[diff] [blame]113
114config IRQ_CROSSBAR
115 bool
116 help
Masanari Iidaf54619f2014-09-18 12:09:42 +0900[diff] [blame]117 Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R96ca8482013-12-03 15:57:23 +0530[diff] [blame]118 The primary irqchip invokes the crossbar's callback which inturn allocates
119 a free irq and configures the IP. Thus the peripheral interrupts are
120 routed to one of the free irqchip interrupt lines.
Grygorii Strashko89323f82014-07-23 17:40:30 +0300[diff] [blame]121
122config KEYSTONE_IRQ
123 tristate "Keystone 2 IRQ controller IP"
124 depends on ARCH_KEYSTONE
125 help
126 Support for Texas Instruments Keystone 2 IRQ controller IP which
127 is part of the Keystone 2 IPC mechanism