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Wei WANG4c4b8c12013-04-11 10:43:40 +08001/* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 128, West Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#include <linux/module.h>
24#include <linux/delay.h>
25#include <linux/mfd/rtsx_pci.h>
26
27#include "rtsx_pcr.h"
28
29static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
30{
31 u8 val;
32
33 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
34 return val & 0x0F;
35}
36
Wei WANG773ccdf2013-08-20 14:18:51 +080037static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
38{
39 u8 driving_3v3[4][3] = {
40 {0x11, 0x11, 0x11},
41 {0x55, 0x55, 0x5C},
42 {0x99, 0x99, 0x92},
43 {0x99, 0x99, 0x92},
44 };
45 u8 driving_1v8[4][3] = {
46 {0x3C, 0x3C, 0x3C},
47 {0xB3, 0xB3, 0xB3},
48 {0xFE, 0xFE, 0xFE},
49 {0xC4, 0xC4, 0xC4},
50 };
51 u8 (*driving)[3], drive_sel;
52
53 if (voltage == OUTPUT_3V3) {
54 driving = driving_3v3;
55 drive_sel = pcr->sd30_drive_sel_3v3;
56 } else {
57 driving = driving_1v8;
58 drive_sel = pcr->sd30_drive_sel_1v8;
59 }
60
61 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
62 0xFF, driving[drive_sel][0]);
63 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
64 0xFF, driving[drive_sel][1]);
65 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
66 0xFF, driving[drive_sel][2]);
67}
68
69static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
70{
71 u32 reg;
72
73 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
74 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
75
76 if (!rtsx_vendor_setting_valid(reg))
77 return;
78
79 pcr->aspm_en = rtsx_reg_to_aspm(reg);
80 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
81 pcr->card_drive_sel &= 0x3F;
82 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
83
84 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
85 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
86 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
87 if (rtsx_reg_check_reverse_socket(reg))
88 pcr->flags |= PCR_REVERSE_SOCKET;
89}
90
Wei WANG5947c162013-08-20 14:18:52 +080091static void rts5249_force_power_down(struct rtsx_pcr *pcr)
92{
93 /* Set relink_time to 0 */
94 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
95 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
96 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
97
98 rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
99}
100
Wei WANG4c4b8c12013-04-11 10:43:40 +0800101static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
102{
103 rtsx_pci_init_cmd(pcr);
104
105 /* Configure GPIO as output */
106 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
107 /* Switch LDO3318 source from DV33 to card_3v3 */
108 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
109 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
110 /* LED shine disabled, set initial shine cycle period */
111 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
Wei WANG773ccdf2013-08-20 14:18:51 +0800112 /* Configure driving */
113 rts5249_fill_driving(pcr, OUTPUT_3V3);
114 if (pcr->flags & PCR_REVERSE_SOCKET)
115 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
116 AUTOLOAD_CFG_BASE + 3, 0xB0, 0xB0);
117 else
118 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
119 AUTOLOAD_CFG_BASE + 3, 0xB0, 0x80);
Wei WANG4c4b8c12013-04-11 10:43:40 +0800120
121 return rtsx_pci_send_cmd(pcr, 100);
122}
123
124static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
125{
126 int err;
127
128 err = rtsx_pci_write_phy_register(pcr, PHY_REG_REV, 0xFE46);
129 if (err < 0)
130 return err;
131
132 msleep(1);
133
134 return rtsx_pci_write_phy_register(pcr, PHY_BPCR, 0x05C0);
135}
136
137static int rts5249_turn_on_led(struct rtsx_pcr *pcr)
138{
139 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
140}
141
142static int rts5249_turn_off_led(struct rtsx_pcr *pcr)
143{
144 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
145}
146
147static int rts5249_enable_auto_blink(struct rtsx_pcr *pcr)
148{
149 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
150}
151
152static int rts5249_disable_auto_blink(struct rtsx_pcr *pcr)
153{
154 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
155}
156
157static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
158{
159 int err;
160
161 rtsx_pci_init_cmd(pcr);
162 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
163 SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
164 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
165 LDO3318_PWR_MASK, 0x02);
166 err = rtsx_pci_send_cmd(pcr, 100);
167 if (err < 0)
168 return err;
169
170 msleep(5);
171
172 rtsx_pci_init_cmd(pcr);
173 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
174 SD_POWER_MASK, SD_VCC_POWER_ON);
175 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
176 LDO3318_PWR_MASK, 0x06);
177 err = rtsx_pci_send_cmd(pcr, 100);
178 if (err < 0)
179 return err;
180
181 return 0;
182}
183
184static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
185{
186 rtsx_pci_init_cmd(pcr);
187 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
188 SD_POWER_MASK, SD_POWER_OFF);
189 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
190 LDO3318_PWR_MASK, 0x00);
191 return rtsx_pci_send_cmd(pcr, 100);
192}
193
194static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
195{
196 int err;
Wei WANG4c4b8c12013-04-11 10:43:40 +0800197
198 if (voltage == OUTPUT_3V3) {
199 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 | 0x24);
200 if (err < 0)
201 return err;
Wei WANG4c4b8c12013-04-11 10:43:40 +0800202 } else if (voltage == OUTPUT_1V8) {
203 err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02);
204 if (err < 0)
205 return err;
206 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 | 0x24);
207 if (err < 0)
208 return err;
Wei WANG4c4b8c12013-04-11 10:43:40 +0800209 } else {
210 return -EINVAL;
211 }
212
213 /* set pad drive */
214 rtsx_pci_init_cmd(pcr);
Wei WANG773ccdf2013-08-20 14:18:51 +0800215 rts5249_fill_driving(pcr, voltage);
Wei WANG4c4b8c12013-04-11 10:43:40 +0800216 return rtsx_pci_send_cmd(pcr, 100);
217}
218
219static const struct pcr_ops rts5249_pcr_ops = {
Wei WANG773ccdf2013-08-20 14:18:51 +0800220 .fetch_vendor_settings = rts5249_fetch_vendor_settings,
Wei WANG4c4b8c12013-04-11 10:43:40 +0800221 .extra_init_hw = rts5249_extra_init_hw,
222 .optimize_phy = rts5249_optimize_phy,
223 .turn_on_led = rts5249_turn_on_led,
224 .turn_off_led = rts5249_turn_off_led,
225 .enable_auto_blink = rts5249_enable_auto_blink,
226 .disable_auto_blink = rts5249_disable_auto_blink,
227 .card_power_on = rts5249_card_power_on,
228 .card_power_off = rts5249_card_power_off,
229 .switch_output_voltage = rts5249_switch_output_voltage,
Wei WANG5947c162013-08-20 14:18:52 +0800230 .force_power_down = rts5249_force_power_down,
Wei WANG4c4b8c12013-04-11 10:43:40 +0800231};
232
233/* SD Pull Control Enable:
234 * SD_DAT[3:0] ==> pull up
235 * SD_CD ==> pull up
236 * SD_WP ==> pull up
237 * SD_CMD ==> pull up
238 * SD_CLK ==> pull down
239 */
240static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
241 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
242 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
243 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
244 RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
245 0,
246};
247
248/* SD Pull Control Disable:
249 * SD_DAT[3:0] ==> pull down
250 * SD_CD ==> pull up
251 * SD_WP ==> pull down
252 * SD_CMD ==> pull down
253 * SD_CLK ==> pull down
254 */
255static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
256 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
257 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
258 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
259 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
260 0,
261};
262
263/* MS Pull Control Enable:
264 * MS CD ==> pull up
265 * others ==> pull down
266 */
267static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
268 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
269 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
270 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
271 0,
272};
273
274/* MS Pull Control Disable:
275 * MS CD ==> pull up
276 * others ==> pull down
277 */
278static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
279 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
280 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
281 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
282 0,
283};
284
285void rts5249_init_params(struct rtsx_pcr *pcr)
286{
287 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
288 pcr->num_slots = 2;
289 pcr->ops = &rts5249_pcr_ops;
290
Wei WANG773ccdf2013-08-20 14:18:51 +0800291 pcr->flags = 0;
292 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
293 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_C;
294 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
295 pcr->aspm_en = ASPM_L1_EN;
296
Wei WANG4c4b8c12013-04-11 10:43:40 +0800297 pcr->ic_version = rts5249_get_ic_version(pcr);
298 pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
299 pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
300 pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
301 pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
302}