Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1 | /* |
Maciej Sosnowski | 211a22c | 2009-02-26 11:05:43 +0100 | [diff] [blame] | 2 | * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms of the GNU General Public License as published by the Free |
| 6 | * Software Foundation; either version 2 of the License, or (at your option) |
| 7 | * any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 14 | * The full GNU General Public License is included in this distribution in the |
| 15 | * file called COPYING. |
| 16 | */ |
| 17 | #ifndef IOATDMA_H |
| 18 | #define IOATDMA_H |
| 19 | |
| 20 | #include <linux/dmaengine.h> |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 21 | #include <linux/init.h> |
| 22 | #include <linux/dmapool.h> |
| 23 | #include <linux/cache.h> |
David S. Miller | 57c651f | 2006-05-23 17:39:49 -0700 | [diff] [blame] | 24 | #include <linux/pci_ids.h> |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 25 | #include <linux/circ_buf.h> |
| 26 | #include <linux/interrupt.h> |
| 27 | #include "registers.h" |
| 28 | #include "hw.h" |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 29 | |
Dan Williams | 3208ca5 | 2009-09-10 11:27:36 -0700 | [diff] [blame] | 30 | #define IOAT_DMA_VERSION "4.00" |
Shannon Nelson | 5149fd0 | 2007-10-18 03:07:13 -0700 | [diff] [blame] | 31 | |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 32 | #define IOAT_DMA_DCA_ANY_CPU ~0 |
| 33 | |
Dave Jiang | 55f878e | 2015-08-11 08:48:27 -0700 | [diff] [blame] | 34 | #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, dma_dev) |
| 35 | #define to_dev(ioat_chan) (&(ioat_chan)->ioat_dma->pdev->dev) |
| 36 | #define to_pdev(ioat_chan) ((ioat_chan)->ioat_dma->pdev) |
Dan Williams | 1f27adc2 | 2009-09-08 17:29:02 -0700 | [diff] [blame] | 37 | |
Dave Jiang | 55f878e | 2015-08-11 08:48:27 -0700 | [diff] [blame] | 38 | #define chan_num(ch) ((int)((ch)->reg_base - (ch)->ioat_dma->reg_base) / 0x80) |
Dan Williams | 1f27adc2 | 2009-09-08 17:29:02 -0700 | [diff] [blame] | 39 | |
Dave Jiang | 599d49d | 2015-08-11 08:48:49 -0700 | [diff] [blame^] | 40 | /* ioat hardware assumes at least two sources for raid operations */ |
| 41 | #define src_cnt_to_sw(x) ((x) + 2) |
| 42 | #define src_cnt_to_hw(x) ((x) - 2) |
| 43 | #define ndest_to_sw(x) ((x) + 1) |
| 44 | #define ndest_to_hw(x) ((x) - 1) |
| 45 | #define src16_cnt_to_sw(x) ((x) + 9) |
| 46 | #define src16_cnt_to_hw(x) ((x) - 9) |
| 47 | |
Dan Williams | 1f27adc2 | 2009-09-08 17:29:02 -0700 | [diff] [blame] | 48 | /* |
| 49 | * workaround for IOAT ver.3.0 null descriptor issue |
| 50 | * (channel returns error when size is 0) |
| 51 | */ |
| 52 | #define NULL_DESC_BUFFER_SIZE 1 |
| 53 | |
Dave Jiang | 8a52b9f | 2013-03-26 15:42:47 -0700 | [diff] [blame] | 54 | enum ioat_irq_mode { |
| 55 | IOAT_NOIRQ = 0, |
| 56 | IOAT_MSIX, |
Dave Jiang | 8a52b9f | 2013-03-26 15:42:47 -0700 | [diff] [blame] | 57 | IOAT_MSI, |
| 58 | IOAT_INTX |
| 59 | }; |
| 60 | |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 61 | /** |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 62 | * struct ioatdma_device - internal representation of a IOAT device |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 63 | * @pdev: PCI-Express device |
| 64 | * @reg_base: MMIO register space base address |
| 65 | * @dma_pool: for allocating DMA descriptors |
Dave Jiang | 55f878e | 2015-08-11 08:48:27 -0700 | [diff] [blame] | 66 | * @dma_dev: embedded struct dma_device |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 67 | * @version: version of ioatdma device |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 68 | * @msix_entries: irq handlers |
| 69 | * @idx: per channel data |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 70 | * @dca: direct cache access context |
| 71 | * @intr_quirk: interrupt setup quirk (for ioat_v1 devices) |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 72 | * @enumerate_channels: hw version specific channel enumeration |
Dan Williams | a6d52d7 | 2009-12-19 15:36:02 -0700 | [diff] [blame] | 73 | * @reset_hw: hw version specific channel (re)initialization |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 74 | * @cleanup_fn: select between the v2 and v3 cleanup routines |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 75 | * @timer_fn: select between the v2 and v3 timer watchdog routines |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 76 | * @self_test: hardware version specific self test for each supported op type |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 77 | * |
| 78 | * Note: the v3 cleanup routine supports raid operations |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 79 | */ |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 80 | struct ioatdma_device { |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 81 | struct pci_dev *pdev; |
Al Viro | 47b1653 | 2006-10-10 22:45:47 +0100 | [diff] [blame] | 82 | void __iomem *reg_base; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 83 | struct pci_pool *dma_pool; |
| 84 | struct pci_pool *completion_pool; |
Dave Jiang | 7727eaa | 2013-04-15 10:25:56 -0700 | [diff] [blame] | 85 | #define MAX_SED_POOLS 5 |
| 86 | struct dma_pool *sed_hw_pool[MAX_SED_POOLS]; |
Dave Jiang | 55f878e | 2015-08-11 08:48:27 -0700 | [diff] [blame] | 87 | struct dma_device dma_dev; |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 88 | u8 version; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 89 | struct msix_entry msix_entries[4]; |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 90 | struct ioatdma_chan *idx[4]; |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 91 | struct dca_provider *dca; |
Dave Jiang | 8a52b9f | 2013-03-26 15:42:47 -0700 | [diff] [blame] | 92 | enum ioat_irq_mode irq_mode; |
Dave Jiang | 75c6f0a | 2013-04-10 16:44:39 -0700 | [diff] [blame] | 93 | u32 cap; |
Dave Jiang | 55f878e | 2015-08-11 08:48:27 -0700 | [diff] [blame] | 94 | void (*intr_quirk)(struct ioatdma_device *ioat_dma); |
| 95 | int (*enumerate_channels)(struct ioatdma_device *ioat_dma); |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 96 | int (*reset_hw)(struct ioatdma_chan *ioat_chan); |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 97 | void (*cleanup_fn)(unsigned long data); |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 98 | void (*timer_fn)(unsigned long data); |
Dave Jiang | 55f878e | 2015-08-11 08:48:27 -0700 | [diff] [blame] | 99 | int (*self_test)(struct ioatdma_device *ioat_dma); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 100 | }; |
| 101 | |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 102 | struct ioatdma_chan { |
| 103 | struct dma_chan dma_chan; |
Al Viro | 47b1653 | 2006-10-10 22:45:47 +0100 | [diff] [blame] | 104 | void __iomem *reg_base; |
Dan Williams | 2750293 | 2012-03-23 13:36:42 -0700 | [diff] [blame] | 105 | dma_addr_t last_completion; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 106 | spinlock_t cleanup_lock; |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 107 | unsigned long state; |
| 108 | #define IOAT_COMPLETION_PENDING 0 |
| 109 | #define IOAT_COMPLETION_ACK 1 |
| 110 | #define IOAT_RESET_PENDING 2 |
Dan Williams | 5669e31 | 2009-09-08 17:42:56 -0700 | [diff] [blame] | 111 | #define IOAT_KOBJ_INIT_FAIL 3 |
Dan Williams | 074cc47 | 2010-05-01 15:22:55 -0700 | [diff] [blame] | 112 | #define IOAT_RESHAPE_PENDING 4 |
Dan Williams | 556ab45 | 2010-07-23 15:47:56 -0700 | [diff] [blame] | 113 | #define IOAT_RUN 5 |
Dave Jiang | 4dec23d | 2013-02-07 14:38:32 -0700 | [diff] [blame] | 114 | #define IOAT_CHAN_ACTIVE 6 |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 115 | struct timer_list timer; |
| 116 | #define COMPLETION_TIMEOUT msecs_to_jiffies(100) |
Dan Williams | a309218 | 2009-09-08 12:02:01 -0700 | [diff] [blame] | 117 | #define IDLE_TIMEOUT msecs_to_jiffies(2000) |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 118 | #define RESET_DELAY msecs_to_jiffies(100) |
Dave Jiang | 55f878e | 2015-08-11 08:48:27 -0700 | [diff] [blame] | 119 | struct ioatdma_device *ioat_dma; |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame] | 120 | dma_addr_t completion_dma; |
| 121 | u64 *completion; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 122 | struct tasklet_struct cleanup_task; |
Dan Williams | 5669e31 | 2009-09-08 17:42:56 -0700 | [diff] [blame] | 123 | struct kobject kobj; |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 124 | |
| 125 | /* ioat v2 / v3 channel attributes |
| 126 | * @xfercap_log; log2 of channel max transfer length (for fast division) |
| 127 | * @head: allocated index |
| 128 | * @issued: hardware notification point |
| 129 | * @tail: cleanup index |
| 130 | * @dmacount: identical to 'head' except for occasionally resetting to zero |
| 131 | * @alloc_order: log2 of the number of allocated descriptors |
| 132 | * @produce: number of descriptors to produce at submit time |
| 133 | * @ring: software ring buffer implementation of hardware ring |
| 134 | * @prep_lock: serializes descriptor preparation (producers) |
| 135 | */ |
| 136 | size_t xfercap_log; |
| 137 | u16 head; |
| 138 | u16 issued; |
| 139 | u16 tail; |
| 140 | u16 dmacount; |
| 141 | u16 alloc_order; |
| 142 | u16 produce; |
| 143 | struct ioat_ring_ent **ring; |
| 144 | spinlock_t prep_lock; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 145 | }; |
| 146 | |
Dan Williams | 5669e31 | 2009-09-08 17:42:56 -0700 | [diff] [blame] | 147 | struct ioat_sysfs_entry { |
| 148 | struct attribute attr; |
| 149 | ssize_t (*show)(struct dma_chan *, char *); |
| 150 | }; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 151 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 152 | /** |
Dave Jiang | 7727eaa | 2013-04-15 10:25:56 -0700 | [diff] [blame] | 153 | * struct ioat_sed_ent - wrapper around super extended hardware descriptor |
| 154 | * @hw: hardware SED |
| 155 | * @sed_dma: dma address for the SED |
| 156 | * @list: list member |
| 157 | * @parent: point to the dma descriptor that's the parent |
| 158 | */ |
| 159 | struct ioat_sed_ent { |
| 160 | struct ioat_sed_raw_descriptor *hw; |
| 161 | dma_addr_t dma; |
| 162 | struct ioat_ring_ent *parent; |
| 163 | unsigned int hw_pool; |
| 164 | }; |
| 165 | |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 166 | /** |
| 167 | * struct ioat_ring_ent - wrapper around hardware descriptor |
| 168 | * @hw: hardware DMA descriptor (for memcpy) |
| 169 | * @fill: hardware fill descriptor |
| 170 | * @xor: hardware xor descriptor |
| 171 | * @xor_ex: hardware xor extension descriptor |
| 172 | * @pq: hardware pq descriptor |
| 173 | * @pq_ex: hardware pq extension descriptor |
| 174 | * @pqu: hardware pq update descriptor |
| 175 | * @raw: hardware raw (un-typed) descriptor |
| 176 | * @txd: the generic software descriptor for all engines |
| 177 | * @len: total transaction length for unmap |
| 178 | * @result: asynchronous result of validate operations |
| 179 | * @id: identifier for debug |
| 180 | */ |
| 181 | |
| 182 | struct ioat_ring_ent { |
| 183 | union { |
| 184 | struct ioat_dma_descriptor *hw; |
| 185 | struct ioat_xor_descriptor *xor; |
| 186 | struct ioat_xor_ext_descriptor *xor_ex; |
| 187 | struct ioat_pq_descriptor *pq; |
| 188 | struct ioat_pq_ext_descriptor *pq_ex; |
| 189 | struct ioat_pq_update_descriptor *pqu; |
| 190 | struct ioat_raw_descriptor *raw; |
| 191 | }; |
| 192 | size_t len; |
| 193 | struct dma_async_tx_descriptor txd; |
| 194 | enum sum_check_flags *result; |
| 195 | #ifdef DEBUG |
| 196 | int id; |
| 197 | #endif |
| 198 | struct ioat_sed_ent *sed; |
| 199 | }; |
| 200 | |
Dave Jiang | 599d49d | 2015-08-11 08:48:49 -0700 | [diff] [blame^] | 201 | extern const struct sysfs_ops ioat_sysfs_ops; |
| 202 | extern struct ioat_sysfs_entry ioat_version_attr; |
| 203 | extern struct ioat_sysfs_entry ioat_cap_attr; |
| 204 | extern int ioat_pending_level; |
| 205 | extern int ioat_ring_alloc_order; |
| 206 | extern struct kobj_type ioat_ktype; |
| 207 | extern struct kmem_cache *ioat_cache; |
| 208 | extern int ioat_ring_max_alloc_order; |
| 209 | extern struct kmem_cache *ioat_sed_cache; |
| 210 | |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 211 | static inline struct ioatdma_chan *to_ioat_chan(struct dma_chan *c) |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 212 | { |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 213 | return container_of(c, struct ioatdma_chan, dma_chan); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 214 | } |
| 215 | |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 216 | /* wrapper around hardware descriptor format + additional software fields */ |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 217 | #ifdef DEBUG |
| 218 | #define set_desc_id(desc, i) ((desc)->id = (i)) |
| 219 | #define desc_id(desc) ((desc)->id) |
| 220 | #else |
| 221 | #define set_desc_id(desc, i) |
| 222 | #define desc_id(desc) (0) |
| 223 | #endif |
| 224 | |
| 225 | static inline void |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 226 | __dump_desc_dbg(struct ioatdma_chan *ioat_chan, struct ioat_dma_descriptor *hw, |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 227 | struct dma_async_tx_descriptor *tx, int id) |
| 228 | { |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 229 | struct device *dev = to_dev(ioat_chan); |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 230 | |
| 231 | dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x" |
Dave Jiang | 50f9f97 | 2013-03-04 10:59:54 -0700 | [diff] [blame] | 232 | " ctl: %#10.8x (op: %#x int_en: %d compl: %d)\n", id, |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 233 | (unsigned long long) tx->phys, |
| 234 | (unsigned long long) hw->next, tx->cookie, tx->flags, |
| 235 | hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write); |
| 236 | } |
| 237 | |
| 238 | #define dump_desc_dbg(c, d) \ |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 239 | ({ if (d) __dump_desc_dbg(c, d->hw, &d->txd, desc_id(d)); 0; }) |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 240 | |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 241 | static inline struct ioatdma_chan * |
Dave Jiang | 55f878e | 2015-08-11 08:48:27 -0700 | [diff] [blame] | 242 | ioat_chan_by_index(struct ioatdma_device *ioat_dma, int index) |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 243 | { |
Dave Jiang | 55f878e | 2015-08-11 08:48:27 -0700 | [diff] [blame] | 244 | return ioat_dma->idx[index]; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 245 | } |
| 246 | |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 247 | static inline u64 ioat_chansts_32(struct ioatdma_chan *ioat_chan) |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 248 | { |
Dave Jiang | 55f878e | 2015-08-11 08:48:27 -0700 | [diff] [blame] | 249 | u8 ver = ioat_chan->ioat_dma->version; |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 250 | u64 status; |
| 251 | u32 status_lo; |
| 252 | |
| 253 | /* We need to read the low address first as this causes the |
| 254 | * chipset to latch the upper bits for the subsequent read |
| 255 | */ |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 256 | status_lo = readl(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver)); |
| 257 | status = readl(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver)); |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 258 | status <<= 32; |
| 259 | status |= status_lo; |
| 260 | |
| 261 | return status; |
| 262 | } |
| 263 | |
Dave Jiang | d92a8d7 | 2013-03-26 15:42:41 -0700 | [diff] [blame] | 264 | #if BITS_PER_LONG == 64 |
| 265 | |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 266 | static inline u64 ioat_chansts(struct ioatdma_chan *ioat_chan) |
Dave Jiang | d92a8d7 | 2013-03-26 15:42:41 -0700 | [diff] [blame] | 267 | { |
Dave Jiang | 55f878e | 2015-08-11 08:48:27 -0700 | [diff] [blame] | 268 | u8 ver = ioat_chan->ioat_dma->version; |
Dave Jiang | d92a8d7 | 2013-03-26 15:42:41 -0700 | [diff] [blame] | 269 | u64 status; |
| 270 | |
| 271 | /* With IOAT v3.3 the status register is 64bit. */ |
| 272 | if (ver >= IOAT_VER_3_3) |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 273 | status = readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET(ver)); |
Dave Jiang | d92a8d7 | 2013-03-26 15:42:41 -0700 | [diff] [blame] | 274 | else |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 275 | status = ioat_chansts_32(ioat_chan); |
Dave Jiang | d92a8d7 | 2013-03-26 15:42:41 -0700 | [diff] [blame] | 276 | |
| 277 | return status; |
| 278 | } |
| 279 | |
| 280 | #else |
| 281 | #define ioat_chansts ioat_chansts_32 |
| 282 | #endif |
| 283 | |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 284 | static inline u64 ioat_chansts_to_addr(u64 status) |
| 285 | { |
| 286 | return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; |
| 287 | } |
| 288 | |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 289 | static inline u32 ioat_chanerr(struct ioatdma_chan *ioat_chan) |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 290 | { |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 291 | return readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 292 | } |
| 293 | |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 294 | static inline void ioat_suspend(struct ioatdma_chan *ioat_chan) |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 295 | { |
Dave Jiang | 55f878e | 2015-08-11 08:48:27 -0700 | [diff] [blame] | 296 | u8 ver = ioat_chan->ioat_dma->version; |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 297 | |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 298 | writeb(IOAT_CHANCMD_SUSPEND, |
| 299 | ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 300 | } |
| 301 | |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 302 | static inline void ioat_reset(struct ioatdma_chan *ioat_chan) |
Dan Williams | a6d52d7 | 2009-12-19 15:36:02 -0700 | [diff] [blame] | 303 | { |
Dave Jiang | 55f878e | 2015-08-11 08:48:27 -0700 | [diff] [blame] | 304 | u8 ver = ioat_chan->ioat_dma->version; |
Dan Williams | a6d52d7 | 2009-12-19 15:36:02 -0700 | [diff] [blame] | 305 | |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 306 | writeb(IOAT_CHANCMD_RESET, |
| 307 | ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); |
Dan Williams | a6d52d7 | 2009-12-19 15:36:02 -0700 | [diff] [blame] | 308 | } |
| 309 | |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 310 | static inline bool ioat_reset_pending(struct ioatdma_chan *ioat_chan) |
Dan Williams | a6d52d7 | 2009-12-19 15:36:02 -0700 | [diff] [blame] | 311 | { |
Dave Jiang | 55f878e | 2015-08-11 08:48:27 -0700 | [diff] [blame] | 312 | u8 ver = ioat_chan->ioat_dma->version; |
Dan Williams | a6d52d7 | 2009-12-19 15:36:02 -0700 | [diff] [blame] | 313 | u8 cmd; |
| 314 | |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 315 | cmd = readb(ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); |
Dan Williams | a6d52d7 | 2009-12-19 15:36:02 -0700 | [diff] [blame] | 316 | return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET; |
| 317 | } |
| 318 | |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 319 | static inline bool is_ioat_active(unsigned long status) |
| 320 | { |
| 321 | return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE); |
| 322 | } |
| 323 | |
| 324 | static inline bool is_ioat_idle(unsigned long status) |
| 325 | { |
| 326 | return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE); |
| 327 | } |
| 328 | |
| 329 | static inline bool is_ioat_halted(unsigned long status) |
| 330 | { |
| 331 | return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED); |
| 332 | } |
| 333 | |
| 334 | static inline bool is_ioat_suspended(unsigned long status) |
| 335 | { |
| 336 | return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED); |
| 337 | } |
| 338 | |
| 339 | /* channel was fatally programmed */ |
| 340 | static inline bool is_ioat_bug(unsigned long err) |
| 341 | { |
Dan Williams | b57014d | 2009-11-19 17:10:07 -0700 | [diff] [blame] | 342 | return !!err; |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 343 | } |
| 344 | |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 345 | #define IOAT_MAX_ORDER 16 |
| 346 | #define ioat_get_alloc_order() \ |
| 347 | (min(ioat_ring_alloc_order, IOAT_MAX_ORDER)) |
| 348 | #define ioat_get_max_alloc_order() \ |
| 349 | (min(ioat_ring_max_alloc_order, IOAT_MAX_ORDER)) |
| 350 | |
| 351 | static inline u32 ioat_ring_size(struct ioatdma_chan *ioat_chan) |
| 352 | { |
| 353 | return 1 << ioat_chan->alloc_order; |
| 354 | } |
| 355 | |
| 356 | /* count of descriptors in flight with the engine */ |
| 357 | static inline u16 ioat_ring_active(struct ioatdma_chan *ioat_chan) |
| 358 | { |
| 359 | return CIRC_CNT(ioat_chan->head, ioat_chan->tail, |
| 360 | ioat_ring_size(ioat_chan)); |
| 361 | } |
| 362 | |
| 363 | /* count of descriptors pending submission to hardware */ |
| 364 | static inline u16 ioat_ring_pending(struct ioatdma_chan *ioat_chan) |
| 365 | { |
| 366 | return CIRC_CNT(ioat_chan->head, ioat_chan->issued, |
| 367 | ioat_ring_size(ioat_chan)); |
| 368 | } |
| 369 | |
| 370 | static inline u32 ioat_ring_space(struct ioatdma_chan *ioat_chan) |
| 371 | { |
| 372 | return ioat_ring_size(ioat_chan) - ioat_ring_active(ioat_chan); |
| 373 | } |
| 374 | |
| 375 | static inline u16 |
| 376 | ioat_xferlen_to_descs(struct ioatdma_chan *ioat_chan, size_t len) |
| 377 | { |
| 378 | u16 num_descs = len >> ioat_chan->xfercap_log; |
| 379 | |
| 380 | num_descs += !!(len & ((1 << ioat_chan->xfercap_log) - 1)); |
| 381 | return num_descs; |
| 382 | } |
| 383 | |
| 384 | static inline struct ioat_ring_ent * |
| 385 | ioat_get_ring_ent(struct ioatdma_chan *ioat_chan, u16 idx) |
| 386 | { |
| 387 | return ioat_chan->ring[idx & (ioat_ring_size(ioat_chan) - 1)]; |
| 388 | } |
| 389 | |
| 390 | static inline void |
| 391 | ioat_set_chainaddr(struct ioatdma_chan *ioat_chan, u64 addr) |
| 392 | { |
| 393 | writel(addr & 0x00000000FFFFFFFF, |
| 394 | ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); |
| 395 | writel(addr >> 32, |
| 396 | ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); |
| 397 | } |
| 398 | |
Dave Jiang | 599d49d | 2015-08-11 08:48:49 -0700 | [diff] [blame^] | 399 | /* IOAT Prep functions */ |
| 400 | struct dma_async_tx_descriptor * |
| 401 | ioat_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest, |
| 402 | dma_addr_t dma_src, size_t len, unsigned long flags); |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 403 | struct dma_async_tx_descriptor * |
| 404 | ioat_prep_interrupt_lock(struct dma_chan *c, unsigned long flags); |
| 405 | struct dma_async_tx_descriptor * |
| 406 | ioat_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
| 407 | unsigned int src_cnt, size_t len, unsigned long flags); |
| 408 | struct dma_async_tx_descriptor * |
| 409 | ioat_prep_xor_val(struct dma_chan *chan, dma_addr_t *src, |
| 410 | unsigned int src_cnt, size_t len, |
| 411 | enum sum_check_flags *result, unsigned long flags); |
| 412 | struct dma_async_tx_descriptor * |
| 413 | ioat_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, |
| 414 | unsigned int src_cnt, const unsigned char *scf, size_t len, |
| 415 | unsigned long flags); |
| 416 | struct dma_async_tx_descriptor * |
| 417 | ioat_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, |
| 418 | unsigned int src_cnt, const unsigned char *scf, size_t len, |
| 419 | enum sum_check_flags *pqres, unsigned long flags); |
| 420 | struct dma_async_tx_descriptor * |
| 421 | ioat_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, |
| 422 | unsigned int src_cnt, size_t len, unsigned long flags); |
| 423 | struct dma_async_tx_descriptor * |
| 424 | ioat_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src, |
| 425 | unsigned int src_cnt, size_t len, |
| 426 | enum sum_check_flags *result, unsigned long flags); |
Dave Jiang | 599d49d | 2015-08-11 08:48:49 -0700 | [diff] [blame^] | 427 | |
| 428 | /* IOAT Operation functions */ |
| 429 | irqreturn_t ioat_dma_do_interrupt(int irq, void *data); |
| 430 | irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data); |
| 431 | struct ioat_ring_ent ** |
| 432 | ioat_alloc_ring(struct dma_chan *c, int order, gfp_t flags); |
| 433 | void ioat_start_null_desc(struct ioatdma_chan *ioat_chan); |
| 434 | void ioat_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan); |
| 435 | int ioat_reset_hw(struct ioatdma_chan *ioat_chan); |
Dave Jiang | c0f28ce | 2015-08-11 08:48:43 -0700 | [diff] [blame] | 436 | enum dma_status |
| 437 | ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie, |
| 438 | struct dma_tx_state *txstate); |
| 439 | void ioat_cleanup_event(unsigned long data); |
| 440 | void ioat_timer_event(unsigned long data); |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 441 | enum dma_status ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie, |
| 442 | struct dma_tx_state *txstate); |
Dave Jiang | 5a97688 | 2015-08-11 08:48:21 -0700 | [diff] [blame] | 443 | bool ioat_cleanup_preamble(struct ioatdma_chan *ioat_chan, |
Dan Williams | 2750293 | 2012-03-23 13:36:42 -0700 | [diff] [blame] | 444 | dma_addr_t *phys_complete); |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 445 | int ioat_check_space_lock(struct ioatdma_chan *ioat_chan, int num_descs); |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 446 | void ioat_issue_pending(struct dma_chan *chan); |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 447 | bool reshape_ring(struct ioatdma_chan *ioat, int order); |
| 448 | void __ioat_issue_pending(struct ioatdma_chan *ioat_chan); |
| 449 | void ioat_timer_event(unsigned long data); |
| 450 | int ioat_quiesce(struct ioatdma_chan *ioat_chan, unsigned long tmo); |
| 451 | int ioat_reset_sync(struct ioatdma_chan *ioat_chan, unsigned long tmo); |
Dave Jiang | 599d49d | 2015-08-11 08:48:49 -0700 | [diff] [blame^] | 452 | void __ioat_restart_chan(struct ioatdma_chan *ioat_chan); |
Dave Jiang | 885b201 | 2015-08-11 08:48:32 -0700 | [diff] [blame] | 453 | |
Dave Jiang | 599d49d | 2015-08-11 08:48:49 -0700 | [diff] [blame^] | 454 | /* IOAT Init functions */ |
| 455 | bool is_bwd_ioat(struct pci_dev *pdev); |
| 456 | void ioat_kobject_add(struct ioatdma_device *ioat_dma, struct kobj_type *type); |
| 457 | void ioat_kobject_del(struct ioatdma_device *ioat_dma); |
| 458 | int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma); |
| 459 | void ioat_stop(struct ioatdma_chan *ioat_chan); |
| 460 | struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 461 | #endif /* IOATDMA_H */ |