Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2013 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | #include "i915_drv.h" |
| 26 | #include "intel_drv.h" |
| 27 | |
| 28 | /* IOSF sideband */ |
Jani Nikula | 5a09ae9f | 2013-05-22 15:36:17 +0300 | [diff] [blame^] | 29 | static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn, |
| 30 | u32 port, u32 opcode, u32 addr, u32 *val) |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 31 | { |
Jani Nikula | 5a09ae9f | 2013-05-22 15:36:17 +0300 | [diff] [blame^] | 32 | u32 cmd, be = 0xf, bar = 0; |
| 33 | bool is_read = (opcode == PUNIT_OPCODE_REG_READ || |
| 34 | opcode == DPIO_OPCODE_REG_READ); |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 35 | |
| 36 | cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) | |
| 37 | (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) | |
| 38 | (bar << IOSF_BAR_SHIFT); |
| 39 | |
Jani Nikula | 5a09ae9f | 2013-05-22 15:36:17 +0300 | [diff] [blame^] | 40 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 41 | |
Jani Nikula | 5a09ae9f | 2013-05-22 15:36:17 +0300 | [diff] [blame^] | 42 | if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) { |
| 43 | DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n", |
| 44 | is_read ? "read" : "write"); |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 45 | return -EAGAIN; |
| 46 | } |
| 47 | |
| 48 | I915_WRITE(VLV_IOSF_ADDR, addr); |
Jani Nikula | 5a09ae9f | 2013-05-22 15:36:17 +0300 | [diff] [blame^] | 49 | if (!is_read) |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 50 | I915_WRITE(VLV_IOSF_DATA, *val); |
| 51 | I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd); |
| 52 | |
Jani Nikula | 5a09ae9f | 2013-05-22 15:36:17 +0300 | [diff] [blame^] | 53 | if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) { |
| 54 | DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n", |
| 55 | is_read ? "read" : "write"); |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 56 | return -ETIMEDOUT; |
| 57 | } |
| 58 | |
Jani Nikula | 5a09ae9f | 2013-05-22 15:36:17 +0300 | [diff] [blame^] | 59 | if (is_read) |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 60 | *val = I915_READ(VLV_IOSF_DATA); |
| 61 | I915_WRITE(VLV_IOSF_DATA, 0); |
| 62 | |
| 63 | return 0; |
| 64 | } |
| 65 | |
| 66 | int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val) |
| 67 | { |
Jani Nikula | 5a09ae9f | 2013-05-22 15:36:17 +0300 | [diff] [blame^] | 68 | int ret; |
| 69 | |
| 70 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
| 71 | |
| 72 | mutex_lock(&dev_priv->dpio_lock); |
| 73 | ret = vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT, |
| 74 | PUNIT_OPCODE_REG_READ, addr, val); |
| 75 | mutex_unlock(&dev_priv->dpio_lock); |
| 76 | |
| 77 | return ret; |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 78 | } |
| 79 | |
| 80 | int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val) |
| 81 | { |
Jani Nikula | 5a09ae9f | 2013-05-22 15:36:17 +0300 | [diff] [blame^] | 82 | int ret; |
| 83 | |
| 84 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
| 85 | |
| 86 | mutex_lock(&dev_priv->dpio_lock); |
| 87 | ret = vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT, |
| 88 | PUNIT_OPCODE_REG_WRITE, addr, &val); |
| 89 | mutex_unlock(&dev_priv->dpio_lock); |
| 90 | |
| 91 | return ret; |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 92 | } |
| 93 | |
| 94 | int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val) |
| 95 | { |
Jani Nikula | 5a09ae9f | 2013-05-22 15:36:17 +0300 | [diff] [blame^] | 96 | int ret; |
| 97 | |
| 98 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
| 99 | |
| 100 | mutex_lock(&dev_priv->dpio_lock); |
| 101 | ret = vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC, |
| 102 | PUNIT_OPCODE_REG_READ, addr, val); |
| 103 | mutex_unlock(&dev_priv->dpio_lock); |
| 104 | |
| 105 | return ret; |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 106 | } |
| 107 | |
| 108 | u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg) |
| 109 | { |
Jani Nikula | 5a09ae9f | 2013-05-22 15:36:17 +0300 | [diff] [blame^] | 110 | u32 val = 0; |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 111 | |
Jani Nikula | 5a09ae9f | 2013-05-22 15:36:17 +0300 | [diff] [blame^] | 112 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_DPIO, |
| 113 | DPIO_OPCODE_REG_READ, reg, &val); |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 114 | |
Jani Nikula | 5a09ae9f | 2013-05-22 15:36:17 +0300 | [diff] [blame^] | 115 | return val; |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 116 | } |
| 117 | |
| 118 | void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val) |
| 119 | { |
Jani Nikula | 5a09ae9f | 2013-05-22 15:36:17 +0300 | [diff] [blame^] | 120 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_DPIO, |
| 121 | DPIO_OPCODE_REG_WRITE, reg, &val); |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 122 | } |
| 123 | |
| 124 | /* SBI access */ |
| 125 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
| 126 | enum intel_sbi_destination destination) |
| 127 | { |
| 128 | u32 value = 0; |
| 129 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
| 130 | |
| 131 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
| 132 | 100)) { |
| 133 | DRM_ERROR("timeout waiting for SBI to become ready\n"); |
| 134 | return 0; |
| 135 | } |
| 136 | |
| 137 | I915_WRITE(SBI_ADDR, (reg << 16)); |
| 138 | |
| 139 | if (destination == SBI_ICLK) |
| 140 | value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD; |
| 141 | else |
| 142 | value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD; |
| 143 | I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY); |
| 144 | |
| 145 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
| 146 | 100)) { |
| 147 | DRM_ERROR("timeout waiting for SBI to complete read transaction\n"); |
| 148 | return 0; |
| 149 | } |
| 150 | |
| 151 | return I915_READ(SBI_DATA); |
| 152 | } |
| 153 | |
| 154 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, |
| 155 | enum intel_sbi_destination destination) |
| 156 | { |
| 157 | u32 tmp; |
| 158 | |
| 159 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
| 160 | |
| 161 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
| 162 | 100)) { |
| 163 | DRM_ERROR("timeout waiting for SBI to become ready\n"); |
| 164 | return; |
| 165 | } |
| 166 | |
| 167 | I915_WRITE(SBI_ADDR, (reg << 16)); |
| 168 | I915_WRITE(SBI_DATA, value); |
| 169 | |
| 170 | if (destination == SBI_ICLK) |
| 171 | tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR; |
| 172 | else |
| 173 | tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR; |
| 174 | I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp); |
| 175 | |
| 176 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
| 177 | 100)) { |
| 178 | DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); |
| 179 | return; |
| 180 | } |
| 181 | } |