Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Imagination Technologies |
| 3 | * Author: Paul Burton <paul.burton@imgtec.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License as published by the |
| 7 | * Free Software Foundation; either version 2 of the License, or (at your |
| 8 | * option) any later version. |
| 9 | */ |
| 10 | |
| 11 | #include <asm/addrspace.h> |
| 12 | #include <asm/asm.h> |
| 13 | #include <asm/asm-offsets.h> |
| 14 | #include <asm/asmmacro.h> |
| 15 | #include <asm/cacheops.h> |
Markos Chandras | 6521d9a | 2014-07-21 14:35:56 +0100 | [diff] [blame] | 16 | #include <asm/eva.h> |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 17 | #include <asm/mipsregs.h> |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 18 | #include <asm/mipsmtregs.h> |
Paul Burton | 3179d37 | 2014-04-14 11:00:56 +0100 | [diff] [blame] | 19 | #include <asm/pm.h> |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 20 | |
Paul Burton | 5a3e7c0 | 2016-02-03 03:15:33 +0000 | [diff] [blame^] | 21 | #define GCR_CPC_BASE_OFS 0x0088 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 22 | #define GCR_CL_COHERENCE_OFS 0x2008 |
| 23 | #define GCR_CL_ID_OFS 0x2028 |
| 24 | |
Paul Burton | 5a3e7c0 | 2016-02-03 03:15:33 +0000 | [diff] [blame^] | 25 | #define CPC_CL_VC_RUN_OFS 0x2028 |
| 26 | |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 27 | .extern mips_cm_base |
| 28 | |
| 29 | .set noreorder |
| 30 | |
Paul Burton | 8fe2c547 | 2015-09-22 11:12:10 -0700 | [diff] [blame] | 31 | #ifdef CONFIG_64BIT |
| 32 | # define STATUS_BITDEPS ST0_KX |
| 33 | #else |
| 34 | # define STATUS_BITDEPS 0 |
| 35 | #endif |
| 36 | |
Paul Burton | 609cf6f | 2015-09-22 11:12:11 -0700 | [diff] [blame] | 37 | #ifdef CONFIG_MIPS_CPS_NS16550 |
| 38 | |
| 39 | #define DUMP_EXCEP(name) \ |
| 40 | PTR_LA a0, 8f; \ |
| 41 | jal mips_cps_bev_dump; \ |
| 42 | nop; \ |
| 43 | TEXT(name) |
| 44 | |
| 45 | #else /* !CONFIG_MIPS_CPS_NS16550 */ |
| 46 | |
| 47 | #define DUMP_EXCEP(name) |
| 48 | |
| 49 | #endif /* !CONFIG_MIPS_CPS_NS16550 */ |
| 50 | |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 51 | /* |
| 52 | * Set dest to non-zero if the core supports the MT ASE, else zero. If |
| 53 | * MT is not supported then branch to nomt. |
| 54 | */ |
| 55 | .macro has_mt dest, nomt |
Paul Burton | 192fbc2 | 2015-09-22 11:12:13 -0700 | [diff] [blame] | 56 | mfc0 \dest, CP0_CONFIG, 1 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 57 | bgez \dest, \nomt |
| 58 | mfc0 \dest, CP0_CONFIG, 2 |
| 59 | bgez \dest, \nomt |
| 60 | mfc0 \dest, CP0_CONFIG, 3 |
| 61 | andi \dest, \dest, MIPS_CONF3_MT |
| 62 | beqz \dest, \nomt |
Paul Burton | 1e5fb28 | 2015-08-05 15:42:36 -0700 | [diff] [blame] | 63 | nop |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 64 | .endm |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 65 | |
Paul Burton | 5a3e7c0 | 2016-02-03 03:15:33 +0000 | [diff] [blame^] | 66 | /* |
| 67 | * Set dest to non-zero if the core supports MIPSr6 multithreading |
| 68 | * (ie. VPs), else zero. If MIPSr6 multithreading is not supported then |
| 69 | * branch to nomt. |
| 70 | */ |
| 71 | .macro has_vp dest, nomt |
| 72 | mfc0 \dest, CP0_CONFIG, 1 |
| 73 | bgez \dest, \nomt |
| 74 | mfc0 \dest, CP0_CONFIG, 2 |
| 75 | bgez \dest, \nomt |
| 76 | mfc0 \dest, CP0_CONFIG, 3 |
| 77 | bgez \dest, \nomt |
| 78 | mfc0 \dest, CP0_CONFIG, 4 |
| 79 | bgez \dest, \nomt |
| 80 | mfc0 \dest, CP0_CONFIG, 5 |
| 81 | andi \dest, \dest, MIPS_CONF5_VP |
| 82 | beqz \dest, \nomt |
| 83 | nop |
| 84 | .endm |
| 85 | |
Paul Burton | f12401d | 2016-02-03 03:15:31 +0000 | [diff] [blame] | 86 | /* Calculate an uncached address for the CM GCRs */ |
| 87 | .macro cmgcrb dest |
| 88 | .set push |
| 89 | .set noat |
| 90 | MFC0 $1, CP0_CMGCRBASE |
| 91 | PTR_SLL $1, $1, 4 |
| 92 | PTR_LI \dest, UNCAC_BASE |
| 93 | PTR_ADDU \dest, \dest, $1 |
| 94 | .set pop |
| 95 | .endm |
| 96 | |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 97 | .section .text.cps-vec |
| 98 | .balign 0x1000 |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 99 | |
| 100 | LEAF(mips_cps_core_entry) |
| 101 | /* |
Paul Burton | 946db17 | 2015-09-22 11:12:12 -0700 | [diff] [blame] | 102 | * These first 4 bytes will be patched by cps_smp_setup to load the |
| 103 | * CCA to use into register s0. |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 104 | */ |
Paul Burton | 0155a06 | 2014-04-16 11:10:57 +0100 | [diff] [blame] | 105 | .word 0 |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 106 | |
| 107 | /* Check whether we're here due to an NMI */ |
| 108 | mfc0 k0, CP0_STATUS |
| 109 | and k0, k0, ST0_NMI |
| 110 | beqz k0, not_nmi |
| 111 | nop |
| 112 | |
| 113 | /* This is an NMI */ |
Markos Chandras | 81a02e3 | 2015-07-01 09:13:29 +0100 | [diff] [blame] | 114 | PTR_LA k0, nmi_handler |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 115 | jr k0 |
| 116 | nop |
| 117 | |
| 118 | not_nmi: |
| 119 | /* Setup Cause */ |
| 120 | li t0, CAUSEF_IV |
| 121 | mtc0 t0, CP0_CAUSE |
| 122 | |
| 123 | /* Setup Status */ |
Paul Burton | 8fe2c547 | 2015-09-22 11:12:10 -0700 | [diff] [blame] | 124 | li t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 125 | mtc0 t0, CP0_STATUS |
| 126 | |
Paul Burton | 87a70bc | 2016-02-03 03:15:32 +0000 | [diff] [blame] | 127 | /* Skip cache & coherence setup if we're already coherent */ |
| 128 | cmgcrb v1 |
| 129 | lw s7, GCR_CL_COHERENCE_OFS(v1) |
| 130 | bnez s7, 1f |
| 131 | nop |
| 132 | |
Paul Burton | 3dbc997 | 2016-02-03 03:15:30 +0000 | [diff] [blame] | 133 | /* Initialize the L1 caches */ |
| 134 | jal mips_cps_cache_init |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 135 | nop |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 136 | |
Paul Burton | 87a70bc | 2016-02-03 03:15:32 +0000 | [diff] [blame] | 137 | /* Enter the coherent domain */ |
| 138 | li t0, 0xff |
| 139 | sw t0, GCR_CL_COHERENCE_OFS(v1) |
| 140 | ehb |
| 141 | |
Paul Burton | 0155a06 | 2014-04-16 11:10:57 +0100 | [diff] [blame] | 142 | /* Set Kseg0 CCA to that in s0 */ |
Paul Burton | 87a70bc | 2016-02-03 03:15:32 +0000 | [diff] [blame] | 143 | 1: mfc0 t0, CP0_CONFIG |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 144 | ori t0, 0x7 |
Paul Burton | 0155a06 | 2014-04-16 11:10:57 +0100 | [diff] [blame] | 145 | xori t0, 0x7 |
| 146 | or t0, t0, s0 |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 147 | mtc0 t0, CP0_CONFIG |
| 148 | ehb |
| 149 | |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 150 | /* Jump to kseg0 */ |
Markos Chandras | 81a02e3 | 2015-07-01 09:13:29 +0100 | [diff] [blame] | 151 | PTR_LA t0, 1f |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 152 | jr t0 |
| 153 | nop |
| 154 | |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 155 | /* |
Paul Burton | 87a70bc | 2016-02-03 03:15:32 +0000 | [diff] [blame] | 156 | * We're up, cached & coherent. Perform any EVA initialization necessary |
| 157 | * before we access memory. |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 158 | */ |
Paul Burton | 87a70bc | 2016-02-03 03:15:32 +0000 | [diff] [blame] | 159 | 1: eva_init |
Markos Chandras | 6521d9a | 2014-07-21 14:35:56 +0100 | [diff] [blame] | 160 | |
Paul Burton | f12401d | 2016-02-03 03:15:31 +0000 | [diff] [blame] | 161 | /* Retrieve boot configuration pointers */ |
| 162 | jal mips_cps_get_bootcfg |
| 163 | nop |
| 164 | |
Paul Burton | 87a70bc | 2016-02-03 03:15:32 +0000 | [diff] [blame] | 165 | /* Skip core-level init if we started up coherent */ |
| 166 | bnez s7, 1f |
| 167 | nop |
| 168 | |
| 169 | /* Perform any further required core-level initialisation */ |
| 170 | jal mips_cps_core_init |
| 171 | nop |
| 172 | |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 173 | /* |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 174 | * Boot any other VPEs within this core that should be online, and |
| 175 | * deactivate this VPE if it should be offline. |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 176 | */ |
Paul Burton | f12401d | 2016-02-03 03:15:31 +0000 | [diff] [blame] | 177 | move a1, t9 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 178 | jal mips_cps_boot_vpes |
Paul Burton | f12401d | 2016-02-03 03:15:31 +0000 | [diff] [blame] | 179 | move a0, v0 |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 180 | |
| 181 | /* Off we go! */ |
Paul Burton | 87a70bc | 2016-02-03 03:15:32 +0000 | [diff] [blame] | 182 | 1: PTR_L t1, VPEBOOTCFG_PC(v1) |
Paul Burton | f12401d | 2016-02-03 03:15:31 +0000 | [diff] [blame] | 183 | PTR_L gp, VPEBOOTCFG_GP(v1) |
| 184 | PTR_L sp, VPEBOOTCFG_SP(v1) |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 185 | jr t1 |
| 186 | nop |
| 187 | END(mips_cps_core_entry) |
| 188 | |
| 189 | .org 0x200 |
| 190 | LEAF(excep_tlbfill) |
Paul Burton | 609cf6f | 2015-09-22 11:12:11 -0700 | [diff] [blame] | 191 | DUMP_EXCEP("TLB Fill") |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 192 | b . |
| 193 | nop |
| 194 | END(excep_tlbfill) |
| 195 | |
| 196 | .org 0x280 |
| 197 | LEAF(excep_xtlbfill) |
Paul Burton | 609cf6f | 2015-09-22 11:12:11 -0700 | [diff] [blame] | 198 | DUMP_EXCEP("XTLB Fill") |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 199 | b . |
| 200 | nop |
| 201 | END(excep_xtlbfill) |
| 202 | |
| 203 | .org 0x300 |
| 204 | LEAF(excep_cache) |
Paul Burton | 609cf6f | 2015-09-22 11:12:11 -0700 | [diff] [blame] | 205 | DUMP_EXCEP("Cache") |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 206 | b . |
| 207 | nop |
| 208 | END(excep_cache) |
| 209 | |
| 210 | .org 0x380 |
| 211 | LEAF(excep_genex) |
Paul Burton | 609cf6f | 2015-09-22 11:12:11 -0700 | [diff] [blame] | 212 | DUMP_EXCEP("General") |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 213 | b . |
| 214 | nop |
| 215 | END(excep_genex) |
| 216 | |
| 217 | .org 0x400 |
| 218 | LEAF(excep_intex) |
Paul Burton | 609cf6f | 2015-09-22 11:12:11 -0700 | [diff] [blame] | 219 | DUMP_EXCEP("Interrupt") |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 220 | b . |
| 221 | nop |
| 222 | END(excep_intex) |
| 223 | |
| 224 | .org 0x480 |
| 225 | LEAF(excep_ejtag) |
Paul Burton | 609cf6f | 2015-09-22 11:12:11 -0700 | [diff] [blame] | 226 | DUMP_EXCEP("EJTAG") |
Markos Chandras | 81a02e3 | 2015-07-01 09:13:29 +0100 | [diff] [blame] | 227 | PTR_LA k0, ejtag_debug_handler |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 228 | jr k0 |
| 229 | nop |
| 230 | END(excep_ejtag) |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 231 | |
| 232 | LEAF(mips_cps_core_init) |
Paul Burton | 7a63076 | 2015-08-05 15:42:38 -0700 | [diff] [blame] | 233 | #ifdef CONFIG_MIPS_MT_SMP |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 234 | /* Check that the core implements the MT ASE */ |
| 235 | has_mt t0, 3f |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 236 | |
| 237 | .set push |
| 238 | .set mt |
| 239 | |
| 240 | /* Only allow 1 TC per VPE to execute... */ |
| 241 | dmt |
| 242 | |
| 243 | /* ...and for the moment only 1 VPE */ |
| 244 | dvpe |
Markos Chandras | 81a02e3 | 2015-07-01 09:13:29 +0100 | [diff] [blame] | 245 | PTR_LA t1, 1f |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 246 | jr.hb t1 |
| 247 | nop |
| 248 | |
| 249 | /* Enter VPE configuration state */ |
| 250 | 1: mfc0 t0, CP0_MVPCONTROL |
| 251 | ori t0, t0, MVPCONTROL_VPC |
| 252 | mtc0 t0, CP0_MVPCONTROL |
| 253 | |
| 254 | /* Retrieve the number of VPEs within the core */ |
| 255 | mfc0 t0, CP0_MVPCONF0 |
| 256 | srl t0, t0, MVPCONF0_PVPE_SHIFT |
| 257 | andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT) |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 258 | addiu ta3, t0, 1 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 259 | |
| 260 | /* If there's only 1, we're done */ |
| 261 | beqz t0, 2f |
| 262 | nop |
| 263 | |
| 264 | /* Loop through each VPE within this core */ |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 265 | li ta1, 1 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 266 | |
| 267 | 1: /* Operate on the appropriate TC */ |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 268 | mtc0 ta1, CP0_VPECONTROL |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 269 | ehb |
| 270 | |
| 271 | /* Bind TC to VPE (1:1 TC:VPE mapping) */ |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 272 | mttc0 ta1, CP0_TCBIND |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 273 | |
| 274 | /* Set exclusive TC, non-active, master */ |
| 275 | li t0, VPECONF0_MVP |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 276 | sll t1, ta1, VPECONF0_XTC_SHIFT |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 277 | or t0, t0, t1 |
| 278 | mttc0 t0, CP0_VPECONF0 |
| 279 | |
| 280 | /* Set TC non-active, non-allocatable */ |
| 281 | mttc0 zero, CP0_TCSTATUS |
| 282 | |
| 283 | /* Set TC halted */ |
| 284 | li t0, TCHALT_H |
| 285 | mttc0 t0, CP0_TCHALT |
| 286 | |
| 287 | /* Next VPE */ |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 288 | addiu ta1, ta1, 1 |
| 289 | slt t0, ta1, ta3 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 290 | bnez t0, 1b |
| 291 | nop |
| 292 | |
| 293 | /* Leave VPE configuration state */ |
| 294 | 2: mfc0 t0, CP0_MVPCONTROL |
| 295 | xori t0, t0, MVPCONTROL_VPC |
| 296 | mtc0 t0, CP0_MVPCONTROL |
| 297 | |
| 298 | 3: .set pop |
| 299 | #endif |
| 300 | jr ra |
| 301 | nop |
| 302 | END(mips_cps_core_init) |
| 303 | |
Paul Burton | f12401d | 2016-02-03 03:15:31 +0000 | [diff] [blame] | 304 | /** |
| 305 | * mips_cps_get_bootcfg() - retrieve boot configuration pointers |
| 306 | * |
| 307 | * Returns: pointer to struct core_boot_config in v0, pointer to |
| 308 | * struct vpe_boot_config in v1, VPE ID in t9 |
| 309 | */ |
| 310 | LEAF(mips_cps_get_bootcfg) |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 311 | /* Calculate a pointer to this cores struct core_boot_config */ |
Paul Burton | f12401d | 2016-02-03 03:15:31 +0000 | [diff] [blame] | 312 | cmgcrb t0 |
Paul Burton | 9099651 | 2015-08-05 15:42:35 -0700 | [diff] [blame] | 313 | lw t0, GCR_CL_ID_OFS(t0) |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 314 | li t1, COREBOOTCFG_SIZE |
| 315 | mul t0, t0, t1 |
Markos Chandras | 81a02e3 | 2015-07-01 09:13:29 +0100 | [diff] [blame] | 316 | PTR_LA t1, mips_cps_core_bootcfg |
Markos Chandras | b677bc0 | 2015-07-01 09:13:33 +0100 | [diff] [blame] | 317 | PTR_L t1, 0(t1) |
Paul Burton | f12401d | 2016-02-03 03:15:31 +0000 | [diff] [blame] | 318 | PTR_ADDU v0, t0, t1 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 319 | |
| 320 | /* Calculate this VPEs ID. If the core doesn't support MT use 0 */ |
Paul Burton | 1e5fb28 | 2015-08-05 15:42:36 -0700 | [diff] [blame] | 321 | li t9, 0 |
Paul Burton | 5a3e7c0 | 2016-02-03 03:15:33 +0000 | [diff] [blame^] | 322 | #if defined(CONFIG_CPU_MIPSR6) |
| 323 | has_vp ta2, 1f |
| 324 | |
| 325 | /* |
| 326 | * Assume non-contiguous numbering. Perhaps some day we'll need |
| 327 | * to handle contiguous VP numbering, but no such systems yet |
| 328 | * exist. |
| 329 | */ |
| 330 | mfc0 t9, $3, 1 |
| 331 | andi t9, t9, 0xff |
| 332 | #elif defined(CONFIG_MIPS_MT_SMP) |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 333 | has_mt ta2, 1f |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 334 | |
| 335 | /* Find the number of VPEs present in the core */ |
| 336 | mfc0 t1, CP0_MVPCONF0 |
| 337 | srl t1, t1, MVPCONF0_PVPE_SHIFT |
| 338 | andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT |
Markos Chandras | acac410 | 2014-11-24 14:40:11 +0000 | [diff] [blame] | 339 | addiu t1, t1, 1 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 340 | |
| 341 | /* Calculate a mask for the VPE ID from EBase.CPUNum */ |
| 342 | clz t1, t1 |
| 343 | li t2, 31 |
| 344 | subu t1, t2, t1 |
| 345 | li t2, 1 |
| 346 | sll t1, t2, t1 |
| 347 | addiu t1, t1, -1 |
| 348 | |
| 349 | /* Retrieve the VPE ID from EBase.CPUNum */ |
| 350 | mfc0 t9, $15, 1 |
| 351 | and t9, t9, t1 |
Paul Burton | a5b0f6d | 2015-08-05 15:42:37 -0700 | [diff] [blame] | 352 | #endif |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 353 | |
| 354 | 1: /* Calculate a pointer to this VPEs struct vpe_boot_config */ |
| 355 | li t1, VPEBOOTCFG_SIZE |
Paul Burton | f12401d | 2016-02-03 03:15:31 +0000 | [diff] [blame] | 356 | mul v1, t9, t1 |
| 357 | PTR_L ta3, COREBOOTCFG_VPECONFIG(v0) |
| 358 | PTR_ADDU v1, v1, ta3 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 359 | |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 360 | jr ra |
| 361 | nop |
Paul Burton | f12401d | 2016-02-03 03:15:31 +0000 | [diff] [blame] | 362 | END(mips_cps_get_bootcfg) |
| 363 | |
| 364 | LEAF(mips_cps_boot_vpes) |
| 365 | PTR_L ta2, COREBOOTCFG_VPEMASK(a0) |
| 366 | PTR_L ta3, COREBOOTCFG_VPECONFIG(a0) |
| 367 | |
Paul Burton | 5a3e7c0 | 2016-02-03 03:15:33 +0000 | [diff] [blame^] | 368 | #if defined(CONFIG_CPU_MIPSR6) |
| 369 | |
| 370 | has_vp t0, 5f |
| 371 | |
| 372 | /* Find base address of CPC */ |
| 373 | cmgcrb t3 |
| 374 | PTR_L t1, GCR_CPC_BASE_OFS(t3) |
| 375 | PTR_LI t2, ~0x7fff |
| 376 | and t1, t1, t2 |
| 377 | PTR_LI t2, UNCAC_BASE |
| 378 | PTR_ADD t1, t1, t2 |
| 379 | |
| 380 | /* Set VC_RUN to the VPE mask */ |
| 381 | PTR_S ta2, CPC_CL_VC_RUN_OFS(t1) |
| 382 | ehb |
| 383 | |
| 384 | #elif defined(CONFIG_MIPS_MT) |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 385 | |
| 386 | .set push |
| 387 | .set mt |
| 388 | |
Paul Burton | f12401d | 2016-02-03 03:15:31 +0000 | [diff] [blame] | 389 | /* If the core doesn't support MT then return */ |
| 390 | has_mt t0, 5f |
| 391 | |
| 392 | /* Enter VPE configuration state */ |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 393 | dvpe |
Markos Chandras | 81a02e3 | 2015-07-01 09:13:29 +0100 | [diff] [blame] | 394 | PTR_LA t1, 1f |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 395 | jr.hb t1 |
| 396 | nop |
| 397 | 1: mfc0 t1, CP0_MVPCONTROL |
| 398 | ori t1, t1, MVPCONTROL_VPC |
| 399 | mtc0 t1, CP0_MVPCONTROL |
| 400 | ehb |
| 401 | |
| 402 | /* Loop through each VPE */ |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 403 | move t8, ta2 |
| 404 | li ta1, 0 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 405 | |
| 406 | /* Check whether the VPE should be running. If not, skip it */ |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 407 | 1: andi t0, ta2, 1 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 408 | beqz t0, 2f |
| 409 | nop |
| 410 | |
| 411 | /* Operate on the appropriate TC */ |
| 412 | mfc0 t0, CP0_VPECONTROL |
| 413 | ori t0, t0, VPECONTROL_TARGTC |
| 414 | xori t0, t0, VPECONTROL_TARGTC |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 415 | or t0, t0, ta1 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 416 | mtc0 t0, CP0_VPECONTROL |
| 417 | ehb |
| 418 | |
| 419 | /* Skip the VPE if its TC is not halted */ |
| 420 | mftc0 t0, CP0_TCHALT |
| 421 | beqz t0, 2f |
| 422 | nop |
| 423 | |
| 424 | /* Calculate a pointer to the VPEs struct vpe_boot_config */ |
| 425 | li t0, VPEBOOTCFG_SIZE |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 426 | mul t0, t0, ta1 |
| 427 | addu t0, t0, ta3 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 428 | |
| 429 | /* Set the TC restart PC */ |
| 430 | lw t1, VPEBOOTCFG_PC(t0) |
| 431 | mttc0 t1, CP0_TCRESTART |
| 432 | |
| 433 | /* Set the TC stack pointer */ |
| 434 | lw t1, VPEBOOTCFG_SP(t0) |
| 435 | mttgpr t1, sp |
| 436 | |
| 437 | /* Set the TC global pointer */ |
| 438 | lw t1, VPEBOOTCFG_GP(t0) |
| 439 | mttgpr t1, gp |
| 440 | |
| 441 | /* Copy config from this VPE */ |
| 442 | mfc0 t0, CP0_CONFIG |
| 443 | mttc0 t0, CP0_CONFIG |
| 444 | |
| 445 | /* Ensure no software interrupts are pending */ |
| 446 | mttc0 zero, CP0_CAUSE |
| 447 | mttc0 zero, CP0_STATUS |
| 448 | |
| 449 | /* Set TC active, not interrupt exempt */ |
| 450 | mftc0 t0, CP0_TCSTATUS |
| 451 | li t1, ~TCSTATUS_IXMT |
| 452 | and t0, t0, t1 |
| 453 | ori t0, t0, TCSTATUS_A |
| 454 | mttc0 t0, CP0_TCSTATUS |
| 455 | |
| 456 | /* Clear the TC halt bit */ |
| 457 | mttc0 zero, CP0_TCHALT |
| 458 | |
| 459 | /* Set VPE active */ |
| 460 | mftc0 t0, CP0_VPECONF0 |
| 461 | ori t0, t0, VPECONF0_VPA |
| 462 | mttc0 t0, CP0_VPECONF0 |
| 463 | |
| 464 | /* Next VPE */ |
Markos Chandras | 0586ac7 | 2015-07-01 09:13:31 +0100 | [diff] [blame] | 465 | 2: srl ta2, ta2, 1 |
| 466 | addiu ta1, ta1, 1 |
| 467 | bnez ta2, 1b |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 468 | nop |
| 469 | |
| 470 | /* Leave VPE configuration state */ |
| 471 | mfc0 t1, CP0_MVPCONTROL |
| 472 | xori t1, t1, MVPCONTROL_VPC |
| 473 | mtc0 t1, CP0_MVPCONTROL |
| 474 | ehb |
| 475 | evpe |
| 476 | |
| 477 | /* Check whether this VPE is meant to be running */ |
| 478 | li t0, 1 |
Paul Burton | f12401d | 2016-02-03 03:15:31 +0000 | [diff] [blame] | 479 | sll t0, t0, a1 |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 480 | and t0, t0, t8 |
| 481 | bnez t0, 2f |
| 482 | nop |
| 483 | |
| 484 | /* This VPE should be offline, halt the TC */ |
| 485 | li t0, TCHALT_H |
| 486 | mtc0 t0, CP0_TCHALT |
Markos Chandras | 81a02e3 | 2015-07-01 09:13:29 +0100 | [diff] [blame] | 487 | PTR_LA t0, 1f |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 488 | 1: jr.hb t0 |
| 489 | nop |
| 490 | |
| 491 | 2: .set pop |
| 492 | |
Paul Burton | 7a63076 | 2015-08-05 15:42:38 -0700 | [diff] [blame] | 493 | #endif /* CONFIG_MIPS_MT_SMP */ |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 494 | |
| 495 | /* Return */ |
Paul Burton | f12401d | 2016-02-03 03:15:31 +0000 | [diff] [blame] | 496 | 5: jr ra |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 497 | nop |
| 498 | END(mips_cps_boot_vpes) |
Paul Burton | 3179d37 | 2014-04-14 11:00:56 +0100 | [diff] [blame] | 499 | |
Paul Burton | 3dbc997 | 2016-02-03 03:15:30 +0000 | [diff] [blame] | 500 | LEAF(mips_cps_cache_init) |
| 501 | /* |
| 502 | * Clear the bits used to index the caches. Note that the architecture |
| 503 | * dictates that writing to any of TagLo or TagHi selects 0 or 2 should |
| 504 | * be valid for all MIPS32 CPUs, even those for which said writes are |
| 505 | * unnecessary. |
| 506 | */ |
| 507 | mtc0 zero, CP0_TAGLO, 0 |
| 508 | mtc0 zero, CP0_TAGHI, 0 |
| 509 | mtc0 zero, CP0_TAGLO, 2 |
| 510 | mtc0 zero, CP0_TAGHI, 2 |
| 511 | ehb |
| 512 | |
| 513 | /* Primary cache configuration is indicated by Config1 */ |
| 514 | mfc0 v0, CP0_CONFIG, 1 |
| 515 | |
| 516 | /* Detect I-cache line size */ |
| 517 | _EXT t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ |
| 518 | beqz t0, icache_done |
| 519 | li t1, 2 |
| 520 | sllv t0, t1, t0 |
| 521 | |
| 522 | /* Detect I-cache size */ |
| 523 | _EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ |
| 524 | xori t2, t1, 0x7 |
| 525 | beqz t2, 1f |
| 526 | li t3, 32 |
| 527 | addiu t1, t1, 1 |
| 528 | sllv t1, t3, t1 |
| 529 | 1: /* At this point t1 == I-cache sets per way */ |
| 530 | _EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ |
| 531 | addiu t2, t2, 1 |
| 532 | mul t1, t1, t0 |
| 533 | mul t1, t1, t2 |
| 534 | |
| 535 | li a0, CKSEG0 |
| 536 | PTR_ADD a1, a0, t1 |
| 537 | 1: cache Index_Store_Tag_I, 0(a0) |
| 538 | PTR_ADD a0, a0, t0 |
| 539 | bne a0, a1, 1b |
| 540 | nop |
| 541 | icache_done: |
| 542 | |
| 543 | /* Detect D-cache line size */ |
| 544 | _EXT t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ |
| 545 | beqz t0, dcache_done |
| 546 | li t1, 2 |
| 547 | sllv t0, t1, t0 |
| 548 | |
| 549 | /* Detect D-cache size */ |
| 550 | _EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ |
| 551 | xori t2, t1, 0x7 |
| 552 | beqz t2, 1f |
| 553 | li t3, 32 |
| 554 | addiu t1, t1, 1 |
| 555 | sllv t1, t3, t1 |
| 556 | 1: /* At this point t1 == D-cache sets per way */ |
| 557 | _EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ |
| 558 | addiu t2, t2, 1 |
| 559 | mul t1, t1, t0 |
| 560 | mul t1, t1, t2 |
| 561 | |
| 562 | li a0, CKSEG0 |
| 563 | PTR_ADDU a1, a0, t1 |
| 564 | PTR_SUBU a1, a1, t0 |
| 565 | 1: cache Index_Store_Tag_D, 0(a0) |
| 566 | bne a0, a1, 1b |
| 567 | PTR_ADD a0, a0, t0 |
| 568 | dcache_done: |
| 569 | |
| 570 | jr ra |
| 571 | nop |
| 572 | END(mips_cps_cache_init) |
| 573 | |
Paul Burton | 3179d37 | 2014-04-14 11:00:56 +0100 | [diff] [blame] | 574 | #if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM) |
| 575 | |
| 576 | /* Calculate a pointer to this CPUs struct mips_static_suspend_state */ |
| 577 | .macro psstate dest |
| 578 | .set push |
| 579 | .set noat |
| 580 | lw $1, TI_CPU(gp) |
| 581 | sll $1, $1, LONGLOG |
Markos Chandras | 81a02e3 | 2015-07-01 09:13:29 +0100 | [diff] [blame] | 582 | PTR_LA \dest, __per_cpu_offset |
Paul Burton | 3179d37 | 2014-04-14 11:00:56 +0100 | [diff] [blame] | 583 | addu $1, $1, \dest |
| 584 | lw $1, 0($1) |
Markos Chandras | 81a02e3 | 2015-07-01 09:13:29 +0100 | [diff] [blame] | 585 | PTR_LA \dest, cps_cpu_state |
Paul Burton | 3179d37 | 2014-04-14 11:00:56 +0100 | [diff] [blame] | 586 | addu \dest, \dest, $1 |
| 587 | .set pop |
| 588 | .endm |
| 589 | |
| 590 | LEAF(mips_cps_pm_save) |
| 591 | /* Save CPU state */ |
| 592 | SUSPEND_SAVE_REGS |
| 593 | psstate t1 |
| 594 | SUSPEND_SAVE_STATIC |
| 595 | jr v0 |
| 596 | nop |
| 597 | END(mips_cps_pm_save) |
| 598 | |
| 599 | LEAF(mips_cps_pm_restore) |
| 600 | /* Restore CPU state */ |
| 601 | psstate t1 |
| 602 | RESUME_RESTORE_STATIC |
| 603 | RESUME_RESTORE_REGS_RETURN |
| 604 | END(mips_cps_pm_restore) |
| 605 | |
| 606 | #endif /* CONFIG_MIPS_CPS_PM && CONFIG_CPU_PM */ |