Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 1 | # |
| 2 | # Memory devices |
| 3 | # |
| 4 | |
| 5 | menuconfig MEMORY |
| 6 | bool "Memory Controller drivers" |
| 7 | |
| 8 | if MEMORY |
| 9 | |
| 10 | config TI_EMIF |
| 11 | tristate "Texas Instruments EMIF driver" |
Santosh Shilimkar | 18e9a97 | 2012-05-04 11:38:11 +0530 | [diff] [blame] | 12 | depends on ARCH_OMAP2PLUS |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 13 | select DDR |
| 14 | help |
| 15 | This driver is for the EMIF module available in Texas Instruments |
| 16 | SoCs. EMIF is an SDRAM controller that, based on its revision, |
| 17 | supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols. |
| 18 | This driver takes care of only LPDDR2 memories presently. The |
| 19 | functions of the driver includes re-configuring AC timing |
| 20 | parameters and other settings during frequency, voltage and |
| 21 | temperature changes |
| 22 | |
Ezequiel Garcia | 3edad32 | 2013-04-23 16:21:26 -0300 | [diff] [blame] | 23 | config MVEBU_DEVBUS |
| 24 | bool "Marvell EBU Device Bus Controller" |
| 25 | default y |
| 26 | depends on PLAT_ORION && OF |
| 27 | help |
| 28 | This driver is for the Device Bus controller available in some |
| 29 | Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and |
| 30 | Armada 370 and Armada XP. This controller allows to handle flash |
| 31 | devices such as NOR, NAND, SRAM, and FPGA. |
| 32 | |
Hiroshi DOYU | c542fb7 | 2012-05-10 10:42:30 +0300 | [diff] [blame] | 33 | config TEGRA20_MC |
Hiroshi DOYU | f0e33f9 | 2012-05-11 09:56:24 +0300 | [diff] [blame] | 34 | bool "Tegra20 Memory Controller(MC) driver" |
| 35 | default y |
Hiroshi DOYU | c542fb7 | 2012-05-10 10:42:30 +0300 | [diff] [blame] | 36 | depends on ARCH_TEGRA_2x_SOC |
Hiroshi DOYU | f0e33f9 | 2012-05-11 09:56:24 +0300 | [diff] [blame] | 37 | help |
| 38 | This driver is for the Memory Controller(MC) module available |
| 39 | in Tegra20 SoCs, mainly for a address translation fault |
| 40 | analysis, especially for IOMMU/GART(Graphics Address |
| 41 | Relocation Table) module. |
Hiroshi DOYU | c542fb7 | 2012-05-10 10:42:30 +0300 | [diff] [blame] | 42 | |
Hiroshi DOYU | af46810 | 2012-05-10 10:42:32 +0300 | [diff] [blame] | 43 | config TEGRA30_MC |
Hiroshi DOYU | 42d1149 | 2012-05-11 09:56:25 +0300 | [diff] [blame] | 44 | bool "Tegra30 Memory Controller(MC) driver" |
| 45 | default y |
Hiroshi DOYU | af46810 | 2012-05-10 10:42:32 +0300 | [diff] [blame] | 46 | depends on ARCH_TEGRA_3x_SOC |
Hiroshi DOYU | 42d1149 | 2012-05-11 09:56:25 +0300 | [diff] [blame] | 47 | help |
| 48 | This driver is for the Memory Controller(MC) module available |
| 49 | in Tegra30 SoCs, mainly for a address translation fault |
| 50 | analysis, especially for IOMMU/SMMU(System Memory Management |
| 51 | Unit) module. |
Hiroshi DOYU | af46810 | 2012-05-10 10:42:32 +0300 | [diff] [blame] | 52 | |
Paul Gortmaker | 42d87b1 | 2014-02-19 17:46:40 -0500 | [diff] [blame] | 53 | config FSL_IFC |
| 54 | bool |
| 55 | depends on FSL_SOC |
| 56 | |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 57 | endif |