Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 1 | /* |
| 2 | * HD audio interface patch for Creative CA0132 chip |
| 3 | * |
| 4 | * Copyright (c) 2011, Creative Technology Ltd. |
| 5 | * |
| 6 | * Based on patch_ca0110.c |
| 7 | * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> |
| 8 | * |
| 9 | * This driver is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This driver is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/delay.h> |
| 26 | #include <linux/slab.h> |
| 27 | #include <linux/pci.h> |
| 28 | #include <linux/mutex.h> |
Paul Gortmaker | da155d5 | 2011-07-15 12:38:28 -0400 | [diff] [blame] | 29 | #include <linux/module.h> |
Ian Minett | 4aa3bb0 | 2012-09-20 20:29:15 -0700 | [diff] [blame] | 30 | #include <linux/firmware.h> |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 31 | #include <sound/core.h> |
| 32 | #include "hda_codec.h" |
| 33 | #include "hda_local.h" |
Takashi Iwai | 128bc4b | 2012-05-07 17:42:31 +0200 | [diff] [blame] | 34 | #include "hda_auto_parser.h" |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 35 | #include "hda_jack.h" |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 36 | |
Ian Minett | bcd109c | 2012-09-20 20:29:14 -0700 | [diff] [blame] | 37 | #include "ca0132_regs.h" |
| 38 | |
Ian Minett | ef6b2ea | 2012-12-20 18:53:33 -0800 | [diff] [blame] | 39 | /* Enable this to see controls for tuning purpose. */ |
| 40 | /*#define ENABLE_TUNING_CONTROLS*/ |
| 41 | |
| 42 | #define FLOAT_ZERO 0x00000000 |
| 43 | #define FLOAT_ONE 0x3f800000 |
| 44 | #define FLOAT_TWO 0x40000000 |
| 45 | #define FLOAT_MINUS_5 0xc0a00000 |
| 46 | |
| 47 | #define UNSOL_TAG_HP 0x10 |
| 48 | #define UNSOL_TAG_AMIC1 0x12 |
| 49 | #define UNSOL_TAG_DSP 0x16 |
| 50 | |
Ian Minett | 4aa3bb0 | 2012-09-20 20:29:15 -0700 | [diff] [blame] | 51 | #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) |
| 52 | #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) |
| 53 | |
| 54 | #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 |
| 55 | #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 |
| 56 | #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 |
| 57 | |
| 58 | #define MASTERCONTROL 0x80 |
Ian Minett | ef6b2ea | 2012-12-20 18:53:33 -0800 | [diff] [blame] | 59 | #define MASTERCONTROL_ALLOC_DMA_CHAN 10 |
| 60 | #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 |
Ian Minett | 4aa3bb0 | 2012-09-20 20:29:15 -0700 | [diff] [blame] | 61 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 62 | #define WIDGET_CHIP_CTRL 0x15 |
| 63 | #define WIDGET_DSP_CTRL 0x16 |
| 64 | |
Ian Minett | 4aa3bb0 | 2012-09-20 20:29:15 -0700 | [diff] [blame] | 65 | #define MEM_CONNID_MICIN1 3 |
| 66 | #define MEM_CONNID_MICIN2 5 |
| 67 | #define MEM_CONNID_MICOUT1 12 |
| 68 | #define MEM_CONNID_MICOUT2 14 |
| 69 | #define MEM_CONNID_WUH 10 |
| 70 | #define MEM_CONNID_DSP 16 |
| 71 | #define MEM_CONNID_DMIC 100 |
| 72 | |
| 73 | #define SCP_SET 0 |
| 74 | #define SCP_GET 1 |
| 75 | |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 76 | #define EFX_FILE "ctefx.bin" |
| 77 | |
| 78 | MODULE_FIRMWARE(EFX_FILE); |
| 79 | |
Ian Minett | ef6b2ea | 2012-12-20 18:53:33 -0800 | [diff] [blame] | 80 | static char *dirstr[2] = { "Playback", "Capture" }; |
| 81 | |
| 82 | enum { |
| 83 | SPEAKER_OUT, |
| 84 | HEADPHONE_OUT |
| 85 | }; |
| 86 | |
| 87 | enum { |
| 88 | DIGITAL_MIC, |
| 89 | LINE_MIC_IN |
| 90 | }; |
| 91 | |
| 92 | enum { |
| 93 | #define VNODE_START_NID 0x80 |
| 94 | VNID_SPK = VNODE_START_NID, /* Speaker vnid */ |
| 95 | VNID_MIC, |
| 96 | VNID_HP_SEL, |
| 97 | VNID_AMIC1_SEL, |
| 98 | VNID_HP_ASEL, |
| 99 | VNID_AMIC1_ASEL, |
| 100 | VNODE_END_NID, |
| 101 | #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) |
| 102 | |
| 103 | #define EFFECT_START_NID 0x90 |
| 104 | #define OUT_EFFECT_START_NID EFFECT_START_NID |
| 105 | SURROUND = OUT_EFFECT_START_NID, |
| 106 | CRYSTALIZER, |
| 107 | DIALOG_PLUS, |
| 108 | SMART_VOLUME, |
| 109 | X_BASS, |
| 110 | EQUALIZER, |
| 111 | OUT_EFFECT_END_NID, |
| 112 | #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) |
| 113 | |
| 114 | #define IN_EFFECT_START_NID OUT_EFFECT_END_NID |
| 115 | ECHO_CANCELLATION = IN_EFFECT_START_NID, |
| 116 | VOICE_FOCUS, |
| 117 | MIC_SVM, |
| 118 | NOISE_REDUCTION, |
| 119 | IN_EFFECT_END_NID, |
| 120 | #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) |
| 121 | |
| 122 | VOICEFX = IN_EFFECT_END_NID, |
| 123 | PLAY_ENHANCEMENT, |
| 124 | CRYSTAL_VOICE, |
| 125 | EFFECT_END_NID |
| 126 | #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) |
| 127 | }; |
| 128 | |
| 129 | /* Effects values size*/ |
| 130 | #define EFFECT_VALS_MAX_COUNT 12 |
| 131 | |
| 132 | struct ct_effect { |
| 133 | char name[44]; |
| 134 | hda_nid_t nid; |
| 135 | int mid; /*effect module ID*/ |
| 136 | int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ |
| 137 | int direct; /* 0:output; 1:input*/ |
| 138 | int params; /* number of default non-on/off params */ |
| 139 | /*effect default values, 1st is on/off. */ |
| 140 | unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; |
| 141 | }; |
| 142 | |
| 143 | #define EFX_DIR_OUT 0 |
| 144 | #define EFX_DIR_IN 1 |
| 145 | |
| 146 | static struct ct_effect ca0132_effects[EFFECTS_COUNT] = { |
| 147 | { .name = "Surround", |
| 148 | .nid = SURROUND, |
| 149 | .mid = 0x96, |
| 150 | .reqs = {0, 1}, |
| 151 | .direct = EFX_DIR_OUT, |
| 152 | .params = 1, |
| 153 | .def_vals = {0x3F800000, 0x3F2B851F} |
| 154 | }, |
| 155 | { .name = "Crystalizer", |
| 156 | .nid = CRYSTALIZER, |
| 157 | .mid = 0x96, |
| 158 | .reqs = {7, 8}, |
| 159 | .direct = EFX_DIR_OUT, |
| 160 | .params = 1, |
| 161 | .def_vals = {0x3F800000, 0x3F266666} |
| 162 | }, |
| 163 | { .name = "Dialog Plus", |
| 164 | .nid = DIALOG_PLUS, |
| 165 | .mid = 0x96, |
| 166 | .reqs = {2, 3}, |
| 167 | .direct = EFX_DIR_OUT, |
| 168 | .params = 1, |
| 169 | .def_vals = {0x00000000, 0x3F000000} |
| 170 | }, |
| 171 | { .name = "Smart Volume", |
| 172 | .nid = SMART_VOLUME, |
| 173 | .mid = 0x96, |
| 174 | .reqs = {4, 5, 6}, |
| 175 | .direct = EFX_DIR_OUT, |
| 176 | .params = 2, |
| 177 | .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} |
| 178 | }, |
| 179 | { .name = "X-Bass", |
| 180 | .nid = X_BASS, |
| 181 | .mid = 0x96, |
| 182 | .reqs = {24, 23, 25}, |
| 183 | .direct = EFX_DIR_OUT, |
| 184 | .params = 2, |
| 185 | .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} |
| 186 | }, |
| 187 | { .name = "Equalizer", |
| 188 | .nid = EQUALIZER, |
| 189 | .mid = 0x96, |
| 190 | .reqs = {9, 10, 11, 12, 13, 14, |
| 191 | 15, 16, 17, 18, 19, 20}, |
| 192 | .direct = EFX_DIR_OUT, |
| 193 | .params = 11, |
| 194 | .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 195 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 196 | 0x00000000, 0x00000000, 0x00000000, 0x00000000} |
| 197 | }, |
| 198 | { .name = "Echo Cancellation", |
| 199 | .nid = ECHO_CANCELLATION, |
| 200 | .mid = 0x95, |
| 201 | .reqs = {0, 1, 2, 3}, |
| 202 | .direct = EFX_DIR_IN, |
| 203 | .params = 3, |
| 204 | .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} |
| 205 | }, |
| 206 | { .name = "Voice Focus", |
| 207 | .nid = VOICE_FOCUS, |
| 208 | .mid = 0x95, |
| 209 | .reqs = {6, 7, 8, 9}, |
| 210 | .direct = EFX_DIR_IN, |
| 211 | .params = 3, |
| 212 | .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} |
| 213 | }, |
| 214 | { .name = "Mic SVM", |
| 215 | .nid = MIC_SVM, |
| 216 | .mid = 0x95, |
| 217 | .reqs = {44, 45}, |
| 218 | .direct = EFX_DIR_IN, |
| 219 | .params = 1, |
| 220 | .def_vals = {0x00000000, 0x3F3D70A4} |
| 221 | }, |
| 222 | { .name = "Noise Reduction", |
| 223 | .nid = NOISE_REDUCTION, |
| 224 | .mid = 0x95, |
| 225 | .reqs = {4, 5}, |
| 226 | .direct = EFX_DIR_IN, |
| 227 | .params = 1, |
| 228 | .def_vals = {0x3F800000, 0x3F000000} |
| 229 | }, |
| 230 | { .name = "VoiceFX", |
| 231 | .nid = VOICEFX, |
| 232 | .mid = 0x95, |
| 233 | .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, |
| 234 | .direct = EFX_DIR_IN, |
| 235 | .params = 8, |
| 236 | .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, |
| 237 | 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, |
| 238 | 0x00000000} |
| 239 | } |
| 240 | }; |
| 241 | |
| 242 | /* Tuning controls */ |
| 243 | #ifdef ENABLE_TUNING_CONTROLS |
| 244 | |
| 245 | enum { |
| 246 | #define TUNING_CTL_START_NID 0xC0 |
| 247 | WEDGE_ANGLE = TUNING_CTL_START_NID, |
| 248 | SVM_LEVEL, |
| 249 | EQUALIZER_BAND_0, |
| 250 | EQUALIZER_BAND_1, |
| 251 | EQUALIZER_BAND_2, |
| 252 | EQUALIZER_BAND_3, |
| 253 | EQUALIZER_BAND_4, |
| 254 | EQUALIZER_BAND_5, |
| 255 | EQUALIZER_BAND_6, |
| 256 | EQUALIZER_BAND_7, |
| 257 | EQUALIZER_BAND_8, |
| 258 | EQUALIZER_BAND_9, |
| 259 | TUNING_CTL_END_NID |
| 260 | #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) |
| 261 | }; |
| 262 | |
| 263 | struct ct_tuning_ctl { |
| 264 | char name[44]; |
| 265 | hda_nid_t parent_nid; |
| 266 | hda_nid_t nid; |
| 267 | int mid; /*effect module ID*/ |
| 268 | int req; /*effect module request*/ |
| 269 | int direct; /* 0:output; 1:input*/ |
| 270 | unsigned int def_val;/*effect default values*/ |
| 271 | }; |
| 272 | |
| 273 | static struct ct_tuning_ctl ca0132_tuning_ctls[] = { |
| 274 | { .name = "Wedge Angle", |
| 275 | .parent_nid = VOICE_FOCUS, |
| 276 | .nid = WEDGE_ANGLE, |
| 277 | .mid = 0x95, |
| 278 | .req = 8, |
| 279 | .direct = EFX_DIR_IN, |
| 280 | .def_val = 0x41F00000 |
| 281 | }, |
| 282 | { .name = "SVM Level", |
| 283 | .parent_nid = MIC_SVM, |
| 284 | .nid = SVM_LEVEL, |
| 285 | .mid = 0x95, |
| 286 | .req = 45, |
| 287 | .direct = EFX_DIR_IN, |
| 288 | .def_val = 0x3F3D70A4 |
| 289 | }, |
| 290 | { .name = "EQ Band0", |
| 291 | .parent_nid = EQUALIZER, |
| 292 | .nid = EQUALIZER_BAND_0, |
| 293 | .mid = 0x96, |
| 294 | .req = 11, |
| 295 | .direct = EFX_DIR_OUT, |
| 296 | .def_val = 0x00000000 |
| 297 | }, |
| 298 | { .name = "EQ Band1", |
| 299 | .parent_nid = EQUALIZER, |
| 300 | .nid = EQUALIZER_BAND_1, |
| 301 | .mid = 0x96, |
| 302 | .req = 12, |
| 303 | .direct = EFX_DIR_OUT, |
| 304 | .def_val = 0x00000000 |
| 305 | }, |
| 306 | { .name = "EQ Band2", |
| 307 | .parent_nid = EQUALIZER, |
| 308 | .nid = EQUALIZER_BAND_2, |
| 309 | .mid = 0x96, |
| 310 | .req = 13, |
| 311 | .direct = EFX_DIR_OUT, |
| 312 | .def_val = 0x00000000 |
| 313 | }, |
| 314 | { .name = "EQ Band3", |
| 315 | .parent_nid = EQUALIZER, |
| 316 | .nid = EQUALIZER_BAND_3, |
| 317 | .mid = 0x96, |
| 318 | .req = 14, |
| 319 | .direct = EFX_DIR_OUT, |
| 320 | .def_val = 0x00000000 |
| 321 | }, |
| 322 | { .name = "EQ Band4", |
| 323 | .parent_nid = EQUALIZER, |
| 324 | .nid = EQUALIZER_BAND_4, |
| 325 | .mid = 0x96, |
| 326 | .req = 15, |
| 327 | .direct = EFX_DIR_OUT, |
| 328 | .def_val = 0x00000000 |
| 329 | }, |
| 330 | { .name = "EQ Band5", |
| 331 | .parent_nid = EQUALIZER, |
| 332 | .nid = EQUALIZER_BAND_5, |
| 333 | .mid = 0x96, |
| 334 | .req = 16, |
| 335 | .direct = EFX_DIR_OUT, |
| 336 | .def_val = 0x00000000 |
| 337 | }, |
| 338 | { .name = "EQ Band6", |
| 339 | .parent_nid = EQUALIZER, |
| 340 | .nid = EQUALIZER_BAND_6, |
| 341 | .mid = 0x96, |
| 342 | .req = 17, |
| 343 | .direct = EFX_DIR_OUT, |
| 344 | .def_val = 0x00000000 |
| 345 | }, |
| 346 | { .name = "EQ Band7", |
| 347 | .parent_nid = EQUALIZER, |
| 348 | .nid = EQUALIZER_BAND_7, |
| 349 | .mid = 0x96, |
| 350 | .req = 18, |
| 351 | .direct = EFX_DIR_OUT, |
| 352 | .def_val = 0x00000000 |
| 353 | }, |
| 354 | { .name = "EQ Band8", |
| 355 | .parent_nid = EQUALIZER, |
| 356 | .nid = EQUALIZER_BAND_8, |
| 357 | .mid = 0x96, |
| 358 | .req = 19, |
| 359 | .direct = EFX_DIR_OUT, |
| 360 | .def_val = 0x00000000 |
| 361 | }, |
| 362 | { .name = "EQ Band9", |
| 363 | .parent_nid = EQUALIZER, |
| 364 | .nid = EQUALIZER_BAND_9, |
| 365 | .mid = 0x96, |
| 366 | .req = 20, |
| 367 | .direct = EFX_DIR_OUT, |
| 368 | .def_val = 0x00000000 |
| 369 | } |
| 370 | }; |
| 371 | #endif |
| 372 | |
| 373 | /* Voice FX Presets */ |
| 374 | #define VOICEFX_MAX_PARAM_COUNT 9 |
| 375 | |
| 376 | struct ct_voicefx { |
| 377 | char *name; |
| 378 | hda_nid_t nid; |
| 379 | int mid; |
| 380 | int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ |
| 381 | }; |
| 382 | |
| 383 | struct ct_voicefx_preset { |
| 384 | char *name; /*preset name*/ |
| 385 | unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; |
| 386 | }; |
| 387 | |
| 388 | struct ct_voicefx ca0132_voicefx = { |
| 389 | .name = "VoiceFX Capture Switch", |
| 390 | .nid = VOICEFX, |
| 391 | .mid = 0x95, |
| 392 | .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} |
| 393 | }; |
| 394 | |
| 395 | struct ct_voicefx_preset ca0132_voicefx_presets[] = { |
| 396 | { .name = "Neutral", |
| 397 | .vals = { 0x00000000, 0x43C80000, 0x44AF0000, |
| 398 | 0x44FA0000, 0x3F800000, 0x3F800000, |
| 399 | 0x3F800000, 0x00000000, 0x00000000 } |
| 400 | }, |
| 401 | { .name = "Female2Male", |
| 402 | .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, |
| 403 | 0x44FA0000, 0x3F19999A, 0x3F866666, |
| 404 | 0x3F800000, 0x00000000, 0x00000000 } |
| 405 | }, |
| 406 | { .name = "Male2Female", |
| 407 | .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, |
| 408 | 0x450AC000, 0x4017AE14, 0x3F6B851F, |
| 409 | 0x3F800000, 0x00000000, 0x00000000 } |
| 410 | }, |
| 411 | { .name = "ScrappyKid", |
| 412 | .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, |
| 413 | 0x44FA0000, 0x40400000, 0x3F28F5C3, |
| 414 | 0x3F800000, 0x00000000, 0x00000000 } |
| 415 | }, |
| 416 | { .name = "Elderly", |
| 417 | .vals = { 0x3F800000, 0x44324000, 0x44BB8000, |
| 418 | 0x44E10000, 0x3FB33333, 0x3FB9999A, |
| 419 | 0x3F800000, 0x3E3A2E43, 0x00000000 } |
| 420 | }, |
| 421 | { .name = "Orc", |
| 422 | .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, |
| 423 | 0x45098000, 0x3F266666, 0x3FC00000, |
| 424 | 0x3F800000, 0x00000000, 0x00000000 } |
| 425 | }, |
| 426 | { .name = "Elf", |
| 427 | .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, |
| 428 | 0x45193000, 0x3F8E147B, 0x3F75C28F, |
| 429 | 0x3F800000, 0x00000000, 0x00000000 } |
| 430 | }, |
| 431 | { .name = "Dwarf", |
| 432 | .vals = { 0x3F800000, 0x43930000, 0x44BEE000, |
| 433 | 0x45007000, 0x3F451EB8, 0x3F7851EC, |
| 434 | 0x3F800000, 0x00000000, 0x00000000 } |
| 435 | }, |
| 436 | { .name = "AlienBrute", |
| 437 | .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, |
| 438 | 0x451F6000, 0x3F266666, 0x3FA7D945, |
| 439 | 0x3F800000, 0x3CF5C28F, 0x00000000 } |
| 440 | }, |
| 441 | { .name = "Robot", |
| 442 | .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, |
| 443 | 0x44FA0000, 0x3FB2718B, 0x3F800000, |
| 444 | 0xBC07010E, 0x00000000, 0x00000000 } |
| 445 | }, |
| 446 | { .name = "Marine", |
| 447 | .vals = { 0x3F800000, 0x43C20000, 0x44906000, |
| 448 | 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, |
| 449 | 0x3F0A3D71, 0x00000000, 0x00000000 } |
| 450 | }, |
| 451 | { .name = "Emo", |
| 452 | .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, |
| 453 | 0x44FA0000, 0x3F800000, 0x3F800000, |
| 454 | 0x3E4CCCCD, 0x00000000, 0x00000000 } |
| 455 | }, |
| 456 | { .name = "DeepVoice", |
| 457 | .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, |
| 458 | 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, |
| 459 | 0x3F800000, 0x00000000, 0x00000000 } |
| 460 | }, |
| 461 | { .name = "Munchkin", |
| 462 | .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, |
| 463 | 0x44FA0000, 0x3F800000, 0x3F1A043C, |
| 464 | 0x3F800000, 0x00000000, 0x00000000 } |
| 465 | } |
| 466 | }; |
| 467 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 468 | enum hda_cmd_vendor_io { |
| 469 | /* for DspIO node */ |
| 470 | VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, |
| 471 | VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, |
| 472 | |
| 473 | VENDOR_DSPIO_STATUS = 0xF01, |
| 474 | VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, |
| 475 | VENDOR_DSPIO_SCP_READ_DATA = 0xF02, |
| 476 | VENDOR_DSPIO_DSP_INIT = 0x703, |
| 477 | VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, |
| 478 | VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, |
| 479 | |
| 480 | /* for ChipIO node */ |
| 481 | VENDOR_CHIPIO_ADDRESS_LOW = 0x000, |
| 482 | VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, |
| 483 | VENDOR_CHIPIO_STREAM_FORMAT = 0x200, |
| 484 | VENDOR_CHIPIO_DATA_LOW = 0x300, |
| 485 | VENDOR_CHIPIO_DATA_HIGH = 0x400, |
| 486 | |
| 487 | VENDOR_CHIPIO_GET_PARAMETER = 0xF00, |
| 488 | VENDOR_CHIPIO_STATUS = 0xF01, |
| 489 | VENDOR_CHIPIO_HIC_POST_READ = 0x702, |
| 490 | VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, |
| 491 | |
Ian Minett | 4aa3bb0 | 2012-09-20 20:29:15 -0700 | [diff] [blame] | 492 | VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, |
| 493 | VENDOR_CHIPIO_8051_DATA_READ = 0xF07, |
| 494 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 495 | VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, |
Ian Minett | 4aa3bb0 | 2012-09-20 20:29:15 -0700 | [diff] [blame] | 496 | VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 497 | |
| 498 | VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, |
| 499 | VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, |
| 500 | VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, |
| 501 | VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, |
| 502 | VENDOR_CHIPIO_FLAG_SET = 0x70F, |
| 503 | VENDOR_CHIPIO_FLAGS_GET = 0xF0F, |
Ian Minett | 4aa3bb0 | 2012-09-20 20:29:15 -0700 | [diff] [blame] | 504 | VENDOR_CHIPIO_PARAM_SET = 0x710, |
| 505 | VENDOR_CHIPIO_PARAM_GET = 0xF10, |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 506 | |
| 507 | VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, |
| 508 | VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, |
| 509 | VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, |
| 510 | VENDOR_CHIPIO_PORT_FREE_SET = 0x713, |
| 511 | |
Ian Minett | 4aa3bb0 | 2012-09-20 20:29:15 -0700 | [diff] [blame] | 512 | VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, |
| 513 | VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, |
| 514 | VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, |
| 515 | VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, |
| 516 | |
| 517 | VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, |
| 518 | VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, |
| 519 | VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, |
| 520 | VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, |
| 521 | VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, |
| 522 | VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, |
| 523 | |
| 524 | VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 525 | }; |
| 526 | |
| 527 | /* |
| 528 | * Control flag IDs |
| 529 | */ |
| 530 | enum control_flag_id { |
| 531 | /* Connection manager stream setup is bypassed/enabled */ |
| 532 | CONTROL_FLAG_C_MGR = 0, |
| 533 | /* DSP DMA is bypassed/enabled */ |
| 534 | CONTROL_FLAG_DMA = 1, |
| 535 | /* 8051 'idle' mode is disabled/enabled */ |
| 536 | CONTROL_FLAG_IDLE_ENABLE = 2, |
| 537 | /* Tracker for the SPDIF-in path is bypassed/enabled */ |
| 538 | CONTROL_FLAG_TRACKER = 3, |
| 539 | /* DigitalOut to Spdif2Out connection is disabled/enabled */ |
| 540 | CONTROL_FLAG_SPDIF2OUT = 4, |
| 541 | /* Digital Microphone is disabled/enabled */ |
| 542 | CONTROL_FLAG_DMIC = 5, |
| 543 | /* ADC_B rate is 48 kHz/96 kHz */ |
| 544 | CONTROL_FLAG_ADC_B_96KHZ = 6, |
| 545 | /* ADC_C rate is 48 kHz/96 kHz */ |
| 546 | CONTROL_FLAG_ADC_C_96KHZ = 7, |
| 547 | /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ |
| 548 | CONTROL_FLAG_DAC_96KHZ = 8, |
| 549 | /* DSP rate is 48 kHz/96 kHz */ |
| 550 | CONTROL_FLAG_DSP_96KHZ = 9, |
| 551 | /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ |
| 552 | CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, |
| 553 | /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ |
| 554 | CONTROL_FLAG_SRC_RATE_96KHZ = 11, |
| 555 | /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ |
| 556 | CONTROL_FLAG_DECODE_LOOP = 12, |
| 557 | /* De-emphasis filter on DAC-1 disabled/enabled */ |
| 558 | CONTROL_FLAG_DAC1_DEEMPHASIS = 13, |
| 559 | /* De-emphasis filter on DAC-2 disabled/enabled */ |
| 560 | CONTROL_FLAG_DAC2_DEEMPHASIS = 14, |
| 561 | /* De-emphasis filter on DAC-3 disabled/enabled */ |
| 562 | CONTROL_FLAG_DAC3_DEEMPHASIS = 15, |
| 563 | /* High-pass filter on ADC_B disabled/enabled */ |
| 564 | CONTROL_FLAG_ADC_B_HIGH_PASS = 16, |
| 565 | /* High-pass filter on ADC_C disabled/enabled */ |
| 566 | CONTROL_FLAG_ADC_C_HIGH_PASS = 17, |
| 567 | /* Common mode on Port_A disabled/enabled */ |
| 568 | CONTROL_FLAG_PORT_A_COMMON_MODE = 18, |
| 569 | /* Common mode on Port_D disabled/enabled */ |
| 570 | CONTROL_FLAG_PORT_D_COMMON_MODE = 19, |
| 571 | /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ |
| 572 | CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, |
| 573 | /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ |
Ian Minett | 4aa3bb0 | 2012-09-20 20:29:15 -0700 | [diff] [blame] | 574 | CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 575 | /* ASI rate is 48kHz/96kHz */ |
| 576 | CONTROL_FLAG_ASI_96KHZ = 22, |
| 577 | /* DAC power settings able to control attached ports no/yes */ |
| 578 | CONTROL_FLAG_DACS_CONTROL_PORTS = 23, |
| 579 | /* Clock Stop OK reporting is disabled/enabled */ |
| 580 | CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, |
| 581 | /* Number of control flags */ |
| 582 | CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) |
| 583 | }; |
| 584 | |
| 585 | /* |
| 586 | * Control parameter IDs |
| 587 | */ |
Ian Minett | 4aa3bb0 | 2012-09-20 20:29:15 -0700 | [diff] [blame] | 588 | enum control_param_id { |
Ian Minett | ef6b2ea | 2012-12-20 18:53:33 -0800 | [diff] [blame] | 589 | /* 0: None, 1: Mic1In*/ |
| 590 | CONTROL_PARAM_VIP_SOURCE = 1, |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 591 | /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ |
| 592 | CONTROL_PARAM_SPDIF1_SOURCE = 2, |
Ian Minett | ef6b2ea | 2012-12-20 18:53:33 -0800 | [diff] [blame] | 593 | /* Port A output stage gain setting to use when 16 Ohm output |
| 594 | * impedance is selected*/ |
| 595 | CONTROL_PARAM_PORTA_160OHM_GAIN = 8, |
| 596 | /* Port D output stage gain setting to use when 16 Ohm output |
| 597 | * impedance is selected*/ |
| 598 | CONTROL_PARAM_PORTD_160OHM_GAIN = 10, |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 599 | |
| 600 | /* Stream Control */ |
| 601 | |
| 602 | /* Select stream with the given ID */ |
| 603 | CONTROL_PARAM_STREAM_ID = 24, |
| 604 | /* Source connection point for the selected stream */ |
| 605 | CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, |
| 606 | /* Destination connection point for the selected stream */ |
| 607 | CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, |
| 608 | /* Number of audio channels in the selected stream */ |
| 609 | CONTROL_PARAM_STREAMS_CHANNELS = 27, |
| 610 | /*Enable control for the selected stream */ |
| 611 | CONTROL_PARAM_STREAM_CONTROL = 28, |
| 612 | |
| 613 | /* Connection Point Control */ |
| 614 | |
| 615 | /* Select connection point with the given ID */ |
| 616 | CONTROL_PARAM_CONN_POINT_ID = 29, |
| 617 | /* Connection point sample rate */ |
| 618 | CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, |
| 619 | |
| 620 | /* Node Control */ |
| 621 | |
| 622 | /* Select HDA node with the given ID */ |
| 623 | CONTROL_PARAM_NODE_ID = 31 |
| 624 | }; |
| 625 | |
| 626 | /* |
| 627 | * Dsp Io Status codes |
| 628 | */ |
| 629 | enum hda_vendor_status_dspio { |
| 630 | /* Success */ |
| 631 | VENDOR_STATUS_DSPIO_OK = 0x00, |
| 632 | /* Busy, unable to accept new command, the host must retry */ |
| 633 | VENDOR_STATUS_DSPIO_BUSY = 0x01, |
| 634 | /* SCP command queue is full */ |
| 635 | VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, |
| 636 | /* SCP response queue is empty */ |
| 637 | VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 |
| 638 | }; |
| 639 | |
| 640 | /* |
| 641 | * Chip Io Status codes |
| 642 | */ |
| 643 | enum hda_vendor_status_chipio { |
| 644 | /* Success */ |
| 645 | VENDOR_STATUS_CHIPIO_OK = 0x00, |
| 646 | /* Busy, unable to accept new command, the host must retry */ |
| 647 | VENDOR_STATUS_CHIPIO_BUSY = 0x01 |
| 648 | }; |
| 649 | |
| 650 | /* |
| 651 | * CA0132 sample rate |
| 652 | */ |
| 653 | enum ca0132_sample_rate { |
| 654 | SR_6_000 = 0x00, |
| 655 | SR_8_000 = 0x01, |
| 656 | SR_9_600 = 0x02, |
| 657 | SR_11_025 = 0x03, |
| 658 | SR_16_000 = 0x04, |
| 659 | SR_22_050 = 0x05, |
| 660 | SR_24_000 = 0x06, |
| 661 | SR_32_000 = 0x07, |
| 662 | SR_44_100 = 0x08, |
| 663 | SR_48_000 = 0x09, |
| 664 | SR_88_200 = 0x0A, |
| 665 | SR_96_000 = 0x0B, |
| 666 | SR_144_000 = 0x0C, |
| 667 | SR_176_400 = 0x0D, |
| 668 | SR_192_000 = 0x0E, |
| 669 | SR_384_000 = 0x0F, |
| 670 | |
| 671 | SR_COUNT = 0x10, |
| 672 | |
| 673 | SR_RATE_UNKNOWN = 0x1F |
| 674 | }; |
| 675 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 676 | static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) |
| 677 | { |
| 678 | if (pin) { |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 679 | snd_hda_codec_write(codec, pin, 0, |
| 680 | AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_HP); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 681 | if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) |
| 682 | snd_hda_codec_write(codec, pin, 0, |
| 683 | AC_VERB_SET_AMP_GAIN_MUTE, |
| 684 | AMP_OUT_UNMUTE); |
| 685 | } |
Takashi Iwai | 8e13fc1 | 2012-08-08 17:26:54 +0200 | [diff] [blame] | 686 | if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 687 | snd_hda_codec_write(codec, dac, 0, |
| 688 | AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); |
| 689 | } |
| 690 | |
| 691 | static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) |
| 692 | { |
| 693 | if (pin) { |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 694 | snd_hda_codec_write(codec, pin, 0, |
| 695 | AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_VREF80); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 696 | if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) |
| 697 | snd_hda_codec_write(codec, pin, 0, |
| 698 | AC_VERB_SET_AMP_GAIN_MUTE, |
| 699 | AMP_IN_UNMUTE(0)); |
| 700 | } |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 701 | if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 702 | snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, |
| 703 | AMP_IN_UNMUTE(0)); |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 704 | |
| 705 | /* init to 0 dB and unmute. */ |
| 706 | snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, |
| 707 | HDA_AMP_VOLMASK, 0x5a); |
| 708 | snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, |
| 709 | HDA_AMP_MUTE, 0); |
| 710 | } |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 711 | } |
| 712 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 713 | static int _add_switch(struct hda_codec *codec, hda_nid_t nid, const char *pfx, |
| 714 | int chan, int dir) |
| 715 | { |
| 716 | char namestr[44]; |
| 717 | int type = dir ? HDA_INPUT : HDA_OUTPUT; |
| 718 | struct snd_kcontrol_new knew = |
| 719 | HDA_CODEC_MUTE_MONO(namestr, nid, chan, 0, type); |
David Henningsson | c41999a | 2012-08-20 11:17:00 +0200 | [diff] [blame] | 720 | if ((query_amp_caps(codec, nid, type) & AC_AMPCAP_MUTE) == 0) { |
| 721 | snd_printdd("Skipping '%s %s Switch' (no mute on node 0x%x)\n", pfx, dirstr[dir], nid); |
| 722 | return 0; |
| 723 | } |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 724 | sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); |
| 725 | return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); |
| 726 | } |
| 727 | |
| 728 | static int _add_volume(struct hda_codec *codec, hda_nid_t nid, const char *pfx, |
| 729 | int chan, int dir) |
| 730 | { |
| 731 | char namestr[44]; |
| 732 | int type = dir ? HDA_INPUT : HDA_OUTPUT; |
| 733 | struct snd_kcontrol_new knew = |
| 734 | HDA_CODEC_VOLUME_MONO(namestr, nid, chan, 0, type); |
David Henningsson | c41999a | 2012-08-20 11:17:00 +0200 | [diff] [blame] | 735 | if ((query_amp_caps(codec, nid, type) & AC_AMPCAP_NUM_STEPS) == 0) { |
| 736 | snd_printdd("Skipping '%s %s Volume' (no amp on node 0x%x)\n", pfx, dirstr[dir], nid); |
| 737 | return 0; |
| 738 | } |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 739 | sprintf(namestr, "%s %s Volume", pfx, dirstr[dir]); |
| 740 | return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); |
| 741 | } |
| 742 | |
| 743 | #define add_out_switch(codec, nid, pfx) _add_switch(codec, nid, pfx, 3, 0) |
| 744 | #define add_out_volume(codec, nid, pfx) _add_volume(codec, nid, pfx, 3, 0) |
| 745 | #define add_in_switch(codec, nid, pfx) _add_switch(codec, nid, pfx, 3, 1) |
| 746 | #define add_in_volume(codec, nid, pfx) _add_volume(codec, nid, pfx, 3, 1) |
| 747 | #define add_mono_switch(codec, nid, pfx, chan) \ |
| 748 | _add_switch(codec, nid, pfx, chan, 0) |
| 749 | #define add_mono_volume(codec, nid, pfx, chan) \ |
| 750 | _add_volume(codec, nid, pfx, chan, 0) |
| 751 | #define add_in_mono_switch(codec, nid, pfx, chan) \ |
| 752 | _add_switch(codec, nid, pfx, chan, 1) |
| 753 | #define add_in_mono_volume(codec, nid, pfx, chan) \ |
| 754 | _add_volume(codec, nid, pfx, chan, 1) |
| 755 | |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 756 | enum dsp_download_state { |
| 757 | DSP_DOWNLOAD_FAILED = -1, |
| 758 | DSP_DOWNLOAD_INIT = 0, |
| 759 | DSP_DOWNLOADING = 1, |
| 760 | DSP_DOWNLOADED = 2 |
| 761 | }; |
| 762 | |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 763 | /* retrieve parameters from hda format */ |
| 764 | #define get_hdafmt_chs(fmt) (fmt & 0xf) |
| 765 | #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) |
| 766 | #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) |
| 767 | #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 768 | |
| 769 | /* |
| 770 | * CA0132 specific |
| 771 | */ |
| 772 | |
| 773 | struct ca0132_spec { |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 774 | const struct hda_verb *base_init_verbs; |
| 775 | const struct hda_verb *base_exit_verbs; |
| 776 | const struct hda_verb *init_verbs[5]; |
| 777 | unsigned int num_init_verbs; /* exclude base init verbs */ |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 778 | struct auto_pin_cfg autocfg; |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 779 | |
| 780 | /* Nodes configurations */ |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 781 | struct hda_multi_out multiout; |
| 782 | hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; |
| 783 | hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; |
| 784 | hda_nid_t hp_dac; |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 785 | unsigned int num_outputs; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 786 | hda_nid_t input_pins[AUTO_PIN_LAST]; |
| 787 | hda_nid_t adcs[AUTO_PIN_LAST]; |
| 788 | hda_nid_t dig_out; |
| 789 | hda_nid_t dig_in; |
| 790 | unsigned int num_inputs; |
| 791 | long curr_hp_switch; |
| 792 | long curr_hp_volume[2]; |
| 793 | long curr_speaker_switch; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 794 | const char *input_labels[AUTO_PIN_LAST]; |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 795 | struct hda_pcm pcm_rec[5]; /* PCM information */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 796 | |
| 797 | /* chip access */ |
| 798 | struct mutex chipio_mutex; /* chip access mutex */ |
| 799 | u32 curr_chip_addx; |
| 800 | |
| 801 | /* DSP download related */ |
| 802 | enum dsp_download_state dsp_state; |
| 803 | unsigned int dsp_stream_id; |
| 804 | unsigned int wait_scp; |
| 805 | unsigned int wait_scp_header; |
| 806 | unsigned int wait_num_data; |
| 807 | unsigned int scp_resp_header; |
| 808 | unsigned int scp_resp_data[4]; |
| 809 | unsigned int scp_resp_count; |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 810 | |
| 811 | /* mixer and effects related */ |
| 812 | unsigned char dmic_ctl; |
| 813 | int cur_out_type; |
| 814 | int cur_mic_type; |
| 815 | long vnode_lvol[VNODES_COUNT]; |
| 816 | long vnode_rvol[VNODES_COUNT]; |
| 817 | long vnode_lswitch[VNODES_COUNT]; |
| 818 | long vnode_rswitch[VNODES_COUNT]; |
| 819 | long effects_switch[EFFECTS_COUNT]; |
| 820 | long voicefx_val; |
| 821 | long cur_mic_boost; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 822 | }; |
| 823 | |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 824 | /* |
| 825 | * CA0132 codec access |
| 826 | */ |
| 827 | unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, |
| 828 | unsigned int verb, unsigned int parm, unsigned int *res) |
| 829 | { |
| 830 | unsigned int response; |
| 831 | response = snd_hda_codec_read(codec, nid, 0, verb, parm); |
| 832 | *res = response; |
| 833 | |
| 834 | return ((response == -1) ? -1 : 0); |
| 835 | } |
| 836 | |
| 837 | static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, |
| 838 | unsigned short converter_format, unsigned int *res) |
| 839 | { |
| 840 | return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, |
| 841 | converter_format & 0xffff, res); |
| 842 | } |
| 843 | |
| 844 | static int codec_set_converter_stream_channel(struct hda_codec *codec, |
| 845 | hda_nid_t nid, unsigned char stream, |
| 846 | unsigned char channel, unsigned int *res) |
| 847 | { |
| 848 | unsigned char converter_stream_channel = 0; |
| 849 | |
| 850 | converter_stream_channel = (stream << 4) | (channel & 0x0f); |
| 851 | return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, |
| 852 | converter_stream_channel, res); |
| 853 | } |
| 854 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 855 | /* Chip access helper function */ |
| 856 | static int chipio_send(struct hda_codec *codec, |
| 857 | unsigned int reg, |
| 858 | unsigned int data) |
| 859 | { |
| 860 | unsigned int res; |
| 861 | int retry = 50; |
| 862 | |
| 863 | /* send bits of data specified by reg */ |
| 864 | do { |
| 865 | res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, |
| 866 | reg, data); |
| 867 | if (res == VENDOR_STATUS_CHIPIO_OK) |
| 868 | return 0; |
| 869 | } while (--retry); |
| 870 | return -EIO; |
| 871 | } |
| 872 | |
| 873 | /* |
| 874 | * Write chip address through the vendor widget -- NOT protected by the Mutex! |
| 875 | */ |
| 876 | static int chipio_write_address(struct hda_codec *codec, |
| 877 | unsigned int chip_addx) |
| 878 | { |
Ian Minett | 4861af8 | 2012-09-20 20:29:20 -0700 | [diff] [blame] | 879 | struct ca0132_spec *spec = codec->spec; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 880 | int res; |
| 881 | |
Ian Minett | 4861af8 | 2012-09-20 20:29:20 -0700 | [diff] [blame] | 882 | if (spec->curr_chip_addx == chip_addx) |
| 883 | return 0; |
| 884 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 885 | /* send low 16 bits of the address */ |
| 886 | res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, |
| 887 | chip_addx & 0xffff); |
| 888 | |
| 889 | if (res != -EIO) { |
| 890 | /* send high 16 bits of the address */ |
| 891 | res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, |
| 892 | chip_addx >> 16); |
| 893 | } |
| 894 | |
Ian Minett | 4861af8 | 2012-09-20 20:29:20 -0700 | [diff] [blame] | 895 | spec->curr_chip_addx = (res < 0) ? ~0UL : chip_addx; |
| 896 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 897 | return res; |
| 898 | } |
| 899 | |
| 900 | /* |
| 901 | * Write data through the vendor widget -- NOT protected by the Mutex! |
| 902 | */ |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 903 | static int chipio_write_data(struct hda_codec *codec, unsigned int data) |
| 904 | { |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 905 | struct ca0132_spec *spec = codec->spec; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 906 | int res; |
| 907 | |
| 908 | /* send low 16 bits of the data */ |
| 909 | res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); |
| 910 | |
| 911 | if (res != -EIO) { |
| 912 | /* send high 16 bits of the data */ |
| 913 | res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, |
| 914 | data >> 16); |
| 915 | } |
| 916 | |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 917 | /*If no error encountered, automatically increment the address |
| 918 | as per chip behaviour*/ |
| 919 | spec->curr_chip_addx = (res != -EIO) ? |
| 920 | (spec->curr_chip_addx + 4) : ~0UL; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 921 | return res; |
| 922 | } |
| 923 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 924 | /* |
| 925 | * Write multiple data through the vendor widget -- NOT protected by the Mutex! |
| 926 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 927 | static int chipio_write_data_multiple(struct hda_codec *codec, |
| 928 | const u32 *data, |
| 929 | unsigned int count) |
| 930 | { |
| 931 | int status = 0; |
| 932 | |
| 933 | if (data == NULL) { |
| 934 | snd_printdd(KERN_ERR "chipio_write_data null ptr"); |
| 935 | return -EINVAL; |
| 936 | } |
| 937 | |
| 938 | while ((count-- != 0) && (status == 0)) |
| 939 | status = chipio_write_data(codec, *data++); |
| 940 | |
| 941 | return status; |
| 942 | } |
| 943 | |
| 944 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 945 | /* |
| 946 | * Read data through the vendor widget -- NOT protected by the Mutex! |
| 947 | */ |
| 948 | static int chipio_read_data(struct hda_codec *codec, unsigned int *data) |
| 949 | { |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 950 | struct ca0132_spec *spec = codec->spec; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 951 | int res; |
| 952 | |
| 953 | /* post read */ |
| 954 | res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); |
| 955 | |
| 956 | if (res != -EIO) { |
| 957 | /* read status */ |
| 958 | res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); |
| 959 | } |
| 960 | |
| 961 | if (res != -EIO) { |
| 962 | /* read data */ |
| 963 | *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, |
| 964 | VENDOR_CHIPIO_HIC_READ_DATA, |
| 965 | 0); |
| 966 | } |
| 967 | |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 968 | /*If no error encountered, automatically increment the address |
| 969 | as per chip behaviour*/ |
| 970 | spec->curr_chip_addx = (res != -EIO) ? |
| 971 | (spec->curr_chip_addx + 4) : ~0UL; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 972 | return res; |
| 973 | } |
| 974 | |
| 975 | /* |
| 976 | * Write given value to the given address through the chip I/O widget. |
| 977 | * protected by the Mutex |
| 978 | */ |
| 979 | static int chipio_write(struct hda_codec *codec, |
| 980 | unsigned int chip_addx, const unsigned int data) |
| 981 | { |
| 982 | struct ca0132_spec *spec = codec->spec; |
| 983 | int err; |
| 984 | |
| 985 | mutex_lock(&spec->chipio_mutex); |
| 986 | |
| 987 | /* write the address, and if successful proceed to write data */ |
| 988 | err = chipio_write_address(codec, chip_addx); |
| 989 | if (err < 0) |
| 990 | goto exit; |
| 991 | |
| 992 | err = chipio_write_data(codec, data); |
| 993 | if (err < 0) |
| 994 | goto exit; |
| 995 | |
| 996 | exit: |
| 997 | mutex_unlock(&spec->chipio_mutex); |
| 998 | return err; |
| 999 | } |
| 1000 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1001 | /* |
| 1002 | * Write multiple values to the given address through the chip I/O widget. |
| 1003 | * protected by the Mutex |
| 1004 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1005 | static int chipio_write_multiple(struct hda_codec *codec, |
| 1006 | u32 chip_addx, |
| 1007 | const u32 *data, |
| 1008 | unsigned int count) |
| 1009 | { |
| 1010 | struct ca0132_spec *spec = codec->spec; |
| 1011 | int status; |
| 1012 | |
| 1013 | mutex_lock(&spec->chipio_mutex); |
Ian Minett | 4861af8 | 2012-09-20 20:29:20 -0700 | [diff] [blame] | 1014 | status = chipio_write_address(codec, chip_addx); |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1015 | if (status < 0) |
| 1016 | goto error; |
| 1017 | |
| 1018 | status = chipio_write_data_multiple(codec, data, count); |
| 1019 | error: |
| 1020 | mutex_unlock(&spec->chipio_mutex); |
| 1021 | |
| 1022 | return status; |
| 1023 | } |
| 1024 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 1025 | /* |
| 1026 | * Read the given address through the chip I/O widget |
| 1027 | * protected by the Mutex |
| 1028 | */ |
| 1029 | static int chipio_read(struct hda_codec *codec, |
| 1030 | unsigned int chip_addx, unsigned int *data) |
| 1031 | { |
| 1032 | struct ca0132_spec *spec = codec->spec; |
| 1033 | int err; |
| 1034 | |
| 1035 | mutex_lock(&spec->chipio_mutex); |
| 1036 | |
| 1037 | /* write the address, and if successful proceed to write data */ |
| 1038 | err = chipio_write_address(codec, chip_addx); |
| 1039 | if (err < 0) |
| 1040 | goto exit; |
| 1041 | |
| 1042 | err = chipio_read_data(codec, data); |
| 1043 | if (err < 0) |
| 1044 | goto exit; |
| 1045 | |
| 1046 | exit: |
| 1047 | mutex_unlock(&spec->chipio_mutex); |
| 1048 | return err; |
| 1049 | } |
| 1050 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1051 | /* |
| 1052 | * Set chip control flags through the chip I/O widget. |
| 1053 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1054 | static void chipio_set_control_flag(struct hda_codec *codec, |
| 1055 | enum control_flag_id flag_id, |
| 1056 | bool flag_state) |
| 1057 | { |
| 1058 | unsigned int val; |
| 1059 | unsigned int flag_bit; |
| 1060 | |
| 1061 | flag_bit = (flag_state ? 1 : 0); |
| 1062 | val = (flag_bit << 7) | (flag_id); |
| 1063 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 1064 | VENDOR_CHIPIO_FLAG_SET, val); |
| 1065 | } |
| 1066 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1067 | /* |
| 1068 | * Set chip parameters through the chip I/O widget. |
| 1069 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1070 | static void chipio_set_control_param(struct hda_codec *codec, |
| 1071 | enum control_param_id param_id, int param_val) |
| 1072 | { |
| 1073 | struct ca0132_spec *spec = codec->spec; |
| 1074 | int val; |
| 1075 | |
| 1076 | if ((param_id < 32) && (param_val < 8)) { |
| 1077 | val = (param_val << 5) | (param_id); |
| 1078 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 1079 | VENDOR_CHIPIO_PARAM_SET, val); |
| 1080 | } else { |
| 1081 | mutex_lock(&spec->chipio_mutex); |
| 1082 | if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { |
| 1083 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 1084 | VENDOR_CHIPIO_PARAM_EX_ID_SET, |
| 1085 | param_id); |
| 1086 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 1087 | VENDOR_CHIPIO_PARAM_EX_VALUE_SET, |
| 1088 | param_val); |
| 1089 | } |
| 1090 | mutex_unlock(&spec->chipio_mutex); |
| 1091 | } |
| 1092 | } |
| 1093 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1094 | /* |
| 1095 | * Set sampling rate of the connection point. |
| 1096 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1097 | static void chipio_set_conn_rate(struct hda_codec *codec, |
| 1098 | int connid, enum ca0132_sample_rate rate) |
| 1099 | { |
| 1100 | chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); |
| 1101 | chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, |
| 1102 | rate); |
| 1103 | } |
| 1104 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1105 | /* |
| 1106 | * Enable clocks. |
| 1107 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1108 | static void chipio_enable_clocks(struct hda_codec *codec) |
| 1109 | { |
| 1110 | struct ca0132_spec *spec = codec->spec; |
| 1111 | |
| 1112 | mutex_lock(&spec->chipio_mutex); |
| 1113 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 1114 | VENDOR_CHIPIO_8051_ADDRESS_LOW, 0); |
| 1115 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 1116 | VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); |
| 1117 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 1118 | VENDOR_CHIPIO_8051_ADDRESS_LOW, 5); |
| 1119 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 1120 | VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b); |
| 1121 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 1122 | VENDOR_CHIPIO_8051_ADDRESS_LOW, 6); |
| 1123 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 1124 | VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); |
| 1125 | mutex_unlock(&spec->chipio_mutex); |
| 1126 | } |
| 1127 | |
| 1128 | /* |
| 1129 | * CA0132 DSP IO stuffs |
| 1130 | */ |
| 1131 | static int dspio_send(struct hda_codec *codec, unsigned int reg, |
| 1132 | unsigned int data) |
| 1133 | { |
| 1134 | unsigned int res; |
| 1135 | int retry = 50; |
| 1136 | |
| 1137 | /* send bits of data specified by reg to dsp */ |
| 1138 | do { |
| 1139 | res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); |
| 1140 | if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) |
| 1141 | return res; |
| 1142 | } while (--retry); |
| 1143 | |
| 1144 | return -EIO; |
| 1145 | } |
| 1146 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1147 | /* |
| 1148 | * Wait for DSP to be ready for commands |
| 1149 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1150 | static void dspio_write_wait(struct hda_codec *codec) |
| 1151 | { |
Ian Minett | 4861af8 | 2012-09-20 20:29:20 -0700 | [diff] [blame] | 1152 | int status; |
| 1153 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1154 | |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1155 | do { |
Ian Minett | 4861af8 | 2012-09-20 20:29:20 -0700 | [diff] [blame] | 1156 | status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, |
| 1157 | VENDOR_DSPIO_STATUS, 0); |
| 1158 | if ((status == VENDOR_STATUS_DSPIO_OK) || |
| 1159 | (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) |
| 1160 | break; |
| 1161 | msleep(1); |
| 1162 | } while (time_before(jiffies, timeout)); |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1163 | } |
| 1164 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1165 | /* |
| 1166 | * Write SCP data to DSP |
| 1167 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1168 | static int dspio_write(struct hda_codec *codec, unsigned int scp_data) |
| 1169 | { |
| 1170 | struct ca0132_spec *spec = codec->spec; |
| 1171 | int status; |
| 1172 | |
| 1173 | dspio_write_wait(codec); |
| 1174 | |
| 1175 | mutex_lock(&spec->chipio_mutex); |
| 1176 | status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, |
| 1177 | scp_data & 0xffff); |
| 1178 | if (status < 0) |
| 1179 | goto error; |
| 1180 | |
| 1181 | status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, |
| 1182 | scp_data >> 16); |
| 1183 | if (status < 0) |
| 1184 | goto error; |
| 1185 | |
| 1186 | /* OK, now check if the write itself has executed*/ |
| 1187 | status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, |
| 1188 | VENDOR_DSPIO_STATUS, 0); |
| 1189 | error: |
| 1190 | mutex_unlock(&spec->chipio_mutex); |
| 1191 | |
| 1192 | return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? |
| 1193 | -EIO : 0; |
| 1194 | } |
| 1195 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1196 | /* |
| 1197 | * Write multiple SCP data to DSP |
| 1198 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1199 | static int dspio_write_multiple(struct hda_codec *codec, |
| 1200 | unsigned int *buffer, unsigned int size) |
| 1201 | { |
| 1202 | int status = 0; |
| 1203 | unsigned int count; |
| 1204 | |
| 1205 | if ((buffer == NULL)) |
| 1206 | return -EINVAL; |
| 1207 | |
| 1208 | count = 0; |
| 1209 | while (count < size) { |
| 1210 | status = dspio_write(codec, *buffer++); |
| 1211 | if (status != 0) |
| 1212 | break; |
| 1213 | count++; |
| 1214 | } |
| 1215 | |
| 1216 | return status; |
| 1217 | } |
| 1218 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1219 | /* |
| 1220 | * Construct the SCP header using corresponding fields |
| 1221 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1222 | static inline unsigned int |
| 1223 | make_scp_header(unsigned int target_id, unsigned int source_id, |
| 1224 | unsigned int get_flag, unsigned int req, |
| 1225 | unsigned int device_flag, unsigned int resp_flag, |
| 1226 | unsigned int error_flag, unsigned int data_size) |
| 1227 | { |
| 1228 | unsigned int header = 0; |
| 1229 | |
| 1230 | header = (data_size & 0x1f) << 27; |
| 1231 | header |= (error_flag & 0x01) << 26; |
| 1232 | header |= (resp_flag & 0x01) << 25; |
| 1233 | header |= (device_flag & 0x01) << 24; |
| 1234 | header |= (req & 0x7f) << 17; |
| 1235 | header |= (get_flag & 0x01) << 16; |
| 1236 | header |= (source_id & 0xff) << 8; |
| 1237 | header |= target_id & 0xff; |
| 1238 | |
| 1239 | return header; |
| 1240 | } |
| 1241 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1242 | /* |
| 1243 | * Extract corresponding fields from SCP header |
| 1244 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1245 | static inline void |
| 1246 | extract_scp_header(unsigned int header, |
| 1247 | unsigned int *target_id, unsigned int *source_id, |
| 1248 | unsigned int *get_flag, unsigned int *req, |
| 1249 | unsigned int *device_flag, unsigned int *resp_flag, |
| 1250 | unsigned int *error_flag, unsigned int *data_size) |
| 1251 | { |
| 1252 | if (data_size) |
| 1253 | *data_size = (header >> 27) & 0x1f; |
| 1254 | if (error_flag) |
| 1255 | *error_flag = (header >> 26) & 0x01; |
| 1256 | if (resp_flag) |
| 1257 | *resp_flag = (header >> 25) & 0x01; |
| 1258 | if (device_flag) |
| 1259 | *device_flag = (header >> 24) & 0x01; |
| 1260 | if (req) |
| 1261 | *req = (header >> 17) & 0x7f; |
| 1262 | if (get_flag) |
| 1263 | *get_flag = (header >> 16) & 0x01; |
| 1264 | if (source_id) |
| 1265 | *source_id = (header >> 8) & 0xff; |
| 1266 | if (target_id) |
| 1267 | *target_id = header & 0xff; |
| 1268 | } |
| 1269 | |
| 1270 | #define SCP_MAX_DATA_WORDS (16) |
| 1271 | |
| 1272 | /* Structure to contain any SCP message */ |
| 1273 | struct scp_msg { |
| 1274 | unsigned int hdr; |
| 1275 | unsigned int data[SCP_MAX_DATA_WORDS]; |
| 1276 | }; |
| 1277 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1278 | /* |
| 1279 | * Send SCP message to DSP |
| 1280 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1281 | static int dspio_send_scp_message(struct hda_codec *codec, |
| 1282 | unsigned char *send_buf, |
| 1283 | unsigned int send_buf_size, |
| 1284 | unsigned char *return_buf, |
| 1285 | unsigned int return_buf_size, |
| 1286 | unsigned int *bytes_returned) |
| 1287 | { |
| 1288 | struct ca0132_spec *spec = codec->spec; |
| 1289 | int retry; |
| 1290 | int status = -1; |
| 1291 | unsigned int scp_send_size = 0; |
| 1292 | unsigned int total_size; |
| 1293 | bool waiting_for_resp = false; |
| 1294 | unsigned int header; |
| 1295 | struct scp_msg *ret_msg; |
| 1296 | unsigned int resp_src_id, resp_target_id; |
| 1297 | unsigned int data_size, src_id, target_id, get_flag, device_flag; |
| 1298 | |
| 1299 | if (bytes_returned) |
| 1300 | *bytes_returned = 0; |
| 1301 | |
| 1302 | /* get scp header from buffer */ |
| 1303 | header = *((unsigned int *)send_buf); |
| 1304 | extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, |
| 1305 | &device_flag, NULL, NULL, &data_size); |
| 1306 | scp_send_size = data_size + 1; |
| 1307 | total_size = (scp_send_size * 4); |
| 1308 | |
| 1309 | if (send_buf_size < total_size) |
| 1310 | return -EINVAL; |
| 1311 | |
| 1312 | if (get_flag || device_flag) { |
| 1313 | if (!return_buf || return_buf_size < 4 || !bytes_returned) |
| 1314 | return -EINVAL; |
| 1315 | |
| 1316 | spec->wait_scp_header = *((unsigned int *)send_buf); |
| 1317 | |
| 1318 | /* swap source id with target id */ |
| 1319 | resp_target_id = src_id; |
| 1320 | resp_src_id = target_id; |
| 1321 | spec->wait_scp_header &= 0xffff0000; |
| 1322 | spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); |
| 1323 | spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; |
| 1324 | spec->wait_scp = 1; |
| 1325 | waiting_for_resp = true; |
| 1326 | } |
| 1327 | |
| 1328 | status = dspio_write_multiple(codec, (unsigned int *)send_buf, |
| 1329 | scp_send_size); |
| 1330 | if (status < 0) { |
| 1331 | spec->wait_scp = 0; |
| 1332 | return status; |
| 1333 | } |
| 1334 | |
| 1335 | if (waiting_for_resp) { |
| 1336 | memset(return_buf, 0, return_buf_size); |
| 1337 | retry = 50; |
| 1338 | do { |
| 1339 | msleep(20); |
| 1340 | } while (spec->wait_scp && (--retry != 0)); |
| 1341 | waiting_for_resp = false; |
| 1342 | if (retry != 0) { |
| 1343 | ret_msg = (struct scp_msg *)return_buf; |
| 1344 | memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); |
| 1345 | memcpy(&ret_msg->data, spec->scp_resp_data, |
| 1346 | spec->wait_num_data); |
| 1347 | *bytes_returned = (spec->scp_resp_count + 1) * 4; |
| 1348 | status = 0; |
| 1349 | } else { |
| 1350 | status = -EIO; |
| 1351 | } |
| 1352 | spec->wait_scp = 0; |
| 1353 | } |
| 1354 | |
| 1355 | return status; |
| 1356 | } |
| 1357 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1358 | /** |
| 1359 | * Prepare and send the SCP message to DSP |
| 1360 | * @codec: the HDA codec |
| 1361 | * @mod_id: ID of the DSP module to send the command |
| 1362 | * @req: ID of request to send to the DSP module |
| 1363 | * @dir: SET or GET |
| 1364 | * @data: pointer to the data to send with the request, request specific |
| 1365 | * @len: length of the data, in bytes |
| 1366 | * @reply: point to the buffer to hold data returned for a reply |
| 1367 | * @reply_len: length of the reply buffer returned from GET |
| 1368 | * |
| 1369 | * Returns zero or a negative error code. |
| 1370 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1371 | static int dspio_scp(struct hda_codec *codec, |
| 1372 | int mod_id, int req, int dir, void *data, unsigned int len, |
| 1373 | void *reply, unsigned int *reply_len) |
| 1374 | { |
| 1375 | int status = 0; |
| 1376 | struct scp_msg scp_send, scp_reply; |
| 1377 | unsigned int ret_bytes, send_size, ret_size; |
| 1378 | unsigned int send_get_flag, reply_resp_flag, reply_error_flag; |
| 1379 | unsigned int reply_data_size; |
| 1380 | |
| 1381 | memset(&scp_send, 0, sizeof(scp_send)); |
| 1382 | memset(&scp_reply, 0, sizeof(scp_reply)); |
| 1383 | |
| 1384 | if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) |
| 1385 | return -EINVAL; |
| 1386 | |
| 1387 | if (dir == SCP_GET && reply == NULL) { |
| 1388 | snd_printdd(KERN_ERR "dspio_scp get but has no buffer"); |
| 1389 | return -EINVAL; |
| 1390 | } |
| 1391 | |
| 1392 | if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { |
| 1393 | snd_printdd(KERN_ERR "dspio_scp bad resp buf len parms"); |
| 1394 | return -EINVAL; |
| 1395 | } |
| 1396 | |
| 1397 | scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req, |
| 1398 | 0, 0, 0, len/sizeof(unsigned int)); |
| 1399 | if (data != NULL && len > 0) { |
| 1400 | len = min((unsigned int)(sizeof(scp_send.data)), len); |
| 1401 | memcpy(scp_send.data, data, len); |
| 1402 | } |
| 1403 | |
| 1404 | ret_bytes = 0; |
| 1405 | send_size = sizeof(unsigned int) + len; |
| 1406 | status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, |
| 1407 | send_size, (unsigned char *)&scp_reply, |
| 1408 | sizeof(scp_reply), &ret_bytes); |
| 1409 | |
| 1410 | if (status < 0) { |
| 1411 | snd_printdd(KERN_ERR "dspio_scp: send scp msg failed"); |
| 1412 | return status; |
| 1413 | } |
| 1414 | |
| 1415 | /* extract send and reply headers members */ |
| 1416 | extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, |
| 1417 | NULL, NULL, NULL, NULL, NULL); |
| 1418 | extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, |
| 1419 | &reply_resp_flag, &reply_error_flag, |
| 1420 | &reply_data_size); |
| 1421 | |
| 1422 | if (!send_get_flag) |
| 1423 | return 0; |
| 1424 | |
| 1425 | if (reply_resp_flag && !reply_error_flag) { |
| 1426 | ret_size = (ret_bytes - sizeof(scp_reply.hdr)) |
| 1427 | / sizeof(unsigned int); |
| 1428 | |
| 1429 | if (*reply_len < ret_size*sizeof(unsigned int)) { |
| 1430 | snd_printdd(KERN_ERR "reply too long for buf"); |
| 1431 | return -EINVAL; |
| 1432 | } else if (ret_size != reply_data_size) { |
| 1433 | snd_printdd(KERN_ERR "RetLen and HdrLen .NE."); |
| 1434 | return -EINVAL; |
| 1435 | } else { |
| 1436 | *reply_len = ret_size*sizeof(unsigned int); |
| 1437 | memcpy(reply, scp_reply.data, *reply_len); |
| 1438 | } |
| 1439 | } else { |
| 1440 | snd_printdd(KERN_ERR "reply ill-formed or errflag set"); |
| 1441 | return -EIO; |
| 1442 | } |
| 1443 | |
| 1444 | return status; |
| 1445 | } |
| 1446 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1447 | /* |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 1448 | * Set DSP parameters |
| 1449 | */ |
| 1450 | static int dspio_set_param(struct hda_codec *codec, int mod_id, |
| 1451 | int req, void *data, unsigned int len) |
| 1452 | { |
| 1453 | return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL); |
| 1454 | } |
| 1455 | |
| 1456 | static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, |
| 1457 | int req, unsigned int data) |
| 1458 | { |
| 1459 | return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int)); |
| 1460 | } |
| 1461 | |
| 1462 | /* |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1463 | * Allocate a DSP DMA channel via an SCP message |
| 1464 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1465 | static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) |
| 1466 | { |
| 1467 | int status = 0; |
| 1468 | unsigned int size = sizeof(dma_chan); |
| 1469 | |
| 1470 | snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- begin"); |
| 1471 | status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN, |
| 1472 | SCP_GET, NULL, 0, dma_chan, &size); |
| 1473 | |
| 1474 | if (status < 0) { |
| 1475 | snd_printdd(KERN_INFO "dspio_alloc_dma_chan: SCP Failed"); |
| 1476 | return status; |
| 1477 | } |
| 1478 | |
| 1479 | if ((*dma_chan + 1) == 0) { |
| 1480 | snd_printdd(KERN_INFO "no free dma channels to allocate"); |
| 1481 | return -EBUSY; |
| 1482 | } |
| 1483 | |
| 1484 | snd_printdd("dspio_alloc_dma_chan: chan=%d\n", *dma_chan); |
| 1485 | snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- complete"); |
| 1486 | |
| 1487 | return status; |
| 1488 | } |
| 1489 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1490 | /* |
| 1491 | * Free a DSP DMA via an SCP message |
| 1492 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1493 | static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) |
| 1494 | { |
| 1495 | int status = 0; |
| 1496 | unsigned int dummy = 0; |
| 1497 | |
| 1498 | snd_printdd(KERN_INFO " dspio_free_dma_chan() -- begin"); |
| 1499 | snd_printdd("dspio_free_dma_chan: chan=%d\n", dma_chan); |
| 1500 | |
| 1501 | status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN, |
| 1502 | SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy); |
| 1503 | |
| 1504 | if (status < 0) { |
| 1505 | snd_printdd(KERN_INFO "dspio_free_dma_chan: SCP Failed"); |
| 1506 | return status; |
| 1507 | } |
| 1508 | |
| 1509 | snd_printdd(KERN_INFO " dspio_free_dma_chan() -- complete"); |
| 1510 | |
| 1511 | return status; |
| 1512 | } |
| 1513 | |
| 1514 | /* |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1515 | * (Re)start the DSP |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1516 | */ |
| 1517 | static int dsp_set_run_state(struct hda_codec *codec) |
| 1518 | { |
| 1519 | unsigned int dbg_ctrl_reg; |
| 1520 | unsigned int halt_state; |
| 1521 | int err; |
| 1522 | |
| 1523 | err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); |
| 1524 | if (err < 0) |
| 1525 | return err; |
| 1526 | |
| 1527 | halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> |
| 1528 | DSP_DBGCNTL_STATE_LOBIT; |
| 1529 | |
| 1530 | if (halt_state != 0) { |
| 1531 | dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & |
| 1532 | DSP_DBGCNTL_SS_MASK); |
| 1533 | err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, |
| 1534 | dbg_ctrl_reg); |
| 1535 | if (err < 0) |
| 1536 | return err; |
| 1537 | |
| 1538 | dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & |
| 1539 | DSP_DBGCNTL_EXEC_MASK; |
| 1540 | err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, |
| 1541 | dbg_ctrl_reg); |
| 1542 | if (err < 0) |
| 1543 | return err; |
| 1544 | } |
| 1545 | |
| 1546 | return 0; |
| 1547 | } |
| 1548 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1549 | /* |
| 1550 | * Reset the DSP |
| 1551 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1552 | static int dsp_reset(struct hda_codec *codec) |
| 1553 | { |
| 1554 | unsigned int res; |
| 1555 | int retry = 20; |
| 1556 | |
| 1557 | snd_printdd("dsp_reset\n"); |
| 1558 | do { |
| 1559 | res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); |
| 1560 | retry--; |
| 1561 | } while (res == -EIO && retry); |
| 1562 | |
| 1563 | if (!retry) { |
| 1564 | snd_printdd("dsp_reset timeout\n"); |
| 1565 | return -EIO; |
| 1566 | } |
| 1567 | |
| 1568 | return 0; |
| 1569 | } |
| 1570 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1571 | /* |
| 1572 | * Convert chip address to DSP address |
| 1573 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1574 | static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, |
| 1575 | bool *code, bool *yram) |
| 1576 | { |
| 1577 | *code = *yram = false; |
| 1578 | |
| 1579 | if (UC_RANGE(chip_addx, 1)) { |
| 1580 | *code = true; |
| 1581 | return UC_OFF(chip_addx); |
| 1582 | } else if (X_RANGE_ALL(chip_addx, 1)) { |
| 1583 | return X_OFF(chip_addx); |
| 1584 | } else if (Y_RANGE_ALL(chip_addx, 1)) { |
| 1585 | *yram = true; |
| 1586 | return Y_OFF(chip_addx); |
| 1587 | } |
| 1588 | |
| 1589 | return (unsigned int)INVALID_CHIP_ADDRESS; |
| 1590 | } |
| 1591 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1592 | /* |
| 1593 | * Check if the DSP DMA is active |
| 1594 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1595 | static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) |
| 1596 | { |
| 1597 | unsigned int dma_chnlstart_reg; |
| 1598 | |
| 1599 | chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); |
| 1600 | |
| 1601 | return ((dma_chnlstart_reg & (1 << |
| 1602 | (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); |
| 1603 | } |
| 1604 | |
| 1605 | static int dsp_dma_setup_common(struct hda_codec *codec, |
| 1606 | unsigned int chip_addx, |
| 1607 | unsigned int dma_chan, |
| 1608 | unsigned int port_map_mask, |
| 1609 | bool ovly) |
| 1610 | { |
| 1611 | int status = 0; |
| 1612 | unsigned int chnl_prop; |
| 1613 | unsigned int dsp_addx; |
| 1614 | unsigned int active; |
| 1615 | bool code, yram; |
| 1616 | |
| 1617 | snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Begin ---------"); |
| 1618 | |
| 1619 | if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { |
| 1620 | snd_printdd(KERN_ERR "dma chan num invalid"); |
| 1621 | return -EINVAL; |
| 1622 | } |
| 1623 | |
| 1624 | if (dsp_is_dma_active(codec, dma_chan)) { |
| 1625 | snd_printdd(KERN_ERR "dma already active"); |
| 1626 | return -EBUSY; |
| 1627 | } |
| 1628 | |
| 1629 | dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); |
| 1630 | |
| 1631 | if (dsp_addx == INVALID_CHIP_ADDRESS) { |
| 1632 | snd_printdd(KERN_ERR "invalid chip addr"); |
| 1633 | return -ENXIO; |
| 1634 | } |
| 1635 | |
| 1636 | chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; |
| 1637 | active = 0; |
| 1638 | |
| 1639 | snd_printdd(KERN_INFO " dsp_dma_setup_common() start reg pgm"); |
| 1640 | |
| 1641 | if (ovly) { |
| 1642 | status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, |
| 1643 | &chnl_prop); |
| 1644 | |
| 1645 | if (status < 0) { |
| 1646 | snd_printdd(KERN_ERR "read CHNLPROP Reg fail"); |
| 1647 | return status; |
| 1648 | } |
| 1649 | snd_printdd(KERN_INFO "dsp_dma_setup_common() Read CHNLPROP"); |
| 1650 | } |
| 1651 | |
| 1652 | if (!code) |
| 1653 | chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); |
| 1654 | else |
| 1655 | chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); |
| 1656 | |
| 1657 | chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); |
| 1658 | |
| 1659 | status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); |
| 1660 | if (status < 0) { |
| 1661 | snd_printdd(KERN_ERR "write CHNLPROP Reg fail"); |
| 1662 | return status; |
| 1663 | } |
| 1664 | snd_printdd(KERN_INFO " dsp_dma_setup_common() Write CHNLPROP"); |
| 1665 | |
| 1666 | if (ovly) { |
| 1667 | status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, |
| 1668 | &active); |
| 1669 | |
| 1670 | if (status < 0) { |
| 1671 | snd_printdd(KERN_ERR "read ACTIVE Reg fail"); |
| 1672 | return status; |
| 1673 | } |
| 1674 | snd_printdd(KERN_INFO "dsp_dma_setup_common() Read ACTIVE"); |
| 1675 | } |
| 1676 | |
| 1677 | active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & |
| 1678 | DSPDMAC_ACTIVE_AAR_MASK; |
| 1679 | |
| 1680 | status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); |
| 1681 | if (status < 0) { |
| 1682 | snd_printdd(KERN_ERR "write ACTIVE Reg fail"); |
| 1683 | return status; |
| 1684 | } |
| 1685 | |
| 1686 | snd_printdd(KERN_INFO " dsp_dma_setup_common() Write ACTIVE"); |
| 1687 | |
| 1688 | status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), |
| 1689 | port_map_mask); |
| 1690 | if (status < 0) { |
| 1691 | snd_printdd(KERN_ERR "write AUDCHSEL Reg fail"); |
| 1692 | return status; |
| 1693 | } |
| 1694 | snd_printdd(KERN_INFO " dsp_dma_setup_common() Write AUDCHSEL"); |
| 1695 | |
| 1696 | status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), |
| 1697 | DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); |
| 1698 | if (status < 0) { |
| 1699 | snd_printdd(KERN_ERR "write IRQCNT Reg fail"); |
| 1700 | return status; |
| 1701 | } |
| 1702 | snd_printdd(KERN_INFO " dsp_dma_setup_common() Write IRQCNT"); |
| 1703 | |
| 1704 | snd_printdd( |
| 1705 | "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " |
| 1706 | "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", |
| 1707 | chip_addx, dsp_addx, dma_chan, |
| 1708 | port_map_mask, chnl_prop, active); |
| 1709 | |
| 1710 | snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Complete ------"); |
| 1711 | |
| 1712 | return 0; |
| 1713 | } |
| 1714 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1715 | /* |
| 1716 | * Setup the DSP DMA per-transfer-specific registers |
| 1717 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1718 | static int dsp_dma_setup(struct hda_codec *codec, |
| 1719 | unsigned int chip_addx, |
| 1720 | unsigned int count, |
| 1721 | unsigned int dma_chan) |
| 1722 | { |
| 1723 | int status = 0; |
| 1724 | bool code, yram; |
| 1725 | unsigned int dsp_addx; |
| 1726 | unsigned int addr_field; |
| 1727 | unsigned int incr_field; |
| 1728 | unsigned int base_cnt; |
| 1729 | unsigned int cur_cnt; |
| 1730 | unsigned int dma_cfg = 0; |
| 1731 | unsigned int adr_ofs = 0; |
| 1732 | unsigned int xfr_cnt = 0; |
| 1733 | const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - |
| 1734 | DSPDMAC_XFRCNT_BCNT_LOBIT + 1); |
| 1735 | |
| 1736 | snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Begin ---------"); |
| 1737 | |
| 1738 | if (count > max_dma_count) { |
| 1739 | snd_printdd(KERN_ERR "count too big"); |
| 1740 | return -EINVAL; |
| 1741 | } |
| 1742 | |
| 1743 | dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); |
| 1744 | if (dsp_addx == INVALID_CHIP_ADDRESS) { |
| 1745 | snd_printdd(KERN_ERR "invalid chip addr"); |
| 1746 | return -ENXIO; |
| 1747 | } |
| 1748 | |
| 1749 | snd_printdd(KERN_INFO " dsp_dma_setup() start reg pgm"); |
| 1750 | |
| 1751 | addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; |
| 1752 | incr_field = 0; |
| 1753 | |
| 1754 | if (!code) { |
| 1755 | addr_field <<= 1; |
| 1756 | if (yram) |
| 1757 | addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); |
| 1758 | |
| 1759 | incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); |
| 1760 | } |
| 1761 | |
| 1762 | dma_cfg = addr_field + incr_field; |
| 1763 | status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), |
| 1764 | dma_cfg); |
| 1765 | if (status < 0) { |
| 1766 | snd_printdd(KERN_ERR "write DMACFG Reg fail"); |
| 1767 | return status; |
| 1768 | } |
| 1769 | snd_printdd(KERN_INFO " dsp_dma_setup() Write DMACFG"); |
| 1770 | |
| 1771 | adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + |
| 1772 | (code ? 0 : 1)); |
| 1773 | |
| 1774 | status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), |
| 1775 | adr_ofs); |
| 1776 | if (status < 0) { |
| 1777 | snd_printdd(KERN_ERR "write DSPADROFS Reg fail"); |
| 1778 | return status; |
| 1779 | } |
| 1780 | snd_printdd(KERN_INFO " dsp_dma_setup() Write DSPADROFS"); |
| 1781 | |
| 1782 | base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; |
| 1783 | |
| 1784 | cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; |
| 1785 | |
| 1786 | xfr_cnt = base_cnt | cur_cnt; |
| 1787 | |
| 1788 | status = chipio_write(codec, |
| 1789 | DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); |
| 1790 | if (status < 0) { |
| 1791 | snd_printdd(KERN_ERR "write XFRCNT Reg fail"); |
| 1792 | return status; |
| 1793 | } |
| 1794 | snd_printdd(KERN_INFO " dsp_dma_setup() Write XFRCNT"); |
| 1795 | |
| 1796 | snd_printdd( |
| 1797 | "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " |
| 1798 | "ADROFS=0x%x, XFRCNT=0x%x\n", |
| 1799 | chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); |
| 1800 | |
| 1801 | snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Complete ---------"); |
| 1802 | |
| 1803 | return 0; |
| 1804 | } |
| 1805 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1806 | /* |
| 1807 | * Start the DSP DMA |
| 1808 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1809 | static int dsp_dma_start(struct hda_codec *codec, |
| 1810 | unsigned int dma_chan, bool ovly) |
| 1811 | { |
| 1812 | unsigned int reg = 0; |
| 1813 | int status = 0; |
| 1814 | |
| 1815 | snd_printdd(KERN_INFO "-- dsp_dma_start() -- Begin ---------"); |
| 1816 | |
| 1817 | if (ovly) { |
| 1818 | status = chipio_read(codec, |
| 1819 | DSPDMAC_CHNLSTART_INST_OFFSET, ®); |
| 1820 | |
| 1821 | if (status < 0) { |
| 1822 | snd_printdd(KERN_ERR "read CHNLSTART reg fail"); |
| 1823 | return status; |
| 1824 | } |
| 1825 | snd_printdd(KERN_INFO "-- dsp_dma_start() Read CHNLSTART"); |
| 1826 | |
| 1827 | reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | |
| 1828 | DSPDMAC_CHNLSTART_DIS_MASK); |
| 1829 | } |
| 1830 | |
| 1831 | status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, |
| 1832 | reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); |
| 1833 | if (status < 0) { |
| 1834 | snd_printdd(KERN_ERR "write CHNLSTART reg fail"); |
| 1835 | return status; |
| 1836 | } |
| 1837 | snd_printdd(KERN_INFO "-- dsp_dma_start() -- Complete ---------"); |
| 1838 | |
| 1839 | return status; |
| 1840 | } |
| 1841 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1842 | /* |
| 1843 | * Stop the DSP DMA |
| 1844 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1845 | static int dsp_dma_stop(struct hda_codec *codec, |
| 1846 | unsigned int dma_chan, bool ovly) |
| 1847 | { |
| 1848 | unsigned int reg = 0; |
| 1849 | int status = 0; |
| 1850 | |
| 1851 | snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Begin ---------"); |
| 1852 | |
| 1853 | if (ovly) { |
| 1854 | status = chipio_read(codec, |
| 1855 | DSPDMAC_CHNLSTART_INST_OFFSET, ®); |
| 1856 | |
| 1857 | if (status < 0) { |
| 1858 | snd_printdd(KERN_ERR "read CHNLSTART reg fail"); |
| 1859 | return status; |
| 1860 | } |
| 1861 | snd_printdd(KERN_INFO "-- dsp_dma_stop() Read CHNLSTART"); |
| 1862 | reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | |
| 1863 | DSPDMAC_CHNLSTART_DIS_MASK); |
| 1864 | } |
| 1865 | |
| 1866 | status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, |
| 1867 | reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); |
| 1868 | if (status < 0) { |
| 1869 | snd_printdd(KERN_ERR "write CHNLSTART reg fail"); |
| 1870 | return status; |
| 1871 | } |
| 1872 | snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Complete ---------"); |
| 1873 | |
| 1874 | return status; |
| 1875 | } |
| 1876 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1877 | /** |
| 1878 | * Allocate router ports |
| 1879 | * |
| 1880 | * @codec: the HDA codec |
| 1881 | * @num_chans: number of channels in the stream |
| 1882 | * @ports_per_channel: number of ports per channel |
| 1883 | * @start_device: start device |
| 1884 | * @port_map: pointer to the port list to hold the allocated ports |
| 1885 | * |
| 1886 | * Returns zero or a negative error code. |
| 1887 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1888 | static int dsp_allocate_router_ports(struct hda_codec *codec, |
| 1889 | unsigned int num_chans, |
| 1890 | unsigned int ports_per_channel, |
| 1891 | unsigned int start_device, |
| 1892 | unsigned int *port_map) |
| 1893 | { |
| 1894 | int status = 0; |
| 1895 | int res; |
| 1896 | u8 val; |
| 1897 | |
| 1898 | status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); |
| 1899 | if (status < 0) |
| 1900 | return status; |
| 1901 | |
| 1902 | val = start_device << 6; |
| 1903 | val |= (ports_per_channel - 1) << 4; |
| 1904 | val |= num_chans - 1; |
| 1905 | |
| 1906 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 1907 | VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, |
| 1908 | val); |
| 1909 | |
| 1910 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 1911 | VENDOR_CHIPIO_PORT_ALLOC_SET, |
| 1912 | MEM_CONNID_DSP); |
| 1913 | |
| 1914 | status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); |
| 1915 | if (status < 0) |
| 1916 | return status; |
| 1917 | |
| 1918 | res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, |
| 1919 | VENDOR_CHIPIO_PORT_ALLOC_GET, 0); |
| 1920 | |
| 1921 | *port_map = res; |
| 1922 | |
| 1923 | return (res < 0) ? res : 0; |
| 1924 | } |
| 1925 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1926 | /* |
| 1927 | * Free router ports |
| 1928 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1929 | static int dsp_free_router_ports(struct hda_codec *codec) |
| 1930 | { |
| 1931 | int status = 0; |
| 1932 | |
| 1933 | status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); |
| 1934 | if (status < 0) |
| 1935 | return status; |
| 1936 | |
| 1937 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 1938 | VENDOR_CHIPIO_PORT_FREE_SET, |
| 1939 | MEM_CONNID_DSP); |
| 1940 | |
| 1941 | status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); |
| 1942 | |
| 1943 | return status; |
| 1944 | } |
| 1945 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1946 | /* |
| 1947 | * Allocate DSP ports for the download stream |
| 1948 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1949 | static int dsp_allocate_ports(struct hda_codec *codec, |
| 1950 | unsigned int num_chans, |
| 1951 | unsigned int rate_multi, unsigned int *port_map) |
| 1952 | { |
| 1953 | int status; |
| 1954 | |
| 1955 | snd_printdd(KERN_INFO " dsp_allocate_ports() -- begin"); |
| 1956 | |
| 1957 | if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { |
| 1958 | snd_printdd(KERN_ERR "bad rate multiple"); |
| 1959 | return -EINVAL; |
| 1960 | } |
| 1961 | |
| 1962 | status = dsp_allocate_router_ports(codec, num_chans, |
| 1963 | rate_multi, 0, port_map); |
| 1964 | |
| 1965 | snd_printdd(KERN_INFO " dsp_allocate_ports() -- complete"); |
| 1966 | |
| 1967 | return status; |
| 1968 | } |
| 1969 | |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 1970 | static int dsp_allocate_ports_format(struct hda_codec *codec, |
| 1971 | const unsigned short fmt, |
| 1972 | unsigned int *port_map) |
| 1973 | { |
| 1974 | int status; |
| 1975 | unsigned int num_chans; |
| 1976 | |
| 1977 | unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; |
| 1978 | unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; |
| 1979 | unsigned int rate_multi = sample_rate_mul / sample_rate_div; |
| 1980 | |
| 1981 | if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { |
| 1982 | snd_printdd(KERN_ERR "bad rate multiple"); |
| 1983 | return -EINVAL; |
| 1984 | } |
| 1985 | |
| 1986 | num_chans = get_hdafmt_chs(fmt) + 1; |
| 1987 | |
| 1988 | status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map); |
| 1989 | |
| 1990 | return status; |
| 1991 | } |
| 1992 | |
| 1993 | /* |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 1994 | * free DSP ports |
| 1995 | */ |
| 1996 | static int dsp_free_ports(struct hda_codec *codec) |
| 1997 | { |
| 1998 | int status; |
| 1999 | |
| 2000 | snd_printdd(KERN_INFO " dsp_free_ports() -- begin"); |
| 2001 | |
| 2002 | status = dsp_free_router_ports(codec); |
| 2003 | if (status < 0) { |
| 2004 | snd_printdd(KERN_ERR "free router ports fail"); |
| 2005 | return status; |
| 2006 | } |
| 2007 | snd_printdd(KERN_INFO " dsp_free_ports() -- complete"); |
| 2008 | |
| 2009 | return status; |
| 2010 | } |
| 2011 | |
| 2012 | /* |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2013 | * HDA DMA engine stuffs for DSP code download |
| 2014 | */ |
| 2015 | struct dma_engine { |
| 2016 | struct hda_codec *codec; |
| 2017 | unsigned short m_converter_format; |
| 2018 | struct snd_dma_buffer *dmab; |
| 2019 | unsigned int buf_size; |
| 2020 | }; |
| 2021 | |
| 2022 | |
| 2023 | enum dma_state { |
| 2024 | DMA_STATE_STOP = 0, |
| 2025 | DMA_STATE_RUN = 1 |
| 2026 | }; |
| 2027 | |
| 2028 | static int dma_convert_to_hda_format( |
Ian Minett | e97249d | 2012-09-20 20:29:21 -0700 | [diff] [blame] | 2029 | unsigned int sample_rate, |
| 2030 | unsigned short channels, |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2031 | unsigned short *hda_format) |
| 2032 | { |
| 2033 | unsigned int format_val; |
| 2034 | |
| 2035 | format_val = snd_hda_calc_stream_format( |
Ian Minett | e97249d | 2012-09-20 20:29:21 -0700 | [diff] [blame] | 2036 | sample_rate, |
| 2037 | channels, |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2038 | SNDRV_PCM_FORMAT_S32_LE, |
Ian Minett | e97249d | 2012-09-20 20:29:21 -0700 | [diff] [blame] | 2039 | 32, 0); |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2040 | |
| 2041 | if (hda_format) |
| 2042 | *hda_format = (unsigned short)format_val; |
| 2043 | |
| 2044 | return 0; |
| 2045 | } |
| 2046 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 2047 | /* |
| 2048 | * Reset DMA for DSP download |
| 2049 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2050 | static int dma_reset(struct dma_engine *dma) |
| 2051 | { |
| 2052 | struct hda_codec *codec = dma->codec; |
| 2053 | struct ca0132_spec *spec = codec->spec; |
| 2054 | int status; |
| 2055 | |
| 2056 | if (dma->dmab) |
| 2057 | snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); |
| 2058 | |
| 2059 | status = snd_hda_codec_load_dsp_prepare(codec, |
| 2060 | dma->m_converter_format, |
| 2061 | dma->buf_size, |
| 2062 | dma->dmab); |
| 2063 | if (status < 0) |
| 2064 | return status; |
| 2065 | spec->dsp_stream_id = status; |
| 2066 | return 0; |
| 2067 | } |
| 2068 | |
| 2069 | static int dma_set_state(struct dma_engine *dma, enum dma_state state) |
| 2070 | { |
| 2071 | bool cmd; |
| 2072 | |
| 2073 | snd_printdd("dma_set_state state=%d\n", state); |
| 2074 | |
| 2075 | switch (state) { |
| 2076 | case DMA_STATE_STOP: |
| 2077 | cmd = false; |
| 2078 | break; |
| 2079 | case DMA_STATE_RUN: |
| 2080 | cmd = true; |
| 2081 | break; |
| 2082 | default: |
| 2083 | return 0; |
| 2084 | } |
| 2085 | |
| 2086 | snd_hda_codec_load_dsp_trigger(dma->codec, cmd); |
| 2087 | return 0; |
| 2088 | } |
| 2089 | |
| 2090 | static unsigned int dma_get_buffer_size(struct dma_engine *dma) |
| 2091 | { |
| 2092 | return dma->dmab->bytes; |
| 2093 | } |
| 2094 | |
| 2095 | static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) |
| 2096 | { |
| 2097 | return dma->dmab->area; |
| 2098 | } |
| 2099 | |
| 2100 | static int dma_xfer(struct dma_engine *dma, |
| 2101 | const unsigned int *data, |
| 2102 | unsigned int count) |
| 2103 | { |
| 2104 | memcpy(dma->dmab->area, data, count); |
| 2105 | return 0; |
| 2106 | } |
| 2107 | |
| 2108 | static void dma_get_converter_format( |
| 2109 | struct dma_engine *dma, |
| 2110 | unsigned short *format) |
| 2111 | { |
| 2112 | if (format) |
| 2113 | *format = dma->m_converter_format; |
| 2114 | } |
| 2115 | |
| 2116 | static unsigned int dma_get_stream_id(struct dma_engine *dma) |
| 2117 | { |
| 2118 | struct ca0132_spec *spec = dma->codec->spec; |
| 2119 | |
| 2120 | return spec->dsp_stream_id; |
| 2121 | } |
| 2122 | |
| 2123 | struct dsp_image_seg { |
| 2124 | u32 magic; |
| 2125 | u32 chip_addr; |
| 2126 | u32 count; |
| 2127 | u32 data[0]; |
| 2128 | }; |
| 2129 | |
| 2130 | static const u32 g_magic_value = 0x4c46584d; |
| 2131 | static const u32 g_chip_addr_magic_value = 0xFFFFFF01; |
| 2132 | |
| 2133 | static bool is_valid(const struct dsp_image_seg *p) |
| 2134 | { |
| 2135 | return p->magic == g_magic_value; |
| 2136 | } |
| 2137 | |
| 2138 | static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) |
| 2139 | { |
| 2140 | return g_chip_addr_magic_value == p->chip_addr; |
| 2141 | } |
| 2142 | |
| 2143 | static bool is_last(const struct dsp_image_seg *p) |
| 2144 | { |
| 2145 | return p->count == 0; |
| 2146 | } |
| 2147 | |
| 2148 | static size_t dsp_sizeof(const struct dsp_image_seg *p) |
| 2149 | { |
| 2150 | return sizeof(*p) + p->count*sizeof(u32); |
| 2151 | } |
| 2152 | |
| 2153 | static const struct dsp_image_seg *get_next_seg_ptr( |
| 2154 | const struct dsp_image_seg *p) |
| 2155 | { |
| 2156 | return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); |
| 2157 | } |
| 2158 | |
| 2159 | /* |
| 2160 | * CA0132 chip DSP transfer stuffs. For DSP download. |
| 2161 | */ |
| 2162 | #define INVALID_DMA_CHANNEL (~0UL) |
| 2163 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 2164 | /* |
| 2165 | * Program a list of address/data pairs via the ChipIO widget. |
| 2166 | * The segment data is in the format of successive pairs of words. |
| 2167 | * These are repeated as indicated by the segment's count field. |
| 2168 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2169 | static int dspxfr_hci_write(struct hda_codec *codec, |
| 2170 | const struct dsp_image_seg *fls) |
| 2171 | { |
| 2172 | int status; |
| 2173 | const u32 *data; |
| 2174 | unsigned int count; |
| 2175 | |
| 2176 | if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { |
| 2177 | snd_printdd(KERN_ERR "hci_write invalid params"); |
| 2178 | return -EINVAL; |
| 2179 | } |
| 2180 | |
| 2181 | count = fls->count; |
| 2182 | data = (u32 *)(fls->data); |
| 2183 | while (count >= 2) { |
| 2184 | status = chipio_write(codec, data[0], data[1]); |
| 2185 | if (status < 0) { |
| 2186 | snd_printdd(KERN_ERR "hci_write chipio failed"); |
| 2187 | return status; |
| 2188 | } |
| 2189 | count -= 2; |
| 2190 | data += 2; |
| 2191 | } |
| 2192 | return 0; |
| 2193 | } |
| 2194 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 2195 | /** |
| 2196 | * Write a block of data into DSP code or data RAM using pre-allocated |
| 2197 | * DMA engine. |
| 2198 | * |
| 2199 | * @codec: the HDA codec |
| 2200 | * @fls: pointer to a fast load image |
| 2201 | * @reloc: Relocation address for loading single-segment overlays, or 0 for |
| 2202 | * no relocation |
| 2203 | * @dma_engine: pointer to DMA engine to be used for DSP download |
| 2204 | * @dma_chan: The number of DMA channels used for DSP download |
| 2205 | * @port_map_mask: port mapping |
| 2206 | * @ovly: TRUE if overlay format is required |
| 2207 | * |
| 2208 | * Returns zero or a negative error code. |
| 2209 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2210 | static int dspxfr_one_seg(struct hda_codec *codec, |
| 2211 | const struct dsp_image_seg *fls, |
| 2212 | unsigned int reloc, |
| 2213 | struct dma_engine *dma_engine, |
| 2214 | unsigned int dma_chan, |
| 2215 | unsigned int port_map_mask, |
| 2216 | bool ovly) |
| 2217 | { |
| 2218 | int status; |
| 2219 | bool comm_dma_setup_done = false; |
| 2220 | const unsigned int *data; |
| 2221 | unsigned int chip_addx; |
| 2222 | unsigned int words_to_write; |
| 2223 | unsigned int buffer_size_words; |
| 2224 | unsigned char *buffer_addx; |
| 2225 | unsigned short hda_format; |
| 2226 | unsigned int sample_rate_div; |
| 2227 | unsigned int sample_rate_mul; |
| 2228 | unsigned int num_chans; |
| 2229 | unsigned int hda_frame_size_words; |
| 2230 | unsigned int remainder_words; |
| 2231 | const u32 *data_remainder; |
| 2232 | u32 chip_addx_remainder; |
| 2233 | unsigned int run_size_words; |
| 2234 | const struct dsp_image_seg *hci_write = NULL; |
| 2235 | int retry; |
| 2236 | |
| 2237 | if (fls == NULL) |
| 2238 | return -EINVAL; |
| 2239 | if (is_hci_prog_list_seg(fls)) { |
| 2240 | hci_write = fls; |
| 2241 | fls = get_next_seg_ptr(fls); |
| 2242 | } |
| 2243 | |
| 2244 | if (hci_write && (!fls || is_last(fls))) { |
| 2245 | snd_printdd("hci_write\n"); |
| 2246 | return dspxfr_hci_write(codec, hci_write); |
| 2247 | } |
| 2248 | |
| 2249 | if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { |
| 2250 | snd_printdd("Invalid Params\n"); |
| 2251 | return -EINVAL; |
| 2252 | } |
| 2253 | |
| 2254 | data = fls->data; |
| 2255 | chip_addx = fls->chip_addr, |
| 2256 | words_to_write = fls->count; |
| 2257 | |
| 2258 | if (!words_to_write) |
| 2259 | return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; |
| 2260 | if (reloc) |
| 2261 | chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); |
| 2262 | |
| 2263 | if (!UC_RANGE(chip_addx, words_to_write) && |
| 2264 | !X_RANGE_ALL(chip_addx, words_to_write) && |
| 2265 | !Y_RANGE_ALL(chip_addx, words_to_write)) { |
| 2266 | snd_printdd("Invalid chip_addx Params\n"); |
| 2267 | return -EINVAL; |
| 2268 | } |
| 2269 | |
| 2270 | buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / |
| 2271 | sizeof(u32); |
| 2272 | |
| 2273 | buffer_addx = dma_get_buffer_addr(dma_engine); |
| 2274 | |
| 2275 | if (buffer_addx == NULL) { |
| 2276 | snd_printdd(KERN_ERR "dma_engine buffer NULL\n"); |
| 2277 | return -EINVAL; |
| 2278 | } |
| 2279 | |
| 2280 | dma_get_converter_format(dma_engine, &hda_format); |
| 2281 | sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; |
| 2282 | sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; |
| 2283 | num_chans = get_hdafmt_chs(hda_format) + 1; |
| 2284 | |
| 2285 | hda_frame_size_words = ((sample_rate_div == 0) ? 0 : |
| 2286 | (num_chans * sample_rate_mul / sample_rate_div)); |
| 2287 | |
| 2288 | buffer_size_words = min(buffer_size_words, |
| 2289 | (unsigned int)(UC_RANGE(chip_addx, 1) ? |
| 2290 | 65536 : 32768)); |
| 2291 | buffer_size_words -= buffer_size_words % hda_frame_size_words; |
| 2292 | snd_printdd( |
| 2293 | "chpadr=0x%08x frmsz=%u nchan=%u " |
| 2294 | "rate_mul=%u div=%u bufsz=%u\n", |
| 2295 | chip_addx, hda_frame_size_words, num_chans, |
| 2296 | sample_rate_mul, sample_rate_div, buffer_size_words); |
| 2297 | |
| 2298 | if ((buffer_addx == NULL) || (hda_frame_size_words == 0) || |
| 2299 | (buffer_size_words < hda_frame_size_words)) { |
| 2300 | snd_printdd(KERN_ERR "dspxfr_one_seg:failed\n"); |
| 2301 | return -EINVAL; |
| 2302 | } |
| 2303 | |
| 2304 | remainder_words = words_to_write % hda_frame_size_words; |
| 2305 | data_remainder = data; |
| 2306 | chip_addx_remainder = chip_addx; |
| 2307 | |
| 2308 | data += remainder_words; |
| 2309 | chip_addx += remainder_words*sizeof(u32); |
| 2310 | words_to_write -= remainder_words; |
| 2311 | |
| 2312 | while (words_to_write != 0) { |
| 2313 | run_size_words = min(buffer_size_words, words_to_write); |
| 2314 | snd_printdd("dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", |
| 2315 | words_to_write, run_size_words, remainder_words); |
| 2316 | dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); |
| 2317 | if (!comm_dma_setup_done) { |
| 2318 | status = dsp_dma_stop(codec, dma_chan, ovly); |
| 2319 | if (status < 0) |
| 2320 | return -EIO; |
| 2321 | status = dsp_dma_setup_common(codec, chip_addx, |
| 2322 | dma_chan, port_map_mask, ovly); |
| 2323 | if (status < 0) |
| 2324 | return status; |
| 2325 | comm_dma_setup_done = true; |
| 2326 | } |
| 2327 | |
| 2328 | status = dsp_dma_setup(codec, chip_addx, |
| 2329 | run_size_words, dma_chan); |
| 2330 | if (status < 0) |
| 2331 | return status; |
| 2332 | status = dsp_dma_start(codec, dma_chan, ovly); |
| 2333 | if (status < 0) |
| 2334 | return status; |
| 2335 | if (!dsp_is_dma_active(codec, dma_chan)) { |
| 2336 | snd_printdd(KERN_ERR "dspxfr:DMA did not start"); |
| 2337 | return -EIO; |
| 2338 | } |
| 2339 | status = dma_set_state(dma_engine, DMA_STATE_RUN); |
| 2340 | if (status < 0) |
| 2341 | return status; |
| 2342 | if (remainder_words != 0) { |
| 2343 | status = chipio_write_multiple(codec, |
| 2344 | chip_addx_remainder, |
| 2345 | data_remainder, |
| 2346 | remainder_words); |
| 2347 | remainder_words = 0; |
| 2348 | } |
| 2349 | if (hci_write) { |
| 2350 | status = dspxfr_hci_write(codec, hci_write); |
| 2351 | hci_write = NULL; |
| 2352 | } |
| 2353 | retry = 5000; |
| 2354 | while (dsp_is_dma_active(codec, dma_chan)) { |
| 2355 | if (--retry <= 0) |
| 2356 | break; |
| 2357 | } |
| 2358 | snd_printdd(KERN_INFO "+++++ DMA complete"); |
| 2359 | dma_set_state(dma_engine, DMA_STATE_STOP); |
| 2360 | dma_reset(dma_engine); |
| 2361 | |
| 2362 | if (status < 0) |
| 2363 | return status; |
| 2364 | |
| 2365 | data += run_size_words; |
| 2366 | chip_addx += run_size_words*sizeof(u32); |
| 2367 | words_to_write -= run_size_words; |
| 2368 | } |
| 2369 | |
| 2370 | if (remainder_words != 0) { |
| 2371 | status = chipio_write_multiple(codec, chip_addx_remainder, |
| 2372 | data_remainder, remainder_words); |
| 2373 | } |
| 2374 | |
| 2375 | return status; |
| 2376 | } |
| 2377 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 2378 | /** |
| 2379 | * Write the entire DSP image of a DSP code/data overlay to DSP memories |
| 2380 | * |
| 2381 | * @codec: the HDA codec |
| 2382 | * @fls_data: pointer to a fast load image |
| 2383 | * @reloc: Relocation address for loading single-segment overlays, or 0 for |
| 2384 | * no relocation |
Ian Minett | e97249d | 2012-09-20 20:29:21 -0700 | [diff] [blame] | 2385 | * @sample_rate: sampling rate of the stream used for DSP download |
| 2386 | * @number_channels: channels of the stream used for DSP download |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 2387 | * @ovly: TRUE if overlay format is required |
| 2388 | * |
| 2389 | * Returns zero or a negative error code. |
| 2390 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2391 | static int dspxfr_image(struct hda_codec *codec, |
| 2392 | const struct dsp_image_seg *fls_data, |
Ian Minett | e97249d | 2012-09-20 20:29:21 -0700 | [diff] [blame] | 2393 | unsigned int reloc, |
| 2394 | unsigned int sample_rate, |
| 2395 | unsigned short channels, |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2396 | bool ovly) |
| 2397 | { |
| 2398 | struct ca0132_spec *spec = codec->spec; |
| 2399 | int status; |
| 2400 | unsigned short hda_format = 0; |
| 2401 | unsigned int response; |
| 2402 | unsigned char stream_id = 0; |
| 2403 | struct dma_engine *dma_engine; |
| 2404 | unsigned int dma_chan; |
| 2405 | unsigned int port_map_mask; |
| 2406 | |
| 2407 | if (fls_data == NULL) |
| 2408 | return -EINVAL; |
| 2409 | |
| 2410 | dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL); |
Takashi Iwai | 063bca0 | 2012-09-21 13:44:34 +0200 | [diff] [blame] | 2411 | if (!dma_engine) |
| 2412 | return -ENOMEM; |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2413 | |
| 2414 | dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL); |
| 2415 | if (!dma_engine->dmab) { |
| 2416 | status = -ENOMEM; |
| 2417 | goto exit; |
| 2418 | } |
| 2419 | |
| 2420 | dma_engine->codec = codec; |
Ian Minett | e97249d | 2012-09-20 20:29:21 -0700 | [diff] [blame] | 2421 | dma_convert_to_hda_format(sample_rate, channels, &hda_format); |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2422 | dma_engine->m_converter_format = hda_format; |
| 2423 | dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : |
| 2424 | DSP_DMA_WRITE_BUFLEN_INIT) * 2; |
| 2425 | |
| 2426 | dma_chan = 0; |
| 2427 | |
| 2428 | status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, |
| 2429 | hda_format, &response); |
| 2430 | |
| 2431 | if (status < 0) { |
| 2432 | snd_printdd(KERN_ERR "set converter format fail"); |
| 2433 | goto exit; |
| 2434 | } |
| 2435 | |
| 2436 | status = snd_hda_codec_load_dsp_prepare(codec, |
| 2437 | dma_engine->m_converter_format, |
| 2438 | dma_engine->buf_size, |
| 2439 | dma_engine->dmab); |
| 2440 | if (status < 0) |
| 2441 | goto exit; |
| 2442 | spec->dsp_stream_id = status; |
| 2443 | |
| 2444 | if (ovly) { |
| 2445 | status = dspio_alloc_dma_chan(codec, &dma_chan); |
| 2446 | if (status < 0) { |
| 2447 | snd_printdd(KERN_ERR "alloc dmachan fail"); |
| 2448 | dma_chan = (unsigned int)INVALID_DMA_CHANNEL; |
| 2449 | goto exit; |
| 2450 | } |
| 2451 | } |
| 2452 | |
| 2453 | port_map_mask = 0; |
| 2454 | status = dsp_allocate_ports_format(codec, hda_format, |
| 2455 | &port_map_mask); |
| 2456 | if (status < 0) { |
| 2457 | snd_printdd(KERN_ERR "alloc ports fail"); |
| 2458 | goto exit; |
| 2459 | } |
| 2460 | |
| 2461 | stream_id = dma_get_stream_id(dma_engine); |
| 2462 | status = codec_set_converter_stream_channel(codec, |
| 2463 | WIDGET_CHIP_CTRL, stream_id, 0, &response); |
| 2464 | if (status < 0) { |
| 2465 | snd_printdd(KERN_ERR "set stream chan fail"); |
| 2466 | goto exit; |
| 2467 | } |
| 2468 | |
| 2469 | while ((fls_data != NULL) && !is_last(fls_data)) { |
| 2470 | if (!is_valid(fls_data)) { |
| 2471 | snd_printdd(KERN_ERR "FLS check fail"); |
| 2472 | status = -EINVAL; |
| 2473 | goto exit; |
| 2474 | } |
| 2475 | status = dspxfr_one_seg(codec, fls_data, reloc, |
| 2476 | dma_engine, dma_chan, |
| 2477 | port_map_mask, ovly); |
| 2478 | if (status < 0) |
| 2479 | break; |
| 2480 | |
| 2481 | if (is_hci_prog_list_seg(fls_data)) |
| 2482 | fls_data = get_next_seg_ptr(fls_data); |
| 2483 | |
| 2484 | if ((fls_data != NULL) && !is_last(fls_data)) |
| 2485 | fls_data = get_next_seg_ptr(fls_data); |
| 2486 | } |
| 2487 | |
| 2488 | if (port_map_mask != 0) |
| 2489 | status = dsp_free_ports(codec); |
| 2490 | |
| 2491 | if (status < 0) |
| 2492 | goto exit; |
| 2493 | |
| 2494 | status = codec_set_converter_stream_channel(codec, |
| 2495 | WIDGET_CHIP_CTRL, 0, 0, &response); |
| 2496 | |
| 2497 | exit: |
| 2498 | if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) |
| 2499 | dspio_free_dma_chan(codec, dma_chan); |
| 2500 | |
| 2501 | if (dma_engine->dmab) |
| 2502 | snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); |
| 2503 | kfree(dma_engine->dmab); |
| 2504 | kfree(dma_engine); |
| 2505 | |
| 2506 | return status; |
| 2507 | } |
| 2508 | |
| 2509 | /* |
| 2510 | * CA0132 DSP download stuffs. |
| 2511 | */ |
| 2512 | static void dspload_post_setup(struct hda_codec *codec) |
| 2513 | { |
| 2514 | snd_printdd(KERN_INFO "---- dspload_post_setup ------"); |
| 2515 | |
| 2516 | /*set DSP speaker to 2.0 configuration*/ |
| 2517 | chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); |
| 2518 | chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); |
| 2519 | |
| 2520 | /*update write pointer*/ |
| 2521 | chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); |
| 2522 | } |
| 2523 | |
Ian Minett | d5c21b8 | 2012-09-20 20:29:18 -0700 | [diff] [blame] | 2524 | /** |
| 2525 | * Download DSP from a DSP Image Fast Load structure. This structure is a |
| 2526 | * linear, non-constant sized element array of structures, each of which |
| 2527 | * contain the count of the data to be loaded, the data itself, and the |
| 2528 | * corresponding starting chip address of the starting data location. |
| 2529 | * |
| 2530 | * @codec: the HDA codec |
| 2531 | * @fls: pointer to a fast load image |
| 2532 | * @ovly: TRUE if overlay format is required |
| 2533 | * @reloc: Relocation address for loading single-segment overlays, or 0 for |
| 2534 | * no relocation |
| 2535 | * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE |
| 2536 | * @router_chans: number of audio router channels to be allocated (0 means use |
| 2537 | * internal defaults; max is 32) |
| 2538 | * |
| 2539 | * Returns zero or a negative error code. |
| 2540 | */ |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2541 | static int dspload_image(struct hda_codec *codec, |
| 2542 | const struct dsp_image_seg *fls, |
| 2543 | bool ovly, |
| 2544 | unsigned int reloc, |
| 2545 | bool autostart, |
| 2546 | int router_chans) |
| 2547 | { |
| 2548 | int status = 0; |
Ian Minett | e97249d | 2012-09-20 20:29:21 -0700 | [diff] [blame] | 2549 | unsigned int sample_rate; |
| 2550 | unsigned short channels; |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2551 | |
| 2552 | snd_printdd(KERN_INFO "---- dspload_image begin ------"); |
| 2553 | if (router_chans == 0) { |
| 2554 | if (!ovly) |
| 2555 | router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; |
| 2556 | else |
| 2557 | router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; |
| 2558 | } |
| 2559 | |
Ian Minett | e97249d | 2012-09-20 20:29:21 -0700 | [diff] [blame] | 2560 | sample_rate = 48000; |
| 2561 | channels = (unsigned short)router_chans; |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2562 | |
Ian Minett | e97249d | 2012-09-20 20:29:21 -0700 | [diff] [blame] | 2563 | while (channels > 16) { |
| 2564 | sample_rate *= 2; |
| 2565 | channels /= 2; |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2566 | } |
| 2567 | |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2568 | do { |
| 2569 | snd_printdd(KERN_INFO "Ready to program DMA"); |
| 2570 | if (!ovly) |
| 2571 | status = dsp_reset(codec); |
| 2572 | |
| 2573 | if (status < 0) |
| 2574 | break; |
| 2575 | |
| 2576 | snd_printdd(KERN_INFO "dsp_reset() complete"); |
Ian Minett | e97249d | 2012-09-20 20:29:21 -0700 | [diff] [blame] | 2577 | status = dspxfr_image(codec, fls, reloc, sample_rate, channels, |
| 2578 | ovly); |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2579 | |
| 2580 | if (status < 0) |
| 2581 | break; |
| 2582 | |
| 2583 | snd_printdd(KERN_INFO "dspxfr_image() complete"); |
| 2584 | if (autostart && !ovly) { |
| 2585 | dspload_post_setup(codec); |
| 2586 | status = dsp_set_run_state(codec); |
| 2587 | } |
| 2588 | |
| 2589 | snd_printdd(KERN_INFO "LOAD FINISHED"); |
| 2590 | } while (0); |
| 2591 | |
| 2592 | return status; |
| 2593 | } |
| 2594 | |
Ian Minett | c3b4eea2 | 2012-09-20 20:29:17 -0700 | [diff] [blame] | 2595 | static const struct firmware *fw_efx; |
| 2596 | |
| 2597 | static int request_firmware_cached(const struct firmware **firmware_p, |
| 2598 | const char *name, struct device *device) |
| 2599 | { |
| 2600 | if (*firmware_p) |
| 2601 | return 0; /* already loaded */ |
| 2602 | return request_firmware(firmware_p, name, device); |
| 2603 | } |
| 2604 | |
| 2605 | static void release_cached_firmware(void) |
| 2606 | { |
| 2607 | if (fw_efx) { |
| 2608 | release_firmware(fw_efx); |
| 2609 | fw_efx = NULL; |
| 2610 | } |
| 2611 | } |
| 2612 | |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 2613 | static bool dspload_is_loaded(struct hda_codec *codec) |
| 2614 | { |
| 2615 | unsigned int data = 0; |
| 2616 | int status = 0; |
| 2617 | |
| 2618 | status = chipio_read(codec, 0x40004, &data); |
| 2619 | if ((status < 0) || (data != 1)) |
| 2620 | return false; |
| 2621 | |
| 2622 | return true; |
| 2623 | } |
| 2624 | |
| 2625 | static bool dspload_wait_loaded(struct hda_codec *codec) |
| 2626 | { |
| 2627 | int retry = 100; |
| 2628 | |
| 2629 | do { |
| 2630 | msleep(20); |
| 2631 | if (dspload_is_loaded(codec)) { |
| 2632 | pr_info("ca0132 DOWNLOAD OK :-) DSP IS RUNNING.\n"); |
| 2633 | return true; |
| 2634 | } |
| 2635 | } while (--retry); |
| 2636 | |
| 2637 | pr_err("ca0132 DOWNLOAD FAILED!!! DSP IS NOT RUNNING.\n"); |
| 2638 | return false; |
| 2639 | } |
| 2640 | |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 2641 | /* |
| 2642 | * Controls stuffs. |
| 2643 | */ |
Ian Minett | ef6b2ea | 2012-12-20 18:53:33 -0800 | [diff] [blame] | 2644 | |
| 2645 | /* |
| 2646 | * Mixer controls helpers. |
| 2647 | */ |
| 2648 | #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ |
| 2649 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
| 2650 | .name = xname, \ |
| 2651 | .subdevice = HDA_SUBDEV_AMP_FLAG, \ |
| 2652 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ |
| 2653 | SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ |
| 2654 | SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ |
| 2655 | .info = ca0132_volume_info, \ |
| 2656 | .get = ca0132_volume_get, \ |
| 2657 | .put = ca0132_volume_put, \ |
| 2658 | .tlv = { .c = ca0132_volume_tlv }, \ |
| 2659 | .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } |
| 2660 | |
| 2661 | #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ |
| 2662 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
| 2663 | .name = xname, \ |
| 2664 | .subdevice = HDA_SUBDEV_AMP_FLAG, \ |
| 2665 | .info = snd_hda_mixer_amp_switch_info, \ |
| 2666 | .get = ca0132_switch_get, \ |
| 2667 | .put = ca0132_switch_put, \ |
| 2668 | .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } |
| 2669 | |
| 2670 | /* stereo */ |
| 2671 | #define CA0132_CODEC_VOL(xname, nid, dir) \ |
| 2672 | CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) |
| 2673 | #define CA0132_CODEC_MUTE(xname, nid, dir) \ |
| 2674 | CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) |
| 2675 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2676 | /* |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2677 | * PCM callbacks |
| 2678 | */ |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 2679 | static int ca0132_playback_pcm_open(struct hda_pcm_stream *hinfo, |
| 2680 | struct hda_codec *codec, |
| 2681 | struct snd_pcm_substream *substream) |
| 2682 | { |
| 2683 | struct ca0132_spec *spec = codec->spec; |
| 2684 | return snd_hda_multi_out_analog_open(codec, &spec->multiout, substream, |
| 2685 | hinfo); |
| 2686 | } |
| 2687 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2688 | static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, |
| 2689 | struct hda_codec *codec, |
| 2690 | unsigned int stream_tag, |
| 2691 | unsigned int format, |
| 2692 | struct snd_pcm_substream *substream) |
| 2693 | { |
| 2694 | struct ca0132_spec *spec = codec->spec; |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 2695 | return snd_hda_multi_out_analog_prepare(codec, &spec->multiout, |
| 2696 | stream_tag, format, substream); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2697 | } |
| 2698 | |
| 2699 | static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, |
| 2700 | struct hda_codec *codec, |
| 2701 | struct snd_pcm_substream *substream) |
| 2702 | { |
| 2703 | struct ca0132_spec *spec = codec->spec; |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 2704 | return snd_hda_multi_out_analog_cleanup(codec, &spec->multiout); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2705 | } |
| 2706 | |
| 2707 | /* |
| 2708 | * Digital out |
| 2709 | */ |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 2710 | static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, |
| 2711 | struct hda_codec *codec, |
| 2712 | struct snd_pcm_substream *substream) |
| 2713 | { |
| 2714 | struct ca0132_spec *spec = codec->spec; |
| 2715 | return snd_hda_multi_out_dig_open(codec, &spec->multiout); |
| 2716 | } |
| 2717 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2718 | static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, |
| 2719 | struct hda_codec *codec, |
| 2720 | unsigned int stream_tag, |
| 2721 | unsigned int format, |
| 2722 | struct snd_pcm_substream *substream) |
| 2723 | { |
| 2724 | struct ca0132_spec *spec = codec->spec; |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 2725 | return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, |
| 2726 | stream_tag, format, substream); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2727 | } |
| 2728 | |
| 2729 | static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, |
| 2730 | struct hda_codec *codec, |
| 2731 | struct snd_pcm_substream *substream) |
| 2732 | { |
| 2733 | struct ca0132_spec *spec = codec->spec; |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 2734 | return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2735 | } |
| 2736 | |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 2737 | static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, |
| 2738 | struct hda_codec *codec, |
| 2739 | struct snd_pcm_substream *substream) |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2740 | { |
| 2741 | struct ca0132_spec *spec = codec->spec; |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 2742 | return snd_hda_multi_out_dig_close(codec, &spec->multiout); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 2743 | } |
| 2744 | |
| 2745 | /* |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 2746 | * Select the active output. |
| 2747 | * If autodetect is enabled, output will be selected based on jack detection. |
| 2748 | * If jack inserted, headphone will be selected, else built-in speakers |
| 2749 | * If autodetect is disabled, output will be selected based on selection. |
| 2750 | */ |
| 2751 | static int ca0132_select_out(struct hda_codec *codec) |
| 2752 | { |
| 2753 | struct ca0132_spec *spec = codec->spec; |
| 2754 | unsigned int pin_ctl; |
| 2755 | int jack_present; |
| 2756 | int auto_jack; |
| 2757 | unsigned int tmp; |
| 2758 | int err; |
| 2759 | |
| 2760 | snd_printdd(KERN_INFO "ca0132_select_out\n"); |
| 2761 | |
| 2762 | snd_hda_power_up(codec); |
| 2763 | |
| 2764 | auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; |
| 2765 | |
| 2766 | if (auto_jack) |
| 2767 | jack_present = snd_hda_jack_detect(codec, spec->out_pins[1]); |
| 2768 | else |
| 2769 | jack_present = |
| 2770 | spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; |
| 2771 | |
| 2772 | if (jack_present) |
| 2773 | spec->cur_out_type = HEADPHONE_OUT; |
| 2774 | else |
| 2775 | spec->cur_out_type = SPEAKER_OUT; |
| 2776 | |
| 2777 | if (spec->cur_out_type == SPEAKER_OUT) { |
| 2778 | snd_printdd(KERN_INFO "ca0132_select_out speaker\n"); |
| 2779 | /*speaker out config*/ |
| 2780 | tmp = FLOAT_ONE; |
| 2781 | err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); |
| 2782 | if (err < 0) |
| 2783 | goto exit; |
| 2784 | /*enable speaker EQ*/ |
| 2785 | tmp = FLOAT_ONE; |
| 2786 | err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); |
| 2787 | if (err < 0) |
| 2788 | goto exit; |
| 2789 | |
| 2790 | /* Setup EAPD */ |
| 2791 | snd_hda_codec_write(codec, spec->out_pins[1], 0, |
| 2792 | VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); |
| 2793 | snd_hda_codec_write(codec, spec->out_pins[0], 0, |
| 2794 | AC_VERB_SET_EAPD_BTLENABLE, 0x00); |
| 2795 | snd_hda_codec_write(codec, spec->out_pins[0], 0, |
| 2796 | VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); |
| 2797 | snd_hda_codec_write(codec, spec->out_pins[0], 0, |
| 2798 | AC_VERB_SET_EAPD_BTLENABLE, 0x02); |
| 2799 | |
| 2800 | /* disable headphone node */ |
| 2801 | pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, |
| 2802 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); |
| 2803 | snd_hda_codec_write(codec, spec->out_pins[1], 0, |
| 2804 | AC_VERB_SET_PIN_WIDGET_CONTROL, |
| 2805 | pin_ctl & 0xBF); |
| 2806 | /* enable speaker node */ |
| 2807 | pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, |
| 2808 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); |
| 2809 | snd_hda_codec_write(codec, spec->out_pins[0], 0, |
| 2810 | AC_VERB_SET_PIN_WIDGET_CONTROL, |
| 2811 | pin_ctl | 0x40); |
| 2812 | } else { |
| 2813 | snd_printdd(KERN_INFO "ca0132_select_out hp\n"); |
| 2814 | /*headphone out config*/ |
| 2815 | tmp = FLOAT_ZERO; |
| 2816 | err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); |
| 2817 | if (err < 0) |
| 2818 | goto exit; |
| 2819 | /*disable speaker EQ*/ |
| 2820 | tmp = FLOAT_ZERO; |
| 2821 | err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); |
| 2822 | if (err < 0) |
| 2823 | goto exit; |
| 2824 | |
| 2825 | /* Setup EAPD */ |
| 2826 | snd_hda_codec_write(codec, spec->out_pins[0], 0, |
| 2827 | VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); |
| 2828 | snd_hda_codec_write(codec, spec->out_pins[0], 0, |
| 2829 | AC_VERB_SET_EAPD_BTLENABLE, 0x00); |
| 2830 | snd_hda_codec_write(codec, spec->out_pins[1], 0, |
| 2831 | VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); |
| 2832 | snd_hda_codec_write(codec, spec->out_pins[0], 0, |
| 2833 | AC_VERB_SET_EAPD_BTLENABLE, 0x02); |
| 2834 | |
| 2835 | /* disable speaker*/ |
| 2836 | pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, |
| 2837 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); |
| 2838 | snd_hda_codec_write(codec, spec->out_pins[0], 0, |
| 2839 | AC_VERB_SET_PIN_WIDGET_CONTROL, |
| 2840 | pin_ctl & 0xBF); |
| 2841 | /* enable headphone*/ |
| 2842 | pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, |
| 2843 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); |
| 2844 | snd_hda_codec_write(codec, spec->out_pins[1], 0, |
| 2845 | AC_VERB_SET_PIN_WIDGET_CONTROL, |
| 2846 | pin_ctl | 0x40); |
| 2847 | } |
| 2848 | |
| 2849 | exit: |
| 2850 | snd_hda_power_down(codec); |
| 2851 | |
| 2852 | return err < 0 ? err : 0; |
| 2853 | } |
| 2854 | |
| 2855 | static void ca0132_set_dmic(struct hda_codec *codec, int enable); |
| 2856 | static int ca0132_mic_boost_set(struct hda_codec *codec, long val); |
| 2857 | static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); |
| 2858 | |
| 2859 | /* |
| 2860 | * Select the active VIP source |
| 2861 | */ |
| 2862 | static int ca0132_set_vipsource(struct hda_codec *codec, int val) |
| 2863 | { |
| 2864 | struct ca0132_spec *spec = codec->spec; |
| 2865 | unsigned int tmp; |
| 2866 | |
| 2867 | if (!dspload_is_loaded(codec)) |
| 2868 | return 0; |
| 2869 | |
| 2870 | /* if CrystalVoice if off, vipsource should be 0 */ |
| 2871 | if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || |
| 2872 | (val == 0)) { |
| 2873 | chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); |
| 2874 | chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); |
| 2875 | chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); |
| 2876 | if (spec->cur_mic_type == DIGITAL_MIC) |
| 2877 | tmp = FLOAT_TWO; |
| 2878 | else |
| 2879 | tmp = FLOAT_ONE; |
| 2880 | dspio_set_uint_param(codec, 0x80, 0x00, tmp); |
| 2881 | tmp = FLOAT_ZERO; |
| 2882 | dspio_set_uint_param(codec, 0x80, 0x05, tmp); |
| 2883 | } else { |
| 2884 | chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); |
| 2885 | chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); |
| 2886 | if (spec->cur_mic_type == DIGITAL_MIC) |
| 2887 | tmp = FLOAT_TWO; |
| 2888 | else |
| 2889 | tmp = FLOAT_ONE; |
| 2890 | dspio_set_uint_param(codec, 0x80, 0x00, tmp); |
| 2891 | tmp = FLOAT_ONE; |
| 2892 | dspio_set_uint_param(codec, 0x80, 0x05, tmp); |
| 2893 | msleep(20); |
| 2894 | chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); |
| 2895 | } |
| 2896 | |
| 2897 | return 1; |
| 2898 | } |
| 2899 | |
| 2900 | /* |
| 2901 | * Select the active microphone. |
| 2902 | * If autodetect is enabled, mic will be selected based on jack detection. |
| 2903 | * If jack inserted, ext.mic will be selected, else built-in mic |
| 2904 | * If autodetect is disabled, mic will be selected based on selection. |
| 2905 | */ |
| 2906 | static int ca0132_select_mic(struct hda_codec *codec) |
| 2907 | { |
| 2908 | struct ca0132_spec *spec = codec->spec; |
| 2909 | int jack_present; |
| 2910 | int auto_jack; |
| 2911 | |
| 2912 | snd_printdd(KERN_INFO "ca0132_select_mic\n"); |
| 2913 | |
| 2914 | snd_hda_power_up(codec); |
| 2915 | |
| 2916 | auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; |
| 2917 | |
| 2918 | if (auto_jack) |
| 2919 | jack_present = snd_hda_jack_detect(codec, spec->input_pins[0]); |
| 2920 | else |
| 2921 | jack_present = |
| 2922 | spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; |
| 2923 | |
| 2924 | if (jack_present) |
| 2925 | spec->cur_mic_type = LINE_MIC_IN; |
| 2926 | else |
| 2927 | spec->cur_mic_type = DIGITAL_MIC; |
| 2928 | |
| 2929 | if (spec->cur_mic_type == DIGITAL_MIC) { |
| 2930 | /* enable digital Mic */ |
| 2931 | chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); |
| 2932 | ca0132_set_dmic(codec, 1); |
| 2933 | ca0132_mic_boost_set(codec, 0); |
| 2934 | /* set voice focus */ |
| 2935 | ca0132_effects_set(codec, VOICE_FOCUS, |
| 2936 | spec->effects_switch |
| 2937 | [VOICE_FOCUS - EFFECT_START_NID]); |
| 2938 | } else { |
| 2939 | /* disable digital Mic */ |
| 2940 | chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); |
| 2941 | ca0132_set_dmic(codec, 0); |
| 2942 | ca0132_mic_boost_set(codec, spec->cur_mic_boost); |
| 2943 | /* disable voice focus */ |
| 2944 | ca0132_effects_set(codec, VOICE_FOCUS, 0); |
| 2945 | } |
| 2946 | |
| 2947 | snd_hda_power_down(codec); |
| 2948 | |
| 2949 | return 0; |
| 2950 | } |
| 2951 | |
| 2952 | /* |
| 2953 | * Set the effects parameters |
| 2954 | */ |
| 2955 | static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) |
| 2956 | { |
| 2957 | struct ca0132_spec *spec = codec->spec; |
| 2958 | unsigned int on; |
| 2959 | int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; |
| 2960 | int err = 0; |
| 2961 | int idx = nid - EFFECT_START_NID; |
| 2962 | |
| 2963 | if ((idx < 0) || (idx >= num_fx)) |
| 2964 | return 0; /* no changed */ |
| 2965 | |
| 2966 | /* for out effect, qualify with PE */ |
| 2967 | if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { |
| 2968 | /* if PE if off, turn off out effects. */ |
| 2969 | if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) |
| 2970 | val = 0; |
| 2971 | } |
| 2972 | |
| 2973 | /* for in effect, qualify with CrystalVoice */ |
| 2974 | if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { |
| 2975 | /* if CrystalVoice if off, turn off in effects. */ |
| 2976 | if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) |
| 2977 | val = 0; |
| 2978 | |
| 2979 | /* Voice Focus applies to 2-ch Mic, Digital Mic */ |
| 2980 | if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) |
| 2981 | val = 0; |
| 2982 | } |
| 2983 | |
| 2984 | snd_printdd(KERN_INFO, "ca0132_effect_set: nid=0x%x, val=%ld\n", |
| 2985 | nid, val); |
| 2986 | |
| 2987 | on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; |
| 2988 | err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, |
| 2989 | ca0132_effects[idx].reqs[0], on); |
| 2990 | |
| 2991 | if (err < 0) |
| 2992 | return 0; /* no changed */ |
| 2993 | |
| 2994 | return 1; |
| 2995 | } |
| 2996 | |
| 2997 | /* Check if Mic1 is streaming, if so, stop streaming */ |
| 2998 | static int stop_mic1(struct hda_codec *codec) |
| 2999 | { |
| 3000 | struct ca0132_spec *spec = codec->spec; |
| 3001 | unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, |
| 3002 | AC_VERB_GET_CONV, 0); |
| 3003 | if (oldval != 0) |
| 3004 | snd_hda_codec_write(codec, spec->adcs[0], 0, |
| 3005 | AC_VERB_SET_CHANNEL_STREAMID, |
| 3006 | 0); |
| 3007 | return oldval; |
| 3008 | } |
| 3009 | |
| 3010 | /* Resume Mic1 streaming if it was stopped. */ |
| 3011 | static void resume_mic1(struct hda_codec *codec, unsigned int oldval) |
| 3012 | { |
| 3013 | struct ca0132_spec *spec = codec->spec; |
| 3014 | /* Restore the previous stream and channel */ |
| 3015 | if (oldval != 0) |
| 3016 | snd_hda_codec_write(codec, spec->adcs[0], 0, |
| 3017 | AC_VERB_SET_CHANNEL_STREAMID, |
| 3018 | oldval); |
| 3019 | } |
| 3020 | |
| 3021 | /* |
| 3022 | * Set Mic Boost |
| 3023 | */ |
| 3024 | static int ca0132_mic_boost_set(struct hda_codec *codec, long val) |
| 3025 | { |
| 3026 | struct ca0132_spec *spec = codec->spec; |
| 3027 | int ret = 0; |
| 3028 | |
| 3029 | if (val) /* on */ |
| 3030 | ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, |
| 3031 | HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); |
| 3032 | else /* off */ |
| 3033 | ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, |
| 3034 | HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); |
| 3035 | |
| 3036 | return ret; |
| 3037 | } |
| 3038 | |
| 3039 | /* |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3040 | */ |
| 3041 | static struct hda_pcm_stream ca0132_pcm_analog_playback = { |
| 3042 | .substreams = 1, |
| 3043 | .channels_min = 2, |
| 3044 | .channels_max = 2, |
| 3045 | .ops = { |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 3046 | .open = ca0132_playback_pcm_open, |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3047 | .prepare = ca0132_playback_pcm_prepare, |
| 3048 | .cleanup = ca0132_playback_pcm_cleanup |
| 3049 | }, |
| 3050 | }; |
| 3051 | |
| 3052 | static struct hda_pcm_stream ca0132_pcm_analog_capture = { |
| 3053 | .substreams = 1, |
| 3054 | .channels_min = 2, |
| 3055 | .channels_max = 2, |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3056 | }; |
| 3057 | |
| 3058 | static struct hda_pcm_stream ca0132_pcm_digital_playback = { |
| 3059 | .substreams = 1, |
| 3060 | .channels_min = 2, |
| 3061 | .channels_max = 2, |
| 3062 | .ops = { |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 3063 | .open = ca0132_dig_playback_pcm_open, |
| 3064 | .close = ca0132_dig_playback_pcm_close, |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3065 | .prepare = ca0132_dig_playback_pcm_prepare, |
| 3066 | .cleanup = ca0132_dig_playback_pcm_cleanup |
| 3067 | }, |
| 3068 | }; |
| 3069 | |
| 3070 | static struct hda_pcm_stream ca0132_pcm_digital_capture = { |
| 3071 | .substreams = 1, |
| 3072 | .channels_min = 2, |
| 3073 | .channels_max = 2, |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3074 | }; |
| 3075 | |
| 3076 | static int ca0132_build_pcms(struct hda_codec *codec) |
| 3077 | { |
| 3078 | struct ca0132_spec *spec = codec->spec; |
| 3079 | struct hda_pcm *info = spec->pcm_rec; |
| 3080 | |
| 3081 | codec->pcm_info = info; |
| 3082 | codec->num_pcms = 0; |
| 3083 | |
| 3084 | info->name = "CA0132 Analog"; |
| 3085 | info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; |
| 3086 | info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; |
| 3087 | info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = |
| 3088 | spec->multiout.max_channels; |
| 3089 | info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; |
| 3090 | info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = spec->num_inputs; |
| 3091 | info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; |
| 3092 | codec->num_pcms++; |
| 3093 | |
| 3094 | if (!spec->dig_out && !spec->dig_in) |
| 3095 | return 0; |
| 3096 | |
| 3097 | info++; |
| 3098 | info->name = "CA0132 Digital"; |
| 3099 | info->pcm_type = HDA_PCM_TYPE_SPDIF; |
| 3100 | if (spec->dig_out) { |
| 3101 | info->stream[SNDRV_PCM_STREAM_PLAYBACK] = |
| 3102 | ca0132_pcm_digital_playback; |
| 3103 | info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; |
| 3104 | } |
| 3105 | if (spec->dig_in) { |
| 3106 | info->stream[SNDRV_PCM_STREAM_CAPTURE] = |
| 3107 | ca0132_pcm_digital_capture; |
| 3108 | info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; |
| 3109 | } |
| 3110 | codec->num_pcms++; |
| 3111 | |
| 3112 | return 0; |
| 3113 | } |
| 3114 | |
| 3115 | #define REG_CODEC_MUTE 0x18b014 |
| 3116 | #define REG_CODEC_HP_VOL_L 0x18b070 |
| 3117 | #define REG_CODEC_HP_VOL_R 0x18b074 |
| 3118 | |
| 3119 | static int ca0132_hp_switch_get(struct snd_kcontrol *kcontrol, |
| 3120 | struct snd_ctl_elem_value *ucontrol) |
| 3121 | { |
| 3122 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); |
| 3123 | struct ca0132_spec *spec = codec->spec; |
| 3124 | long *valp = ucontrol->value.integer.value; |
| 3125 | |
| 3126 | *valp = spec->curr_hp_switch; |
| 3127 | return 0; |
| 3128 | } |
| 3129 | |
| 3130 | static int ca0132_hp_switch_put(struct snd_kcontrol *kcontrol, |
| 3131 | struct snd_ctl_elem_value *ucontrol) |
| 3132 | { |
| 3133 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); |
| 3134 | struct ca0132_spec *spec = codec->spec; |
| 3135 | long *valp = ucontrol->value.integer.value; |
| 3136 | unsigned int data; |
| 3137 | int err; |
| 3138 | |
| 3139 | /* any change? */ |
| 3140 | if (spec->curr_hp_switch == *valp) |
| 3141 | return 0; |
| 3142 | |
| 3143 | snd_hda_power_up(codec); |
| 3144 | |
| 3145 | err = chipio_read(codec, REG_CODEC_MUTE, &data); |
| 3146 | if (err < 0) |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 3147 | goto exit; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3148 | |
| 3149 | /* *valp 0 is mute, 1 is unmute */ |
| 3150 | data = (data & 0x7f) | (*valp ? 0 : 0x80); |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 3151 | err = chipio_write(codec, REG_CODEC_MUTE, data); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3152 | if (err < 0) |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 3153 | goto exit; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3154 | |
| 3155 | spec->curr_hp_switch = *valp; |
| 3156 | |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 3157 | exit: |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3158 | snd_hda_power_down(codec); |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 3159 | return err < 0 ? err : 1; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3160 | } |
| 3161 | |
| 3162 | static int ca0132_speaker_switch_get(struct snd_kcontrol *kcontrol, |
| 3163 | struct snd_ctl_elem_value *ucontrol) |
| 3164 | { |
| 3165 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); |
| 3166 | struct ca0132_spec *spec = codec->spec; |
| 3167 | long *valp = ucontrol->value.integer.value; |
| 3168 | |
| 3169 | *valp = spec->curr_speaker_switch; |
| 3170 | return 0; |
| 3171 | } |
| 3172 | |
| 3173 | static int ca0132_speaker_switch_put(struct snd_kcontrol *kcontrol, |
| 3174 | struct snd_ctl_elem_value *ucontrol) |
| 3175 | { |
| 3176 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); |
| 3177 | struct ca0132_spec *spec = codec->spec; |
| 3178 | long *valp = ucontrol->value.integer.value; |
| 3179 | unsigned int data; |
| 3180 | int err; |
| 3181 | |
| 3182 | /* any change? */ |
| 3183 | if (spec->curr_speaker_switch == *valp) |
| 3184 | return 0; |
| 3185 | |
| 3186 | snd_hda_power_up(codec); |
| 3187 | |
| 3188 | err = chipio_read(codec, REG_CODEC_MUTE, &data); |
| 3189 | if (err < 0) |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 3190 | goto exit; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3191 | |
| 3192 | /* *valp 0 is mute, 1 is unmute */ |
| 3193 | data = (data & 0xef) | (*valp ? 0 : 0x10); |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 3194 | err = chipio_write(codec, REG_CODEC_MUTE, data); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3195 | if (err < 0) |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 3196 | goto exit; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3197 | |
| 3198 | spec->curr_speaker_switch = *valp; |
| 3199 | |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 3200 | exit: |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3201 | snd_hda_power_down(codec); |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 3202 | return err < 0 ? err : 1; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3203 | } |
| 3204 | |
| 3205 | static int ca0132_hp_volume_get(struct snd_kcontrol *kcontrol, |
| 3206 | struct snd_ctl_elem_value *ucontrol) |
| 3207 | { |
| 3208 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); |
| 3209 | struct ca0132_spec *spec = codec->spec; |
| 3210 | long *valp = ucontrol->value.integer.value; |
| 3211 | |
| 3212 | *valp++ = spec->curr_hp_volume[0]; |
| 3213 | *valp = spec->curr_hp_volume[1]; |
| 3214 | return 0; |
| 3215 | } |
| 3216 | |
| 3217 | static int ca0132_hp_volume_put(struct snd_kcontrol *kcontrol, |
| 3218 | struct snd_ctl_elem_value *ucontrol) |
| 3219 | { |
| 3220 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); |
| 3221 | struct ca0132_spec *spec = codec->spec; |
| 3222 | long *valp = ucontrol->value.integer.value; |
| 3223 | long left_vol, right_vol; |
| 3224 | unsigned int data; |
| 3225 | int val; |
| 3226 | int err; |
| 3227 | |
| 3228 | left_vol = *valp++; |
| 3229 | right_vol = *valp; |
| 3230 | |
| 3231 | /* any change? */ |
| 3232 | if ((spec->curr_hp_volume[0] == left_vol) && |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 3233 | (spec->curr_hp_volume[1] == right_vol)) |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3234 | return 0; |
| 3235 | |
| 3236 | snd_hda_power_up(codec); |
| 3237 | |
| 3238 | err = chipio_read(codec, REG_CODEC_HP_VOL_L, &data); |
| 3239 | if (err < 0) |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 3240 | goto exit; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3241 | |
| 3242 | val = 31 - left_vol; |
| 3243 | data = (data & 0xe0) | val; |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 3244 | err = chipio_write(codec, REG_CODEC_HP_VOL_L, data); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3245 | if (err < 0) |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 3246 | goto exit; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3247 | |
| 3248 | val = 31 - right_vol; |
| 3249 | data = (data & 0xe0) | val; |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 3250 | err = chipio_write(codec, REG_CODEC_HP_VOL_R, data); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3251 | if (err < 0) |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 3252 | goto exit; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3253 | |
| 3254 | spec->curr_hp_volume[0] = left_vol; |
| 3255 | spec->curr_hp_volume[1] = right_vol; |
| 3256 | |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 3257 | exit: |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3258 | snd_hda_power_down(codec); |
Takashi Iwai | b97f6bf | 2012-02-07 11:00:53 +0100 | [diff] [blame] | 3259 | return err < 0 ? err : 1; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3260 | } |
| 3261 | |
| 3262 | static int add_hp_switch(struct hda_codec *codec, hda_nid_t nid) |
| 3263 | { |
| 3264 | struct snd_kcontrol_new knew = |
| 3265 | HDA_CODEC_MUTE_MONO("Headphone Playback Switch", |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 3266 | nid, 1, 0, HDA_OUTPUT); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3267 | knew.get = ca0132_hp_switch_get; |
| 3268 | knew.put = ca0132_hp_switch_put; |
| 3269 | return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); |
| 3270 | } |
| 3271 | |
| 3272 | static int add_hp_volume(struct hda_codec *codec, hda_nid_t nid) |
| 3273 | { |
| 3274 | struct snd_kcontrol_new knew = |
| 3275 | HDA_CODEC_VOLUME_MONO("Headphone Playback Volume", |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 3276 | nid, 3, 0, HDA_OUTPUT); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3277 | knew.get = ca0132_hp_volume_get; |
| 3278 | knew.put = ca0132_hp_volume_put; |
| 3279 | return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); |
| 3280 | } |
| 3281 | |
| 3282 | static int add_speaker_switch(struct hda_codec *codec, hda_nid_t nid) |
| 3283 | { |
| 3284 | struct snd_kcontrol_new knew = |
| 3285 | HDA_CODEC_MUTE_MONO("Speaker Playback Switch", |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 3286 | nid, 1, 0, HDA_OUTPUT); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3287 | knew.get = ca0132_speaker_switch_get; |
| 3288 | knew.put = ca0132_speaker_switch_put; |
| 3289 | return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); |
| 3290 | } |
| 3291 | |
| 3292 | static void ca0132_fix_hp_caps(struct hda_codec *codec) |
| 3293 | { |
| 3294 | struct ca0132_spec *spec = codec->spec; |
| 3295 | struct auto_pin_cfg *cfg = &spec->autocfg; |
| 3296 | unsigned int caps; |
| 3297 | |
| 3298 | /* set mute-capable, 1db step, 32 steps, ofs 6 */ |
| 3299 | caps = 0x80031f06; |
| 3300 | snd_hda_override_amp_caps(codec, cfg->hp_pins[0], HDA_OUTPUT, caps); |
| 3301 | } |
| 3302 | |
| 3303 | static int ca0132_build_controls(struct hda_codec *codec) |
| 3304 | { |
| 3305 | struct ca0132_spec *spec = codec->spec; |
| 3306 | struct auto_pin_cfg *cfg = &spec->autocfg; |
| 3307 | int i, err; |
| 3308 | |
| 3309 | if (spec->multiout.num_dacs) { |
| 3310 | err = add_speaker_switch(codec, spec->out_pins[0]); |
| 3311 | if (err < 0) |
| 3312 | return err; |
| 3313 | } |
| 3314 | |
| 3315 | if (cfg->hp_outs) { |
| 3316 | ca0132_fix_hp_caps(codec); |
| 3317 | err = add_hp_switch(codec, cfg->hp_pins[0]); |
| 3318 | if (err < 0) |
| 3319 | return err; |
| 3320 | err = add_hp_volume(codec, cfg->hp_pins[0]); |
| 3321 | if (err < 0) |
| 3322 | return err; |
| 3323 | } |
| 3324 | |
| 3325 | for (i = 0; i < spec->num_inputs; i++) { |
| 3326 | const char *label = spec->input_labels[i]; |
| 3327 | |
| 3328 | err = add_in_switch(codec, spec->adcs[i], label); |
| 3329 | if (err < 0) |
| 3330 | return err; |
| 3331 | err = add_in_volume(codec, spec->adcs[i], label); |
| 3332 | if (err < 0) |
| 3333 | return err; |
| 3334 | if (cfg->inputs[i].type == AUTO_PIN_MIC) { |
| 3335 | /* add Mic-Boost */ |
| 3336 | err = add_in_mono_volume(codec, spec->input_pins[i], |
| 3337 | "Mic Boost", 1); |
| 3338 | if (err < 0) |
| 3339 | return err; |
| 3340 | } |
| 3341 | } |
| 3342 | |
| 3343 | if (spec->dig_out) { |
Takashi Iwai | efb9f46 | 2011-06-21 07:44:51 +0200 | [diff] [blame] | 3344 | err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, |
| 3345 | spec->dig_out); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3346 | if (err < 0) |
| 3347 | return err; |
Takashi Iwai | 8e13fc1 | 2012-08-08 17:26:54 +0200 | [diff] [blame] | 3348 | err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3349 | if (err < 0) |
| 3350 | return err; |
Takashi Iwai | 8e13fc1 | 2012-08-08 17:26:54 +0200 | [diff] [blame] | 3351 | /* spec->multiout.share_spdif = 1; */ |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3352 | } |
| 3353 | |
| 3354 | if (spec->dig_in) { |
| 3355 | err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); |
| 3356 | if (err < 0) |
| 3357 | return err; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3358 | } |
| 3359 | return 0; |
| 3360 | } |
| 3361 | |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 3362 | static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) |
| 3363 | { |
| 3364 | unsigned int caps; |
| 3365 | |
| 3366 | caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? |
| 3367 | AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); |
| 3368 | snd_hda_override_amp_caps(codec, nid, dir, caps); |
| 3369 | } |
| 3370 | |
| 3371 | /* |
| 3372 | * Switch between Digital built-in mic and analog mic. |
| 3373 | */ |
| 3374 | static void ca0132_set_dmic(struct hda_codec *codec, int enable) |
| 3375 | { |
| 3376 | struct ca0132_spec *spec = codec->spec; |
| 3377 | unsigned int tmp; |
| 3378 | u8 val; |
| 3379 | unsigned int oldval; |
| 3380 | |
| 3381 | snd_printdd(KERN_INFO "ca0132_set_dmic: enable=%d\n", enable); |
| 3382 | |
| 3383 | oldval = stop_mic1(codec); |
| 3384 | ca0132_set_vipsource(codec, 0); |
| 3385 | if (enable) { |
| 3386 | /* set DMic input as 2-ch */ |
| 3387 | tmp = FLOAT_TWO; |
| 3388 | dspio_set_uint_param(codec, 0x80, 0x00, tmp); |
| 3389 | |
| 3390 | val = spec->dmic_ctl; |
| 3391 | val |= 0x80; |
| 3392 | snd_hda_codec_write(codec, spec->input_pins[0], 0, |
| 3393 | VENDOR_CHIPIO_DMIC_CTL_SET, val); |
| 3394 | |
| 3395 | if (!(spec->dmic_ctl & 0x20)) |
| 3396 | chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); |
| 3397 | } else { |
| 3398 | /* set AMic input as mono */ |
| 3399 | tmp = FLOAT_ONE; |
| 3400 | dspio_set_uint_param(codec, 0x80, 0x00, tmp); |
| 3401 | |
| 3402 | val = spec->dmic_ctl; |
| 3403 | /* clear bit7 and bit5 to disable dmic */ |
| 3404 | val &= 0x5f; |
| 3405 | snd_hda_codec_write(codec, spec->input_pins[0], 0, |
| 3406 | VENDOR_CHIPIO_DMIC_CTL_SET, val); |
| 3407 | |
| 3408 | if (!(spec->dmic_ctl & 0x20)) |
| 3409 | chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); |
| 3410 | } |
| 3411 | ca0132_set_vipsource(codec, 1); |
| 3412 | resume_mic1(codec, oldval); |
| 3413 | } |
| 3414 | |
| 3415 | /* |
| 3416 | * Initialization for Digital Mic. |
| 3417 | */ |
| 3418 | static void ca0132_init_dmic(struct hda_codec *codec) |
| 3419 | { |
| 3420 | struct ca0132_spec *spec = codec->spec; |
| 3421 | u8 val; |
| 3422 | |
| 3423 | /* Setup Digital Mic here, but don't enable. |
| 3424 | * Enable based on jack detect. |
| 3425 | */ |
| 3426 | |
| 3427 | /* MCLK uses MPIO1, set to enable. |
| 3428 | * Bit 2-0: MPIO select |
| 3429 | * Bit 3: set to disable |
| 3430 | * Bit 7-4: reserved |
| 3431 | */ |
| 3432 | val = 0x01; |
| 3433 | snd_hda_codec_write(codec, spec->input_pins[0], 0, |
| 3434 | VENDOR_CHIPIO_DMIC_MCLK_SET, val); |
| 3435 | |
| 3436 | /* Data1 uses MPIO3. Data2 not use |
| 3437 | * Bit 2-0: Data1 MPIO select |
| 3438 | * Bit 3: set disable Data1 |
| 3439 | * Bit 6-4: Data2 MPIO select |
| 3440 | * Bit 7: set disable Data2 |
| 3441 | */ |
| 3442 | val = 0x83; |
| 3443 | snd_hda_codec_write(codec, spec->input_pins[0], 0, |
| 3444 | VENDOR_CHIPIO_DMIC_PIN_SET, val); |
| 3445 | |
| 3446 | /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. |
| 3447 | * Bit 3-0: Channel mask |
| 3448 | * Bit 4: set for 48KHz, clear for 32KHz |
| 3449 | * Bit 5: mode |
| 3450 | * Bit 6: set to select Data2, clear for Data1 |
| 3451 | * Bit 7: set to enable DMic, clear for AMic |
| 3452 | */ |
| 3453 | val = 0x23; |
| 3454 | /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ |
| 3455 | spec->dmic_ctl = val; |
| 3456 | snd_hda_codec_write(codec, spec->input_pins[0], 0, |
| 3457 | VENDOR_CHIPIO_DMIC_CTL_SET, val); |
| 3458 | } |
| 3459 | |
| 3460 | /* |
| 3461 | * Initialization for Analog Mic 2 |
| 3462 | */ |
| 3463 | static void ca0132_init_analog_mic2(struct hda_codec *codec) |
| 3464 | { |
| 3465 | struct ca0132_spec *spec = codec->spec; |
| 3466 | |
| 3467 | mutex_lock(&spec->chipio_mutex); |
| 3468 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 3469 | VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); |
| 3470 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 3471 | VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); |
| 3472 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 3473 | VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); |
| 3474 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 3475 | VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D); |
| 3476 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 3477 | VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); |
| 3478 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 3479 | VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); |
| 3480 | mutex_unlock(&spec->chipio_mutex); |
| 3481 | } |
| 3482 | |
| 3483 | static void ca0132_refresh_widget_caps(struct hda_codec *codec) |
| 3484 | { |
| 3485 | struct ca0132_spec *spec = codec->spec; |
| 3486 | int i; |
| 3487 | hda_nid_t nid; |
| 3488 | |
| 3489 | snd_printdd(KERN_INFO "ca0132_refresh_widget_caps.\n"); |
| 3490 | nid = codec->start_nid; |
| 3491 | for (i = 0; i < codec->num_nodes; i++, nid++) |
| 3492 | codec->wcaps[i] = snd_hda_param_read(codec, nid, |
| 3493 | AC_PAR_AUDIO_WIDGET_CAP); |
| 3494 | |
| 3495 | for (i = 0; i < spec->multiout.num_dacs; i++) |
| 3496 | refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); |
| 3497 | |
| 3498 | for (i = 0; i < spec->num_outputs; i++) |
| 3499 | refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); |
| 3500 | |
| 3501 | for (i = 0; i < spec->num_inputs; i++) { |
| 3502 | refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); |
| 3503 | refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); |
| 3504 | } |
| 3505 | } |
| 3506 | |
| 3507 | /* |
| 3508 | * Setup default parameters for DSP |
| 3509 | */ |
| 3510 | static void ca0132_setup_defaults(struct hda_codec *codec) |
| 3511 | { |
| 3512 | unsigned int tmp; |
| 3513 | int num_fx; |
| 3514 | int idx, i; |
| 3515 | |
| 3516 | if (!dspload_is_loaded(codec)) |
| 3517 | return; |
| 3518 | |
| 3519 | /* out, in effects + voicefx */ |
| 3520 | num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; |
| 3521 | for (idx = 0; idx < num_fx; idx++) { |
| 3522 | for (i = 0; i <= ca0132_effects[idx].params; i++) { |
| 3523 | dspio_set_uint_param(codec, ca0132_effects[idx].mid, |
| 3524 | ca0132_effects[idx].reqs[i], |
| 3525 | ca0132_effects[idx].def_vals[i]); |
| 3526 | } |
| 3527 | } |
| 3528 | |
| 3529 | /*remove DSP headroom*/ |
| 3530 | tmp = FLOAT_ZERO; |
| 3531 | dspio_set_uint_param(codec, 0x96, 0x3C, tmp); |
| 3532 | |
| 3533 | /*set speaker EQ bypass attenuation*/ |
| 3534 | dspio_set_uint_param(codec, 0x8f, 0x01, tmp); |
| 3535 | |
| 3536 | /* set AMic1 and AMic2 as mono mic */ |
| 3537 | tmp = FLOAT_ONE; |
| 3538 | dspio_set_uint_param(codec, 0x80, 0x00, tmp); |
| 3539 | dspio_set_uint_param(codec, 0x80, 0x01, tmp); |
| 3540 | |
| 3541 | /* set AMic1 as CrystalVoice input */ |
| 3542 | tmp = FLOAT_ONE; |
| 3543 | dspio_set_uint_param(codec, 0x80, 0x05, tmp); |
| 3544 | |
| 3545 | /* set WUH source */ |
| 3546 | tmp = FLOAT_TWO; |
| 3547 | dspio_set_uint_param(codec, 0x31, 0x00, tmp); |
| 3548 | } |
| 3549 | |
| 3550 | /* |
| 3551 | * Initialization of flags in chip |
| 3552 | */ |
| 3553 | static void ca0132_init_flags(struct hda_codec *codec) |
| 3554 | { |
| 3555 | chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); |
| 3556 | chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0); |
| 3557 | chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0); |
| 3558 | chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); |
| 3559 | chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); |
| 3560 | chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); |
| 3561 | } |
| 3562 | |
| 3563 | /* |
| 3564 | * Initialization of parameters in chip |
| 3565 | */ |
| 3566 | static void ca0132_init_params(struct hda_codec *codec) |
| 3567 | { |
| 3568 | chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); |
| 3569 | chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); |
| 3570 | } |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3571 | |
| 3572 | static void ca0132_set_ct_ext(struct hda_codec *codec, int enable) |
| 3573 | { |
| 3574 | /* Set Creative extension */ |
| 3575 | snd_printdd("SET CREATIVE EXTENSION\n"); |
| 3576 | snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, |
| 3577 | VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, |
| 3578 | enable); |
| 3579 | msleep(20); |
| 3580 | } |
| 3581 | |
| 3582 | |
| 3583 | static void ca0132_config(struct hda_codec *codec) |
| 3584 | { |
| 3585 | struct ca0132_spec *spec = codec->spec; |
| 3586 | struct auto_pin_cfg *cfg = &spec->autocfg; |
| 3587 | |
Takashi Iwai | 27ebeb0 | 2012-08-08 17:20:18 +0200 | [diff] [blame] | 3588 | codec->no_sticky_stream = 1; |
| 3589 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3590 | /* line-outs */ |
| 3591 | cfg->line_outs = 1; |
| 3592 | cfg->line_out_pins[0] = 0x0b; /* front */ |
| 3593 | cfg->line_out_type = AUTO_PIN_LINE_OUT; |
| 3594 | |
| 3595 | spec->dacs[0] = 0x02; |
| 3596 | spec->out_pins[0] = 0x0b; |
| 3597 | spec->multiout.dac_nids = spec->dacs; |
| 3598 | spec->multiout.num_dacs = 1; |
| 3599 | spec->multiout.max_channels = 2; |
| 3600 | |
| 3601 | /* headphone */ |
| 3602 | cfg->hp_outs = 1; |
| 3603 | cfg->hp_pins[0] = 0x0f; |
| 3604 | |
| 3605 | spec->hp_dac = 0; |
| 3606 | spec->multiout.hp_nid = 0; |
| 3607 | |
| 3608 | /* inputs */ |
| 3609 | cfg->num_inputs = 2; /* Mic-in and line-in */ |
| 3610 | cfg->inputs[0].pin = 0x12; |
| 3611 | cfg->inputs[0].type = AUTO_PIN_MIC; |
| 3612 | cfg->inputs[1].pin = 0x11; |
| 3613 | cfg->inputs[1].type = AUTO_PIN_LINE_IN; |
| 3614 | |
| 3615 | /* Mic-in */ |
| 3616 | spec->input_pins[0] = 0x12; |
Takashi Iwai | 55cf87f | 2012-08-08 17:15:55 +0200 | [diff] [blame] | 3617 | spec->input_labels[0] = "Mic"; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3618 | spec->adcs[0] = 0x07; |
| 3619 | |
| 3620 | /* Line-In */ |
| 3621 | spec->input_pins[1] = 0x11; |
Takashi Iwai | 55cf87f | 2012-08-08 17:15:55 +0200 | [diff] [blame] | 3622 | spec->input_labels[1] = "Line"; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3623 | spec->adcs[1] = 0x08; |
| 3624 | spec->num_inputs = 2; |
Takashi Iwai | 8e13fc1 | 2012-08-08 17:26:54 +0200 | [diff] [blame] | 3625 | |
| 3626 | /* SPDIF I/O */ |
| 3627 | spec->dig_out = 0x05; |
| 3628 | spec->multiout.dig_out_nid = spec->dig_out; |
| 3629 | cfg->dig_out_pins[0] = 0x0c; |
| 3630 | cfg->dig_outs = 1; |
| 3631 | cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF; |
| 3632 | spec->dig_in = 0x09; |
| 3633 | cfg->dig_in_pin = 0x0e; |
| 3634 | cfg->dig_in_type = HDA_PCM_TYPE_SPDIF; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3635 | } |
| 3636 | |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 3637 | /* |
| 3638 | * Verbs tables. |
| 3639 | */ |
| 3640 | |
| 3641 | /* Sends before DSP download. */ |
| 3642 | static struct hda_verb ca0132_base_init_verbs[] = { |
| 3643 | /*enable ct extension*/ |
| 3644 | {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, |
| 3645 | /*enable DSP node unsol, needed for DSP download*/ |
| 3646 | {0x16, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_DSP}, |
| 3647 | {} |
| 3648 | }; |
| 3649 | |
| 3650 | /* Send at exit. */ |
| 3651 | static struct hda_verb ca0132_base_exit_verbs[] = { |
| 3652 | /*set afg to D3*/ |
| 3653 | {0x01, AC_VERB_SET_POWER_STATE, 0x03}, |
| 3654 | /*disable ct extension*/ |
| 3655 | {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, |
| 3656 | {} |
| 3657 | }; |
| 3658 | |
| 3659 | /* Other verbs tables. Sends after DSP download. */ |
| 3660 | static struct hda_verb ca0132_init_verbs0[] = { |
| 3661 | /* chip init verbs */ |
| 3662 | {0x15, 0x70D, 0xF0}, |
| 3663 | {0x15, 0x70E, 0xFE}, |
| 3664 | {0x15, 0x707, 0x75}, |
| 3665 | {0x15, 0x707, 0xD3}, |
| 3666 | {0x15, 0x707, 0x09}, |
| 3667 | {0x15, 0x707, 0x53}, |
| 3668 | {0x15, 0x707, 0xD4}, |
| 3669 | {0x15, 0x707, 0xEF}, |
| 3670 | {0x15, 0x707, 0x75}, |
| 3671 | {0x15, 0x707, 0xD3}, |
| 3672 | {0x15, 0x707, 0x09}, |
| 3673 | {0x15, 0x707, 0x02}, |
| 3674 | {0x15, 0x707, 0x37}, |
| 3675 | {0x15, 0x707, 0x78}, |
| 3676 | {0x15, 0x53C, 0xCE}, |
| 3677 | {0x15, 0x575, 0xC9}, |
| 3678 | {0x15, 0x53D, 0xCE}, |
| 3679 | {0x15, 0x5B7, 0xC9}, |
| 3680 | {0x15, 0x70D, 0xE8}, |
| 3681 | {0x15, 0x70E, 0xFE}, |
| 3682 | {0x15, 0x707, 0x02}, |
| 3683 | {0x15, 0x707, 0x68}, |
| 3684 | {0x15, 0x707, 0x62}, |
| 3685 | {0x15, 0x53A, 0xCE}, |
| 3686 | {0x15, 0x546, 0xC9}, |
| 3687 | {0x15, 0x53B, 0xCE}, |
| 3688 | {0x15, 0x5E8, 0xC9}, |
| 3689 | {0x15, 0x717, 0x0D}, |
| 3690 | {0x15, 0x718, 0x20}, |
| 3691 | {} |
| 3692 | }; |
| 3693 | |
| 3694 | static struct hda_verb ca0132_init_verbs1[] = { |
| 3695 | {0x10, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_HP}, |
| 3696 | {0x12, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_AMIC1}, |
| 3697 | /* config EAPD */ |
| 3698 | {0x0b, 0x78D, 0x00}, |
| 3699 | /*{0x0b, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/ |
| 3700 | /*{0x10, 0x78D, 0x02},*/ |
| 3701 | /*{0x10, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/ |
| 3702 | {} |
| 3703 | }; |
| 3704 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3705 | static void ca0132_init_chip(struct hda_codec *codec) |
| 3706 | { |
| 3707 | struct ca0132_spec *spec = codec->spec; |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 3708 | int num_fx; |
| 3709 | int i; |
| 3710 | unsigned int on; |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3711 | |
| 3712 | mutex_init(&spec->chipio_mutex); |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 3713 | |
| 3714 | spec->cur_out_type = SPEAKER_OUT; |
| 3715 | spec->cur_mic_type = DIGITAL_MIC; |
| 3716 | spec->cur_mic_boost = 0; |
| 3717 | |
| 3718 | for (i = 0; i < VNODES_COUNT; i++) { |
| 3719 | spec->vnode_lvol[i] = 0x5a; |
| 3720 | spec->vnode_rvol[i] = 0x5a; |
| 3721 | spec->vnode_lswitch[i] = 0; |
| 3722 | spec->vnode_rswitch[i] = 0; |
| 3723 | } |
| 3724 | |
| 3725 | /* |
| 3726 | * Default states for effects are in ca0132_effects[]. |
| 3727 | */ |
| 3728 | num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; |
| 3729 | for (i = 0; i < num_fx; i++) { |
| 3730 | on = (unsigned int)ca0132_effects[i].reqs[0]; |
| 3731 | spec->effects_switch[i] = on ? 1 : 0; |
| 3732 | } |
| 3733 | |
| 3734 | spec->voicefx_val = 0; |
| 3735 | spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; |
| 3736 | spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; |
| 3737 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3738 | } |
| 3739 | |
| 3740 | static void ca0132_exit_chip(struct hda_codec *codec) |
| 3741 | { |
| 3742 | /* put any chip cleanup stuffs here. */ |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 3743 | |
| 3744 | if (dspload_is_loaded(codec)) |
| 3745 | dsp_reset(codec); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3746 | } |
| 3747 | |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 3748 | static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) |
| 3749 | { |
| 3750 | chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); |
| 3751 | chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); |
| 3752 | chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); |
| 3753 | chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); |
| 3754 | chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); |
| 3755 | chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); |
| 3756 | |
| 3757 | chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); |
| 3758 | chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); |
| 3759 | chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); |
| 3760 | } |
| 3761 | |
| 3762 | static bool ca0132_download_dsp_images(struct hda_codec *codec) |
| 3763 | { |
| 3764 | bool dsp_loaded = false; |
| 3765 | const struct dsp_image_seg *dsp_os_image; |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 3766 | |
Ian Minett | c3b4eea2 | 2012-09-20 20:29:17 -0700 | [diff] [blame] | 3767 | if (request_firmware_cached(&fw_efx, EFX_FILE, |
| 3768 | codec->bus->card->dev) != 0) |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 3769 | return false; |
| 3770 | |
Ian Minett | c3b4eea2 | 2012-09-20 20:29:17 -0700 | [diff] [blame] | 3771 | dsp_os_image = (struct dsp_image_seg *)(fw_efx->data); |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 3772 | dspload_image(codec, dsp_os_image, 0, 0, true, 0); |
| 3773 | dsp_loaded = dspload_wait_loaded(codec); |
| 3774 | |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 3775 | return dsp_loaded; |
| 3776 | } |
| 3777 | |
| 3778 | static void ca0132_download_dsp(struct hda_codec *codec) |
| 3779 | { |
| 3780 | struct ca0132_spec *spec = codec->spec; |
| 3781 | |
| 3782 | spec->dsp_state = DSP_DOWNLOAD_INIT; |
| 3783 | |
| 3784 | if (spec->dsp_state == DSP_DOWNLOAD_INIT) { |
| 3785 | chipio_enable_clocks(codec); |
| 3786 | spec->dsp_state = DSP_DOWNLOADING; |
| 3787 | if (!ca0132_download_dsp_images(codec)) |
| 3788 | spec->dsp_state = DSP_DOWNLOAD_FAILED; |
| 3789 | else |
| 3790 | spec->dsp_state = DSP_DOWNLOADED; |
| 3791 | } |
| 3792 | |
| 3793 | if (spec->dsp_state == DSP_DOWNLOADED) |
| 3794 | ca0132_set_dsp_msr(codec, true); |
| 3795 | } |
| 3796 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3797 | static int ca0132_init(struct hda_codec *codec) |
| 3798 | { |
| 3799 | struct ca0132_spec *spec = codec->spec; |
| 3800 | struct auto_pin_cfg *cfg = &spec->autocfg; |
| 3801 | int i; |
| 3802 | |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 3803 | spec->dsp_state = DSP_DOWNLOAD_INIT; |
| 3804 | spec->curr_chip_addx = (unsigned int)INVALID_CHIP_ADDRESS; |
| 3805 | |
| 3806 | snd_hda_power_up(codec); |
| 3807 | |
| 3808 | ca0132_init_params(codec); |
| 3809 | ca0132_init_flags(codec); |
| 3810 | snd_hda_sequence_write(codec, spec->base_init_verbs); |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 3811 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
| 3812 | ca0132_download_dsp(codec); |
| 3813 | #endif |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 3814 | ca0132_refresh_widget_caps(codec); |
| 3815 | ca0132_setup_defaults(codec); |
| 3816 | ca0132_init_analog_mic2(codec); |
| 3817 | ca0132_init_dmic(codec); |
Ian Minett | 01ef7db | 2012-09-20 20:29:16 -0700 | [diff] [blame] | 3818 | |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 3819 | for (i = 0; i < spec->num_outputs; i++) |
| 3820 | init_output(codec, spec->out_pins[i], spec->dacs[0]); |
| 3821 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3822 | init_output(codec, cfg->dig_out_pins[0], spec->dig_out); |
| 3823 | |
| 3824 | for (i = 0; i < spec->num_inputs; i++) |
| 3825 | init_input(codec, spec->input_pins[i], spec->adcs[i]); |
| 3826 | |
| 3827 | init_input(codec, cfg->dig_in_pin, spec->dig_in); |
| 3828 | |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 3829 | for (i = 0; i < spec->num_init_verbs; i++) |
| 3830 | snd_hda_sequence_write(codec, spec->init_verbs[i]); |
| 3831 | |
| 3832 | ca0132_select_out(codec); |
| 3833 | ca0132_select_mic(codec); |
| 3834 | |
| 3835 | snd_hda_power_down(codec); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3836 | |
| 3837 | return 0; |
| 3838 | } |
| 3839 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3840 | static void ca0132_free(struct hda_codec *codec) |
| 3841 | { |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 3842 | struct ca0132_spec *spec = codec->spec; |
| 3843 | |
| 3844 | snd_hda_power_up(codec); |
| 3845 | snd_hda_sequence_write(codec, spec->base_exit_verbs); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3846 | ca0132_exit_chip(codec); |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 3847 | snd_hda_power_down(codec); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3848 | kfree(codec->spec); |
| 3849 | } |
| 3850 | |
| 3851 | static struct hda_codec_ops ca0132_patch_ops = { |
| 3852 | .build_controls = ca0132_build_controls, |
| 3853 | .build_pcms = ca0132_build_pcms, |
| 3854 | .init = ca0132_init, |
| 3855 | .free = ca0132_free, |
| 3856 | }; |
| 3857 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3858 | static int patch_ca0132(struct hda_codec *codec) |
| 3859 | { |
| 3860 | struct ca0132_spec *spec; |
| 3861 | |
| 3862 | snd_printdd("patch_ca0132\n"); |
| 3863 | |
| 3864 | spec = kzalloc(sizeof(*spec), GFP_KERNEL); |
| 3865 | if (!spec) |
| 3866 | return -ENOMEM; |
| 3867 | codec->spec = spec; |
| 3868 | |
Ian Minett | 5aaca44 | 2012-12-20 18:53:34 -0800 | [diff] [blame^] | 3869 | spec->base_init_verbs = ca0132_base_init_verbs; |
| 3870 | spec->base_exit_verbs = ca0132_base_exit_verbs; |
| 3871 | spec->init_verbs[0] = ca0132_init_verbs0; |
| 3872 | spec->init_verbs[1] = ca0132_init_verbs1; |
| 3873 | spec->num_init_verbs = 2; |
| 3874 | |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3875 | ca0132_init_chip(codec); |
| 3876 | |
| 3877 | ca0132_config(codec); |
| 3878 | |
| 3879 | codec->patch_ops = ca0132_patch_ops; |
| 3880 | |
| 3881 | return 0; |
| 3882 | } |
| 3883 | |
| 3884 | /* |
| 3885 | * patch entries |
| 3886 | */ |
| 3887 | static struct hda_codec_preset snd_hda_preset_ca0132[] = { |
| 3888 | { .id = 0x11020011, .name = "CA0132", .patch = patch_ca0132 }, |
| 3889 | {} /* terminator */ |
| 3890 | }; |
| 3891 | |
| 3892 | MODULE_ALIAS("snd-hda-codec-id:11020011"); |
| 3893 | |
| 3894 | MODULE_LICENSE("GPL"); |
| 3895 | MODULE_DESCRIPTION("Creative CA0132, CA0132 HD-audio codec"); |
| 3896 | |
| 3897 | static struct hda_codec_preset_list ca0132_list = { |
| 3898 | .preset = snd_hda_preset_ca0132, |
| 3899 | .owner = THIS_MODULE, |
| 3900 | }; |
| 3901 | |
| 3902 | static int __init patch_ca0132_init(void) |
| 3903 | { |
| 3904 | return snd_hda_add_codec_preset(&ca0132_list); |
| 3905 | } |
| 3906 | |
| 3907 | static void __exit patch_ca0132_exit(void) |
| 3908 | { |
Ian Minett | c3b4eea2 | 2012-09-20 20:29:17 -0700 | [diff] [blame] | 3909 | release_cached_firmware(); |
Ian Minett | 95c6e9c | 2011-06-15 15:35:17 -0700 | [diff] [blame] | 3910 | snd_hda_delete_codec_preset(&ca0132_list); |
| 3911 | } |
| 3912 | |
| 3913 | module_init(patch_ca0132_init) |
| 3914 | module_exit(patch_ca0132_exit) |