blob: 527d11b5ff142902ad97d504455f79cc228b572e [file] [log] [blame]
Rob Clarke7792ce2013-01-08 19:21:02 -06001/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18
19
20#include <linux/module.h>
21
22#include <drm/drmP.h>
23#include <drm/drm_crtc_helper.h>
24#include <drm/drm_encoder_slave.h>
25#include <drm/drm_edid.h>
26
27
28#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
29
30struct tda998x_priv {
31 struct i2c_client *cec;
32 uint16_t rev;
33 uint8_t current_page;
34 int dpms;
Russell King5e74c222013-08-14 21:43:29 +020035 u8 vip_cntrl_0;
36 u8 vip_cntrl_1;
37 u8 vip_cntrl_2;
Rob Clarke7792ce2013-01-08 19:21:02 -060038};
39
40#define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv)
41
42/* The TDA9988 series of devices use a paged register scheme.. to simplify
43 * things we encode the page # in upper bits of the register #. To read/
44 * write a given register, we need to make sure CURPAGE register is set
45 * appropriately. Which implies reads/writes are not atomic. Fun!
46 */
47
48#define REG(page, addr) (((page) << 8) | (addr))
49#define REG2ADDR(reg) ((reg) & 0xff)
50#define REG2PAGE(reg) (((reg) >> 8) & 0xff)
51
52#define REG_CURPAGE 0xff /* write */
53
54
55/* Page 00h: General Control */
56#define REG_VERSION_LSB REG(0x00, 0x00) /* read */
57#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
58# define MAIN_CNTRL0_SR (1 << 0)
59# define MAIN_CNTRL0_DECS (1 << 1)
60# define MAIN_CNTRL0_DEHS (1 << 2)
61# define MAIN_CNTRL0_CECS (1 << 3)
62# define MAIN_CNTRL0_CEHS (1 << 4)
63# define MAIN_CNTRL0_SCALER (1 << 7)
64#define REG_VERSION_MSB REG(0x00, 0x02) /* read */
65#define REG_SOFTRESET REG(0x00, 0x0a) /* write */
66# define SOFTRESET_AUDIO (1 << 0)
67# define SOFTRESET_I2C_MASTER (1 << 1)
68#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
69#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
70#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
71# define I2C_MASTER_DIS_MM (1 << 0)
72# define I2C_MASTER_DIS_FILT (1 << 1)
73# define I2C_MASTER_APP_STRT_LAT (1 << 2)
74#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
75#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
76#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
77# define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
78#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
79#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
80#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
81#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
82#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
83# define VIP_CNTRL_0_MIRR_A (1 << 7)
84# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
85# define VIP_CNTRL_0_MIRR_B (1 << 3)
86# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
87#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
88# define VIP_CNTRL_1_MIRR_C (1 << 7)
89# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
90# define VIP_CNTRL_1_MIRR_D (1 << 3)
91# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
92#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
93# define VIP_CNTRL_2_MIRR_E (1 << 7)
94# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
95# define VIP_CNTRL_2_MIRR_F (1 << 3)
96# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
97#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
98# define VIP_CNTRL_3_X_TGL (1 << 0)
99# define VIP_CNTRL_3_H_TGL (1 << 1)
100# define VIP_CNTRL_3_V_TGL (1 << 2)
101# define VIP_CNTRL_3_EMB (1 << 3)
102# define VIP_CNTRL_3_SYNC_DE (1 << 4)
103# define VIP_CNTRL_3_SYNC_HS (1 << 5)
104# define VIP_CNTRL_3_DE_INT (1 << 6)
105# define VIP_CNTRL_3_EDGE (1 << 7)
106#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
107# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
108# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
109# define VIP_CNTRL_4_CCIR656 (1 << 4)
110# define VIP_CNTRL_4_656_ALT (1 << 5)
111# define VIP_CNTRL_4_TST_656 (1 << 6)
112# define VIP_CNTRL_4_TST_PAT (1 << 7)
113#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
114# define VIP_CNTRL_5_CKCASE (1 << 0)
115# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
Russell Kingbcb24812013-08-14 21:43:27 +0200116#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
Rob Clarke7792ce2013-01-08 19:21:02 -0600117#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
118# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
119# define MAT_CONTRL_MAT_BP (1 << 2)
120#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
121#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
122#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
123#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
124#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
125#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
126#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
127#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
128#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
129#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
130#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
131#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
132#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
133#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
134#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
135#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
136#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
137#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
138#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
139#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
140#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
141#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
142#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
143#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
144#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
145#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
146#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
147#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
148#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
149#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
150#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
151#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
152#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
153#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
154# define TBG_CNTRL_0_FRAME_DIS (1 << 5)
155# define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
156# define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
157#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
158# define TBG_CNTRL_1_VH_TGL_0 (1 << 0)
159# define TBG_CNTRL_1_VH_TGL_1 (1 << 1)
160# define TBG_CNTRL_1_VH_TGL_2 (1 << 2)
161# define TBG_CNTRL_1_VHX_EXT_DE (1 << 3)
162# define TBG_CNTRL_1_VHX_EXT_HS (1 << 4)
163# define TBG_CNTRL_1_VHX_EXT_VS (1 << 5)
164# define TBG_CNTRL_1_DWIN_DIS (1 << 6)
165#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
166#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
167# define HVF_CNTRL_0_SM (1 << 7)
168# define HVF_CNTRL_0_RWB (1 << 6)
169# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
170# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
171#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
172# define HVF_CNTRL_1_FOR (1 << 0)
173# define HVF_CNTRL_1_YUVBLK (1 << 1)
174# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
175# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
176# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
177#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
178
179
180/* Page 02h: PLL settings */
181#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
182# define PLL_SERIAL_1_SRL_FDN (1 << 0)
183# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
184# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
185#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
186# define PLL_SERIAL_2_SRL_NOSC(x) (((x) & 3) << 0)
187# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
188#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
189# define PLL_SERIAL_3_SRL_CCIR (1 << 0)
190# define PLL_SERIAL_3_SRL_DE (1 << 2)
191# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
192#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
193#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
194#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
195#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
196#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
197#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
198#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
199#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
200#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
201#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
202# define SEL_CLK_SEL_CLK1 (1 << 0)
203# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
204# define SEL_CLK_ENA_SC_CLK (1 << 3)
205#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
206
207
208/* Page 09h: EDID Control */
209#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
210/* next 127 successive registers are the EDID block */
211#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
212#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
213#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
214#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
215#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
216
217
218/* Page 10h: information frames and packets */
219
220
221/* Page 11h: audio settings and content info packets */
222#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
223# define AIP_CNTRL_0_RST_FIFO (1 << 0)
224# define AIP_CNTRL_0_SWAP (1 << 1)
225# define AIP_CNTRL_0_LAYOUT (1 << 2)
226# define AIP_CNTRL_0_ACR_MAN (1 << 5)
227# define AIP_CNTRL_0_RST_CTS (1 << 6)
228#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
229# define ENC_CNTRL_RST_ENC (1 << 0)
230# define ENC_CNTRL_RST_SEL (1 << 1)
231# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
232
233
234/* Page 12h: HDCP and OTP */
235#define REG_TX3 REG(0x12, 0x9a) /* read/write */
Russell King063b4722013-08-14 21:43:26 +0200236#define REG_TX4 REG(0x12, 0x9b) /* read/write */
237# define TX4_PD_RAM (1 << 1)
Rob Clarke7792ce2013-01-08 19:21:02 -0600238#define REG_TX33 REG(0x12, 0xb8) /* read/write */
239# define TX33_HDMI (1 << 1)
240
241
242/* Page 13h: Gamut related metadata packets */
243
244
245
246/* CEC registers: (not paged)
247 */
248#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
249# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
250# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
251# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
252# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
253#define REG_CEC_RXSHPDLEV 0xfe /* read */
254# define CEC_RXSHPDLEV_RXSENS (1 << 0)
255# define CEC_RXSHPDLEV_HPD (1 << 1)
256
257#define REG_CEC_ENAMODS 0xff /* read/write */
258# define CEC_ENAMODS_DIS_FRO (1 << 6)
259# define CEC_ENAMODS_DIS_CCLK (1 << 5)
260# define CEC_ENAMODS_EN_RXSENS (1 << 2)
261# define CEC_ENAMODS_EN_HDMI (1 << 1)
262# define CEC_ENAMODS_EN_CEC (1 << 0)
263
264
265/* Device versions: */
266#define TDA9989N2 0x0101
267#define TDA19989 0x0201
268#define TDA19989N2 0x0202
269#define TDA19988 0x0301
270
271static void
272cec_write(struct drm_encoder *encoder, uint16_t addr, uint8_t val)
273{
274 struct i2c_client *client = to_tda998x_priv(encoder)->cec;
275 uint8_t buf[] = {addr, val};
276 int ret;
277
278 ret = i2c_master_send(client, buf, ARRAY_SIZE(buf));
279 if (ret < 0)
280 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr);
281}
282
283static uint8_t
284cec_read(struct drm_encoder *encoder, uint8_t addr)
285{
286 struct i2c_client *client = to_tda998x_priv(encoder)->cec;
287 uint8_t val;
288 int ret;
289
290 ret = i2c_master_send(client, &addr, sizeof(addr));
291 if (ret < 0)
292 goto fail;
293
294 ret = i2c_master_recv(client, &val, sizeof(val));
295 if (ret < 0)
296 goto fail;
297
298 return val;
299
300fail:
301 dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr);
302 return 0;
303}
304
305static void
306set_page(struct drm_encoder *encoder, uint16_t reg)
307{
308 struct tda998x_priv *priv = to_tda998x_priv(encoder);
309
310 if (REG2PAGE(reg) != priv->current_page) {
311 struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
312 uint8_t buf[] = {
313 REG_CURPAGE, REG2PAGE(reg)
314 };
315 int ret = i2c_master_send(client, buf, sizeof(buf));
316 if (ret < 0)
317 dev_err(&client->dev, "Error %d writing to REG_CURPAGE\n", ret);
318
319 priv->current_page = REG2PAGE(reg);
320 }
321}
322
323static int
324reg_read_range(struct drm_encoder *encoder, uint16_t reg, char *buf, int cnt)
325{
326 struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
327 uint8_t addr = REG2ADDR(reg);
328 int ret;
329
330 set_page(encoder, reg);
331
332 ret = i2c_master_send(client, &addr, sizeof(addr));
333 if (ret < 0)
334 goto fail;
335
336 ret = i2c_master_recv(client, buf, cnt);
337 if (ret < 0)
338 goto fail;
339
340 return ret;
341
342fail:
343 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
344 return ret;
345}
346
347static uint8_t
348reg_read(struct drm_encoder *encoder, uint16_t reg)
349{
350 uint8_t val = 0;
351 reg_read_range(encoder, reg, &val, sizeof(val));
352 return val;
353}
354
355static void
356reg_write(struct drm_encoder *encoder, uint16_t reg, uint8_t val)
357{
358 struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
359 uint8_t buf[] = {REG2ADDR(reg), val};
360 int ret;
361
362 set_page(encoder, reg);
363
364 ret = i2c_master_send(client, buf, ARRAY_SIZE(buf));
365 if (ret < 0)
366 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
367}
368
369static void
370reg_write16(struct drm_encoder *encoder, uint16_t reg, uint16_t val)
371{
372 struct i2c_client *client = drm_i2c_encoder_get_client(encoder);
373 uint8_t buf[] = {REG2ADDR(reg), val >> 8, val};
374 int ret;
375
376 set_page(encoder, reg);
377
378 ret = i2c_master_send(client, buf, ARRAY_SIZE(buf));
379 if (ret < 0)
380 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
381}
382
383static void
384reg_set(struct drm_encoder *encoder, uint16_t reg, uint8_t val)
385{
386 reg_write(encoder, reg, reg_read(encoder, reg) | val);
387}
388
389static void
390reg_clear(struct drm_encoder *encoder, uint16_t reg, uint8_t val)
391{
392 reg_write(encoder, reg, reg_read(encoder, reg) & ~val);
393}
394
395static void
396tda998x_reset(struct drm_encoder *encoder)
397{
398 /* reset audio and i2c master: */
399 reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
400 msleep(50);
401 reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
402 msleep(50);
403
404 /* reset transmitter: */
405 reg_set(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
406 reg_clear(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
407
408 /* PLL registers common configuration */
409 reg_write(encoder, REG_PLL_SERIAL_1, 0x00);
410 reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
411 reg_write(encoder, REG_PLL_SERIAL_3, 0x00);
412 reg_write(encoder, REG_SERIALIZER, 0x00);
413 reg_write(encoder, REG_BUFFER_OUT, 0x00);
414 reg_write(encoder, REG_PLL_SCG1, 0x00);
415 reg_write(encoder, REG_AUDIO_DIV, 0x03);
416 reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
417 reg_write(encoder, REG_PLL_SCGN1, 0xfa);
418 reg_write(encoder, REG_PLL_SCGN2, 0x00);
419 reg_write(encoder, REG_PLL_SCGR1, 0x5b);
420 reg_write(encoder, REG_PLL_SCGR2, 0x00);
421 reg_write(encoder, REG_PLL_SCG2, 0x10);
Russell Kingbcb24812013-08-14 21:43:27 +0200422
423 /* Write the default value MUX register */
424 reg_write(encoder, REG_MUX_VP_VIP_OUT, 0x24);
Rob Clarke7792ce2013-01-08 19:21:02 -0600425}
426
427/* DRM encoder functions */
428
429static void
430tda998x_encoder_set_config(struct drm_encoder *encoder, void *params)
431{
432}
433
434static void
435tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
436{
437 struct tda998x_priv *priv = to_tda998x_priv(encoder);
438
439 /* we only care about on or off: */
440 if (mode != DRM_MODE_DPMS_ON)
441 mode = DRM_MODE_DPMS_OFF;
442
443 if (mode == priv->dpms)
444 return;
445
446 switch (mode) {
447 case DRM_MODE_DPMS_ON:
448 /* enable audio and video ports */
449 reg_write(encoder, REG_ENA_AP, 0xff);
450 reg_write(encoder, REG_ENA_VP_0, 0xff);
451 reg_write(encoder, REG_ENA_VP_1, 0xff);
452 reg_write(encoder, REG_ENA_VP_2, 0xff);
453 /* set muxing after enabling ports: */
Russell King5e74c222013-08-14 21:43:29 +0200454 reg_write(encoder, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
455 reg_write(encoder, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
456 reg_write(encoder, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
Rob Clarke7792ce2013-01-08 19:21:02 -0600457 break;
458 case DRM_MODE_DPMS_OFF:
459 /* disable audio and video ports */
460 reg_write(encoder, REG_ENA_AP, 0x00);
461 reg_write(encoder, REG_ENA_VP_0, 0x00);
462 reg_write(encoder, REG_ENA_VP_1, 0x00);
463 reg_write(encoder, REG_ENA_VP_2, 0x00);
464 break;
465 }
466
467 priv->dpms = mode;
468}
469
470static void
471tda998x_encoder_save(struct drm_encoder *encoder)
472{
473 DBG("");
474}
475
476static void
477tda998x_encoder_restore(struct drm_encoder *encoder)
478{
479 DBG("");
480}
481
482static bool
483tda998x_encoder_mode_fixup(struct drm_encoder *encoder,
484 const struct drm_display_mode *mode,
485 struct drm_display_mode *adjusted_mode)
486{
487 return true;
488}
489
490static int
491tda998x_encoder_mode_valid(struct drm_encoder *encoder,
492 struct drm_display_mode *mode)
493{
494 return MODE_OK;
495}
496
497static void
498tda998x_encoder_mode_set(struct drm_encoder *encoder,
499 struct drm_display_mode *mode,
500 struct drm_display_mode *adjusted_mode)
501{
502 struct tda998x_priv *priv = to_tda998x_priv(encoder);
503 uint16_t hs_start, hs_end, line_start, line_end;
504 uint16_t vwin_start, vwin_end, de_start, de_end;
505 uint16_t ref_pix, ref_line, pix_start2;
506 uint8_t reg, div, rep;
507
508 hs_start = mode->hsync_start - mode->hdisplay;
509 hs_end = mode->hsync_end - mode->hdisplay;
510 line_start = 1;
511 line_end = 1 + mode->vsync_end - mode->vsync_start;
512 vwin_start = mode->vtotal - mode->vsync_start;
513 vwin_end = vwin_start + mode->vdisplay;
514 de_start = mode->htotal - mode->hdisplay;
515 de_end = mode->htotal;
516
517 pix_start2 = 0;
518 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
519 pix_start2 = (mode->htotal / 2) + hs_start;
520
521 /* TODO how is this value calculated? It is 2 for all common
522 * formats in the tables in out of tree nxp driver (assuming
523 * I've properly deciphered their byzantine table system)
524 */
525 ref_line = 2;
526
527 /* this might changes for other color formats from the CRTC: */
528 ref_pix = 3 + hs_start;
529
530 div = 148500 / mode->clock;
531
532 DBG("clock=%d, div=%u", mode->clock, div);
533 DBG("hs_start=%u, hs_end=%u, line_start=%u, line_end=%u",
534 hs_start, hs_end, line_start, line_end);
535 DBG("vwin_start=%u, vwin_end=%u, de_start=%u, de_end=%u",
536 vwin_start, vwin_end, de_start, de_end);
537 DBG("ref_line=%u, ref_pix=%u, pix_start2=%u",
538 ref_line, ref_pix, pix_start2);
539
540 /* mute the audio FIFO: */
541 reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
542
543 /* set HDMI HDCP mode off: */
544 reg_set(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
545 reg_clear(encoder, REG_TX33, TX33_HDMI);
546
547 reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
548 /* no pre-filter or interpolator: */
549 reg_write(encoder, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
550 HVF_CNTRL_0_INTPOL(0));
551 reg_write(encoder, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
552 reg_write(encoder, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
553 VIP_CNTRL_4_BLC(0));
554 reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR);
555
556 reg_clear(encoder, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
557 reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE);
558 reg_write(encoder, REG_SERIALIZER, 0);
559 reg_write(encoder, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
560
561 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
562 rep = 0;
563 reg_write(encoder, REG_RPT_CNTRL, 0);
564 reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
565 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
566
567 reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
568 PLL_SERIAL_2_SRL_PR(rep));
569
570 reg_write16(encoder, REG_VS_PIX_STRT_2_MSB, pix_start2);
571 reg_write16(encoder, REG_VS_PIX_END_2_MSB, pix_start2);
572
573 /* set color matrix bypass flag: */
574 reg_set(encoder, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP);
575
576 /* set BIAS tmds value: */
577 reg_write(encoder, REG_ANA_GENERAL, 0x09);
578
579 reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD);
580
581 reg_write(encoder, REG_VIP_CNTRL_3, 0);
582 reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_SYNC_HS);
583 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
584 reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_V_TGL);
585
586 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
587 reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_H_TGL);
588
589 reg_write(encoder, REG_VIDFORMAT, 0x00);
Russell King20c17672013-08-14 21:43:28 +0200590 reg_write16(encoder, REG_NPIX_MSB, mode->htotal);
591 reg_write16(encoder, REG_NLINE_MSB, mode->vtotal);
Rob Clarke7792ce2013-01-08 19:21:02 -0600592 reg_write16(encoder, REG_VS_LINE_STRT_1_MSB, line_start);
593 reg_write16(encoder, REG_VS_LINE_END_1_MSB, line_end);
594 reg_write16(encoder, REG_VS_PIX_STRT_1_MSB, hs_start);
595 reg_write16(encoder, REG_VS_PIX_END_1_MSB, hs_start);
596 reg_write16(encoder, REG_HS_PIX_START_MSB, hs_start);
597 reg_write16(encoder, REG_HS_PIX_STOP_MSB, hs_end);
598 reg_write16(encoder, REG_VWIN_START_1_MSB, vwin_start);
599 reg_write16(encoder, REG_VWIN_END_1_MSB, vwin_end);
600 reg_write16(encoder, REG_DE_START_MSB, de_start);
601 reg_write16(encoder, REG_DE_STOP_MSB, de_end);
602
603 if (priv->rev == TDA19988) {
604 /* let incoming pixels fill the active space (if any) */
605 reg_write(encoder, REG_ENABLE_SPACE, 0x01);
606 }
607
608 reg_write16(encoder, REG_REFPIX_MSB, ref_pix);
609 reg_write16(encoder, REG_REFLINE_MSB, ref_line);
610
611 reg = TBG_CNTRL_1_VHX_EXT_DE |
612 TBG_CNTRL_1_VHX_EXT_HS |
613 TBG_CNTRL_1_VHX_EXT_VS |
614 TBG_CNTRL_1_DWIN_DIS | /* HDCP off */
615 TBG_CNTRL_1_VH_TGL_2;
616 if (mode->flags & (DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC))
617 reg |= TBG_CNTRL_1_VH_TGL_0;
618 reg_set(encoder, REG_TBG_CNTRL_1, reg);
619
620 /* must be last register set: */
621 reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE);
622}
623
624static enum drm_connector_status
625tda998x_encoder_detect(struct drm_encoder *encoder,
626 struct drm_connector *connector)
627{
628 uint8_t val = cec_read(encoder, REG_CEC_RXSHPDLEV);
629 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
630 connector_status_disconnected;
631}
632
633static int
634read_edid_block(struct drm_encoder *encoder, uint8_t *buf, int blk)
635{
636 uint8_t offset, segptr;
637 int ret, i;
638
639 /* enable EDID read irq: */
640 reg_set(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
641
642 offset = (blk & 1) ? 128 : 0;
643 segptr = blk / 2;
644
645 reg_write(encoder, REG_DDC_ADDR, 0xa0);
646 reg_write(encoder, REG_DDC_OFFS, offset);
647 reg_write(encoder, REG_DDC_SEGM_ADDR, 0x60);
648 reg_write(encoder, REG_DDC_SEGM, segptr);
649
650 /* enable reading EDID: */
651 reg_write(encoder, REG_EDID_CTRL, 0x1);
652
653 /* flag must be cleared by sw: */
654 reg_write(encoder, REG_EDID_CTRL, 0x0);
655
656 /* wait for block read to complete: */
657 for (i = 100; i > 0; i--) {
658 uint8_t val = reg_read(encoder, REG_INT_FLAGS_2);
659 if (val & INT_FLAGS_2_EDID_BLK_RD)
660 break;
661 msleep(1);
662 }
663
664 if (i == 0)
665 return -ETIMEDOUT;
666
667 ret = reg_read_range(encoder, REG_EDID_DATA_0, buf, EDID_LENGTH);
668 if (ret != EDID_LENGTH) {
669 dev_err(encoder->dev->dev, "failed to read edid block %d: %d",
670 blk, ret);
671 return ret;
672 }
673
674 reg_clear(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
675
676 return 0;
677}
678
679static uint8_t *
680do_get_edid(struct drm_encoder *encoder)
681{
Russell King063b4722013-08-14 21:43:26 +0200682 struct tda998x_priv *priv = to_tda998x_priv(encoder);
Rob Clarke7792ce2013-01-08 19:21:02 -0600683 int j = 0, valid_extensions = 0;
684 uint8_t *block, *new;
685 bool print_bad_edid = drm_debug & DRM_UT_KMS;
686
687 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
688 return NULL;
689
Russell King063b4722013-08-14 21:43:26 +0200690 if (priv->rev == TDA19988)
691 reg_clear(encoder, REG_TX4, TX4_PD_RAM);
692
Rob Clarke7792ce2013-01-08 19:21:02 -0600693 /* base block fetch */
694 if (read_edid_block(encoder, block, 0))
695 goto fail;
696
697 if (!drm_edid_block_valid(block, 0, print_bad_edid))
698 goto fail;
699
700 /* if there's no extensions, we're done */
701 if (block[0x7e] == 0)
Russell King063b4722013-08-14 21:43:26 +0200702 goto done;
Rob Clarke7792ce2013-01-08 19:21:02 -0600703
704 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
705 if (!new)
706 goto fail;
707 block = new;
708
709 for (j = 1; j <= block[0x7e]; j++) {
710 uint8_t *ext_block = block + (valid_extensions + 1) * EDID_LENGTH;
711 if (read_edid_block(encoder, ext_block, j))
712 goto fail;
713
714 if (!drm_edid_block_valid(ext_block, j, print_bad_edid))
715 goto fail;
716
717 valid_extensions++;
718 }
719
720 if (valid_extensions != block[0x7e]) {
721 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
722 block[0x7e] = valid_extensions;
723 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
724 if (!new)
725 goto fail;
726 block = new;
727 }
728
Russell King063b4722013-08-14 21:43:26 +0200729done:
730 if (priv->rev == TDA19988)
731 reg_set(encoder, REG_TX4, TX4_PD_RAM);
732
Rob Clarke7792ce2013-01-08 19:21:02 -0600733 return block;
734
735fail:
Russell King063b4722013-08-14 21:43:26 +0200736 if (priv->rev == TDA19988)
737 reg_set(encoder, REG_TX4, TX4_PD_RAM);
Rob Clarke7792ce2013-01-08 19:21:02 -0600738 dev_warn(encoder->dev->dev, "failed to read EDID\n");
739 kfree(block);
740 return NULL;
741}
742
743static int
744tda998x_encoder_get_modes(struct drm_encoder *encoder,
745 struct drm_connector *connector)
746{
747 struct edid *edid = (struct edid *)do_get_edid(encoder);
748 int n = 0;
749
750 if (edid) {
751 drm_mode_connector_update_edid_property(connector, edid);
752 n = drm_add_edid_modes(connector, edid);
753 kfree(edid);
754 }
755
756 return n;
757}
758
759static int
760tda998x_encoder_create_resources(struct drm_encoder *encoder,
761 struct drm_connector *connector)
762{
763 DBG("");
764 return 0;
765}
766
767static int
768tda998x_encoder_set_property(struct drm_encoder *encoder,
769 struct drm_connector *connector,
770 struct drm_property *property,
771 uint64_t val)
772{
773 DBG("");
774 return 0;
775}
776
777static void
778tda998x_encoder_destroy(struct drm_encoder *encoder)
779{
780 struct tda998x_priv *priv = to_tda998x_priv(encoder);
781 drm_i2c_encoder_destroy(encoder);
782 kfree(priv);
783}
784
785static struct drm_encoder_slave_funcs tda998x_encoder_funcs = {
786 .set_config = tda998x_encoder_set_config,
787 .destroy = tda998x_encoder_destroy,
788 .dpms = tda998x_encoder_dpms,
789 .save = tda998x_encoder_save,
790 .restore = tda998x_encoder_restore,
791 .mode_fixup = tda998x_encoder_mode_fixup,
792 .mode_valid = tda998x_encoder_mode_valid,
793 .mode_set = tda998x_encoder_mode_set,
794 .detect = tda998x_encoder_detect,
795 .get_modes = tda998x_encoder_get_modes,
796 .create_resources = tda998x_encoder_create_resources,
797 .set_property = tda998x_encoder_set_property,
798};
799
800/* I2C driver functions */
801
802static int
803tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
804{
805 return 0;
806}
807
808static int
809tda998x_remove(struct i2c_client *client)
810{
811 return 0;
812}
813
814static int
815tda998x_encoder_init(struct i2c_client *client,
816 struct drm_device *dev,
817 struct drm_encoder_slave *encoder_slave)
818{
819 struct drm_encoder *encoder = &encoder_slave->base;
820 struct tda998x_priv *priv;
821
822 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
823 if (!priv)
824 return -ENOMEM;
825
Russell King5e74c222013-08-14 21:43:29 +0200826 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
827 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
828 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
829
Rob Clarke7792ce2013-01-08 19:21:02 -0600830 priv->current_page = 0;
831 priv->cec = i2c_new_dummy(client->adapter, 0x34);
832 priv->dpms = DRM_MODE_DPMS_OFF;
833
834 encoder_slave->slave_priv = priv;
835 encoder_slave->slave_funcs = &tda998x_encoder_funcs;
836
837 /* wake up the device: */
838 cec_write(encoder, REG_CEC_ENAMODS,
839 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
840
841 tda998x_reset(encoder);
842
843 /* read version: */
844 priv->rev = reg_read(encoder, REG_VERSION_LSB) |
845 reg_read(encoder, REG_VERSION_MSB) << 8;
846
847 /* mask off feature bits: */
848 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
849
850 switch (priv->rev) {
851 case TDA9989N2: dev_info(dev->dev, "found TDA9989 n2"); break;
852 case TDA19989: dev_info(dev->dev, "found TDA19989"); break;
853 case TDA19989N2: dev_info(dev->dev, "found TDA19989 n2"); break;
854 case TDA19988: dev_info(dev->dev, "found TDA19988"); break;
855 default:
856 DBG("found unsupported device: %04x", priv->rev);
857 goto fail;
858 }
859
860 /* after reset, enable DDC: */
861 reg_write(encoder, REG_DDC_DISABLE, 0x00);
862
863 /* set clock on DDC channel: */
864 reg_write(encoder, REG_TX3, 39);
865
866 /* if necessary, disable multi-master: */
867 if (priv->rev == TDA19989)
868 reg_set(encoder, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
869
870 cec_write(encoder, REG_CEC_FRO_IM_CLK_CTRL,
871 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
872
873 return 0;
874
875fail:
876 /* if encoder_init fails, the encoder slave is never registered,
877 * so cleanup here:
878 */
879 if (priv->cec)
880 i2c_unregister_device(priv->cec);
881 kfree(priv);
882 encoder_slave->slave_priv = NULL;
883 encoder_slave->slave_funcs = NULL;
884 return -ENXIO;
885}
886
887static struct i2c_device_id tda998x_ids[] = {
888 { "tda998x", 0 },
889 { }
890};
891MODULE_DEVICE_TABLE(i2c, tda998x_ids);
892
893static struct drm_i2c_encoder_driver tda998x_driver = {
894 .i2c_driver = {
895 .probe = tda998x_probe,
896 .remove = tda998x_remove,
897 .driver = {
898 .name = "tda998x",
899 },
900 .id_table = tda998x_ids,
901 },
902 .encoder_init = tda998x_encoder_init,
903};
904
905/* Module initialization */
906
907static int __init
908tda998x_init(void)
909{
910 DBG("");
911 return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver);
912}
913
914static void __exit
915tda998x_exit(void)
916{
917 DBG("");
918 drm_i2c_encoder_unregister(&tda998x_driver);
919}
920
921MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
922MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
923MODULE_LICENSE("GPL");
924
925module_init(tda998x_init);
926module_exit(tda998x_exit);