Blame - drivers/irqchip/Kconfig - kernel/msm-4.9

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Thomas Petazzoni	f6e916b	2012-11-20 23:00:52 +0100	[diff] [blame]	1	config IRQCHIP
				2	def_bool y
				3	depends on OF_IRQ
				4
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	5	config ARM_GIC
				6	bool
				7	select IRQ_DOMAIN
Yingjoe Chen	9a1091e	2014-11-25 16:04:19 +0800	[diff] [blame]	8	select IRQ_DOMAIN_HIERARCHY
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	9	select MULTI_IRQ_HANDLER
				10
Suravee Suthikulpanit	853a33c	2014-11-25 18:47:22 +0000	[diff] [blame]	11	config ARM_GIC_V2M
				12	bool
				13	depends on ARM_GIC
				14	depends on PCI && PCI_MSI
				15	select PCI_MSI_IRQ_DOMAIN
				16
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	17	config GIC_NON_BANKED
				18	bool
				19
Marc Zyngier	021f653	2014-06-30 16:01:31 +0100	[diff] [blame]	20	config ARM_GIC_V3
				21	bool
				22	select IRQ_DOMAIN
				23	select MULTI_IRQ_HANDLER
Marc Zyngier	443acc4	2014-11-24 14:35:09 +0000	[diff] [blame]	24	select IRQ_DOMAIN_HIERARCHY
Marc Zyngier	021f653	2014-06-30 16:01:31 +0100	[diff] [blame]	25
Marc Zyngier	1981272	2014-11-24 14:35:19 +0000	[diff] [blame]	26	config ARM_GIC_V3_ITS
				27	bool
				28	select PCI_MSI_IRQ_DOMAIN
Uwe Kleine-König	292ec08	2013-06-26 09:18:48 +0200	[diff] [blame]	29
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	30	config ARM_NVIC
				31	bool
				32	select IRQ_DOMAIN
				33	select GENERIC_IRQ_CHIP
				34
				35	config ARM_VIC
				36	bool
				37	select IRQ_DOMAIN
				38	select MULTI_IRQ_HANDLER
				39
				40	config ARM_VIC_NR
				41	int
				42	default 4 if ARCH_S5PV210
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	43	default 2
				44	depends on ARM_VIC
				45	help
				46	The maximum number of VICs available in the system, for
				47	power management.
				48
Boris BREZILLON	b1479eb	2014-07-10 19:14:18 +0200	[diff] [blame]	49	config ATMEL_AIC_IRQ
				50	bool
				51	select GENERIC_IRQ_CHIP
				52	select IRQ_DOMAIN
				53	select MULTI_IRQ_HANDLER
				54	select SPARSE_IRQ
				55
				56	config ATMEL_AIC5_IRQ
				57	bool
				58	select GENERIC_IRQ_CHIP
				59	select IRQ_DOMAIN
				60	select MULTI_IRQ_HANDLER
				61	select SPARSE_IRQ
				62
Kevin Cernekee	5f7f031	2014-12-25 09:49:06 -0800	[diff] [blame^]	63	config BCM7038_L1_IRQ
				64	bool
				65	select GENERIC_IRQ_CHIP
				66	select IRQ_DOMAIN
				67
Kevin Cernekee	a4fcbb8	2014-11-06 22:44:27 -0800	[diff] [blame]	68	config BCM7120_L2_IRQ
				69	bool
				70	select GENERIC_IRQ_CHIP
				71	select IRQ_DOMAIN
				72
Florian Fainelli	7f646e9	2014-05-23 17:40:53 -0700	[diff] [blame]	73	config BRCMSTB_L2_IRQ
				74	bool
Florian Fainelli	7f646e9	2014-05-23 17:40:53 -0700	[diff] [blame]	75	select GENERIC_IRQ_CHIP
				76	select IRQ_DOMAIN
				77
Sebastian Hesselbarth	350d71b9	2013-09-09 14:01:20 +0200	[diff] [blame]	78	config DW_APB_ICTL
				79	bool
Jisheng Zhang	e158849	2014-10-22 20:59:10 +0800	[diff] [blame]	80	select GENERIC_IRQ_CHIP
Sebastian Hesselbarth	350d71b9	2013-09-09 14:01:20 +0200	[diff] [blame]	81	select IRQ_DOMAIN
				82
James Hogan	b6ef916	2013-04-22 15:43:50 +0100	[diff] [blame]	83	config IMGPDC_IRQ
				84	bool
				85	select GENERIC_IRQ_CHIP
				86	select IRQ_DOMAIN
				87
Alexander Shiyan	afc98d9	2014-02-02 12:07:46 +0400	[diff] [blame]	88	config CLPS711X_IRQCHIP
				89	bool
				90	depends on ARCH_CLPS711X
				91	select IRQ_DOMAIN
				92	select MULTI_IRQ_HANDLER
				93	select SPARSE_IRQ
				94	default y
				95
Stefan Kristiansson	4db8e6d	2014-05-26 23:31:42 +0300	[diff] [blame]	96	config OR1K_PIC
				97	bool
				98	select IRQ_DOMAIN
				99
Felipe Balbi	8598066	2014-09-15 16:15:02 -0500	[diff] [blame]	100	config OMAP_IRQCHIP
				101	bool
				102	select GENERIC_IRQ_CHIP
				103	select IRQ_DOMAIN
				104
Sebastian Hesselbarth	9dbd90f	2013-06-06 18:27:09 +0200	[diff] [blame]	105	config ORION_IRQCHIP
				106	bool
				107	select IRQ_DOMAIN
				108	select MULTI_IRQ_HANDLER
				109
Magnus Damm	4435804	2013-02-18 23:28:34 +0900	[diff] [blame]	110	config RENESAS_INTC_IRQPIN
				111	bool
				112	select IRQ_DOMAIN
				113
Magnus Damm	fbc83b7	2013-02-27 17:15:01 +0900	[diff] [blame]	114	config RENESAS_IRQC
				115	bool
				116	select IRQ_DOMAIN
				117
Christian Ruppert	b06eb01	2013-06-25 18:29:57 +0200	[diff] [blame]	118	config TB10X_IRQC
				119	bool
				120	select IRQ_DOMAIN
				121	select GENERIC_IRQ_CHIP
				122
Linus Walleij	2389d50	2012-10-31 22:04:31 +0100	[diff] [blame]	123	config VERSATILE_FPGA_IRQ
				124	bool
				125	select IRQ_DOMAIN
				126
				127	config VERSATILE_FPGA_IRQ_NR
				128	int
				129	default 4
				130	depends on VERSATILE_FPGA_IRQ
Max Filippov	26a8e96	2013-12-01 12:04:57 +0400	[diff] [blame]	131
				132	config XTENSA_MX
				133	bool
				134	select IRQ_DOMAIN
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	135
				136	config IRQ_CROSSBAR
				137	bool
				138	help
Masanari Iida	f54619f	2014-09-18 12:09:42 +0900	[diff] [blame]	139	Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	140	The primary irqchip invokes the crossbar's callback which inturn allocates
				141	a free irq and configures the IP. Thus the peripheral interrupts are
				142	routed to one of the free irqchip interrupt lines.
Grygorii Strashko	89323f8	2014-07-23 17:40:30 +0300	[diff] [blame]	143
				144	config KEYSTONE_IRQ
				145	tristate "Keystone 2 IRQ controller IP"
				146	depends on ARCH_KEYSTONE
				147	help
				148	Support for Texas Instruments Keystone 2 IRQ controller IP which
				149	is part of the Keystone 2 IPC mechanism
Andrew Bresticker	8a19b8f	2014-09-18 14:47:19 -0700	[diff] [blame]	150
				151	config MIPS_GIC
				152	bool
				153	select MIPS_CM