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Kumar Gala0bbaf062005-06-20 10:54:21 -05001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * drivers/net/gianfar.h
3 *
4 * Gianfar Ethernet Driver
5 * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming
Kumar Gala4c8d3d92005-11-13 16:06:30 -08009 * Maintainer: Kumar Gala
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +000010 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 *
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +000012 * Copyright 2002-2009 Freescale Semiconductor, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 *
19 * Still left to do:
20 * -Add support for module parameters
Linus Torvalds1da177e2005-04-16 15:20:36 -070021 * -Add patch for ethtool phys id
22 */
23#ifndef __GIANFAR_H
24#define __GIANFAR_H
25
Linus Torvalds1da177e2005-04-16 15:20:36 -070026#include <linux/kernel.h>
27#include <linux/sched.h>
28#include <linux/string.h>
29#include <linux/errno.h>
30#include <linux/slab.h>
31#include <linux/interrupt.h>
32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/netdevice.h>
35#include <linux/etherdevice.h>
36#include <linux/skbuff.h>
37#include <linux/spinlock.h>
38#include <linux/mm.h>
Andy Flemingbb40dcb2005-09-23 22:54:21 -040039#include <linux/mii.h>
40#include <linux/phy.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070041
42#include <asm/io.h>
43#include <asm/irq.h>
44#include <asm/uaccess.h>
45#include <linux/module.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#include <linux/crc32.h>
47#include <linux/workqueue.h>
48#include <linux/ethtool.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070049
50/* The maximum number of packets to be handled in one call of gfar_poll */
51#define GFAR_DEV_WEIGHT 64
52
Kumar Gala0bbaf062005-06-20 10:54:21 -050053/* Length for FCB */
54#define GMAC_FCB_LEN 8
55
56/* Default padding amount */
57#define DEFAULT_PADDING 2
58
Linus Torvalds1da177e2005-04-16 15:20:36 -070059/* Number of bytes to align the rx bufs to */
60#define RXBUF_ALIGNMENT 64
61
62/* The number of bytes which composes a unit for the purpose of
63 * allocating data buffers. ie-for any given MTU, the data buffer
64 * will be the next highest multiple of 512 bytes. */
65#define INCREMENTAL_BUFFER_SIZE 512
66
67
68#define MAC_ADDR_LEN 6
69
70#define PHY_INIT_TIMEOUT 100000
71#define GFAR_PHY_CHANGE_TIME 2
72
Andy Flemingbb40dcb2005-09-23 22:54:21 -040073#define DEVICE_NAME "%s: Gianfar Ethernet Controller Version 1.2, "
Linus Torvalds1da177e2005-04-16 15:20:36 -070074#define DRV_NAME "gfar-enet"
75extern const char gfar_driver_name[];
76extern const char gfar_driver_version[];
77
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +000078/* MAXIMUM NUMBER OF QUEUES SUPPORTED */
79#define MAX_TX_QS 0x8
80#define MAX_RX_QS 0x8
81
Sandeep Gopalpet46ceb602009-11-02 07:03:34 +000082/* MAXIMUM NUMBER OF GROUPS SUPPORTED */
83#define MAXGROUPS 0x2
84
Linus Torvalds1da177e2005-04-16 15:20:36 -070085/* These need to be powers of 2 for this driver */
Linus Torvalds1da177e2005-04-16 15:20:36 -070086#define DEFAULT_TX_RING_SIZE 256
87#define DEFAULT_RX_RING_SIZE 256
Linus Torvalds1da177e2005-04-16 15:20:36 -070088
89#define GFAR_RX_MAX_RING_SIZE 256
90#define GFAR_TX_MAX_RING_SIZE 256
91
Andy Fleming7f7f5312005-11-11 12:38:59 -060092#define GFAR_MAX_FIFO_THRESHOLD 511
93#define GFAR_MAX_FIFO_STARVE 511
94#define GFAR_MAX_FIFO_STARVE_OFF 511
95
Linus Torvalds1da177e2005-04-16 15:20:36 -070096#define DEFAULT_RX_BUFFER_SIZE 1536
97#define TX_RING_MOD_MASK(size) (size-1)
98#define RX_RING_MOD_MASK(size) (size-1)
99#define JUMBO_BUFFER_SIZE 9728
100#define JUMBO_FRAME_SIZE 9600
101
Andy Fleming7f7f5312005-11-11 12:38:59 -0600102#define DEFAULT_FIFO_TX_THR 0x100
103#define DEFAULT_FIFO_TX_STARVE 0x40
104#define DEFAULT_FIFO_TX_STARVE_OFF 0x80
105#define DEFAULT_BD_STASH 1
Dai Harukia3cb96a2008-03-24 10:53:29 -0500106#define DEFAULT_STASH_LENGTH 96
Andy Fleming7f7f5312005-11-11 12:38:59 -0600107#define DEFAULT_STASH_INDEX 0
108
109/* The number of Exact Match registers */
110#define GFAR_EM_NUM 15
111
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112/* Latency of interface clock in nanoseconds */
Kumar Gala0bbaf062005-06-20 10:54:21 -0500113/* Interface clock latency , in this case, means the
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114 * time described by a value of 1 in the interrupt
115 * coalescing registers' time fields. Since those fields
116 * refer to the time it takes for 64 clocks to pass, the
117 * latencies are as such:
118 * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick
119 * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick
120 * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick
121 */
122#define GFAR_GBIT_TIME 512
123#define GFAR_100_TIME 2560
124#define GFAR_10_TIME 25600
125
126#define DEFAULT_TX_COALESCE 1
127#define DEFAULT_TXCOUNT 16
Andy Fleming2f448912008-03-24 10:53:28 -0500128#define DEFAULT_TXTIME 21
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129
Dai Harukid080cd62008-04-09 19:37:51 -0500130#define DEFAULT_RXTIME 21
131
Dai Harukid080cd62008-04-09 19:37:51 -0500132#define DEFAULT_RX_COALESCE 0
133#define DEFAULT_RXCOUNT 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134
Andy Fleming1577ece2009-02-04 16:42:12 -0800135#define GFAR_SUPPORTED (SUPPORTED_10baseT_Half \
136 | SUPPORTED_10baseT_Full \
137 | SUPPORTED_100baseT_Half \
138 | SUPPORTED_100baseT_Full \
139 | SUPPORTED_Autoneg \
140 | SUPPORTED_MII)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141
Kapil Junejad3c12872007-05-11 18:25:11 -0500142/* TBI register addresses */
143#define MII_TBICON 0x11
144
145/* TBICON register bit fields */
146#define TBICON_CLK_SELECT 0x0020
147
Linus Torvalds1da177e2005-04-16 15:20:36 -0700148/* MAC register bits */
149#define MACCFG1_SOFT_RESET 0x80000000
150#define MACCFG1_RESET_RX_MC 0x00080000
151#define MACCFG1_RESET_TX_MC 0x00040000
152#define MACCFG1_RESET_RX_FUN 0x00020000
153#define MACCFG1_RESET_TX_FUN 0x00010000
154#define MACCFG1_LOOPBACK 0x00000100
155#define MACCFG1_RX_FLOW 0x00000020
156#define MACCFG1_TX_FLOW 0x00000010
157#define MACCFG1_SYNCD_RX_EN 0x00000008
158#define MACCFG1_RX_EN 0x00000004
159#define MACCFG1_SYNCD_TX_EN 0x00000002
160#define MACCFG1_TX_EN 0x00000001
161
162#define MACCFG2_INIT_SETTINGS 0x00007205
163#define MACCFG2_FULL_DUPLEX 0x00000001
164#define MACCFG2_IF 0x00000300
165#define MACCFG2_MII 0x00000100
166#define MACCFG2_GMII 0x00000200
167#define MACCFG2_HUGEFRAME 0x00000020
168#define MACCFG2_LENGTHCHECK 0x00000010
Scott Woodd87eb122008-07-11 18:04:45 -0500169#define MACCFG2_MPEN 0x00000008
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170
171#define ECNTRL_INIT_SETTINGS 0x00001000
172#define ECNTRL_TBI_MODE 0x00000020
Andy Fleminge8a2b6a2006-12-01 12:01:06 -0600173#define ECNTRL_REDUCED_MODE 0x00000010
Andy Fleming7f7f5312005-11-11 12:38:59 -0600174#define ECNTRL_R100 0x00000008
Andy Fleminge8a2b6a2006-12-01 12:01:06 -0600175#define ECNTRL_REDUCED_MII_MODE 0x00000004
176#define ECNTRL_SGMII_MODE 0x00000002
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177
178#define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE
179
180#define MINFLR_INIT_SETTINGS 0x00000040
181
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +0000182/* Tqueue control */
183#define TQUEUE_EN0 0x00008000
184#define TQUEUE_EN1 0x00004000
185#define TQUEUE_EN2 0x00002000
186#define TQUEUE_EN3 0x00001000
187#define TQUEUE_EN4 0x00000800
188#define TQUEUE_EN5 0x00000400
189#define TQUEUE_EN6 0x00000200
190#define TQUEUE_EN7 0x00000100
191#define TQUEUE_EN_ALL 0x0000FF00
192
193#define TR03WT_WT0_MASK 0xFF000000
194#define TR03WT_WT1_MASK 0x00FF0000
195#define TR03WT_WT2_MASK 0x0000FF00
196#define TR03WT_WT3_MASK 0x000000FF
197
198#define TR47WT_WT4_MASK 0xFF000000
199#define TR47WT_WT5_MASK 0x00FF0000
200#define TR47WT_WT6_MASK 0x0000FF00
201#define TR47WT_WT7_MASK 0x000000FF
202
203/* Rqueue control */
204#define RQUEUE_EX0 0x00800000
205#define RQUEUE_EX1 0x00400000
206#define RQUEUE_EX2 0x00200000
207#define RQUEUE_EX3 0x00100000
208#define RQUEUE_EX4 0x00080000
209#define RQUEUE_EX5 0x00040000
210#define RQUEUE_EX6 0x00020000
211#define RQUEUE_EX7 0x00010000
212#define RQUEUE_EX_ALL 0x00FF0000
213
214#define RQUEUE_EN0 0x00000080
215#define RQUEUE_EN1 0x00000040
216#define RQUEUE_EN2 0x00000020
217#define RQUEUE_EN3 0x00000010
218#define RQUEUE_EN4 0x00000008
219#define RQUEUE_EN5 0x00000004
220#define RQUEUE_EN6 0x00000002
221#define RQUEUE_EN7 0x00000001
222#define RQUEUE_EN_ALL 0x000000FF
223
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224/* Init to do tx snooping for buffers and descriptors */
225#define DMACTRL_INIT_SETTINGS 0x000000c3
226#define DMACTRL_GRS 0x00000010
227#define DMACTRL_GTS 0x00000008
228
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +0000229#define TSTAT_CLEAR_THALT_ALL 0xFF000000
230#define TSTAT_CLEAR_THALT 0x80000000
231#define TSTAT_CLEAR_THALT0 0x80000000
232#define TSTAT_CLEAR_THALT1 0x40000000
233#define TSTAT_CLEAR_THALT2 0x20000000
234#define TSTAT_CLEAR_THALT3 0x10000000
235#define TSTAT_CLEAR_THALT4 0x08000000
236#define TSTAT_CLEAR_THALT5 0x04000000
237#define TSTAT_CLEAR_THALT6 0x02000000
238#define TSTAT_CLEAR_THALT7 0x01000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239
240/* Interrupt coalescing macros */
241#define IC_ICEN 0x80000000
242#define IC_ICFT_MASK 0x1fe00000
243#define IC_ICFT_SHIFT 21
244#define mk_ic_icft(x) \
245 (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
246#define IC_ICTT_MASK 0x0000ffff
247#define mk_ic_ictt(x) (x&IC_ICTT_MASK)
248
249#define mk_ic_value(count, time) (IC_ICEN | \
250 mk_ic_icft(count) | \
251 mk_ic_ictt(time))
Dai Harukib46a8452008-12-16 15:29:52 -0800252#define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \
253 IC_ICFT_SHIFT)
254#define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK)
255
256#define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME)
257#define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258
Andy Fleming31de1982008-12-16 15:33:40 -0800259#define skip_bd(bdp, stride, base, ring_size) ({ \
260 typeof(bdp) new_bd = (bdp) + (stride); \
261 (new_bd >= (base) + (ring_size)) ? (new_bd - (ring_size)) : new_bd; })
262
263#define next_bd(bdp, base, ring_size) skip_bd(bdp, 1, base, ring_size)
264
Kumar Gala0bbaf062005-06-20 10:54:21 -0500265#define RCTRL_PAL_MASK 0x001f0000
266#define RCTRL_VLEX 0x00002000
267#define RCTRL_FILREN 0x00001000
268#define RCTRL_GHTX 0x00000400
269#define RCTRL_IPCSEN 0x00000200
270#define RCTRL_TUCSEN 0x00000100
271#define RCTRL_PRSDEP_MASK 0x000000c0
272#define RCTRL_PRSDEP_INIT 0x000000c0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700273#define RCTRL_PROM 0x00000008
Andy Fleming7f7f5312005-11-11 12:38:59 -0600274#define RCTRL_EMEN 0x00000002
Dai Haruki77ecaf22008-12-16 15:30:48 -0800275#define RCTRL_REQ_PARSER (RCTRL_VLEX | RCTRL_IPCSEN | \
276 RCTRL_TUCSEN)
277#define RCTRL_CHECKSUMMING (RCTRL_IPCSEN | RCTRL_TUCSEN | \
278 RCTRL_PRSDEP_INIT)
Kumar Gala0bbaf062005-06-20 10:54:21 -0500279#define RCTRL_EXTHASH (RCTRL_GHTX)
280#define RCTRL_VLAN (RCTRL_PRSDEP_INIT)
Andy Fleming7f7f5312005-11-11 12:38:59 -0600281#define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK)
Kumar Gala0bbaf062005-06-20 10:54:21 -0500282
283
Linus Torvalds1da177e2005-04-16 15:20:36 -0700284#define RSTAT_CLEAR_RHALT 0x00800000
285
Kumar Gala0bbaf062005-06-20 10:54:21 -0500286#define TCTRL_IPCSEN 0x00004000
287#define TCTRL_TUCSEN 0x00002000
288#define TCTRL_VLINS 0x00001000
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +0000289#define TCTRL_THDF 0x00000800
290#define TCTRL_RFCPAUSE 0x00000010
291#define TCTRL_TFCPAUSE 0x00000008
292#define TCTRL_TXSCHED_MASK 0x00000006
293#define TCTRL_TXSCHED_INIT 0x00000000
294#define TCTRL_TXSCHED_PRIO 0x00000002
295#define TCTRL_TXSCHED_WRRS 0x00000004
Kumar Gala0bbaf062005-06-20 10:54:21 -0500296#define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
297
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298#define IEVENT_INIT_CLEAR 0xffffffff
299#define IEVENT_BABR 0x80000000
300#define IEVENT_RXC 0x40000000
301#define IEVENT_BSY 0x20000000
302#define IEVENT_EBERR 0x10000000
303#define IEVENT_MSRO 0x04000000
304#define IEVENT_GTSC 0x02000000
305#define IEVENT_BABT 0x01000000
306#define IEVENT_TXC 0x00800000
307#define IEVENT_TXE 0x00400000
308#define IEVENT_TXB 0x00200000
309#define IEVENT_TXF 0x00100000
310#define IEVENT_LC 0x00040000
311#define IEVENT_CRL 0x00020000
312#define IEVENT_XFUN 0x00010000
313#define IEVENT_RXB0 0x00008000
Scott Woodd87eb122008-07-11 18:04:45 -0500314#define IEVENT_MAG 0x00000800
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315#define IEVENT_GRSC 0x00000100
316#define IEVENT_RXF0 0x00000080
Kumar Gala0bbaf062005-06-20 10:54:21 -0500317#define IEVENT_FIR 0x00000008
318#define IEVENT_FIQ 0x00000004
319#define IEVENT_DPE 0x00000002
320#define IEVENT_PERR 0x00000001
Dai Haruki8c7396a2008-12-17 16:52:00 -0800321#define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700322#define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF)
Dai Harukid080cd62008-04-09 19:37:51 -0500323#define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700324#define IEVENT_ERR_MASK \
325(IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
326 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
Scott Woodd87eb122008-07-11 18:04:45 -0500327 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \
Xiaotian Feng18a36c12009-05-26 20:48:04 -0700328 | IEVENT_MAG | IEVENT_BABR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329
330#define IMASK_INIT_CLEAR 0x00000000
331#define IMASK_BABR 0x80000000
332#define IMASK_RXC 0x40000000
333#define IMASK_BSY 0x20000000
334#define IMASK_EBERR 0x10000000
335#define IMASK_MSRO 0x04000000
Sandeep Gopalpet7c65ec72009-12-16 01:15:17 +0000336#define IMASK_GTSC 0x02000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337#define IMASK_BABT 0x01000000
338#define IMASK_TXC 0x00800000
339#define IMASK_TXEEN 0x00400000
340#define IMASK_TXBEN 0x00200000
341#define IMASK_TXFEN 0x00100000
342#define IMASK_LC 0x00040000
343#define IMASK_CRL 0x00020000
344#define IMASK_XFUN 0x00010000
345#define IMASK_RXB0 0x00008000
Scott Woodd87eb122008-07-11 18:04:45 -0500346#define IMASK_MAG 0x00000800
Sandeep Gopalpet7c65ec72009-12-16 01:15:17 +0000347#define IMASK_GRSC 0x00000100
Linus Torvalds1da177e2005-04-16 15:20:36 -0700348#define IMASK_RXFEN0 0x00000080
Kumar Gala0bbaf062005-06-20 10:54:21 -0500349#define IMASK_FIR 0x00000008
350#define IMASK_FIQ 0x00000004
351#define IMASK_DPE 0x00000002
352#define IMASK_PERR 0x00000001
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353#define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
354 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
Kumar Gala0bbaf062005-06-20 10:54:21 -0500355 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
356 | IMASK_PERR)
Dai Harukid080cd62008-04-09 19:37:51 -0500357#define IMASK_RTX_DISABLED ((~(IMASK_RXFEN0 | IMASK_TXFEN | IMASK_BSY)) \
358 & IMASK_DEFAULT)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359
Andy Fleming7f7f5312005-11-11 12:38:59 -0600360/* Fifo management */
361#define FIFO_TX_THR_MASK 0x01ff
362#define FIFO_TX_STARVE_MASK 0x01ff
363#define FIFO_TX_STARVE_OFF_MASK 0x01ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700364
365/* Attribute fields */
366
367/* This enables rx snooping for buffers and descriptors */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700368#define ATTR_BDSTASH 0x00000800
Linus Torvalds1da177e2005-04-16 15:20:36 -0700369
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370#define ATTR_BUFSTASH 0x00004000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700371
372#define ATTR_SNOOPING 0x000000c0
Andy Fleming7f7f5312005-11-11 12:38:59 -0600373#define ATTR_INIT_SETTINGS ATTR_SNOOPING
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374
375#define ATTRELI_INIT_SETTINGS 0x0
Andy Fleming7f7f5312005-11-11 12:38:59 -0600376#define ATTRELI_EL_MASK 0x3fff0000
377#define ATTRELI_EL(x) (x << 16)
378#define ATTRELI_EI_MASK 0x00003fff
379#define ATTRELI_EI(x) (x)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380
Dai Haruki5a5efed2008-12-16 15:34:50 -0800381#define BD_LFLAG(flags) ((flags) << 16)
Andy Fleming1fbe4932009-02-04 16:37:40 -0800382#define BD_LENGTH_MASK 0x0000ffff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383
Sandeep Gopalpet7a8b3372009-11-02 07:03:40 +0000384#define CLASS_CODE_UNRECOG 0x00
385#define CLASS_CODE_DUMMY1 0x01
386#define CLASS_CODE_ETHERTYPE1 0x02
387#define CLASS_CODE_ETHERTYPE2 0x03
388#define CLASS_CODE_USER_PROG1 0x04
389#define CLASS_CODE_USER_PROG2 0x05
390#define CLASS_CODE_USER_PROG3 0x06
391#define CLASS_CODE_USER_PROG4 0x07
392#define CLASS_CODE_TCP_IPV4 0x08
393#define CLASS_CODE_UDP_IPV4 0x09
394#define CLASS_CODE_AH_ESP_IPV4 0x0a
395#define CLASS_CODE_SCTP_IPV4 0x0b
396#define CLASS_CODE_TCP_IPV6 0x0c
397#define CLASS_CODE_UDP_IPV6 0x0d
398#define CLASS_CODE_AH_ESP_IPV6 0x0e
399#define CLASS_CODE_SCTP_IPV6 0x0f
400
401#define FPR_FILER_MASK 0xFFFFFFFF
402#define MAX_FILER_IDX 0xFF
403
Sandeep Gopalpet1ccb8382009-12-16 01:14:58 +0000404/* This default RIR value directly corresponds
405 * to the 3-bit hash value generated */
406#define DEFAULT_RIR0 0x05397700
407
Sandeep Gopalpet7a8b3372009-11-02 07:03:40 +0000408/* RQFCR register bits */
409#define RQFCR_GPI 0x80000000
410#define RQFCR_HASHTBL_Q 0x00000000
411#define RQFCR_HASHTBL_0 0x00020000
412#define RQFCR_HASHTBL_1 0x00040000
413#define RQFCR_HASHTBL_2 0x00060000
414#define RQFCR_HASHTBL_3 0x00080000
415#define RQFCR_HASH 0x00010000
416#define RQFCR_CLE 0x00000200
417#define RQFCR_RJE 0x00000100
418#define RQFCR_AND 0x00000080
419#define RQFCR_CMP_EXACT 0x00000000
420#define RQFCR_CMP_MATCH 0x00000020
421#define RQFCR_CMP_NOEXACT 0x00000040
422#define RQFCR_CMP_NOMATCH 0x00000060
423
424/* RQFCR PID values */
425#define RQFCR_PID_MASK 0x00000000
426#define RQFCR_PID_PARSE 0x00000001
427#define RQFCR_PID_ARB 0x00000002
428#define RQFCR_PID_DAH 0x00000003
429#define RQFCR_PID_DAL 0x00000004
430#define RQFCR_PID_SAH 0x00000005
431#define RQFCR_PID_SAL 0x00000006
432#define RQFCR_PID_ETY 0x00000007
433#define RQFCR_PID_VID 0x00000008
434#define RQFCR_PID_PRI 0x00000009
435#define RQFCR_PID_TOS 0x0000000A
436#define RQFCR_PID_L4P 0x0000000B
437#define RQFCR_PID_DIA 0x0000000C
438#define RQFCR_PID_SIA 0x0000000D
439#define RQFCR_PID_DPT 0x0000000E
440#define RQFCR_PID_SPT 0x0000000F
441
442/* RQFPR when PID is 0x0001 */
443#define RQFPR_HDR_GE_512 0x00200000
444#define RQFPR_LERR 0x00100000
445#define RQFPR_RAR 0x00080000
446#define RQFPR_RARQ 0x00040000
447#define RQFPR_AR 0x00020000
448#define RQFPR_ARQ 0x00010000
449#define RQFPR_EBC 0x00008000
450#define RQFPR_VLN 0x00004000
451#define RQFPR_CFI 0x00002000
452#define RQFPR_JUM 0x00001000
453#define RQFPR_IPF 0x00000800
454#define RQFPR_FIF 0x00000400
455#define RQFPR_IPV4 0x00000200
456#define RQFPR_IPV6 0x00000100
457#define RQFPR_ICC 0x00000080
458#define RQFPR_ICV 0x00000040
459#define RQFPR_TCP 0x00000020
460#define RQFPR_UDP 0x00000010
461#define RQFPR_TUC 0x00000008
462#define RQFPR_TUV 0x00000004
463#define RQFPR_PER 0x00000002
464#define RQFPR_EER 0x00000001
465
Linus Torvalds1da177e2005-04-16 15:20:36 -0700466/* TxBD status field bits */
467#define TXBD_READY 0x8000
468#define TXBD_PADCRC 0x4000
469#define TXBD_WRAP 0x2000
470#define TXBD_INTERRUPT 0x1000
471#define TXBD_LAST 0x0800
472#define TXBD_CRC 0x0400
473#define TXBD_DEF 0x0200
474#define TXBD_HUGEFRAME 0x0080
475#define TXBD_LATECOLLISION 0x0080
476#define TXBD_RETRYLIMIT 0x0040
477#define TXBD_RETRYCOUNTMASK 0x003c
478#define TXBD_UNDERRUN 0x0002
Kumar Gala0bbaf062005-06-20 10:54:21 -0500479#define TXBD_TOE 0x0002
480
481/* Tx FCB param bits */
482#define TXFCB_VLN 0x80
483#define TXFCB_IP 0x40
484#define TXFCB_IP6 0x20
485#define TXFCB_TUP 0x10
486#define TXFCB_UDP 0x08
487#define TXFCB_CIP 0x04
488#define TXFCB_CTU 0x02
489#define TXFCB_NPH 0x01
490#define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700491
492/* RxBD status field bits */
493#define RXBD_EMPTY 0x8000
494#define RXBD_RO1 0x4000
495#define RXBD_WRAP 0x2000
496#define RXBD_INTERRUPT 0x1000
497#define RXBD_LAST 0x0800
498#define RXBD_FIRST 0x0400
499#define RXBD_MISS 0x0100
500#define RXBD_BROADCAST 0x0080
501#define RXBD_MULTICAST 0x0040
502#define RXBD_LARGE 0x0020
503#define RXBD_NONOCTET 0x0010
504#define RXBD_SHORT 0x0008
505#define RXBD_CRCERR 0x0004
506#define RXBD_OVERRUN 0x0002
507#define RXBD_TRUNCATED 0x0001
508#define RXBD_STATS 0x01ff
Andy Fleming99da5002008-03-24 10:53:27 -0500509#define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \
510 | RXBD_CRCERR | RXBD_OVERRUN \
511 | RXBD_TRUNCATED)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700512
Kumar Gala0bbaf062005-06-20 10:54:21 -0500513/* Rx FCB status field bits */
514#define RXFCB_VLN 0x8000
515#define RXFCB_IP 0x4000
516#define RXFCB_IP6 0x2000
517#define RXFCB_TUP 0x1000
518#define RXFCB_CIP 0x0800
519#define RXFCB_CTU 0x0400
520#define RXFCB_EIP 0x0200
521#define RXFCB_ETU 0x0100
Andy Fleming7f7f5312005-11-11 12:38:59 -0600522#define RXFCB_CSUM_MASK 0x0f00
Kumar Gala0bbaf062005-06-20 10:54:21 -0500523#define RXFCB_PERR_MASK 0x000c
524#define RXFCB_PERR_BADL3 0x0008
525
Dai Harukic50a5d92008-12-17 16:51:32 -0800526#define GFAR_INT_NAME_MAX IFNAMSIZ + 4
527
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528struct txbd8
529{
Dai Haruki5a5efed2008-12-16 15:34:50 -0800530 union {
531 struct {
532 u16 status; /* Status Fields */
533 u16 length; /* Buffer length */
534 };
535 u32 lstatus;
536 };
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537 u32 bufPtr; /* Buffer Pointer */
538};
539
Kumar Gala0bbaf062005-06-20 10:54:21 -0500540struct txfcb {
Andy Fleming7f7f5312005-11-11 12:38:59 -0600541 u8 flags;
Kumar Gala0bbaf062005-06-20 10:54:21 -0500542 u8 reserved;
543 u8 l4os; /* Level 4 Header Offset */
544 u8 l3os; /* Level 3 Header Offset */
545 u16 phcs; /* Pseudo-header Checksum */
546 u16 vlctl; /* VLAN control word */
547};
548
Linus Torvalds1da177e2005-04-16 15:20:36 -0700549struct rxbd8
550{
Dai Haruki5a5efed2008-12-16 15:34:50 -0800551 union {
552 struct {
553 u16 status; /* Status Fields */
554 u16 length; /* Buffer Length */
555 };
556 u32 lstatus;
557 };
Linus Torvalds1da177e2005-04-16 15:20:36 -0700558 u32 bufPtr; /* Buffer Pointer */
559};
560
Kumar Gala0bbaf062005-06-20 10:54:21 -0500561struct rxfcb {
Andy Fleming7f7f5312005-11-11 12:38:59 -0600562 u16 flags;
Kumar Gala0bbaf062005-06-20 10:54:21 -0500563 u8 rq; /* Receive Queue index */
564 u8 pro; /* Layer 4 Protocol */
565 u16 reserved;
566 u16 vlctl; /* VLAN control word */
567};
568
Linus Torvalds1da177e2005-04-16 15:20:36 -0700569struct rmon_mib
570{
571 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
572 u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
573 u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
574 u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
575 u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
576 u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
577 u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
578 u32 rbyt; /* 0x.69c - Receive Byte Counter */
579 u32 rpkt; /* 0x.6a0 - Receive Packet Counter */
580 u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */
581 u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */
582 u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */
583 u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */
584 u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */
585 u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */
586 u32 raln; /* 0x.6bc - Receive Alignment Error Counter */
587 u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */
588 u32 rcde; /* 0x.6c4 - Receive Code Error Counter */
589 u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */
590 u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */
591 u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */
592 u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */
593 u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */
594 u32 rdrp; /* 0x.6dc - Receive Drop Counter */
595 u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */
596 u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */
597 u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */
598 u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */
599 u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */
600 u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */
601 u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */
602 u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */
603 u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */
604 u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */
605 u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */
606 u32 tncl; /* 0x.70c - Transmit Total Collision Counter */
607 u8 res1[4];
608 u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */
609 u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */
610 u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */
611 u32 txcf; /* 0x.720 - Transmit Control Frame Counter */
612 u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */
613 u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */
614 u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */
615 u32 car1; /* 0x.730 - Carry Register One */
616 u32 car2; /* 0x.734 - Carry Register Two */
617 u32 cam1; /* 0x.738 - Carry Mask Register One */
618 u32 cam2; /* 0x.73c - Carry Mask Register Two */
619};
620
621struct gfar_extra_stats {
622 u64 kernel_dropped;
623 u64 rx_large;
624 u64 rx_short;
625 u64 rx_nonoctet;
626 u64 rx_crcerr;
627 u64 rx_overrun;
628 u64 rx_bsy;
629 u64 rx_babr;
630 u64 rx_trunc;
631 u64 eberr;
632 u64 tx_babt;
633 u64 tx_underrun;
634 u64 rx_skbmissing;
635 u64 tx_timeout;
636};
637
638#define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
639#define GFAR_EXTRA_STATS_LEN (sizeof(struct gfar_extra_stats)/sizeof(u64))
640
641/* Number of stats in the stats structure (ignore car and cam regs)*/
642#define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
643
644#define GFAR_INFOSTR_LEN 32
645
646struct gfar_stats {
647 u64 extra[GFAR_EXTRA_STATS_LEN];
648 u64 rmon[GFAR_RMON_LEN];
649};
650
651
652struct gfar {
Kumar Gala0bbaf062005-06-20 10:54:21 -0500653 u32 tsec_id; /* 0x.000 - Controller ID register */
Sandeep Gopalpet2e0246c2009-11-02 07:03:28 +0000654 u32 tsec_id2; /* 0x.004 - Controller ID2 register */
655 u8 res1[8];
Kumar Gala0bbaf062005-06-20 10:54:21 -0500656 u32 ievent; /* 0x.010 - Interrupt Event Register */
657 u32 imask; /* 0x.014 - Interrupt Mask Register */
658 u32 edis; /* 0x.018 - Error Disabled Register */
Sandeep Gopalpet2e0246c2009-11-02 07:03:28 +0000659 u32 emapg; /* 0x.01c - Group Error mapping register */
Kumar Gala0bbaf062005-06-20 10:54:21 -0500660 u32 ecntrl; /* 0x.020 - Ethernet Control Register */
661 u32 minflr; /* 0x.024 - Minimum Frame Length Register */
662 u32 ptv; /* 0x.028 - Pause Time Value Register */
663 u32 dmactrl; /* 0x.02c - DMA Control Register */
664 u32 tbipa; /* 0x.030 - TBI PHY Address Register */
Sandeep Gopalpet2e0246c2009-11-02 07:03:28 +0000665 u8 res2[28];
666 u32 fifo_rx_pause; /* 0x.050 - FIFO receive pause start threshold
667 register */
668 u32 fifo_rx_pause_shutoff; /* x.054 - FIFO receive starve shutoff
669 register */
670 u32 fifo_rx_alarm; /* 0x.058 - FIFO receive alarm start threshold
671 register */
672 u32 fifo_rx_alarm_shutoff; /*0x.05c - FIFO receive alarm starve
673 shutoff register */
674 u8 res3[44];
Kumar Gala0bbaf062005-06-20 10:54:21 -0500675 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700676 u8 res4[8];
Kumar Gala0bbaf062005-06-20 10:54:21 -0500677 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
Sandeep Gopalpet2e0246c2009-11-02 07:03:28 +0000679 u8 res5[96];
Kumar Gala0bbaf062005-06-20 10:54:21 -0500680 u32 tctrl; /* 0x.100 - Transmit Control Register */
681 u32 tstat; /* 0x.104 - Transmit Status Register */
682 u32 dfvlan; /* 0x.108 - Default VLAN Control word */
683 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
684 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
685 u32 tqueue; /* 0x.114 - Transmit queue control register */
686 u8 res7[40];
687 u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
688 u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
689 u8 res8[52];
690 u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */
691 u8 res9a[4];
692 u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */
693 u8 res9b[4];
694 u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */
695 u8 res9c[4];
696 u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */
697 u8 res9d[4];
698 u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */
699 u8 res9e[4];
700 u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */
701 u8 res9f[4];
702 u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */
703 u8 res9g[4];
704 u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */
705 u8 res9h[4];
706 u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */
707 u8 res9[64];
708 u32 tbaseh; /* 0x.200 - TxBD base address high */
709 u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */
710 u8 res10a[4];
711 u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */
712 u8 res10b[4];
713 u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */
714 u8 res10c[4];
715 u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */
716 u8 res10d[4];
717 u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */
718 u8 res10e[4];
719 u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */
720 u8 res10f[4];
721 u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */
722 u8 res10g[4];
723 u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */
724 u8 res10[192];
725 u32 rctrl; /* 0x.300 - Receive Control Register */
726 u32 rstat; /* 0x.304 - Receive Status Register */
727 u8 res12[8];
728 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
729 u32 rqueue; /* 0x.314 - Receive queue control register */
Sandeep Gopalpet2e0246c2009-11-02 07:03:28 +0000730 u32 rir0; /* 0x.318 - Ring mapping register 0 */
731 u32 rir1; /* 0x.31c - Ring mapping register 1 */
732 u32 rir2; /* 0x.320 - Ring mapping register 2 */
733 u32 rir3; /* 0x.324 - Ring mapping register 3 */
734 u8 res13[8];
Kumar Gala0bbaf062005-06-20 10:54:21 -0500735 u32 rbifx; /* 0x.330 - Receive bit field extract control register */
736 u32 rqfar; /* 0x.334 - Receive queue filing table address register */
737 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */
738 u32 rqfpr; /* 0x.33c - Receive queue filing table property register */
739 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
740 u8 res14[56];
741 u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */
742 u8 res15a[4];
743 u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */
744 u8 res15b[4];
745 u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */
746 u8 res15c[4];
747 u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */
748 u8 res15d[4];
749 u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */
750 u8 res15e[4];
751 u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */
752 u8 res15f[4];
753 u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */
754 u8 res15g[4];
755 u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */
756 u8 res15h[4];
757 u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */
758 u8 res16[64];
759 u32 rbaseh; /* 0x.400 - RxBD base address high */
760 u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */
761 u8 res17a[4];
762 u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */
763 u8 res17b[4];
764 u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */
765 u8 res17c[4];
766 u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */
767 u8 res17d[4];
768 u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */
769 u8 res17e[4];
770 u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */
771 u8 res17f[4];
772 u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */
773 u8 res17g[4];
774 u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */
775 u8 res17[192];
776 u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */
777 u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */
778 u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
779 u32 hafdup; /* 0x.50c - Half Duplex Register */
780 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781 u8 res18[12];
Andy Flemingbb40dcb2005-09-23 22:54:21 -0400782 u8 gfar_mii_regs[24]; /* See gianfar_phy.h */
Sandeep Gopalpet2e0246c2009-11-02 07:03:28 +0000783 u32 ifctrl; /* 0x.538 - Interface control register */
Kumar Gala0bbaf062005-06-20 10:54:21 -0500784 u32 ifstat; /* 0x.53c - Interface Status Register */
785 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
786 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
787 u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */
788 u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */
789 u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */
790 u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */
791 u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */
792 u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */
793 u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */
794 u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */
795 u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */
796 u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */
797 u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */
798 u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */
799 u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */
800 u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */
801 u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */
802 u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */
803 u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */
804 u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */
805 u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/
806 u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/
807 u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/
808 u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/
809 u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/
810 u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/
811 u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/
812 u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/
813 u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/
814 u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/
815 u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/
816 u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/
817 u8 res20[192];
818 struct rmon_mib rmon; /* 0x.680-0x.73c */
819 u32 rrej; /* 0x.740 - Receive filer rejected packet counter */
820 u8 res21[188];
821 u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/
822 u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/
823 u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/
824 u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/
825 u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/
826 u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/
827 u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/
828 u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700829 u8 res22[96];
Kumar Gala0bbaf062005-06-20 10:54:21 -0500830 u32 gaddr0; /* 0x.880 - Group address register 0 */
831 u32 gaddr1; /* 0x.884 - Group address register 1 */
832 u32 gaddr2; /* 0x.888 - Group address register 2 */
833 u32 gaddr3; /* 0x.88c - Group address register 3 */
834 u32 gaddr4; /* 0x.890 - Group address register 4 */
835 u32 gaddr5; /* 0x.894 - Group address register 5 */
836 u32 gaddr6; /* 0x.898 - Group address register 6 */
837 u32 gaddr7; /* 0x.89c - Group address register 7 */
838 u8 res23a[352];
839 u32 fifocfg; /* 0x.a00 - FIFO interface config register */
840 u8 res23b[252];
841 u8 res23c[248];
842 u32 attr; /* 0x.bf8 - Attributes Register */
843 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
Sandeep Gopalpet2e0246c2009-11-02 07:03:28 +0000844 u8 res24[688];
845 u32 isrg0; /* 0x.eb0 - Interrupt steering group 0 register */
846 u32 isrg1; /* 0x.eb4 - Interrupt steering group 1 register */
847 u32 isrg2; /* 0x.eb8 - Interrupt steering group 2 register */
848 u32 isrg3; /* 0x.ebc - Interrupt steering group 3 register */
849 u8 res25[16];
850 u32 rxic0; /* 0x.ed0 - Ring 0 Rx interrupt coalescing */
851 u32 rxic1; /* 0x.ed4 - Ring 1 Rx interrupt coalescing */
852 u32 rxic2; /* 0x.ed8 - Ring 2 Rx interrupt coalescing */
853 u32 rxic3; /* 0x.edc - Ring 3 Rx interrupt coalescing */
854 u32 rxic4; /* 0x.ee0 - Ring 4 Rx interrupt coalescing */
855 u32 rxic5; /* 0x.ee4 - Ring 5 Rx interrupt coalescing */
856 u32 rxic6; /* 0x.ee8 - Ring 6 Rx interrupt coalescing */
857 u32 rxic7; /* 0x.eec - Ring 7 Rx interrupt coalescing */
858 u8 res26[32];
859 u32 txic0; /* 0x.f10 - Ring 0 Tx interrupt coalescing */
860 u32 txic1; /* 0x.f14 - Ring 1 Tx interrupt coalescing */
861 u32 txic2; /* 0x.f18 - Ring 2 Tx interrupt coalescing */
862 u32 txic3; /* 0x.f1c - Ring 3 Tx interrupt coalescing */
863 u32 txic4; /* 0x.f20 - Ring 4 Tx interrupt coalescing */
864 u32 txic5; /* 0x.f24 - Ring 5 Tx interrupt coalescing */
865 u32 txic6; /* 0x.f28 - Ring 6 Tx interrupt coalescing */
866 u32 txic7; /* 0x.f2c - Ring 7 Tx interrupt coalescing */
867 u8 res27[208];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700868};
869
Andy Flemingb31a1d82008-12-16 15:29:15 -0800870/* Flags related to gianfar device features */
871#define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001
872#define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002
873#define FSL_GIANFAR_DEV_HAS_RMON 0x00000004
874#define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008
875#define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010
876#define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020
877#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040
878#define FSL_GIANFAR_DEV_HAS_PADDING 0x00000080
879#define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100
880#define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200
881#define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400
882
Sandeep Gopalpet46ceb602009-11-02 07:03:34 +0000883#if (MAXGROUPS == 2)
884#define DEFAULT_MAPPING 0xAA
885#else
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +0000886#define DEFAULT_MAPPING 0xFF
Sandeep Gopalpet46ceb602009-11-02 07:03:34 +0000887#endif
888
889#define ISRG_SHIFT_TX 0x10
890#define ISRG_SHIFT_RX 0x18
891
892/* The same driver can operate in two modes */
893/* SQ_SG_MODE: Single Queue Single Group Mode
894 * (Backward compatible mode)
895 * MQ_MG_MODE: Multi Queue Multi Group mode
896 */
897enum {
898 SQ_SG_MODE = 0,
899 MQ_MG_MODE
900};
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +0000901
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +0000902/**
903 * struct gfar_priv_tx_q - per tx queue structure
904 * @txlock: per queue tx spin lock
905 * @tx_skbuff:skb pointers
906 * @skb_curtx: to be used skb pointer
907 * @skb_dirtytx:the last used skb pointer
908 * @qindex: index of this queue
909 * @dev: back pointer to the dev structure
910 * @grp: back pointer to the group to which this queue belongs
911 * @tx_bd_base: First tx buffer descriptor
912 * @cur_tx: Next free ring entry
913 * @dirty_tx: First buffer in line to be transmitted
914 * @tx_ring_size: Tx ring size
915 * @num_txbdfree: number of free TxBds
916 * @txcoalescing: enable/disable tx coalescing
917 * @txic: transmit interrupt coalescing value
918 * @txcount: coalescing value if based on tx frame count
919 * @txtime: coalescing value if based on time
920 */
921struct gfar_priv_tx_q {
922 spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
923 struct sk_buff ** tx_skbuff;
924 /* Buffer descriptor pointers */
925 dma_addr_t tx_bd_dma_base;
926 struct txbd8 *tx_bd_base;
927 struct txbd8 *cur_tx;
928 struct txbd8 *dirty_tx;
929 struct net_device *dev;
Sandeep Gopalpet46ceb602009-11-02 07:03:34 +0000930 struct gfar_priv_grp *grp;
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +0000931 u16 skb_curtx;
932 u16 skb_dirtytx;
933 u16 qindex;
934 unsigned int tx_ring_size;
935 unsigned int num_txbdfree;
936 /* Configuration info for the coalescing features */
937 unsigned char txcoalescing;
938 unsigned long txic;
939 unsigned short txcount;
940 unsigned short txtime;
941};
942
Sandeep Gopalpeta7f38042009-12-16 01:15:07 +0000943/*
944 * Per RX queue stats
945 */
946struct rx_q_stats {
947 unsigned long rx_packets;
948 unsigned long rx_bytes;
949 unsigned long rx_dropped;
950};
951
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +0000952/**
953 * struct gfar_priv_rx_q - per rx queue structure
954 * @rxlock: per queue rx spin lock
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +0000955 * @rx_skbuff: skb pointers
956 * @skb_currx: currently use skb pointer
957 * @rx_bd_base: First rx buffer descriptor
958 * @cur_rx: Next free rx ring entry
959 * @qindex: index of this queue
960 * @dev: back pointer to the dev structure
961 * @rx_ring_size: Rx ring size
962 * @rxcoalescing: enable/disable rx-coalescing
963 * @rxic: receive interrupt coalescing vlaue
964 */
965
966struct gfar_priv_rx_q {
967 spinlock_t rxlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +0000968 struct sk_buff ** rx_skbuff;
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +0000969 dma_addr_t rx_bd_dma_base;
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +0000970 struct rxbd8 *rx_bd_base;
971 struct rxbd8 *cur_rx;
972 struct net_device *dev;
Sandeep Gopalpet46ceb602009-11-02 07:03:34 +0000973 struct gfar_priv_grp *grp;
Sandeep Gopalpeta7f38042009-12-16 01:15:07 +0000974 struct rx_q_stats stats;
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +0000975 u16 skb_currx;
976 u16 qindex;
977 unsigned int rx_ring_size;
978 /* RX Coalescing values */
979 unsigned char rxcoalescing;
980 unsigned long rxic;
981};
982
Sandeep Gopalpetf4983702009-11-02 07:03:09 +0000983/**
984 * struct gfar_priv_grp - per group structure
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +0000985 * @napi: the napi poll function
Sandeep Gopalpetf4983702009-11-02 07:03:09 +0000986 * @priv: back pointer to the priv structure
987 * @regs: the ioremapped register space for this group
988 * @grp_id: group id for this group
989 * @interruptTransmit: The TX interrupt number for this group
990 * @interruptReceive: The RX interrupt number for this group
991 * @interruptError: The ERROR interrupt number for this group
992 * @int_name_tx: tx interrupt name for this group
993 * @int_name_rx: rx interrupt name for this group
994 * @int_name_er: er interrupt name for this group
995 */
996
997struct gfar_priv_grp {
998 spinlock_t grplock __attribute__ ((aligned (SMP_CACHE_BYTES)));
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +0000999 struct napi_struct napi;
Sandeep Gopalpetf4983702009-11-02 07:03:09 +00001000 struct gfar_private *priv;
1001 struct gfar __iomem *regs;
Sandeep Gopalpet46ceb602009-11-02 07:03:34 +00001002 unsigned int grp_id;
Anton Vorontsov18294ad2009-11-04 12:53:00 +00001003 unsigned long rx_bit_map;
1004 unsigned long tx_bit_map;
1005 unsigned long num_tx_queues;
1006 unsigned long num_rx_queues;
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +00001007 unsigned int rstat;
1008 unsigned int tstat;
1009 unsigned int imask;
1010 unsigned int ievent;
Sandeep Gopalpetf4983702009-11-02 07:03:09 +00001011 unsigned int interruptTransmit;
1012 unsigned int interruptReceive;
1013 unsigned int interruptError;
1014
1015 char int_name_tx[GFAR_INT_NAME_MAX];
1016 char int_name_rx[GFAR_INT_NAME_MAX];
1017 char int_name_er[GFAR_INT_NAME_MAX];
1018};
1019
Linus Torvalds1da177e2005-04-16 15:20:36 -07001020/* Struct stolen almost completely (and shamelessly) from the FCC enet source
1021 * (Ok, that's not so true anymore, but there is a family resemblence)
1022 * The GFAR buffer descriptors track the ring buffers. The rx_bd_base
1023 * and tx_bd_base always point to the currently available buffer.
1024 * The dirty_tx tracks the current buffer that is being sent by the
1025 * controller. The cur_tx and dirty_tx are equal under both completely
1026 * empty and completely full conditions. The empty/ready indicator in
1027 * the buffer descriptor determines the actual condition.
1028 */
1029struct gfar_private {
Andy Flemingfef61082006-04-20 16:44:29 -05001030
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +00001031 /* Indicates how many tx, rx queues are enabled */
1032 unsigned int num_tx_queues;
1033 unsigned int num_rx_queues;
Sandeep Gopalpet46ceb602009-11-02 07:03:34 +00001034 unsigned int num_grps;
1035 unsigned int mode;
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +00001036
1037 /* The total tx and rx ring size for the enabled queues */
1038 unsigned int total_tx_ring_size;
1039 unsigned int total_rx_ring_size;
1040
Andy Flemingb31a1d82008-12-16 15:29:15 -08001041 struct device_node *node;
Kumar Gala48268572009-03-18 23:28:22 -07001042 struct net_device *ndev;
1043 struct of_device *ofdev;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001044
Sandeep Gopalpet46ceb602009-11-02 07:03:34 +00001045 struct gfar_priv_grp gfargrp[MAXGROUPS];
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +00001046 struct gfar_priv_tx_q *tx_queue[MAX_TX_QS];
1047 struct gfar_priv_rx_q *rx_queue[MAX_RX_QS];
Andy Flemingfef61082006-04-20 16:44:29 -05001048
Sandeep Gopalpeta12f8012009-11-02 07:03:00 +00001049 /* RX per device parameters */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001050 unsigned int rx_buffer_size;
1051 unsigned int rx_stash_size;
Andy Fleming7f7f5312005-11-11 12:38:59 -06001052 unsigned int rx_stash_index;
Andy Flemingfef61082006-04-20 16:44:29 -05001053
Sandeep Gopalpet7a8b3372009-11-02 07:03:40 +00001054 u32 cur_filer_idx;
1055
Andy Fleming0fd56bb2009-02-04 16:43:16 -08001056 struct sk_buff_head rx_recycle;
1057
Andy Flemingfef61082006-04-20 16:44:29 -05001058 struct vlan_group *vlgrp;
1059
Andy Flemingfef61082006-04-20 16:44:29 -05001060
1061 /* Hash registers and their width */
1062 u32 __iomem *hash_regs[16];
1063 int hash_width;
1064
1065 /* global parameters */
Andy Fleming7f7f5312005-11-11 12:38:59 -06001066 unsigned int fifo_threshold;
1067 unsigned int fifo_starve;
1068 unsigned int fifo_starve_off;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001069
Scott Woodd87eb122008-07-11 18:04:45 -05001070 /* Bitfield update lock */
1071 spinlock_t bflock;
1072
Andy Flemingb31a1d82008-12-16 15:29:15 -08001073 phy_interface_t interface;
Grant Likelyfe192a42009-04-25 12:53:12 +00001074 struct device_node *phy_node;
1075 struct device_node *tbi_node;
Andy Flemingb31a1d82008-12-16 15:29:15 -08001076 u32 device_flags;
Dai Haruki77ecaf22008-12-16 15:30:48 -08001077 unsigned char rx_csum_enable:1,
Andy Fleming7f7f5312005-11-11 12:38:59 -06001078 extended_hash:1,
Scott Woodd87eb122008-07-11 18:04:45 -05001079 bd_stash_en:1,
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +00001080 rx_filer_enable:1,
Scott Woodd87eb122008-07-11 18:04:45 -05001081 wol_en:1; /* Wake-on-LAN enabled */
Kumar Gala0bbaf062005-06-20 10:54:21 -05001082 unsigned short padding;
Andy Flemingfef61082006-04-20 16:44:29 -05001083
Andy Flemingfef61082006-04-20 16:44:29 -05001084 /* PHY stuff */
Andy Flemingbb40dcb2005-09-23 22:54:21 -04001085 struct phy_device *phydev;
1086 struct mii_bus *mii_bus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001087 int oldspeed;
1088 int oldduplex;
1089 int oldlink;
Kumar Gala0bbaf062005-06-20 10:54:21 -05001090
1091 uint32_t msg_enable;
Andy Flemingfef61082006-04-20 16:44:29 -05001092
Sebastian Siewiorab939902008-08-19 21:12:45 +02001093 struct work_struct reset_task;
Dai Harukic50a5d92008-12-17 16:51:32 -08001094
Andy Flemingfef61082006-04-20 16:44:29 -05001095 /* Network Statistics */
Andy Flemingfef61082006-04-20 16:44:29 -05001096 struct gfar_extra_stats extra_stats;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001097};
1098
Sandeep Gopalpet7a8b3372009-11-02 07:03:40 +00001099extern unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
1100extern unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
1101
Kumar Galacc8c6e32006-02-01 15:18:03 -06001102static inline u32 gfar_read(volatile unsigned __iomem *addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001103{
1104 u32 val;
1105 val = in_be32(addr);
1106 return val;
1107}
1108
Kumar Galacc8c6e32006-02-01 15:18:03 -06001109static inline void gfar_write(volatile unsigned __iomem *addr, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001110{
1111 out_be32(addr, val);
1112}
1113
Sandeep Gopalpet7a8b3372009-11-02 07:03:40 +00001114static inline void gfar_write_filer(struct gfar_private *priv,
1115 unsigned int far, unsigned int fcr, unsigned int fpr)
1116{
1117 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1118
1119 gfar_write(&regs->rqfar, far);
1120 gfar_write(&regs->rqfcr, fcr);
1121 gfar_write(&regs->rqfpr, fpr);
1122}
1123
Sandeep Gopalpetfba4ed02009-11-02 07:03:15 +00001124extern void lock_rx_qs(struct gfar_private *priv);
1125extern void lock_tx_qs(struct gfar_private *priv);
1126extern void unlock_rx_qs(struct gfar_private *priv);
1127extern void unlock_tx_qs(struct gfar_private *priv);
David Howells7d12e782006-10-05 14:55:46 +01001128extern irqreturn_t gfar_receive(int irq, void *dev_id);
Andy Flemingbb40dcb2005-09-23 22:54:21 -04001129extern int startup_gfar(struct net_device *dev);
1130extern void stop_gfar(struct net_device *dev);
1131extern void gfar_halt(struct net_device *dev);
1132extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev,
1133 int enable, u32 regnum, u32 read);
Sandeep Gopalpet46ceb602009-11-02 07:03:34 +00001134extern void gfar_configure_coalescing(struct gfar_private *priv,
Anton Vorontsov18294ad2009-11-04 12:53:00 +00001135 unsigned long tx_mask, unsigned long rx_mask);
Andy Fleming7f7f5312005-11-11 12:38:59 -06001136void gfar_init_sysfs(struct net_device *dev);
Andy Flemingbb40dcb2005-09-23 22:54:21 -04001137
Anton Vorontsovb2f66d12009-02-01 00:54:16 -08001138extern const struct ethtool_ops gfar_ethtool_ops;
1139
Linus Torvalds1da177e2005-04-16 15:20:36 -07001140#endif /* __GIANFAR_H */