Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-at91/at91cap9.c |
| 3 | * |
| 4 | * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com> |
| 5 | * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com> |
| 6 | * Copyright (C) 2007 Atmel Corporation. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #include <linux/module.h> |
| 16 | |
Russell King | 80b02c1 | 2009-01-08 10:01:47 +0000 | [diff] [blame] | 17 | #include <asm/irq.h> |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 18 | #include <asm/mach/arch.h> |
| 19 | #include <asm/mach/map.h> |
Stelian Pop | 7be90a6 | 2008-10-22 13:52:08 +0100 | [diff] [blame] | 20 | |
| 21 | #include <mach/cpu.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 22 | #include <mach/at91cap9.h> |
| 23 | #include <mach/at91_pmc.h> |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 24 | |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 25 | #include "soc.h" |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 26 | #include "generic.h" |
| 27 | #include "clock.h" |
Jean-Christophe PLAGNIOL-VILLARD | faee0cc | 2011-10-14 01:37:09 +0800 | [diff] [blame] | 28 | #include "sam9_smc.h" |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 29 | |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 30 | /* -------------------------------------------------------------------- |
| 31 | * Clocks |
| 32 | * -------------------------------------------------------------------- */ |
| 33 | |
| 34 | /* |
| 35 | * The peripheral clocks. |
| 36 | */ |
| 37 | static struct clk pioABCD_clk = { |
| 38 | .name = "pioABCD_clk", |
| 39 | .pmc_mask = 1 << AT91CAP9_ID_PIOABCD, |
| 40 | .type = CLK_TYPE_PERIPHERAL, |
| 41 | }; |
| 42 | static struct clk mpb0_clk = { |
| 43 | .name = "mpb0_clk", |
| 44 | .pmc_mask = 1 << AT91CAP9_ID_MPB0, |
| 45 | .type = CLK_TYPE_PERIPHERAL, |
| 46 | }; |
| 47 | static struct clk mpb1_clk = { |
| 48 | .name = "mpb1_clk", |
| 49 | .pmc_mask = 1 << AT91CAP9_ID_MPB1, |
| 50 | .type = CLK_TYPE_PERIPHERAL, |
| 51 | }; |
| 52 | static struct clk mpb2_clk = { |
| 53 | .name = "mpb2_clk", |
| 54 | .pmc_mask = 1 << AT91CAP9_ID_MPB2, |
| 55 | .type = CLK_TYPE_PERIPHERAL, |
| 56 | }; |
| 57 | static struct clk mpb3_clk = { |
| 58 | .name = "mpb3_clk", |
| 59 | .pmc_mask = 1 << AT91CAP9_ID_MPB3, |
| 60 | .type = CLK_TYPE_PERIPHERAL, |
| 61 | }; |
| 62 | static struct clk mpb4_clk = { |
| 63 | .name = "mpb4_clk", |
| 64 | .pmc_mask = 1 << AT91CAP9_ID_MPB4, |
| 65 | .type = CLK_TYPE_PERIPHERAL, |
| 66 | }; |
| 67 | static struct clk usart0_clk = { |
| 68 | .name = "usart0_clk", |
| 69 | .pmc_mask = 1 << AT91CAP9_ID_US0, |
| 70 | .type = CLK_TYPE_PERIPHERAL, |
| 71 | }; |
| 72 | static struct clk usart1_clk = { |
| 73 | .name = "usart1_clk", |
| 74 | .pmc_mask = 1 << AT91CAP9_ID_US1, |
| 75 | .type = CLK_TYPE_PERIPHERAL, |
| 76 | }; |
| 77 | static struct clk usart2_clk = { |
| 78 | .name = "usart2_clk", |
| 79 | .pmc_mask = 1 << AT91CAP9_ID_US2, |
| 80 | .type = CLK_TYPE_PERIPHERAL, |
| 81 | }; |
| 82 | static struct clk mmc0_clk = { |
| 83 | .name = "mci0_clk", |
| 84 | .pmc_mask = 1 << AT91CAP9_ID_MCI0, |
| 85 | .type = CLK_TYPE_PERIPHERAL, |
| 86 | }; |
| 87 | static struct clk mmc1_clk = { |
| 88 | .name = "mci1_clk", |
| 89 | .pmc_mask = 1 << AT91CAP9_ID_MCI1, |
| 90 | .type = CLK_TYPE_PERIPHERAL, |
| 91 | }; |
| 92 | static struct clk can_clk = { |
| 93 | .name = "can_clk", |
| 94 | .pmc_mask = 1 << AT91CAP9_ID_CAN, |
| 95 | .type = CLK_TYPE_PERIPHERAL, |
| 96 | }; |
| 97 | static struct clk twi_clk = { |
| 98 | .name = "twi_clk", |
| 99 | .pmc_mask = 1 << AT91CAP9_ID_TWI, |
| 100 | .type = CLK_TYPE_PERIPHERAL, |
| 101 | }; |
| 102 | static struct clk spi0_clk = { |
| 103 | .name = "spi0_clk", |
| 104 | .pmc_mask = 1 << AT91CAP9_ID_SPI0, |
| 105 | .type = CLK_TYPE_PERIPHERAL, |
| 106 | }; |
| 107 | static struct clk spi1_clk = { |
| 108 | .name = "spi1_clk", |
| 109 | .pmc_mask = 1 << AT91CAP9_ID_SPI1, |
| 110 | .type = CLK_TYPE_PERIPHERAL, |
| 111 | }; |
| 112 | static struct clk ssc0_clk = { |
| 113 | .name = "ssc0_clk", |
| 114 | .pmc_mask = 1 << AT91CAP9_ID_SSC0, |
| 115 | .type = CLK_TYPE_PERIPHERAL, |
| 116 | }; |
| 117 | static struct clk ssc1_clk = { |
| 118 | .name = "ssc1_clk", |
| 119 | .pmc_mask = 1 << AT91CAP9_ID_SSC1, |
| 120 | .type = CLK_TYPE_PERIPHERAL, |
| 121 | }; |
| 122 | static struct clk ac97_clk = { |
| 123 | .name = "ac97_clk", |
| 124 | .pmc_mask = 1 << AT91CAP9_ID_AC97C, |
| 125 | .type = CLK_TYPE_PERIPHERAL, |
| 126 | }; |
| 127 | static struct clk tcb_clk = { |
| 128 | .name = "tcb_clk", |
| 129 | .pmc_mask = 1 << AT91CAP9_ID_TCB, |
| 130 | .type = CLK_TYPE_PERIPHERAL, |
| 131 | }; |
Andrew Victor | bb1ad68 | 2008-09-18 19:42:37 +0100 | [diff] [blame] | 132 | static struct clk pwm_clk = { |
| 133 | .name = "pwm_clk", |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 134 | .pmc_mask = 1 << AT91CAP9_ID_PWMC, |
| 135 | .type = CLK_TYPE_PERIPHERAL, |
| 136 | }; |
| 137 | static struct clk macb_clk = { |
Jamie Iles | 865d605 | 2011-08-09 16:51:11 +0200 | [diff] [blame] | 138 | .name = "pclk", |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 139 | .pmc_mask = 1 << AT91CAP9_ID_EMAC, |
| 140 | .type = CLK_TYPE_PERIPHERAL, |
| 141 | }; |
| 142 | static struct clk aestdes_clk = { |
| 143 | .name = "aestdes_clk", |
| 144 | .pmc_mask = 1 << AT91CAP9_ID_AESTDES, |
| 145 | .type = CLK_TYPE_PERIPHERAL, |
| 146 | }; |
| 147 | static struct clk adc_clk = { |
| 148 | .name = "adc_clk", |
| 149 | .pmc_mask = 1 << AT91CAP9_ID_ADC, |
| 150 | .type = CLK_TYPE_PERIPHERAL, |
| 151 | }; |
| 152 | static struct clk isi_clk = { |
| 153 | .name = "isi_clk", |
| 154 | .pmc_mask = 1 << AT91CAP9_ID_ISI, |
| 155 | .type = CLK_TYPE_PERIPHERAL, |
| 156 | }; |
| 157 | static struct clk lcdc_clk = { |
| 158 | .name = "lcdc_clk", |
| 159 | .pmc_mask = 1 << AT91CAP9_ID_LCDC, |
| 160 | .type = CLK_TYPE_PERIPHERAL, |
| 161 | }; |
| 162 | static struct clk dma_clk = { |
| 163 | .name = "dma_clk", |
| 164 | .pmc_mask = 1 << AT91CAP9_ID_DMA, |
| 165 | .type = CLK_TYPE_PERIPHERAL, |
| 166 | }; |
| 167 | static struct clk udphs_clk = { |
| 168 | .name = "udphs_clk", |
| 169 | .pmc_mask = 1 << AT91CAP9_ID_UDPHS, |
| 170 | .type = CLK_TYPE_PERIPHERAL, |
| 171 | }; |
| 172 | static struct clk ohci_clk = { |
| 173 | .name = "ohci_clk", |
| 174 | .pmc_mask = 1 << AT91CAP9_ID_UHP, |
| 175 | .type = CLK_TYPE_PERIPHERAL, |
| 176 | }; |
| 177 | |
| 178 | static struct clk *periph_clocks[] __initdata = { |
| 179 | &pioABCD_clk, |
| 180 | &mpb0_clk, |
| 181 | &mpb1_clk, |
| 182 | &mpb2_clk, |
| 183 | &mpb3_clk, |
| 184 | &mpb4_clk, |
| 185 | &usart0_clk, |
| 186 | &usart1_clk, |
| 187 | &usart2_clk, |
| 188 | &mmc0_clk, |
| 189 | &mmc1_clk, |
| 190 | &can_clk, |
| 191 | &twi_clk, |
| 192 | &spi0_clk, |
| 193 | &spi1_clk, |
| 194 | &ssc0_clk, |
| 195 | &ssc1_clk, |
| 196 | &ac97_clk, |
| 197 | &tcb_clk, |
Andrew Victor | bb1ad68 | 2008-09-18 19:42:37 +0100 | [diff] [blame] | 198 | &pwm_clk, |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 199 | &macb_clk, |
| 200 | &aestdes_clk, |
| 201 | &adc_clk, |
| 202 | &isi_clk, |
| 203 | &lcdc_clk, |
| 204 | &dma_clk, |
| 205 | &udphs_clk, |
| 206 | &ohci_clk, |
| 207 | // irq0 .. irq1 |
| 208 | }; |
| 209 | |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 210 | static struct clk_lookup periph_clocks_lookups[] = { |
Jamie Iles | 865d605 | 2011-08-09 16:51:11 +0200 | [diff] [blame] | 211 | /* One additional fake clock for macb_hclk */ |
| 212 | CLKDEV_CON_ID("hclk", &macb_clk), |
Jean-Christophe PLAGNIOL-VILLARD | 9d87159 | 2011-06-21 14:24:33 +0800 | [diff] [blame] | 213 | CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk), |
| 214 | CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk), |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 215 | CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk), |
| 216 | CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk), |
| 217 | CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), |
| 218 | CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), |
| 219 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk), |
Joachim Eastwood | c5efefa | 2011-06-02 01:36:09 +0200 | [diff] [blame] | 220 | CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), |
| 221 | CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), |
Jean-Christophe PLAGNIOL-VILLARD | 0af4316 | 2011-08-30 03:29:28 +0200 | [diff] [blame] | 222 | /* fake hclk clock */ |
| 223 | CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), |
Jean-Christophe PLAGNIOL-VILLARD | 619d4a4 | 2011-11-13 13:00:58 +0800 | [diff] [blame] | 224 | CLKDEV_CON_ID("pioA", &pioABCD_clk), |
| 225 | CLKDEV_CON_ID("pioB", &pioABCD_clk), |
| 226 | CLKDEV_CON_ID("pioC", &pioABCD_clk), |
| 227 | CLKDEV_CON_ID("pioD", &pioABCD_clk), |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 228 | }; |
| 229 | |
| 230 | static struct clk_lookup usart_clocks_lookups[] = { |
| 231 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck), |
| 232 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk), |
| 233 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk), |
| 234 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk), |
| 235 | }; |
| 236 | |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 237 | /* |
| 238 | * The four programmable clocks. |
| 239 | * You must configure pin multiplexing to bring these signals out. |
| 240 | */ |
| 241 | static struct clk pck0 = { |
| 242 | .name = "pck0", |
| 243 | .pmc_mask = AT91_PMC_PCK0, |
| 244 | .type = CLK_TYPE_PROGRAMMABLE, |
| 245 | .id = 0, |
| 246 | }; |
| 247 | static struct clk pck1 = { |
| 248 | .name = "pck1", |
| 249 | .pmc_mask = AT91_PMC_PCK1, |
| 250 | .type = CLK_TYPE_PROGRAMMABLE, |
| 251 | .id = 1, |
| 252 | }; |
| 253 | static struct clk pck2 = { |
| 254 | .name = "pck2", |
| 255 | .pmc_mask = AT91_PMC_PCK2, |
| 256 | .type = CLK_TYPE_PROGRAMMABLE, |
| 257 | .id = 2, |
| 258 | }; |
| 259 | static struct clk pck3 = { |
| 260 | .name = "pck3", |
| 261 | .pmc_mask = AT91_PMC_PCK3, |
| 262 | .type = CLK_TYPE_PROGRAMMABLE, |
| 263 | .id = 3, |
| 264 | }; |
| 265 | |
| 266 | static void __init at91cap9_register_clocks(void) |
| 267 | { |
| 268 | int i; |
| 269 | |
| 270 | for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) |
| 271 | clk_register(periph_clocks[i]); |
| 272 | |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 273 | clkdev_add_table(periph_clocks_lookups, |
| 274 | ARRAY_SIZE(periph_clocks_lookups)); |
| 275 | clkdev_add_table(usart_clocks_lookups, |
| 276 | ARRAY_SIZE(usart_clocks_lookups)); |
| 277 | |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 278 | clk_register(&pck0); |
| 279 | clk_register(&pck1); |
| 280 | clk_register(&pck2); |
| 281 | clk_register(&pck3); |
| 282 | } |
| 283 | |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 284 | static struct clk_lookup console_clock_lookup; |
| 285 | |
| 286 | void __init at91cap9_set_console_clock(int id) |
| 287 | { |
| 288 | if (id >= ARRAY_SIZE(usart_clocks_lookups)) |
| 289 | return; |
| 290 | |
| 291 | console_clock_lookup.con_id = "usart"; |
| 292 | console_clock_lookup.clk = usart_clocks_lookups[id].clk; |
| 293 | clkdev_add(&console_clock_lookup); |
| 294 | } |
| 295 | |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 296 | /* -------------------------------------------------------------------- |
| 297 | * GPIO |
| 298 | * -------------------------------------------------------------------- */ |
| 299 | |
Jean-Christophe PLAGNIOL-VILLARD | 1a2d915 | 2011-10-17 14:28:38 +0800 | [diff] [blame] | 300 | static struct at91_gpio_bank at91cap9_gpio[] __initdata = { |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 301 | { |
| 302 | .id = AT91CAP9_ID_PIOABCD, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 303 | .regbase = AT91CAP9_BASE_PIOA, |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 304 | }, { |
| 305 | .id = AT91CAP9_ID_PIOABCD, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 306 | .regbase = AT91CAP9_BASE_PIOB, |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 307 | }, { |
| 308 | .id = AT91CAP9_ID_PIOABCD, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 309 | .regbase = AT91CAP9_BASE_PIOC, |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 310 | }, { |
| 311 | .id = AT91CAP9_ID_PIOABCD, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 312 | .regbase = AT91CAP9_BASE_PIOD, |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 313 | } |
| 314 | }; |
| 315 | |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 316 | /* -------------------------------------------------------------------- |
| 317 | * AT91CAP9 processor initialization |
| 318 | * -------------------------------------------------------------------- */ |
| 319 | |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 320 | static void __init at91cap9_map_io(void) |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 321 | { |
Jean-Christophe PLAGNIOL-VILLARD | f0051d8 | 2011-05-10 03:20:09 +0800 | [diff] [blame] | 322 | at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE); |
Jean-Christophe PLAGNIOL-VILLARD | 1b021a3 | 2011-04-28 20:19:32 +0800 | [diff] [blame] | 323 | } |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 324 | |
Jean-Christophe PLAGNIOL-VILLARD | cfa5a1f | 2011-10-14 01:17:18 +0800 | [diff] [blame] | 325 | static void __init at91cap9_ioremap_registers(void) |
| 326 | { |
Jean-Christophe PLAGNIOL-VILLARD | f22deee | 2011-11-01 01:23:20 +0800 | [diff] [blame] | 327 | at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC); |
Jean-Christophe PLAGNIOL-VILLARD | e9f68b5 | 2011-11-18 01:25:52 +0800 | [diff] [blame] | 328 | at91_ioremap_rstc(AT91CAP9_BASE_RSTC); |
Jean-Christophe PLAGNIOL-VILLARD | 4ab0c599 | 2011-09-18 22:29:50 +0800 | [diff] [blame] | 329 | at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT); |
Jean-Christophe PLAGNIOL-VILLARD | faee0cc | 2011-10-14 01:37:09 +0800 | [diff] [blame] | 330 | at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC); |
Jean-Christophe PLAGNIOL-VILLARD | cfa5a1f | 2011-10-14 01:17:18 +0800 | [diff] [blame] | 331 | } |
| 332 | |
Jean-Christophe PLAGNIOL-VILLARD | 4653937 | 2011-04-24 18:20:28 +0800 | [diff] [blame] | 333 | static void __init at91cap9_initialize(void) |
| 334 | { |
Jean-Christophe PLAGNIOL-VILLARD | 14f991a | 2011-11-18 01:41:28 +0800 | [diff] [blame] | 335 | arm_pm_restart = at91sam9g45_restart; |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 336 | at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1); |
| 337 | |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 338 | /* Register GPIO subsystem */ |
| 339 | at91_gpio_init(at91cap9_gpio, 4); |
Stelian Pop | 7be90a6 | 2008-10-22 13:52:08 +0100 | [diff] [blame] | 340 | |
| 341 | /* Remember the silicon revision */ |
| 342 | if (cpu_is_at91cap9_revB()) |
| 343 | system_rev = 0xB; |
| 344 | else if (cpu_is_at91cap9_revC()) |
| 345 | system_rev = 0xC; |
Andrew Victor | 2b3b351 | 2008-01-24 15:10:39 +0100 | [diff] [blame] | 346 | } |
| 347 | |
| 348 | /* -------------------------------------------------------------------- |
| 349 | * Interrupt initialization |
| 350 | * -------------------------------------------------------------------- */ |
| 351 | |
| 352 | /* |
| 353 | * The default interrupt priority levels (0 = lowest, 7 = highest). |
| 354 | */ |
| 355 | static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = { |
| 356 | 7, /* Advanced Interrupt Controller (FIQ) */ |
| 357 | 7, /* System Peripherals */ |
| 358 | 1, /* Parallel IO Controller A, B, C and D */ |
| 359 | 0, /* MP Block Peripheral 0 */ |
| 360 | 0, /* MP Block Peripheral 1 */ |
| 361 | 0, /* MP Block Peripheral 2 */ |
| 362 | 0, /* MP Block Peripheral 3 */ |
| 363 | 0, /* MP Block Peripheral 4 */ |
| 364 | 5, /* USART 0 */ |
| 365 | 5, /* USART 1 */ |
| 366 | 5, /* USART 2 */ |
| 367 | 0, /* Multimedia Card Interface 0 */ |
| 368 | 0, /* Multimedia Card Interface 1 */ |
| 369 | 3, /* CAN */ |
| 370 | 6, /* Two-Wire Interface */ |
| 371 | 5, /* Serial Peripheral Interface 0 */ |
| 372 | 5, /* Serial Peripheral Interface 1 */ |
| 373 | 4, /* Serial Synchronous Controller 0 */ |
| 374 | 4, /* Serial Synchronous Controller 1 */ |
| 375 | 5, /* AC97 Controller */ |
| 376 | 0, /* Timer Counter 0, 1 and 2 */ |
| 377 | 0, /* Pulse Width Modulation Controller */ |
| 378 | 3, /* Ethernet */ |
| 379 | 0, /* Advanced Encryption Standard, Triple DES*/ |
| 380 | 0, /* Analog-to-Digital Converter */ |
| 381 | 0, /* Image Sensor Interface */ |
| 382 | 3, /* LCD Controller */ |
| 383 | 0, /* DMA Controller */ |
| 384 | 2, /* USB Device Port */ |
| 385 | 2, /* USB Host port */ |
| 386 | 0, /* Advanced Interrupt Controller (IRQ0) */ |
| 387 | 0, /* Advanced Interrupt Controller (IRQ1) */ |
| 388 | }; |
| 389 | |
Jean-Christophe PLAGNIOL-VILLARD | 8c3583b | 2011-04-23 22:12:57 +0800 | [diff] [blame] | 390 | struct at91_init_soc __initdata at91cap9_soc = { |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 391 | .map_io = at91cap9_map_io, |
Jean-Christophe PLAGNIOL-VILLARD | 92100c1 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 392 | .default_irq_priority = at91cap9_default_irq_priority, |
Jean-Christophe PLAGNIOL-VILLARD | cfa5a1f | 2011-10-14 01:17:18 +0800 | [diff] [blame] | 393 | .ioremap_registers = at91cap9_ioremap_registers, |
Jean-Christophe PLAGNIOL-VILLARD | 51ddec7 | 2011-04-24 18:15:34 +0800 | [diff] [blame] | 394 | .register_clocks = at91cap9_register_clocks, |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 395 | .init = at91cap9_initialize, |
| 396 | }; |