blob: 34aa19352dc1ab87cc2cf11f38e1161dc547a518 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001config FRV
2 bool
3 default y
Sam Ravnborgec7748b2008-02-09 10:46:40 +01004 select HAVE_IDE
David Howells4a3b9892009-06-11 13:05:24 +01005 select HAVE_ARCH_TRACEHOOK
Ingo Molnarcdd6c482009-09-21 12:02:48 +02006 select HAVE_PERF_EVENTS
Catalin Marinasaf1839e2012-10-08 16:28:08 -07007 select HAVE_UID16
Stephen Rothwell4febd952013-03-07 15:48:16 +11008 select VIRT_TO_BUS
Thomas Gleixner3062aa52011-03-29 14:05:13 +01009 select GENERIC_IRQ_SHOW
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070010 select HAVE_DEBUG_BUGVERBOSE
Huang Yingdf013ff2011-07-13 13:14:22 +080011 select ARCH_HAVE_NMI_SAFE_CMPXCHG
Ben Hutchings9f13a1f2012-01-10 03:04:32 +000012 select GENERIC_CPU_DEVICES
Will Deaconc1d7e012012-07-30 14:42:46 -070013 select ARCH_WANT_IPC_PARSE_VERSION
Al Viro39e08a92012-12-25 16:27:55 -050014 select OLD_SIGSUSPEND3
Al Viro177b6702012-12-25 19:30:17 -050015 select OLD_SIGACTION
Dave Hansend1a1dc02013-07-01 13:04:42 -070016 select HAVE_DEBUG_STACKOVERFLOW
Linus Torvalds1da177e2005-04-16 15:20:36 -070017
Christoph Lameter66701b12007-02-10 01:43:09 -080018config ZONE_DMA
19 bool
20 default y
21
Linus Torvalds1da177e2005-04-16 15:20:36 -070022config RWSEM_GENERIC_SPINLOCK
23 bool
24 default y
25
26config RWSEM_XCHGADD_ALGORITHM
27 bool
28
Akinobu Mita1f6d7a92006-03-26 01:39:22 -080029config GENERIC_HWEIGHT
30 bool
31 default y
32
Linus Torvalds1da177e2005-04-16 15:20:36 -070033config GENERIC_CALIBRATE_DELAY
34 bool
35 default n
36
Ingo Molnar06027bd2006-02-14 13:53:15 -080037config TIME_LOW_RES
38 bool
39 default y
40
Christoph Lameter8defab32007-05-09 02:32:48 -070041config QUICKLIST
42 bool
43 default y
44
David Howellsf0d1b0b2006-12-08 02:37:49 -080045config ARCH_HAS_ILOG2_U32
46 bool
47 default y
48
49config ARCH_HAS_ILOG2_U64
50 bool
51 default y
52
H. Peter Anvinbdc80782008-02-08 04:21:26 -080053config HZ
54 int
55 default 1000
56
Linus Torvalds1da177e2005-04-16 15:20:36 -070057source "init/Kconfig"
58
Matt Helsleydc52ddc2008-10-18 20:27:21 -070059source "kernel/Kconfig.freezer"
60
Linus Torvalds1da177e2005-04-16 15:20:36 -070061
62menu "Fujitsu FR-V system setup"
63
64config MMU
65 bool "MMU support"
66 help
67 This options switches on and off support for the FR-V MMU
68 (effectively switching between vmlinux and uClinux). Not all FR-V
69 CPUs support this. Currently only the FR451 has a sufficiently
70 featured MMU.
71
72config FRV_OUTOFLINE_ATOMIC_OPS
73 bool "Out-of-line the FRV atomic operations"
74 default n
75 help
76 Setting this option causes the FR-V atomic operations to be mostly
77 implemented out-of-line.
78
Adrian Bunk0868ff72008-02-03 15:54:28 +020079 See Documentation/frv/atomic-ops.txt for more information.
Linus Torvalds1da177e2005-04-16 15:20:36 -070080
81config HIGHMEM
82 bool "High memory support"
83 depends on MMU
84 default y
85 help
86 If you wish to use more than 256MB of memory with your MMU based
87 system, you will need to select this option. The kernel can only see
88 the memory between 0xC0000000 and 0xD0000000 directly... everything
89 else must be kmapped.
90
91 The arch is, however, capable of supporting up to 3GB of SDRAM.
92
93config HIGHPTE
94 bool "Allocate page tables in highmem"
95 depends on HIGHMEM
96 default y
97 help
98 The VM uses one page of memory for each page table. For systems
99 with a lot of RAM, this can be wasteful of precious low memory.
100 Setting this option will put user-space page tables in high memory.
101
Dave Hansen3f22ab22005-06-23 00:07:43 -0700102source "mm/Kconfig"
103
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104choice
105 prompt "uClinux kernel load address"
106 depends on !MMU
107 default UCPAGE_OFFSET_C0000000
108 help
109 This option sets the base address for the uClinux kernel. The kernel
110 will rearrange the SDRAM layout to start at this address, and move
111 itself to start there. It must be greater than 0, and it must be
112 sufficiently less than 0xE0000000 that the SDRAM does not intersect
113 the I/O region.
114
115 The base address must also be aligned such that the SDRAM controller
116 can decode it. For instance, a 512MB SDRAM bank must be 512MB aligned.
117
118config UCPAGE_OFFSET_20000000
119 bool "0x20000000"
120
121config UCPAGE_OFFSET_40000000
122 bool "0x40000000"
123
124config UCPAGE_OFFSET_60000000
125 bool "0x60000000"
126
127config UCPAGE_OFFSET_80000000
128 bool "0x80000000"
129
130config UCPAGE_OFFSET_A0000000
131 bool "0xA0000000"
132
133config UCPAGE_OFFSET_C0000000
134 bool "0xC0000000 (Recommended)"
135
136endchoice
137
David Howells70382202008-02-04 22:29:53 -0800138config PAGE_OFFSET
139 hex
140 default 0x20000000 if UCPAGE_OFFSET_20000000
141 default 0x40000000 if UCPAGE_OFFSET_40000000
142 default 0x60000000 if UCPAGE_OFFSET_60000000
143 default 0x80000000 if UCPAGE_OFFSET_80000000
144 default 0xA0000000 if UCPAGE_OFFSET_A0000000
145 default 0xC0000000
146
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147config PROTECT_KERNEL
148 bool "Protect core kernel against userspace"
149 depends on !MMU
150 default y
151 help
152 Selecting this option causes the uClinux kernel to change the
153 permittivity of DAMPR register covering the core kernel image to
154 prevent userspace accessing the underlying memory directly.
155
156choice
157 prompt "CPU Caching mode"
158 default FRV_DEFL_CACHE_WBACK
159 help
160 This option determines the default caching mode for the kernel.
161
162 Write-Back caching mode involves the all reads and writes causing
163 the affected cacheline to be read into the cache first before being
164 operated upon. Memory is not then updated by a write until the cache
165 is filled and a cacheline needs to be displaced from the cache to
166 make room. Only at that point is it written back.
167
168 Write-Behind caching is similar to Write-Back caching, except that a
169 write won't fetch a cacheline into the cache if there isn't already
170 one there; it will write directly to memory instead.
171
172 Write-Through caching only fetches cachelines from memory on a
173 read. Writes always get written directly to memory. If the affected
174 cacheline is also in cache, it will be updated too.
175
176 The final option is to turn of caching entirely.
177
178 Note that not all CPUs support Write-Behind caching. If the CPU on
179 which the kernel is running doesn't, it'll fall back to Write-Back
180 caching.
181
182config FRV_DEFL_CACHE_WBACK
183 bool "Write-Back"
184
185config FRV_DEFL_CACHE_WBEHIND
186 bool "Write-Behind"
187
188config FRV_DEFL_CACHE_WTHRU
189 bool "Write-Through"
190
191config FRV_DEFL_CACHE_DISABLED
192 bool "Disabled"
193
194endchoice
195
196menu "CPU core support"
197
198config CPU_FR401
199 bool "Include FR401 core support"
200 depends on !MMU
201 default y
202 help
203 This enables support for the FR401, FR401A and FR403 CPUs
204
205config CPU_FR405
206 bool "Include FR405 core support"
207 depends on !MMU
208 default y
209 help
210 This enables support for the FR405 CPU
211
212config CPU_FR451
213 bool "Include FR451 core support"
214 default y
215 help
216 This enables support for the FR451 CPU
217
218config CPU_FR451_COMPILE
219 bool "Specifically compile for FR451 core"
220 depends on CPU_FR451 && !CPU_FR401 && !CPU_FR405 && !CPU_FR551
221 default y
222 help
223 This causes appropriate flags to be passed to the compiler to
224 optimise for the FR451 CPU
225
226config CPU_FR551
227 bool "Include FR551 core support"
228 depends on !MMU
229 default y
230 help
231 This enables support for the FR555 CPU
232
233config CPU_FR551_COMPILE
234 bool "Specifically compile for FR551 core"
235 depends on CPU_FR551 && !CPU_FR401 && !CPU_FR405 && !CPU_FR451
236 default y
237 help
238 This causes appropriate flags to be passed to the compiler to
239 optimise for the FR555 CPU
240
241config FRV_L1_CACHE_SHIFT
242 int
243 default "5" if CPU_FR401 || CPU_FR405 || CPU_FR451
244 default "6" if CPU_FR551
245
246endmenu
247
248choice
249 prompt "System support"
250 default MB93091_VDK
251
252config MB93091_VDK
253 bool "MB93091 CPU board with or without motherboard"
254
255config MB93093_PDK
256 bool "MB93093 PDK unit"
257
258endchoice
259
260if MB93091_VDK
261choice
262 prompt "Motherboard support"
263 default MB93090_MB00
264
265config MB93090_MB00
266 bool "Use the MB93090-MB00 motherboard"
267 help
268 Select this option if the MB93091 CPU board is going to be used with
269 a MB93090-MB00 VDK motherboard
270
271config MB93091_NO_MB
272 bool "Use standalone"
273 help
274 Select this option if the MB93091 CPU board is going to be used
275 without a motherboard
276
277endchoice
278endif
279
David Howells1bcbba32006-09-25 23:32:04 -0700280config FUJITSU_MB93493
281 bool "MB93493 Multimedia chip"
282 help
283 Select this option if the MB93493 multimedia chip is going to be
284 used.
285
Linus Torvalds1da177e2005-04-16 15:20:36 -0700286choice
287 prompt "GP-Relative data support"
288 default GPREL_DATA_8
289 help
290 This option controls what data, if any, should be placed in the GP
291 relative data sections. Using this means that the compiler can
292 generate accesses to the data using GR16-relative addressing which
293 is faster than absolute instructions and saves space (2 instructions
294 per access).
295
296 However, the GPREL region is limited in size because the immediate
297 value used in the load and store instructions is limited to a 12-bit
298 signed number.
299
300 So if the linker starts complaining that accesses to GPREL data are
301 out of range, try changing this option from the default.
302
303 Note that modules will always be compiled with this feature disabled
304 as the module data will not be in range of the GP base address.
305
306config GPREL_DATA_8
307 bool "Put data objects of up to 8 bytes into GP-REL"
308
309config GPREL_DATA_4
310 bool "Put data objects of up to 4 bytes into GP-REL"
311
312config GPREL_DATA_NONE
313 bool "Don't use GP-REL"
314
315endchoice
316
David Howellsf8aec752006-01-08 01:01:23 -0800317config FRV_ONCPU_SERIAL
318 bool "Use on-CPU serial ports"
319 select SERIAL_8250
320 default y
321
Linus Torvalds1da177e2005-04-16 15:20:36 -0700322config PCI
323 bool "Use PCI"
324 depends on MB93090_MB00
325 default y
Michael S. Tsirkin53224182011-11-29 21:20:06 +0200326 select GENERIC_PCI_IOMAP
Linus Torvalds1da177e2005-04-16 15:20:36 -0700327 help
328 Some FR-V systems (such as the MB93090-MB00 VDK) have PCI
329 onboard. If you have one of these boards and you wish to use the PCI
330 facilities, say Y here.
331
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332config RESERVE_DMA_COHERENT
333 bool "Reserve DMA coherent memory"
334 depends on PCI && !MMU
335 default y
336 help
337 Many PCI drivers require access to uncached memory for DMA device
338 communications (such as is done with some Ethernet buffer rings). If
339 a fully featured MMU is available, this can be done through page
340 table settings, but if not, a region has to be set aside and marked
341 with a special DAMPR register.
342
343 Setting this option causes uClinux to set aside a portion of the
344 available memory for use in this manner. The memory will then be
345 unavailable for normal kernel use.
346
347source "drivers/pci/Kconfig"
348
David Howells7a758312006-01-08 01:01:22 -0800349source "drivers/pcmcia/Kconfig"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700350
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351menu "Power management options"
Johannes Bergf4cb5702007-12-08 02:14:00 +0100352
353config ARCH_SUSPEND_POSSIBLE
354 def_bool y
Johannes Bergf4cb5702007-12-08 02:14:00 +0100355
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356source kernel/power/Kconfig
357endmenu
358
359endmenu
360
361
362menu "Executable formats"
363
364source "fs/Kconfig.binfmt"
365
366endmenu
367
Sam Ravnborgd5950b42005-07-11 21:03:49 -0700368source "net/Kconfig"
369
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370source "drivers/Kconfig"
371
372source "fs/Kconfig"
373
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374source "arch/frv/Kconfig.debug"
375
376source "security/Kconfig"
377
378source "crypto/Kconfig"
379
380source "lib/Kconfig"