Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 1 | /* Agere Systems Inc. |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2 | * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs |
| 3 | * |
| 4 | * Copyright © 2005 Agere Systems Inc. |
| 5 | * All rights reserved. |
| 6 | * http://www.agere.com |
| 7 | * |
| 8 | * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com> |
| 9 | * |
| 10 | *------------------------------------------------------------------------------ |
| 11 | * |
| 12 | * SOFTWARE LICENSE |
| 13 | * |
| 14 | * This software is provided subject to the following terms and conditions, |
| 15 | * which you should read carefully before using the software. Using this |
| 16 | * software indicates your acceptance of these terms and conditions. If you do |
| 17 | * not agree with these terms and conditions, do not use the software. |
| 18 | * |
| 19 | * Copyright © 2005 Agere Systems Inc. |
| 20 | * All rights reserved. |
| 21 | * |
| 22 | * Redistribution and use in source or binary forms, with or without |
| 23 | * modifications, are permitted provided that the following conditions are met: |
| 24 | * |
| 25 | * . Redistributions of source code must retain the above copyright notice, this |
| 26 | * list of conditions and the following Disclaimer as comments in the code as |
| 27 | * well as in the documentation and/or other materials provided with the |
| 28 | * distribution. |
| 29 | * |
| 30 | * . Redistributions in binary form must reproduce the above copyright notice, |
| 31 | * this list of conditions and the following Disclaimer in the documentation |
| 32 | * and/or other materials provided with the distribution. |
| 33 | * |
| 34 | * . Neither the name of Agere Systems Inc. nor the names of the contributors |
| 35 | * may be used to endorse or promote products derived from this software |
| 36 | * without specific prior written permission. |
| 37 | * |
| 38 | * Disclaimer |
| 39 | * |
| 40 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, |
| 41 | * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF |
| 42 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY |
| 43 | * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN |
| 44 | * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY |
| 45 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 46 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 47 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 48 | * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT |
| 49 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 50 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH |
| 51 | * DAMAGE. |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 52 | */ |
| 53 | |
Toshiaki Yamane | e58b89d | 2012-07-19 10:34:32 +0900 | [diff] [blame] | 54 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 55 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 56 | #include <linux/pci.h> |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 57 | #include <linux/module.h> |
| 58 | #include <linux/types.h> |
| 59 | #include <linux/kernel.h> |
| 60 | |
| 61 | #include <linux/sched.h> |
| 62 | #include <linux/ptrace.h> |
| 63 | #include <linux/slab.h> |
| 64 | #include <linux/ctype.h> |
| 65 | #include <linux/string.h> |
| 66 | #include <linux/timer.h> |
| 67 | #include <linux/interrupt.h> |
| 68 | #include <linux/in.h> |
| 69 | #include <linux/delay.h> |
| 70 | #include <linux/bitops.h> |
| 71 | #include <linux/io.h> |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 72 | |
| 73 | #include <linux/netdevice.h> |
| 74 | #include <linux/etherdevice.h> |
| 75 | #include <linux/skbuff.h> |
| 76 | #include <linux/if_arp.h> |
| 77 | #include <linux/ioport.h> |
| 78 | #include <linux/crc32.h> |
| 79 | #include <linux/random.h> |
| 80 | #include <linux/phy.h> |
| 81 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 82 | #include "et131x.h" |
| 83 | |
| 84 | MODULE_AUTHOR("Victor Soriano <vjsoriano@agere.com>"); |
| 85 | MODULE_AUTHOR("Mark Einon <mark.einon@gmail.com>"); |
| 86 | MODULE_LICENSE("Dual BSD/GPL"); |
Adnan Ali | 397d3e6 | 2012-05-25 18:56:40 +0100 | [diff] [blame] | 87 | MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver for the ET1310 by Agere Systems"); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 88 | |
Mark Einon | bd156af | 2011-10-20 01:18:32 +0100 | [diff] [blame] | 89 | /* EEPROM defines */ |
| 90 | #define MAX_NUM_REGISTER_POLLS 1000 |
| 91 | #define MAX_NUM_WRITE_RETRIES 2 |
| 92 | |
| 93 | /* MAC defines */ |
| 94 | #define COUNTER_WRAP_16_BIT 0x10000 |
| 95 | #define COUNTER_WRAP_12_BIT 0x1000 |
| 96 | |
| 97 | /* PCI defines */ |
| 98 | #define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */ |
| 99 | #define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */ |
| 100 | |
| 101 | /* ISR defines */ |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 102 | /* For interrupts, normal running is: |
Mark Einon | bd156af | 2011-10-20 01:18:32 +0100 | [diff] [blame] | 103 | * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt, |
| 104 | * watchdog_interrupt & txdma_xfer_done |
| 105 | * |
| 106 | * In both cases, when flow control is enabled for either Tx or bi-direction, |
| 107 | * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the |
| 108 | * buffer rings are running low. |
| 109 | */ |
| 110 | #define INT_MASK_DISABLE 0xffffffff |
| 111 | |
| 112 | /* NOTE: Masking out MAC_STAT Interrupt for now... |
| 113 | * #define INT_MASK_ENABLE 0xfff6bf17 |
| 114 | * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7 |
| 115 | */ |
| 116 | #define INT_MASK_ENABLE 0xfffebf17 |
| 117 | #define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7 |
| 118 | |
Mark Einon | 1c1c1b5 | 2011-10-20 01:18:36 +0100 | [diff] [blame] | 119 | /* General defines */ |
| 120 | /* Packet and header sizes */ |
| 121 | #define NIC_MIN_PACKET_SIZE 60 |
| 122 | |
| 123 | /* Multicast list size */ |
| 124 | #define NIC_MAX_MCAST_LIST 128 |
| 125 | |
| 126 | /* Supported Filters */ |
| 127 | #define ET131X_PACKET_TYPE_DIRECTED 0x0001 |
| 128 | #define ET131X_PACKET_TYPE_MULTICAST 0x0002 |
| 129 | #define ET131X_PACKET_TYPE_BROADCAST 0x0004 |
| 130 | #define ET131X_PACKET_TYPE_PROMISCUOUS 0x0008 |
| 131 | #define ET131X_PACKET_TYPE_ALL_MULTICAST 0x0010 |
| 132 | |
| 133 | /* Tx Timeout */ |
| 134 | #define ET131X_TX_TIMEOUT (1 * HZ) |
| 135 | #define NIC_SEND_HANG_THRESHOLD 0 |
| 136 | |
| 137 | /* MP_TCB flags */ |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 138 | #define FMP_DEST_MULTI 0x00000001 |
| 139 | #define FMP_DEST_BROAD 0x00000002 |
Mark Einon | 1c1c1b5 | 2011-10-20 01:18:36 +0100 | [diff] [blame] | 140 | |
| 141 | /* MP_ADAPTER flags */ |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 142 | #define FMP_ADAPTER_INTERRUPT_IN_USE 0x00000008 |
Mark Einon | 1c1c1b5 | 2011-10-20 01:18:36 +0100 | [diff] [blame] | 143 | |
| 144 | /* MP_SHARED flags */ |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 145 | #define FMP_ADAPTER_LOWER_POWER 0x00200000 |
Mark Einon | 1c1c1b5 | 2011-10-20 01:18:36 +0100 | [diff] [blame] | 146 | |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 147 | #define FMP_ADAPTER_NON_RECOVER_ERROR 0x00800000 |
| 148 | #define FMP_ADAPTER_HARDWARE_ERROR 0x04000000 |
Mark Einon | 1c1c1b5 | 2011-10-20 01:18:36 +0100 | [diff] [blame] | 149 | |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 150 | #define FMP_ADAPTER_FAIL_SEND_MASK 0x3ff00000 |
Mark Einon | 1c1c1b5 | 2011-10-20 01:18:36 +0100 | [diff] [blame] | 151 | |
| 152 | /* Some offsets in PCI config space that are actually used. */ |
Mark Einon | 1c1c1b5 | 2011-10-20 01:18:36 +0100 | [diff] [blame] | 153 | #define ET1310_PCI_MAC_ADDRESS 0xA4 |
| 154 | #define ET1310_PCI_EEPROM_STATUS 0xB2 |
| 155 | #define ET1310_PCI_ACK_NACK 0xC0 |
| 156 | #define ET1310_PCI_REPLAY 0xC2 |
| 157 | #define ET1310_PCI_L0L1LATENCY 0xCF |
| 158 | |
Mark Einon | 26d19bf | 2011-10-20 01:18:45 +0100 | [diff] [blame] | 159 | /* PCI Product IDs */ |
Mark Einon | 1c1c1b5 | 2011-10-20 01:18:36 +0100 | [diff] [blame] | 160 | #define ET131X_PCI_DEVICE_ID_GIG 0xED00 /* ET1310 1000 Base-T 8 */ |
| 161 | #define ET131X_PCI_DEVICE_ID_FAST 0xED01 /* ET1310 100 Base-T */ |
| 162 | |
| 163 | /* Define order of magnitude converter */ |
| 164 | #define NANO_IN_A_MICRO 1000 |
| 165 | |
| 166 | #define PARM_RX_NUM_BUFS_DEF 4 |
| 167 | #define PARM_RX_TIME_INT_DEF 10 |
| 168 | #define PARM_RX_MEM_END_DEF 0x2bc |
| 169 | #define PARM_TX_TIME_INT_DEF 40 |
| 170 | #define PARM_TX_NUM_BUFS_DEF 4 |
| 171 | #define PARM_DMA_CACHE_DEF 0 |
| 172 | |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 173 | /* RX defines */ |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 174 | #define FBR_CHUNKS 32 |
| 175 | #define MAX_DESC_PER_RING_RX 1024 |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 176 | |
| 177 | /* number of RFDs - default and min */ |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 178 | #define RFD_LOW_WATER_MARK 40 |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 179 | #define NIC_DEFAULT_NUM_RFD 1024 |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 180 | #define NUM_FBRS 2 |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 181 | |
| 182 | #define NUM_PACKETS_HANDLED 256 |
| 183 | |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 184 | #define ALCATEL_MULTICAST_PKT 0x01000000 |
| 185 | #define ALCATEL_BROADCAST_PKT 0x02000000 |
| 186 | |
| 187 | /* typedefs for Free Buffer Descriptors */ |
| 188 | struct fbr_desc { |
| 189 | u32 addr_lo; |
| 190 | u32 addr_hi; |
| 191 | u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */ |
| 192 | }; |
| 193 | |
| 194 | /* Packet Status Ring Descriptors |
| 195 | * |
| 196 | * Word 0: |
| 197 | * |
| 198 | * top 16 bits are from the Alcatel Status Word as enumerated in |
| 199 | * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2) |
| 200 | * |
| 201 | * 0: hp hash pass |
| 202 | * 1: ipa IP checksum assist |
| 203 | * 2: ipp IP checksum pass |
| 204 | * 3: tcpa TCP checksum assist |
| 205 | * 4: tcpp TCP checksum pass |
| 206 | * 5: wol WOL Event |
| 207 | * 6: rxmac_error RXMAC Error Indicator |
| 208 | * 7: drop Drop packet |
| 209 | * 8: ft Frame Truncated |
| 210 | * 9: jp Jumbo Packet |
| 211 | * 10: vp VLAN Packet |
| 212 | * 11-15: unused |
| 213 | * 16: asw_prev_pkt_dropped e.g. IFG too small on previous |
| 214 | * 17: asw_RX_DV_event short receive event detected |
| 215 | * 18: asw_false_carrier_event bad carrier since last good packet |
| 216 | * 19: asw_code_err one or more nibbles signalled as errors |
| 217 | * 20: asw_CRC_err CRC error |
| 218 | * 21: asw_len_chk_err frame length field incorrect |
| 219 | * 22: asw_too_long frame length > 1518 bytes |
| 220 | * 23: asw_OK valid CRC + no code error |
| 221 | * 24: asw_multicast has a multicast address |
| 222 | * 25: asw_broadcast has a broadcast address |
| 223 | * 26: asw_dribble_nibble spurious bits after EOP |
| 224 | * 27: asw_control_frame is a control frame |
| 225 | * 28: asw_pause_frame is a pause frame |
| 226 | * 29: asw_unsupported_op unsupported OP code |
| 227 | * 30: asw_VLAN_tag VLAN tag detected |
| 228 | * 31: asw_long_evt Rx long event |
| 229 | * |
| 230 | * Word 1: |
| 231 | * 0-15: length length in bytes |
| 232 | * 16-25: bi Buffer Index |
| 233 | * 26-27: ri Ring Index |
| 234 | * 28-31: reserved |
| 235 | */ |
| 236 | |
| 237 | struct pkt_stat_desc { |
| 238 | u32 word0; |
| 239 | u32 word1; |
| 240 | }; |
| 241 | |
| 242 | /* Typedefs for the RX DMA status word */ |
| 243 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 244 | /* rx status word 0 holds part of the status bits of the Rx DMA engine |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 245 | * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word |
| 246 | * which contains the Free Buffer ring 0 and 1 available offset. |
| 247 | * |
| 248 | * bit 0-9 FBR1 offset |
| 249 | * bit 10 Wrap flag for FBR1 |
| 250 | * bit 16-25 FBR0 offset |
| 251 | * bit 26 Wrap flag for FBR0 |
| 252 | */ |
| 253 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 254 | /* RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 255 | * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word |
| 256 | * which contains the Packet Status Ring available offset. |
| 257 | * |
| 258 | * bit 0-15 reserved |
| 259 | * bit 16-27 PSRoffset |
| 260 | * bit 28 PSRwrap |
| 261 | * bit 29-31 unused |
| 262 | */ |
| 263 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 264 | /* struct rx_status_block is a structure representing the status of the Rx |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 265 | * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020 |
| 266 | */ |
| 267 | struct rx_status_block { |
| 268 | u32 word0; |
| 269 | u32 word1; |
| 270 | }; |
| 271 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 272 | /* Structure for look-up table holding free buffer ring pointers, addresses |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 273 | * and state. |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 274 | */ |
| 275 | struct fbr_lookup { |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 276 | void *virt[MAX_DESC_PER_RING_RX]; |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 277 | u32 bus_high[MAX_DESC_PER_RING_RX]; |
| 278 | u32 bus_low[MAX_DESC_PER_RING_RX]; |
| 279 | void *ring_virtaddr; |
| 280 | dma_addr_t ring_physaddr; |
| 281 | void *mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS]; |
| 282 | dma_addr_t mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS]; |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 283 | u32 local_full; |
| 284 | u32 num_entries; |
Mark Einon | 983e4b3 | 2012-10-23 23:34:15 +0100 | [diff] [blame] | 285 | dma_addr_t buffsize; |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 286 | }; |
| 287 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 288 | /* struct rx_ring is the sructure representing the adaptor's local |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 289 | * reference(s) to the rings |
| 290 | */ |
| 291 | struct rx_ring { |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 292 | struct fbr_lookup *fbr[NUM_FBRS]; |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 293 | void *ps_ring_virtaddr; |
| 294 | dma_addr_t ps_ring_physaddr; |
| 295 | u32 local_psr_full; |
| 296 | u32 psr_num_entries; |
| 297 | |
| 298 | struct rx_status_block *rx_status_block; |
| 299 | dma_addr_t rx_status_bus; |
| 300 | |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 301 | /* RECV */ |
| 302 | struct list_head recv_list; |
| 303 | u32 num_ready_recv; |
| 304 | |
| 305 | u32 num_rfd; |
| 306 | |
| 307 | bool unfinished_receives; |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 308 | }; |
| 309 | |
Mark Einon | 17ec9ff | 2011-10-20 01:18:38 +0100 | [diff] [blame] | 310 | /* TX defines */ |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 311 | /* word 2 of the control bits in the Tx Descriptor ring for the ET-1310 |
Mark Einon | 17ec9ff | 2011-10-20 01:18:38 +0100 | [diff] [blame] | 312 | * |
| 313 | * 0-15: length of packet |
| 314 | * 16-27: VLAN tag |
| 315 | * 28: VLAN CFI |
| 316 | * 29-31: VLAN priority |
| 317 | * |
| 318 | * word 3 of the control bits in the Tx Descriptor ring for the ET-1310 |
| 319 | * |
| 320 | * 0: last packet in the sequence |
| 321 | * 1: first packet in the sequence |
| 322 | * 2: interrupt the processor when this pkt sent |
| 323 | * 3: Control word - no packet data |
| 324 | * 4: Issue half-duplex backpressure : XON/XOFF |
| 325 | * 5: send pause frame |
| 326 | * 6: Tx frame has error |
| 327 | * 7: append CRC |
| 328 | * 8: MAC override |
| 329 | * 9: pad packet |
| 330 | * 10: Packet is a Huge packet |
| 331 | * 11: append VLAN tag |
| 332 | * 12: IP checksum assist |
| 333 | * 13: TCP checksum assist |
| 334 | * 14: UDP checksum assist |
| 335 | */ |
| 336 | |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 337 | #define TXDESC_FLAG_LASTPKT 0x0001 |
| 338 | #define TXDESC_FLAG_FIRSTPKT 0x0002 |
| 339 | #define TXDESC_FLAG_INTPROC 0x0004 |
| 340 | |
Mark Einon | 17ec9ff | 2011-10-20 01:18:38 +0100 | [diff] [blame] | 341 | /* struct tx_desc represents each descriptor on the ring */ |
| 342 | struct tx_desc { |
| 343 | u32 addr_hi; |
| 344 | u32 addr_lo; |
| 345 | u32 len_vlan; /* control words how to xmit the */ |
| 346 | u32 flags; /* data (detailed above) */ |
| 347 | }; |
| 348 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 349 | /* The status of the Tx DMA engine it sits in free memory, and is pointed to |
Mark Einon | 17ec9ff | 2011-10-20 01:18:38 +0100 | [diff] [blame] | 350 | * by 0x101c / 0x1020. This is a DMA10 type |
| 351 | */ |
| 352 | |
| 353 | /* TCB (Transmit Control Block: Host Side) */ |
| 354 | struct tcb { |
| 355 | struct tcb *next; /* Next entry in ring */ |
| 356 | u32 flags; /* Our flags for the packet */ |
| 357 | u32 count; /* Used to spot stuck/lost packets */ |
| 358 | u32 stale; /* Used to spot stuck/lost packets */ |
| 359 | struct sk_buff *skb; /* Network skb we are tied to */ |
| 360 | u32 index; /* Ring indexes */ |
| 361 | u32 index_start; |
| 362 | }; |
| 363 | |
| 364 | /* Structure representing our local reference(s) to the ring */ |
| 365 | struct tx_ring { |
| 366 | /* TCB (Transmit Control Block) memory and lists */ |
| 367 | struct tcb *tcb_ring; |
| 368 | |
| 369 | /* List of TCBs that are ready to be used */ |
| 370 | struct tcb *tcb_qhead; |
| 371 | struct tcb *tcb_qtail; |
| 372 | |
| 373 | /* list of TCBs that are currently being sent. NOTE that access to all |
| 374 | * three of these (including used) are controlled via the |
| 375 | * TCBSendQLock. This lock should be secured prior to incementing / |
| 376 | * decrementing used, or any queue manipulation on send_head / |
| 377 | * tail |
| 378 | */ |
| 379 | struct tcb *send_head; |
| 380 | struct tcb *send_tail; |
| 381 | int used; |
| 382 | |
| 383 | /* The actual descriptor ring */ |
| 384 | struct tx_desc *tx_desc_ring; |
| 385 | dma_addr_t tx_desc_ring_pa; |
| 386 | |
| 387 | /* send_idx indicates where we last wrote to in the descriptor ring. */ |
| 388 | u32 send_idx; |
| 389 | |
| 390 | /* The location of the write-back status block */ |
| 391 | u32 *tx_status; |
| 392 | dma_addr_t tx_status_pa; |
| 393 | |
| 394 | /* Packets since the last IRQ: used for interrupt coalescing */ |
| 395 | int since_irq; |
| 396 | }; |
| 397 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 398 | /* Do not change these values: if changed, then change also in respective |
Mark Einon | fd0651a | 2011-10-20 01:18:35 +0100 | [diff] [blame] | 399 | * TXdma and Rxdma engines |
| 400 | */ |
| 401 | #define NUM_DESC_PER_RING_TX 512 /* TX Do not change these values */ |
| 402 | #define NUM_TCB 64 |
| 403 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 404 | /* These values are all superseded by registry entries to facilitate tuning. |
Mark Einon | fd0651a | 2011-10-20 01:18:35 +0100 | [diff] [blame] | 405 | * Once the desired performance has been achieved, the optimal registry values |
| 406 | * should be re-populated to these #defines: |
| 407 | */ |
Mark Einon | fd0651a | 2011-10-20 01:18:35 +0100 | [diff] [blame] | 408 | #define TX_ERROR_PERIOD 1000 |
| 409 | |
| 410 | #define LO_MARK_PERCENT_FOR_PSR 15 |
| 411 | #define LO_MARK_PERCENT_FOR_RX 15 |
| 412 | |
| 413 | /* RFD (Receive Frame Descriptor) */ |
| 414 | struct rfd { |
| 415 | struct list_head list_node; |
| 416 | struct sk_buff *skb; |
| 417 | u32 len; /* total size of receive frame */ |
| 418 | u16 bufferindex; |
| 419 | u8 ringindex; |
| 420 | }; |
| 421 | |
| 422 | /* Flow Control */ |
| 423 | #define FLOW_BOTH 0 |
| 424 | #define FLOW_TXONLY 1 |
| 425 | #define FLOW_RXONLY 2 |
| 426 | #define FLOW_NONE 3 |
| 427 | |
| 428 | /* Struct to define some device statistics */ |
| 429 | struct ce_stats { |
| 430 | /* MIB II variables |
| 431 | * |
| 432 | * NOTE: atomic_t types are only guaranteed to store 24-bits; if we |
| 433 | * MUST have 32, then we'll need another way to perform atomic |
| 434 | * operations |
| 435 | */ |
| 436 | u32 unicast_pkts_rcvd; |
| 437 | atomic_t unicast_pkts_xmtd; |
| 438 | u32 multicast_pkts_rcvd; |
| 439 | atomic_t multicast_pkts_xmtd; |
| 440 | u32 broadcast_pkts_rcvd; |
| 441 | atomic_t broadcast_pkts_xmtd; |
| 442 | u32 rcvd_pkts_dropped; |
| 443 | |
| 444 | /* Tx Statistics. */ |
| 445 | u32 tx_underflows; |
| 446 | |
| 447 | u32 tx_collisions; |
| 448 | u32 tx_excessive_collisions; |
| 449 | u32 tx_first_collisions; |
| 450 | u32 tx_late_collisions; |
| 451 | u32 tx_max_pkt_errs; |
| 452 | u32 tx_deferred; |
| 453 | |
| 454 | /* Rx Statistics. */ |
| 455 | u32 rx_overflows; |
| 456 | |
| 457 | u32 rx_length_errs; |
| 458 | u32 rx_align_errs; |
| 459 | u32 rx_crc_errs; |
| 460 | u32 rx_code_violations; |
| 461 | u32 rx_other_errs; |
| 462 | |
| 463 | u32 synchronous_iterations; |
| 464 | u32 interrupt_status; |
| 465 | }; |
| 466 | |
| 467 | /* The private adapter structure */ |
| 468 | struct et131x_adapter { |
| 469 | struct net_device *netdev; |
| 470 | struct pci_dev *pdev; |
| 471 | struct mii_bus *mii_bus; |
| 472 | struct phy_device *phydev; |
| 473 | struct work_struct task; |
| 474 | |
| 475 | /* Flags that indicate current state of the adapter */ |
| 476 | u32 flags; |
| 477 | |
| 478 | /* local link state, to determine if a state change has occurred */ |
| 479 | int link; |
| 480 | |
| 481 | /* Configuration */ |
| 482 | u8 rom_addr[ETH_ALEN]; |
| 483 | u8 addr[ETH_ALEN]; |
| 484 | bool has_eeprom; |
| 485 | u8 eeprom_data[2]; |
| 486 | |
| 487 | /* Spinlocks */ |
Mark Einon | fd0651a | 2011-10-20 01:18:35 +0100 | [diff] [blame] | 488 | spinlock_t tcb_send_qlock; |
| 489 | spinlock_t tcb_ready_qlock; |
| 490 | spinlock_t send_hw_lock; |
| 491 | |
| 492 | spinlock_t rcv_lock; |
Mark Einon | fd0651a | 2011-10-20 01:18:35 +0100 | [diff] [blame] | 493 | spinlock_t fbr_lock; |
| 494 | |
Mark Einon | fd0651a | 2011-10-20 01:18:35 +0100 | [diff] [blame] | 495 | /* Packet Filter and look ahead size */ |
| 496 | u32 packet_filter; |
| 497 | |
| 498 | /* multicast list */ |
| 499 | u32 multicast_addr_count; |
| 500 | u8 multicast_list[NIC_MAX_MCAST_LIST][ETH_ALEN]; |
| 501 | |
| 502 | /* Pointer to the device's PCI register space */ |
| 503 | struct address_map __iomem *regs; |
| 504 | |
| 505 | /* Registry parameters */ |
| 506 | u8 wanted_flow; /* Flow we want for 802.3x flow control */ |
| 507 | u32 registry_jumbo_packet; /* Max supported ethernet packet size */ |
| 508 | |
| 509 | /* Derived from the registry: */ |
| 510 | u8 flowcontrol; /* flow control validated by the far-end */ |
| 511 | |
| 512 | /* Minimize init-time */ |
| 513 | struct timer_list error_timer; |
| 514 | |
| 515 | /* variable putting the phy into coma mode when boot up with no cable |
| 516 | * plugged in after 5 seconds |
| 517 | */ |
| 518 | u8 boot_coma; |
| 519 | |
| 520 | /* Next two used to save power information at power down. This |
| 521 | * information will be used during power up to set up parts of Power |
| 522 | * Management in JAGCore |
| 523 | */ |
| 524 | u16 pdown_speed; |
| 525 | u8 pdown_duplex; |
| 526 | |
| 527 | /* Tx Memory Variables */ |
| 528 | struct tx_ring tx_ring; |
| 529 | |
| 530 | /* Rx Memory Variables */ |
| 531 | struct rx_ring rx_ring; |
| 532 | |
| 533 | /* Stats */ |
| 534 | struct ce_stats stats; |
| 535 | |
| 536 | struct net_device_stats net_stats; |
| 537 | }; |
| 538 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 539 | static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status) |
| 540 | { |
| 541 | u32 reg; |
| 542 | int i; |
| 543 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 544 | /* 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 545 | * bits 7,1:0 both equal to 1, at least once after reset. |
| 546 | * Subsequent operations need only to check that bits 1:0 are equal |
| 547 | * to 1 prior to starting a single byte read/write |
| 548 | */ |
| 549 | |
| 550 | for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) { |
| 551 | /* Read registers grouped in DWORD1 */ |
| 552 | if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, ®)) |
| 553 | return -EIO; |
| 554 | |
| 555 | /* I2C idle and Phy Queue Avail both true */ |
| 556 | if ((reg & 0x3000) == 0x3000) { |
| 557 | if (status) |
| 558 | *status = reg; |
| 559 | return reg & 0xFF; |
| 560 | } |
| 561 | } |
| 562 | return -ETIMEDOUT; |
| 563 | } |
| 564 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 565 | /* eeprom_write - Write a byte to the ET1310's EEPROM |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 566 | * @adapter: pointer to our private adapter structure |
| 567 | * @addr: the address to write |
| 568 | * @data: the value to write |
| 569 | * |
| 570 | * Returns 1 for a successful write. |
| 571 | */ |
| 572 | static int eeprom_write(struct et131x_adapter *adapter, u32 addr, u8 data) |
| 573 | { |
| 574 | struct pci_dev *pdev = adapter->pdev; |
| 575 | int index = 0; |
| 576 | int retries; |
| 577 | int err = 0; |
| 578 | int i2c_wack = 0; |
| 579 | int writeok = 0; |
| 580 | u32 status; |
| 581 | u32 val = 0; |
| 582 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 583 | /* For an EEPROM, an I2C single byte write is defined as a START |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 584 | * condition followed by the device address, EEPROM address, one byte |
| 585 | * of data and a STOP condition. The STOP condition will trigger the |
| 586 | * EEPROM's internally timed write cycle to the nonvolatile memory. |
| 587 | * All inputs are disabled during this write cycle and the EEPROM will |
| 588 | * not respond to any access until the internal write is complete. |
| 589 | */ |
| 590 | |
| 591 | err = eeprom_wait_ready(pdev, NULL); |
Devendra Naga | 8dd4a96 | 2013-03-12 01:34:45 -0400 | [diff] [blame] | 592 | if (err < 0) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 593 | return err; |
| 594 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 595 | /* 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0, |
| 596 | * and bits 1:0 both =0. Bit 5 should be set according to the |
| 597 | * type of EEPROM being accessed (1=two byte addressing, 0=one |
| 598 | * byte addressing). |
| 599 | */ |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 600 | if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER, |
| 601 | LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE)) |
| 602 | return -EIO; |
| 603 | |
| 604 | i2c_wack = 1; |
| 605 | |
| 606 | /* Prepare EEPROM address for Step 3 */ |
| 607 | |
| 608 | for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) { |
| 609 | /* Write the address to the LBCIF Address Register */ |
| 610 | if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr)) |
| 611 | break; |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 612 | /* Write the data to the LBCIF Data Register (the I2C write |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 613 | * will begin). |
| 614 | */ |
| 615 | if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data)) |
| 616 | break; |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 617 | /* Monitor bit 1:0 of the LBCIF Status Register. When bits |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 618 | * 1:0 are both equal to 1, the I2C write has completed and the |
| 619 | * internal write cycle of the EEPROM is about to start. |
| 620 | * (bits 1:0 = 01 is a legal state while waiting from both |
| 621 | * equal to 1, but bits 1:0 = 10 is invalid and implies that |
| 622 | * something is broken). |
| 623 | */ |
| 624 | err = eeprom_wait_ready(pdev, &status); |
| 625 | if (err < 0) |
| 626 | return 0; |
| 627 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 628 | /* Check bit 3 of the LBCIF Status Register. If equal to 1, |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 629 | * an error has occurred.Don't break here if we are revision |
| 630 | * 1, this is so we do a blind write for load bug. |
| 631 | */ |
| 632 | if ((status & LBCIF_STATUS_GENERAL_ERROR) |
| 633 | && adapter->pdev->revision == 0) |
| 634 | break; |
| 635 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 636 | /* Check bit 2 of the LBCIF Status Register. If equal to 1 an |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 637 | * ACK error has occurred on the address phase of the write. |
| 638 | * This could be due to an actual hardware failure or the |
| 639 | * EEPROM may still be in its internal write cycle from a |
| 640 | * previous write. This write operation was ignored and must be |
| 641 | *repeated later. |
| 642 | */ |
| 643 | if (status & LBCIF_STATUS_ACK_ERROR) { |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 644 | /* This could be due to an actual hardware failure |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 645 | * or the EEPROM may still be in its internal write |
| 646 | * cycle from a previous write. This write operation |
| 647 | * was ignored and must be repeated later. |
| 648 | */ |
| 649 | udelay(10); |
| 650 | continue; |
| 651 | } |
| 652 | |
| 653 | writeok = 1; |
| 654 | break; |
| 655 | } |
| 656 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 657 | /* Set bit 6 of the LBCIF Control Register = 0. |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 658 | */ |
| 659 | udelay(10); |
| 660 | |
| 661 | while (i2c_wack) { |
| 662 | if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER, |
| 663 | LBCIF_CONTROL_LBCIF_ENABLE)) |
| 664 | writeok = 0; |
| 665 | |
| 666 | /* Do read until internal ACK_ERROR goes away meaning write |
| 667 | * completed |
| 668 | */ |
| 669 | do { |
| 670 | pci_write_config_dword(pdev, |
| 671 | LBCIF_ADDRESS_REGISTER, |
| 672 | addr); |
| 673 | do { |
| 674 | pci_read_config_dword(pdev, |
| 675 | LBCIF_DATA_REGISTER, &val); |
| 676 | } while ((val & 0x00010000) == 0); |
| 677 | } while (val & 0x00040000); |
| 678 | |
| 679 | if ((val & 0xFF00) != 0xC000 || index == 10000) |
| 680 | break; |
| 681 | index++; |
| 682 | } |
| 683 | return writeok ? 0 : -EIO; |
| 684 | } |
| 685 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 686 | /* eeprom_read - Read a byte from the ET1310's EEPROM |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 687 | * @adapter: pointer to our private adapter structure |
| 688 | * @addr: the address from which to read |
| 689 | * @pdata: a pointer to a byte in which to store the value of the read |
| 690 | * @eeprom_id: the ID of the EEPROM |
| 691 | * @addrmode: how the EEPROM is to be accessed |
| 692 | * |
| 693 | * Returns 1 for a successful read |
| 694 | */ |
| 695 | static int eeprom_read(struct et131x_adapter *adapter, u32 addr, u8 *pdata) |
| 696 | { |
| 697 | struct pci_dev *pdev = adapter->pdev; |
| 698 | int err; |
| 699 | u32 status; |
| 700 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 701 | /* A single byte read is similar to the single byte write, with the |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 702 | * exception of the data flow: |
| 703 | */ |
| 704 | |
| 705 | err = eeprom_wait_ready(pdev, NULL); |
Devendra Naga | 8dd4a96 | 2013-03-12 01:34:45 -0400 | [diff] [blame] | 706 | if (err < 0) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 707 | return err; |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 708 | /* Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0, |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 709 | * and bits 1:0 both =0. Bit 5 should be set according to the type |
| 710 | * of EEPROM being accessed (1=two byte addressing, 0=one byte |
| 711 | * addressing). |
| 712 | */ |
| 713 | if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER, |
| 714 | LBCIF_CONTROL_LBCIF_ENABLE)) |
| 715 | return -EIO; |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 716 | /* Write the address to the LBCIF Address Register (I2C read will |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 717 | * begin). |
| 718 | */ |
| 719 | if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr)) |
| 720 | return -EIO; |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 721 | /* Monitor bit 0 of the LBCIF Status Register. When = 1, I2C read |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 722 | * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure |
| 723 | * has occurred). |
| 724 | */ |
| 725 | err = eeprom_wait_ready(pdev, &status); |
| 726 | if (err < 0) |
| 727 | return err; |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 728 | /* Regardless of error status, read data byte from LBCIF Data |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 729 | * Register. |
| 730 | */ |
| 731 | *pdata = err; |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 732 | /* Check bit 2 of the LBCIF Status Register. If = 1, |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 733 | * then an error has occurred. |
| 734 | */ |
| 735 | return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0; |
| 736 | } |
| 737 | |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 738 | static int et131x_init_eeprom(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 739 | { |
| 740 | struct pci_dev *pdev = adapter->pdev; |
| 741 | u8 eestatus; |
| 742 | |
| 743 | /* We first need to check the EEPROM Status code located at offset |
| 744 | * 0xB2 of config space |
| 745 | */ |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 746 | pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 747 | |
| 748 | /* THIS IS A WORKAROUND: |
| 749 | * I need to call this function twice to get my card in a |
| 750 | * LG M1 Express Dual running. I tried also a msleep before this |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 751 | * function, because I thought there could be some time conditions |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 752 | * but it didn't work. Call the whole function twice also work. |
| 753 | */ |
| 754 | if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) { |
| 755 | dev_err(&pdev->dev, |
| 756 | "Could not read PCI config space for EEPROM Status\n"); |
| 757 | return -EIO; |
| 758 | } |
| 759 | |
| 760 | /* Determine if the error(s) we care about are present. If they are |
| 761 | * present we need to fail. |
| 762 | */ |
| 763 | if (eestatus & 0x4C) { |
| 764 | int write_failed = 0; |
| 765 | if (pdev->revision == 0x01) { |
| 766 | int i; |
| 767 | static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF }; |
| 768 | |
| 769 | /* Re-write the first 4 bytes if we have an eeprom |
| 770 | * present and the revision id is 1, this fixes the |
| 771 | * corruption seen with 1310 B Silicon |
| 772 | */ |
| 773 | for (i = 0; i < 3; i++) |
| 774 | if (eeprom_write(adapter, i, eedata[i]) < 0) |
| 775 | write_failed = 1; |
| 776 | } |
| 777 | if (pdev->revision != 0x01 || write_failed) { |
| 778 | dev_err(&pdev->dev, |
| 779 | "Fatal EEPROM Status Error - 0x%04x\n", eestatus); |
| 780 | |
| 781 | /* This error could mean that there was an error |
| 782 | * reading the eeprom or that the eeprom doesn't exist. |
| 783 | * We will treat each case the same and not try to |
| 784 | * gather additional information that normally would |
| 785 | * come from the eeprom, like MAC Address |
| 786 | */ |
| 787 | adapter->has_eeprom = 0; |
| 788 | return -EIO; |
| 789 | } |
| 790 | } |
| 791 | adapter->has_eeprom = 1; |
| 792 | |
| 793 | /* Read the EEPROM for information regarding LED behavior. Refer to |
| 794 | * ET1310_phy.c, et131x_xcvr_init(), for its use. |
| 795 | */ |
| 796 | eeprom_read(adapter, 0x70, &adapter->eeprom_data[0]); |
| 797 | eeprom_read(adapter, 0x71, &adapter->eeprom_data[1]); |
| 798 | |
| 799 | if (adapter->eeprom_data[0] != 0xcd) |
| 800 | /* Disable all optional features */ |
| 801 | adapter->eeprom_data[1] = 0x00; |
| 802 | |
| 803 | return 0; |
| 804 | } |
| 805 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 806 | /* et131x_rx_dma_enable - re-start of Rx_DMA on the ET1310. |
Mark Einon | 8310c60 | 2011-10-23 10:22:52 +0100 | [diff] [blame] | 807 | * @adapter: pointer to our adapter structure |
| 808 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 809 | static void et131x_rx_dma_enable(struct et131x_adapter *adapter) |
Mark Einon | 8310c60 | 2011-10-23 10:22:52 +0100 | [diff] [blame] | 810 | { |
| 811 | /* Setup the receive dma configuration register for normal operation */ |
Mark Einon | 3040d05 | 2013-01-04 22:25:45 +0000 | [diff] [blame] | 812 | u32 csr = ET_RXDMA_CSR_FBR1_ENABLE; |
ZHAO Gang | 8f7fa96 | 2013-12-08 11:01:06 +0800 | [diff] [blame] | 813 | struct rx_ring *rx_ring = &adapter->rx_ring; |
Mark Einon | 8310c60 | 2011-10-23 10:22:52 +0100 | [diff] [blame] | 814 | |
ZHAO Gang | 8f7fa96 | 2013-12-08 11:01:06 +0800 | [diff] [blame] | 815 | if (rx_ring->fbr[1]->buffsize == 4096) |
Mark Einon | 3040d05 | 2013-01-04 22:25:45 +0000 | [diff] [blame] | 816 | csr |= ET_RXDMA_CSR_FBR1_SIZE_LO; |
ZHAO Gang | 8f7fa96 | 2013-12-08 11:01:06 +0800 | [diff] [blame] | 817 | else if (rx_ring->fbr[1]->buffsize == 8192) |
Mark Einon | 3040d05 | 2013-01-04 22:25:45 +0000 | [diff] [blame] | 818 | csr |= ET_RXDMA_CSR_FBR1_SIZE_HI; |
ZHAO Gang | 8f7fa96 | 2013-12-08 11:01:06 +0800 | [diff] [blame] | 819 | else if (rx_ring->fbr[1]->buffsize == 16384) |
Mark Einon | 3040d05 | 2013-01-04 22:25:45 +0000 | [diff] [blame] | 820 | csr |= ET_RXDMA_CSR_FBR1_SIZE_LO | ET_RXDMA_CSR_FBR1_SIZE_HI; |
Mark Einon | b525486 | 2012-10-19 23:08:16 +0100 | [diff] [blame] | 821 | |
Mark Einon | 3040d05 | 2013-01-04 22:25:45 +0000 | [diff] [blame] | 822 | csr |= ET_RXDMA_CSR_FBR0_ENABLE; |
ZHAO Gang | 8f7fa96 | 2013-12-08 11:01:06 +0800 | [diff] [blame] | 823 | if (rx_ring->fbr[0]->buffsize == 256) |
Mark Einon | 3040d05 | 2013-01-04 22:25:45 +0000 | [diff] [blame] | 824 | csr |= ET_RXDMA_CSR_FBR0_SIZE_LO; |
ZHAO Gang | 8f7fa96 | 2013-12-08 11:01:06 +0800 | [diff] [blame] | 825 | else if (rx_ring->fbr[0]->buffsize == 512) |
Mark Einon | 3040d05 | 2013-01-04 22:25:45 +0000 | [diff] [blame] | 826 | csr |= ET_RXDMA_CSR_FBR0_SIZE_HI; |
ZHAO Gang | 8f7fa96 | 2013-12-08 11:01:06 +0800 | [diff] [blame] | 827 | else if (rx_ring->fbr[0]->buffsize == 1024) |
Mark Einon | 3040d05 | 2013-01-04 22:25:45 +0000 | [diff] [blame] | 828 | csr |= ET_RXDMA_CSR_FBR0_SIZE_LO | ET_RXDMA_CSR_FBR0_SIZE_HI; |
Mark Einon | 8310c60 | 2011-10-23 10:22:52 +0100 | [diff] [blame] | 829 | writel(csr, &adapter->regs->rxdma.csr); |
| 830 | |
| 831 | csr = readl(&adapter->regs->rxdma.csr); |
Mark Einon | 3040d05 | 2013-01-04 22:25:45 +0000 | [diff] [blame] | 832 | if (csr & ET_RXDMA_CSR_HALT_STATUS) { |
Mark Einon | 8310c60 | 2011-10-23 10:22:52 +0100 | [diff] [blame] | 833 | udelay(5); |
| 834 | csr = readl(&adapter->regs->rxdma.csr); |
Mark Einon | 3040d05 | 2013-01-04 22:25:45 +0000 | [diff] [blame] | 835 | if (csr & ET_RXDMA_CSR_HALT_STATUS) { |
Mark Einon | 8310c60 | 2011-10-23 10:22:52 +0100 | [diff] [blame] | 836 | dev_err(&adapter->pdev->dev, |
| 837 | "RX Dma failed to exit halt state. CSR 0x%08x\n", |
| 838 | csr); |
| 839 | } |
| 840 | } |
| 841 | } |
| 842 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 843 | /* et131x_rx_dma_disable - Stop of Rx_DMA on the ET1310 |
Mark Einon | 8310c60 | 2011-10-23 10:22:52 +0100 | [diff] [blame] | 844 | * @adapter: pointer to our adapter structure |
| 845 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 846 | static void et131x_rx_dma_disable(struct et131x_adapter *adapter) |
Mark Einon | 8310c60 | 2011-10-23 10:22:52 +0100 | [diff] [blame] | 847 | { |
| 848 | u32 csr; |
| 849 | /* Setup the receive dma configuration register */ |
Mark Einon | 3040d05 | 2013-01-04 22:25:45 +0000 | [diff] [blame] | 850 | writel(ET_RXDMA_CSR_HALT | ET_RXDMA_CSR_FBR1_ENABLE, |
| 851 | &adapter->regs->rxdma.csr); |
Mark Einon | 8310c60 | 2011-10-23 10:22:52 +0100 | [diff] [blame] | 852 | csr = readl(&adapter->regs->rxdma.csr); |
Mark Einon | 3040d05 | 2013-01-04 22:25:45 +0000 | [diff] [blame] | 853 | if (!(csr & ET_RXDMA_CSR_HALT_STATUS)) { |
Mark Einon | 8310c60 | 2011-10-23 10:22:52 +0100 | [diff] [blame] | 854 | udelay(5); |
| 855 | csr = readl(&adapter->regs->rxdma.csr); |
Mark Einon | 3040d05 | 2013-01-04 22:25:45 +0000 | [diff] [blame] | 856 | if (!(csr & ET_RXDMA_CSR_HALT_STATUS)) |
Mark Einon | 8310c60 | 2011-10-23 10:22:52 +0100 | [diff] [blame] | 857 | dev_err(&adapter->pdev->dev, |
Mark Einon | 3040d05 | 2013-01-04 22:25:45 +0000 | [diff] [blame] | 858 | "RX Dma failed to enter halt state. CSR 0x%08x\n", |
| 859 | csr); |
Mark Einon | 8310c60 | 2011-10-23 10:22:52 +0100 | [diff] [blame] | 860 | } |
| 861 | } |
| 862 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 863 | /* et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310. |
Mark Einon | 8310c60 | 2011-10-23 10:22:52 +0100 | [diff] [blame] | 864 | * @adapter: pointer to our adapter structure |
| 865 | * |
| 866 | * Mainly used after a return to the D0 (full-power) state from a lower state. |
| 867 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 868 | static void et131x_tx_dma_enable(struct et131x_adapter *adapter) |
Mark Einon | 8310c60 | 2011-10-23 10:22:52 +0100 | [diff] [blame] | 869 | { |
| 870 | /* Setup the transmit dma configuration register for normal |
| 871 | * operation |
| 872 | */ |
| 873 | writel(ET_TXDMA_SNGL_EPKT|(PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT), |
| 874 | &adapter->regs->txdma.csr); |
| 875 | } |
| 876 | |
| 877 | static inline void add_10bit(u32 *v, int n) |
| 878 | { |
| 879 | *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP); |
| 880 | } |
| 881 | |
| 882 | static inline void add_12bit(u32 *v, int n) |
| 883 | { |
| 884 | *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP); |
| 885 | } |
| 886 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 887 | /* et1310_config_mac_regs1 - Initialize the first part of MAC regs |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 888 | * @adapter: pointer to our adapter structure |
| 889 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 890 | static void et1310_config_mac_regs1(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 891 | { |
| 892 | struct mac_regs __iomem *macregs = &adapter->regs->mac; |
| 893 | u32 station1; |
| 894 | u32 station2; |
| 895 | u32 ipg; |
| 896 | |
| 897 | /* First we need to reset everything. Write to MAC configuration |
| 898 | * register 1 to perform reset. |
| 899 | */ |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 900 | writel(ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET | |
| 901 | ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC | |
| 902 | ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC, |
| 903 | ¯egs->cfg1); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 904 | |
| 905 | /* Next lets configure the MAC Inter-packet gap register */ |
| 906 | ipg = 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */ |
| 907 | ipg |= 0x50 << 8; /* ifg enforce 0x50 */ |
| 908 | writel(ipg, ¯egs->ipg); |
| 909 | |
| 910 | /* Next lets configure the MAC Half Duplex register */ |
| 911 | /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */ |
| 912 | writel(0x00A1F037, ¯egs->hfdp); |
| 913 | |
| 914 | /* Next lets configure the MAC Interface Control register */ |
| 915 | writel(0, ¯egs->if_ctrl); |
| 916 | |
| 917 | /* Let's move on to setting up the mii management configuration */ |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 918 | writel(ET_MAC_MIIMGMT_CLK_RST, ¯egs->mii_mgmt_cfg); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 919 | |
| 920 | /* Next lets configure the MAC Station Address register. These |
| 921 | * values are read from the EEPROM during initialization and stored |
| 922 | * in the adapter structure. We write what is stored in the adapter |
| 923 | * structure to the MAC Station Address registers high and low. This |
| 924 | * station address is used for generating and checking pause control |
| 925 | * packets. |
| 926 | */ |
| 927 | station2 = (adapter->addr[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT) | |
| 928 | (adapter->addr[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT); |
| 929 | station1 = (adapter->addr[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT) | |
| 930 | (adapter->addr[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT) | |
| 931 | (adapter->addr[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT) | |
| 932 | adapter->addr[2]; |
| 933 | writel(station1, ¯egs->station_addr_1); |
| 934 | writel(station2, ¯egs->station_addr_2); |
| 935 | |
Justin P. Mattock | ac399bc | 2012-02-20 18:23:09 -0800 | [diff] [blame] | 936 | /* Max ethernet packet in bytes that will be passed by the mac without |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 937 | * being truncated. Allow the MAC to pass 4 more than our max packet |
| 938 | * size. This is 4 for the Ethernet CRC. |
| 939 | * |
| 940 | * Packets larger than (registry_jumbo_packet) that do not contain a |
| 941 | * VLAN ID will be dropped by the Rx function. |
| 942 | */ |
| 943 | writel(adapter->registry_jumbo_packet + 4, ¯egs->max_fm_len); |
| 944 | |
| 945 | /* clear out MAC config reset */ |
| 946 | writel(0, ¯egs->cfg1); |
| 947 | } |
| 948 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 949 | /* et1310_config_mac_regs2 - Initialize the second part of MAC regs |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 950 | * @adapter: pointer to our adapter structure |
| 951 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 952 | static void et1310_config_mac_regs2(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 953 | { |
| 954 | int32_t delay = 0; |
| 955 | struct mac_regs __iomem *mac = &adapter->regs->mac; |
| 956 | struct phy_device *phydev = adapter->phydev; |
| 957 | u32 cfg1; |
| 958 | u32 cfg2; |
| 959 | u32 ifctrl; |
| 960 | u32 ctl; |
| 961 | |
| 962 | ctl = readl(&adapter->regs->txmac.ctl); |
| 963 | cfg1 = readl(&mac->cfg1); |
| 964 | cfg2 = readl(&mac->cfg2); |
| 965 | ifctrl = readl(&mac->if_ctrl); |
| 966 | |
| 967 | /* Set up the if mode bits */ |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 968 | cfg2 &= ~ET_MAC_CFG2_IFMODE_MASK; |
Mark Einon | 76af014 | 2013-12-05 22:37:41 +0000 | [diff] [blame] | 969 | if (phydev->speed == SPEED_1000) { |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 970 | cfg2 |= ET_MAC_CFG2_IFMODE_1000; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 971 | /* Phy mode bit */ |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 972 | ifctrl &= ~ET_MAC_IFCTRL_PHYMODE; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 973 | } else { |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 974 | cfg2 |= ET_MAC_CFG2_IFMODE_100; |
| 975 | ifctrl |= ET_MAC_IFCTRL_PHYMODE; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 976 | } |
| 977 | |
| 978 | /* We need to enable Rx/Tx */ |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 979 | cfg1 |= ET_MAC_CFG1_RX_ENABLE | ET_MAC_CFG1_TX_ENABLE | |
| 980 | ET_MAC_CFG1_TX_FLOW; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 981 | /* Initialize loop back to off */ |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 982 | cfg1 &= ~(ET_MAC_CFG1_LOOPBACK | ET_MAC_CFG1_RX_FLOW); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 983 | if (adapter->flowcontrol == FLOW_RXONLY || |
| 984 | adapter->flowcontrol == FLOW_BOTH) |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 985 | cfg1 |= ET_MAC_CFG1_RX_FLOW; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 986 | writel(cfg1, &mac->cfg1); |
| 987 | |
| 988 | /* Now we need to initialize the MAC Configuration 2 register */ |
| 989 | /* preamble 7, check length, huge frame off, pad crc, crc enable |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 990 | * full duplex off |
| 991 | */ |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 992 | cfg2 |= 0x7 << ET_MAC_CFG2_PREAMBLE_SHIFT; |
| 993 | cfg2 |= ET_MAC_CFG2_IFMODE_LEN_CHECK; |
| 994 | cfg2 |= ET_MAC_CFG2_IFMODE_PAD_CRC; |
| 995 | cfg2 |= ET_MAC_CFG2_IFMODE_CRC_ENABLE; |
| 996 | cfg2 &= ~ET_MAC_CFG2_IFMODE_HUGE_FRAME; |
| 997 | cfg2 &= ~ET_MAC_CFG2_IFMODE_FULL_DPLX; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 998 | |
| 999 | /* Turn on duplex if needed */ |
Mark Einon | 76af014 | 2013-12-05 22:37:41 +0000 | [diff] [blame] | 1000 | if (phydev->duplex == DUPLEX_FULL) |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1001 | cfg2 |= ET_MAC_CFG2_IFMODE_FULL_DPLX; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1002 | |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1003 | ifctrl &= ~ET_MAC_IFCTRL_GHDMODE; |
Mark Einon | 76af014 | 2013-12-05 22:37:41 +0000 | [diff] [blame] | 1004 | if (phydev->duplex == DUPLEX_HALF) |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1005 | ifctrl |= ET_MAC_IFCTRL_GHDMODE; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1006 | |
| 1007 | writel(ifctrl, &mac->if_ctrl); |
| 1008 | writel(cfg2, &mac->cfg2); |
| 1009 | |
| 1010 | do { |
| 1011 | udelay(10); |
| 1012 | delay++; |
| 1013 | cfg1 = readl(&mac->cfg1); |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1014 | } while ((cfg1 & ET_MAC_CFG1_WAIT) != ET_MAC_CFG1_WAIT && delay < 100); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1015 | |
| 1016 | if (delay == 100) { |
| 1017 | dev_warn(&adapter->pdev->dev, |
| 1018 | "Syncd bits did not respond correctly cfg1 word 0x%08x\n", |
| 1019 | cfg1); |
| 1020 | } |
| 1021 | |
| 1022 | /* Enable txmac */ |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1023 | ctl |= ET_TX_CTRL_TXMAC_ENABLE | ET_TX_CTRL_FC_DISABLE; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1024 | writel(ctl, &adapter->regs->txmac.ctl); |
| 1025 | |
| 1026 | /* Ready to start the RXDMA/TXDMA engine */ |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 1027 | if (adapter->flags & FMP_ADAPTER_LOWER_POWER) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1028 | et131x_rx_dma_enable(adapter); |
| 1029 | et131x_tx_dma_enable(adapter); |
| 1030 | } |
| 1031 | } |
| 1032 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 1033 | /* et1310_in_phy_coma - check if the device is in phy coma |
Mark Einon | 2288760e | 2011-10-23 10:22:51 +0100 | [diff] [blame] | 1034 | * @adapter: pointer to our adapter structure |
| 1035 | * |
| 1036 | * Returns 0 if the device is not in phy coma, 1 if it is in phy coma |
| 1037 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1038 | static int et1310_in_phy_coma(struct et131x_adapter *adapter) |
Mark Einon | 2288760e | 2011-10-23 10:22:51 +0100 | [diff] [blame] | 1039 | { |
Mark Einon | 12a2f3f | 2013-12-05 22:37:46 +0000 | [diff] [blame] | 1040 | u32 pmcsr = readl(&adapter->regs->global.pm_csr); |
Mark Einon | 2288760e | 2011-10-23 10:22:51 +0100 | [diff] [blame] | 1041 | |
| 1042 | return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0; |
| 1043 | } |
| 1044 | |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1045 | static void et1310_setup_device_for_multicast(struct et131x_adapter *adapter) |
Mark Einon | a4d444b | 2011-10-23 10:22:50 +0100 | [diff] [blame] | 1046 | { |
| 1047 | struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac; |
Francois Romieu | 834d0ee | 2011-10-23 19:11:19 +0200 | [diff] [blame] | 1048 | u32 hash1 = 0; |
| 1049 | u32 hash2 = 0; |
| 1050 | u32 hash3 = 0; |
| 1051 | u32 hash4 = 0; |
Mark Einon | a4d444b | 2011-10-23 10:22:50 +0100 | [diff] [blame] | 1052 | u32 pm_csr; |
| 1053 | |
| 1054 | /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision |
| 1055 | * the multi-cast LIST. If it is NOT specified, (and "ALL" is not |
| 1056 | * specified) then we should pass NO multi-cast addresses to the |
| 1057 | * driver. |
| 1058 | */ |
| 1059 | if (adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST) { |
Francois Romieu | 834d0ee | 2011-10-23 19:11:19 +0200 | [diff] [blame] | 1060 | int i; |
| 1061 | |
Mark Einon | a4d444b | 2011-10-23 10:22:50 +0100 | [diff] [blame] | 1062 | /* Loop through our multicast array and set up the device */ |
Francois Romieu | 834d0ee | 2011-10-23 19:11:19 +0200 | [diff] [blame] | 1063 | for (i = 0; i < adapter->multicast_addr_count; i++) { |
| 1064 | u32 result; |
| 1065 | |
| 1066 | result = ether_crc(6, adapter->multicast_list[i]); |
Mark Einon | a4d444b | 2011-10-23 10:22:50 +0100 | [diff] [blame] | 1067 | |
| 1068 | result = (result & 0x3F800000) >> 23; |
| 1069 | |
| 1070 | if (result < 32) { |
| 1071 | hash1 |= (1 << result); |
| 1072 | } else if ((31 < result) && (result < 64)) { |
| 1073 | result -= 32; |
| 1074 | hash2 |= (1 << result); |
| 1075 | } else if ((63 < result) && (result < 96)) { |
| 1076 | result -= 64; |
| 1077 | hash3 |= (1 << result); |
| 1078 | } else { |
| 1079 | result -= 96; |
| 1080 | hash4 |= (1 << result); |
| 1081 | } |
| 1082 | } |
| 1083 | } |
| 1084 | |
| 1085 | /* Write out the new hash to the device */ |
| 1086 | pm_csr = readl(&adapter->regs->global.pm_csr); |
| 1087 | if (!et1310_in_phy_coma(adapter)) { |
| 1088 | writel(hash1, &rxmac->multi_hash1); |
| 1089 | writel(hash2, &rxmac->multi_hash2); |
| 1090 | writel(hash3, &rxmac->multi_hash3); |
| 1091 | writel(hash4, &rxmac->multi_hash4); |
| 1092 | } |
| 1093 | } |
| 1094 | |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1095 | static void et1310_setup_device_for_unicast(struct et131x_adapter *adapter) |
Mark Einon | a4d444b | 2011-10-23 10:22:50 +0100 | [diff] [blame] | 1096 | { |
| 1097 | struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac; |
| 1098 | u32 uni_pf1; |
| 1099 | u32 uni_pf2; |
| 1100 | u32 uni_pf3; |
| 1101 | u32 pm_csr; |
| 1102 | |
| 1103 | /* Set up unicast packet filter reg 3 to be the first two octets of |
| 1104 | * the MAC address for both address |
| 1105 | * |
| 1106 | * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the |
| 1107 | * MAC address for second address |
| 1108 | * |
| 1109 | * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the |
| 1110 | * MAC address for first address |
| 1111 | */ |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1112 | uni_pf3 = (adapter->addr[0] << ET_RX_UNI_PF_ADDR2_1_SHIFT) | |
| 1113 | (adapter->addr[1] << ET_RX_UNI_PF_ADDR2_2_SHIFT) | |
| 1114 | (adapter->addr[0] << ET_RX_UNI_PF_ADDR1_1_SHIFT) | |
Mark Einon | a4d444b | 2011-10-23 10:22:50 +0100 | [diff] [blame] | 1115 | adapter->addr[1]; |
| 1116 | |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1117 | uni_pf2 = (adapter->addr[2] << ET_RX_UNI_PF_ADDR2_3_SHIFT) | |
| 1118 | (adapter->addr[3] << ET_RX_UNI_PF_ADDR2_4_SHIFT) | |
| 1119 | (adapter->addr[4] << ET_RX_UNI_PF_ADDR2_5_SHIFT) | |
Mark Einon | a4d444b | 2011-10-23 10:22:50 +0100 | [diff] [blame] | 1120 | adapter->addr[5]; |
| 1121 | |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1122 | uni_pf1 = (adapter->addr[2] << ET_RX_UNI_PF_ADDR1_3_SHIFT) | |
| 1123 | (adapter->addr[3] << ET_RX_UNI_PF_ADDR1_4_SHIFT) | |
| 1124 | (adapter->addr[4] << ET_RX_UNI_PF_ADDR1_5_SHIFT) | |
Mark Einon | a4d444b | 2011-10-23 10:22:50 +0100 | [diff] [blame] | 1125 | adapter->addr[5]; |
| 1126 | |
| 1127 | pm_csr = readl(&adapter->regs->global.pm_csr); |
| 1128 | if (!et1310_in_phy_coma(adapter)) { |
| 1129 | writel(uni_pf1, &rxmac->uni_pf_addr1); |
| 1130 | writel(uni_pf2, &rxmac->uni_pf_addr2); |
| 1131 | writel(uni_pf3, &rxmac->uni_pf_addr3); |
| 1132 | } |
| 1133 | } |
| 1134 | |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1135 | static void et1310_config_rxmac_regs(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1136 | { |
| 1137 | struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac; |
| 1138 | struct phy_device *phydev = adapter->phydev; |
| 1139 | u32 sa_lo; |
| 1140 | u32 sa_hi = 0; |
| 1141 | u32 pf_ctrl = 0; |
| 1142 | |
| 1143 | /* Disable the MAC while it is being configured (also disable WOL) */ |
| 1144 | writel(0x8, &rxmac->ctrl); |
| 1145 | |
| 1146 | /* Initialize WOL to disabled. */ |
| 1147 | writel(0, &rxmac->crc0); |
| 1148 | writel(0, &rxmac->crc12); |
| 1149 | writel(0, &rxmac->crc34); |
| 1150 | |
| 1151 | /* We need to set the WOL mask0 - mask4 next. We initialize it to |
| 1152 | * its default Values of 0x00000000 because there are not WOL masks |
| 1153 | * as of this time. |
| 1154 | */ |
| 1155 | writel(0, &rxmac->mask0_word0); |
| 1156 | writel(0, &rxmac->mask0_word1); |
| 1157 | writel(0, &rxmac->mask0_word2); |
| 1158 | writel(0, &rxmac->mask0_word3); |
| 1159 | |
| 1160 | writel(0, &rxmac->mask1_word0); |
| 1161 | writel(0, &rxmac->mask1_word1); |
| 1162 | writel(0, &rxmac->mask1_word2); |
| 1163 | writel(0, &rxmac->mask1_word3); |
| 1164 | |
| 1165 | writel(0, &rxmac->mask2_word0); |
| 1166 | writel(0, &rxmac->mask2_word1); |
| 1167 | writel(0, &rxmac->mask2_word2); |
| 1168 | writel(0, &rxmac->mask2_word3); |
| 1169 | |
| 1170 | writel(0, &rxmac->mask3_word0); |
| 1171 | writel(0, &rxmac->mask3_word1); |
| 1172 | writel(0, &rxmac->mask3_word2); |
| 1173 | writel(0, &rxmac->mask3_word3); |
| 1174 | |
| 1175 | writel(0, &rxmac->mask4_word0); |
| 1176 | writel(0, &rxmac->mask4_word1); |
| 1177 | writel(0, &rxmac->mask4_word2); |
| 1178 | writel(0, &rxmac->mask4_word3); |
| 1179 | |
| 1180 | /* Lets setup the WOL Source Address */ |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1181 | sa_lo = (adapter->addr[2] << ET_RX_WOL_LO_SA3_SHIFT) | |
| 1182 | (adapter->addr[3] << ET_RX_WOL_LO_SA4_SHIFT) | |
| 1183 | (adapter->addr[4] << ET_RX_WOL_LO_SA5_SHIFT) | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1184 | adapter->addr[5]; |
| 1185 | writel(sa_lo, &rxmac->sa_lo); |
| 1186 | |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1187 | sa_hi = (u32) (adapter->addr[0] << ET_RX_WOL_HI_SA1_SHIFT) | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1188 | adapter->addr[1]; |
| 1189 | writel(sa_hi, &rxmac->sa_hi); |
| 1190 | |
| 1191 | /* Disable all Packet Filtering */ |
| 1192 | writel(0, &rxmac->pf_ctrl); |
| 1193 | |
| 1194 | /* Let's initialize the Unicast Packet filtering address */ |
| 1195 | if (adapter->packet_filter & ET131X_PACKET_TYPE_DIRECTED) { |
| 1196 | et1310_setup_device_for_unicast(adapter); |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1197 | pf_ctrl |= ET_RX_PFCTRL_UNICST_FILTER_ENABLE; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1198 | } else { |
| 1199 | writel(0, &rxmac->uni_pf_addr1); |
| 1200 | writel(0, &rxmac->uni_pf_addr2); |
| 1201 | writel(0, &rxmac->uni_pf_addr3); |
| 1202 | } |
| 1203 | |
| 1204 | /* Let's initialize the Multicast hash */ |
| 1205 | if (!(adapter->packet_filter & ET131X_PACKET_TYPE_ALL_MULTICAST)) { |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1206 | pf_ctrl |= ET_RX_PFCTRL_MLTCST_FILTER_ENABLE; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1207 | et1310_setup_device_for_multicast(adapter); |
| 1208 | } |
| 1209 | |
| 1210 | /* Runt packet filtering. Didn't work in version A silicon. */ |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1211 | pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << ET_RX_PFCTRL_MIN_PKT_SZ_SHIFT; |
| 1212 | pf_ctrl |= ET_RX_PFCTRL_FRAG_FILTER_ENABLE; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1213 | |
| 1214 | if (adapter->registry_jumbo_packet > 8192) |
| 1215 | /* In order to transmit jumbo packets greater than 8k, the |
| 1216 | * FIFO between RxMAC and RxDMA needs to be reduced in size |
| 1217 | * to (16k - Jumbo packet size). In order to implement this, |
| 1218 | * we must use "cut through" mode in the RxMAC, which chops |
| 1219 | * packets down into segments which are (max_size * 16). In |
| 1220 | * this case we selected 256 bytes, since this is the size of |
| 1221 | * the PCI-Express TLP's that the 1310 uses. |
| 1222 | * |
| 1223 | * seg_en on, fc_en off, size 0x10 |
| 1224 | */ |
| 1225 | writel(0x41, &rxmac->mcif_ctrl_max_seg); |
| 1226 | else |
| 1227 | writel(0, &rxmac->mcif_ctrl_max_seg); |
| 1228 | |
| 1229 | /* Initialize the MCIF water marks */ |
| 1230 | writel(0, &rxmac->mcif_water_mark); |
| 1231 | |
| 1232 | /* Initialize the MIF control */ |
| 1233 | writel(0, &rxmac->mif_ctrl); |
| 1234 | |
| 1235 | /* Initialize the Space Available Register */ |
| 1236 | writel(0, &rxmac->space_avail); |
| 1237 | |
| 1238 | /* Initialize the the mif_ctrl register |
| 1239 | * bit 3: Receive code error. One or more nibbles were signaled as |
| 1240 | * errors during the reception of the packet. Clear this |
| 1241 | * bit in Gigabit, set it in 100Mbit. This was derived |
| 1242 | * experimentally at UNH. |
| 1243 | * bit 4: Receive CRC error. The packet's CRC did not match the |
| 1244 | * internally generated CRC. |
| 1245 | * bit 5: Receive length check error. Indicates that frame length |
| 1246 | * field value in the packet does not match the actual data |
| 1247 | * byte length and is not a type field. |
| 1248 | * bit 16: Receive frame truncated. |
| 1249 | * bit 17: Drop packet enable |
| 1250 | */ |
| 1251 | if (phydev && phydev->speed == SPEED_100) |
| 1252 | writel(0x30038, &rxmac->mif_ctrl); |
| 1253 | else |
| 1254 | writel(0x30030, &rxmac->mif_ctrl); |
| 1255 | |
| 1256 | /* Finally we initialize RxMac to be enabled & WOL disabled. Packet |
| 1257 | * filter is always enabled since it is where the runt packets are |
| 1258 | * supposed to be dropped. For version A silicon, runt packet |
| 1259 | * dropping doesn't work, so it is disabled in the pf_ctrl register, |
| 1260 | * but we still leave the packet filter on. |
| 1261 | */ |
| 1262 | writel(pf_ctrl, &rxmac->pf_ctrl); |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1263 | writel(ET_RX_CTRL_RXMAC_ENABLE | ET_RX_CTRL_WOL_DISABLE, &rxmac->ctrl); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1264 | } |
| 1265 | |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1266 | static void et1310_config_txmac_regs(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1267 | { |
| 1268 | struct txmac_regs __iomem *txmac = &adapter->regs->txmac; |
| 1269 | |
| 1270 | /* We need to update the Control Frame Parameters |
| 1271 | * cfpt - control frame pause timer set to 64 (0x40) |
| 1272 | * cfep - control frame extended pause timer set to 0x0 |
| 1273 | */ |
| 1274 | if (adapter->flowcontrol == FLOW_NONE) |
| 1275 | writel(0, &txmac->cf_param); |
| 1276 | else |
| 1277 | writel(0x40, &txmac->cf_param); |
| 1278 | } |
| 1279 | |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1280 | static void et1310_config_macstat_regs(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1281 | { |
| 1282 | struct macstat_regs __iomem *macstat = |
| 1283 | &adapter->regs->macstat; |
| 1284 | |
| 1285 | /* Next we need to initialize all the macstat registers to zero on |
| 1286 | * the device. |
| 1287 | */ |
| 1288 | writel(0, &macstat->txrx_0_64_byte_frames); |
| 1289 | writel(0, &macstat->txrx_65_127_byte_frames); |
| 1290 | writel(0, &macstat->txrx_128_255_byte_frames); |
| 1291 | writel(0, &macstat->txrx_256_511_byte_frames); |
| 1292 | writel(0, &macstat->txrx_512_1023_byte_frames); |
| 1293 | writel(0, &macstat->txrx_1024_1518_byte_frames); |
| 1294 | writel(0, &macstat->txrx_1519_1522_gvln_frames); |
| 1295 | |
| 1296 | writel(0, &macstat->rx_bytes); |
| 1297 | writel(0, &macstat->rx_packets); |
| 1298 | writel(0, &macstat->rx_fcs_errs); |
| 1299 | writel(0, &macstat->rx_multicast_packets); |
| 1300 | writel(0, &macstat->rx_broadcast_packets); |
| 1301 | writel(0, &macstat->rx_control_frames); |
| 1302 | writel(0, &macstat->rx_pause_frames); |
| 1303 | writel(0, &macstat->rx_unknown_opcodes); |
| 1304 | writel(0, &macstat->rx_align_errs); |
| 1305 | writel(0, &macstat->rx_frame_len_errs); |
| 1306 | writel(0, &macstat->rx_code_errs); |
| 1307 | writel(0, &macstat->rx_carrier_sense_errs); |
| 1308 | writel(0, &macstat->rx_undersize_packets); |
| 1309 | writel(0, &macstat->rx_oversize_packets); |
| 1310 | writel(0, &macstat->rx_fragment_packets); |
| 1311 | writel(0, &macstat->rx_jabbers); |
| 1312 | writel(0, &macstat->rx_drops); |
| 1313 | |
| 1314 | writel(0, &macstat->tx_bytes); |
| 1315 | writel(0, &macstat->tx_packets); |
| 1316 | writel(0, &macstat->tx_multicast_packets); |
| 1317 | writel(0, &macstat->tx_broadcast_packets); |
| 1318 | writel(0, &macstat->tx_pause_frames); |
| 1319 | writel(0, &macstat->tx_deferred); |
| 1320 | writel(0, &macstat->tx_excessive_deferred); |
| 1321 | writel(0, &macstat->tx_single_collisions); |
| 1322 | writel(0, &macstat->tx_multiple_collisions); |
| 1323 | writel(0, &macstat->tx_late_collisions); |
| 1324 | writel(0, &macstat->tx_excessive_collisions); |
| 1325 | writel(0, &macstat->tx_total_collisions); |
| 1326 | writel(0, &macstat->tx_pause_honored_frames); |
| 1327 | writel(0, &macstat->tx_drops); |
| 1328 | writel(0, &macstat->tx_jabbers); |
| 1329 | writel(0, &macstat->tx_fcs_errs); |
| 1330 | writel(0, &macstat->tx_control_frames); |
| 1331 | writel(0, &macstat->tx_oversize_frames); |
| 1332 | writel(0, &macstat->tx_undersize_frames); |
| 1333 | writel(0, &macstat->tx_fragments); |
| 1334 | writel(0, &macstat->carry_reg1); |
| 1335 | writel(0, &macstat->carry_reg2); |
| 1336 | |
| 1337 | /* Unmask any counters that we want to track the overflow of. |
| 1338 | * Initially this will be all counters. It may become clear later |
| 1339 | * that we do not need to track all counters. |
| 1340 | */ |
| 1341 | writel(0xFFFFBE32, &macstat->carry_reg1_mask); |
| 1342 | writel(0xFFFE7E8B, &macstat->carry_reg2_mask); |
| 1343 | } |
| 1344 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 1345 | /* et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC |
Mark Einon | 2288760e | 2011-10-23 10:22:51 +0100 | [diff] [blame] | 1346 | * @adapter: pointer to our private adapter structure |
| 1347 | * @addr: the address of the transceiver |
| 1348 | * @reg: the register to read |
| 1349 | * @value: pointer to a 16-bit value in which the value will be stored |
Mark Einon | 2288760e | 2011-10-23 10:22:51 +0100 | [diff] [blame] | 1350 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1351 | static int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr, |
Mark Einon | 2288760e | 2011-10-23 10:22:51 +0100 | [diff] [blame] | 1352 | u8 reg, u16 *value) |
| 1353 | { |
| 1354 | struct mac_regs __iomem *mac = &adapter->regs->mac; |
| 1355 | int status = 0; |
| 1356 | u32 delay = 0; |
| 1357 | u32 mii_addr; |
| 1358 | u32 mii_cmd; |
| 1359 | u32 mii_indicator; |
| 1360 | |
| 1361 | /* Save a local copy of the registers we are dealing with so we can |
| 1362 | * set them back |
| 1363 | */ |
| 1364 | mii_addr = readl(&mac->mii_mgmt_addr); |
| 1365 | mii_cmd = readl(&mac->mii_mgmt_cmd); |
| 1366 | |
| 1367 | /* Stop the current operation */ |
| 1368 | writel(0, &mac->mii_mgmt_cmd); |
| 1369 | |
| 1370 | /* Set up the register we need to read from on the correct PHY */ |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1371 | writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr); |
Mark Einon | 2288760e | 2011-10-23 10:22:51 +0100 | [diff] [blame] | 1372 | |
| 1373 | writel(0x1, &mac->mii_mgmt_cmd); |
| 1374 | |
| 1375 | do { |
| 1376 | udelay(50); |
| 1377 | delay++; |
| 1378 | mii_indicator = readl(&mac->mii_mgmt_indicator); |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1379 | } while ((mii_indicator & ET_MAC_MGMT_WAIT) && delay < 50); |
Mark Einon | 2288760e | 2011-10-23 10:22:51 +0100 | [diff] [blame] | 1380 | |
| 1381 | /* If we hit the max delay, we could not read the register */ |
| 1382 | if (delay == 50) { |
| 1383 | dev_warn(&adapter->pdev->dev, |
| 1384 | "reg 0x%08x could not be read\n", reg); |
| 1385 | dev_warn(&adapter->pdev->dev, "status is 0x%08x\n", |
| 1386 | mii_indicator); |
| 1387 | |
| 1388 | status = -EIO; |
Zhao, Gang | a863a15 | 2014-02-06 00:10:34 +0800 | [diff] [blame] | 1389 | goto out; |
Mark Einon | 2288760e | 2011-10-23 10:22:51 +0100 | [diff] [blame] | 1390 | } |
| 1391 | |
| 1392 | /* If we hit here we were able to read the register and we need to |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 1393 | * return the value to the caller |
| 1394 | */ |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1395 | *value = readl(&mac->mii_mgmt_stat) & ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK; |
Mark Einon | 2288760e | 2011-10-23 10:22:51 +0100 | [diff] [blame] | 1396 | |
Zhao, Gang | a863a15 | 2014-02-06 00:10:34 +0800 | [diff] [blame] | 1397 | out: |
Mark Einon | 2288760e | 2011-10-23 10:22:51 +0100 | [diff] [blame] | 1398 | /* Stop the read operation */ |
| 1399 | writel(0, &mac->mii_mgmt_cmd); |
| 1400 | |
| 1401 | /* set the registers we touched back to the state at which we entered |
| 1402 | * this function |
| 1403 | */ |
| 1404 | writel(mii_addr, &mac->mii_mgmt_addr); |
| 1405 | writel(mii_cmd, &mac->mii_mgmt_cmd); |
| 1406 | |
| 1407 | return status; |
| 1408 | } |
| 1409 | |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1410 | static int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value) |
Mark Einon | 2288760e | 2011-10-23 10:22:51 +0100 | [diff] [blame] | 1411 | { |
| 1412 | struct phy_device *phydev = adapter->phydev; |
| 1413 | |
| 1414 | if (!phydev) |
| 1415 | return -EIO; |
| 1416 | |
| 1417 | return et131x_phy_mii_read(adapter, phydev->addr, reg, value); |
| 1418 | } |
| 1419 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 1420 | /* et131x_mii_write - Write to a PHY reg through the MII interface of the MAC |
Mark Einon | 2288760e | 2011-10-23 10:22:51 +0100 | [diff] [blame] | 1421 | * @adapter: pointer to our private adapter structure |
| 1422 | * @reg: the register to read |
| 1423 | * @value: 16-bit value to write |
Mark Einon | 2288760e | 2011-10-23 10:22:51 +0100 | [diff] [blame] | 1424 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1425 | static int et131x_mii_write(struct et131x_adapter *adapter, u8 reg, u16 value) |
Mark Einon | 2288760e | 2011-10-23 10:22:51 +0100 | [diff] [blame] | 1426 | { |
| 1427 | struct mac_regs __iomem *mac = &adapter->regs->mac; |
| 1428 | struct phy_device *phydev = adapter->phydev; |
| 1429 | int status = 0; |
| 1430 | u8 addr; |
| 1431 | u32 delay = 0; |
| 1432 | u32 mii_addr; |
| 1433 | u32 mii_cmd; |
| 1434 | u32 mii_indicator; |
| 1435 | |
| 1436 | if (!phydev) |
| 1437 | return -EIO; |
| 1438 | |
| 1439 | addr = phydev->addr; |
| 1440 | |
| 1441 | /* Save a local copy of the registers we are dealing with so we can |
| 1442 | * set them back |
| 1443 | */ |
| 1444 | mii_addr = readl(&mac->mii_mgmt_addr); |
| 1445 | mii_cmd = readl(&mac->mii_mgmt_cmd); |
| 1446 | |
| 1447 | /* Stop the current operation */ |
| 1448 | writel(0, &mac->mii_mgmt_cmd); |
| 1449 | |
| 1450 | /* Set up the register we need to write to on the correct PHY */ |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1451 | writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr); |
Mark Einon | 2288760e | 2011-10-23 10:22:51 +0100 | [diff] [blame] | 1452 | |
| 1453 | /* Add the value to write to the registers to the mac */ |
| 1454 | writel(value, &mac->mii_mgmt_ctrl); |
| 1455 | |
| 1456 | do { |
| 1457 | udelay(50); |
| 1458 | delay++; |
| 1459 | mii_indicator = readl(&mac->mii_mgmt_indicator); |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1460 | } while ((mii_indicator & ET_MAC_MGMT_BUSY) && delay < 100); |
Mark Einon | 2288760e | 2011-10-23 10:22:51 +0100 | [diff] [blame] | 1461 | |
| 1462 | /* If we hit the max delay, we could not write the register */ |
| 1463 | if (delay == 100) { |
| 1464 | u16 tmp; |
| 1465 | |
| 1466 | dev_warn(&adapter->pdev->dev, |
| 1467 | "reg 0x%08x could not be written", reg); |
| 1468 | dev_warn(&adapter->pdev->dev, "status is 0x%08x\n", |
| 1469 | mii_indicator); |
| 1470 | dev_warn(&adapter->pdev->dev, "command is 0x%08x\n", |
| 1471 | readl(&mac->mii_mgmt_cmd)); |
| 1472 | |
| 1473 | et131x_mii_read(adapter, reg, &tmp); |
| 1474 | |
| 1475 | status = -EIO; |
| 1476 | } |
| 1477 | /* Stop the write operation */ |
| 1478 | writel(0, &mac->mii_mgmt_cmd); |
| 1479 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 1480 | /* set the registers we touched back to the state at which we entered |
Mark Einon | 2288760e | 2011-10-23 10:22:51 +0100 | [diff] [blame] | 1481 | * this function |
| 1482 | */ |
| 1483 | writel(mii_addr, &mac->mii_mgmt_addr); |
| 1484 | writel(mii_cmd, &mac->mii_mgmt_cmd); |
| 1485 | |
| 1486 | return status; |
| 1487 | } |
| 1488 | |
Mark Einon | 19d857d | 2013-12-05 22:37:43 +0000 | [diff] [blame] | 1489 | static void et1310_phy_read_mii_bit(struct et131x_adapter *adapter, |
| 1490 | u16 regnum, |
| 1491 | u16 bitnum, |
| 1492 | u8 *value) |
Mark Einon | 2288760e | 2011-10-23 10:22:51 +0100 | [diff] [blame] | 1493 | { |
| 1494 | u16 reg; |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1495 | u16 mask = 1 << bitnum; |
Mark Einon | 2288760e | 2011-10-23 10:22:51 +0100 | [diff] [blame] | 1496 | |
| 1497 | /* Read the requested register */ |
| 1498 | et131x_mii_read(adapter, regnum, ®); |
| 1499 | |
Mark Einon | 19d857d | 2013-12-05 22:37:43 +0000 | [diff] [blame] | 1500 | *value = (reg & mask) >> bitnum; |
Mark Einon | 2288760e | 2011-10-23 10:22:51 +0100 | [diff] [blame] | 1501 | } |
| 1502 | |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1503 | static void et1310_config_flow_control(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1504 | { |
| 1505 | struct phy_device *phydev = adapter->phydev; |
| 1506 | |
| 1507 | if (phydev->duplex == DUPLEX_HALF) { |
| 1508 | adapter->flowcontrol = FLOW_NONE; |
| 1509 | } else { |
| 1510 | char remote_pause, remote_async_pause; |
| 1511 | |
Mark Einon | 19d857d | 2013-12-05 22:37:43 +0000 | [diff] [blame] | 1512 | et1310_phy_read_mii_bit(adapter, 5, 10, &remote_pause); |
| 1513 | et1310_phy_read_mii_bit(adapter, 5, 11, &remote_async_pause); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1514 | |
Mark Einon | 19d857d | 2013-12-05 22:37:43 +0000 | [diff] [blame] | 1515 | if (remote_pause && remote_async_pause) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1516 | adapter->flowcontrol = adapter->wanted_flow; |
Mark Einon | 19d857d | 2013-12-05 22:37:43 +0000 | [diff] [blame] | 1517 | } else if (remote_pause && !remote_async_pause) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1518 | if (adapter->wanted_flow == FLOW_BOTH) |
| 1519 | adapter->flowcontrol = FLOW_BOTH; |
| 1520 | else |
| 1521 | adapter->flowcontrol = FLOW_NONE; |
Mark Einon | 19d857d | 2013-12-05 22:37:43 +0000 | [diff] [blame] | 1522 | } else if (!remote_pause && !remote_async_pause) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1523 | adapter->flowcontrol = FLOW_NONE; |
Mark Einon | 19d857d | 2013-12-05 22:37:43 +0000 | [diff] [blame] | 1524 | } else { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1525 | if (adapter->wanted_flow == FLOW_BOTH) |
| 1526 | adapter->flowcontrol = FLOW_RXONLY; |
| 1527 | else |
| 1528 | adapter->flowcontrol = FLOW_NONE; |
| 1529 | } |
| 1530 | } |
| 1531 | } |
| 1532 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 1533 | /* et1310_update_macstat_host_counters - Update local copy of the statistics */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1534 | static void et1310_update_macstat_host_counters(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1535 | { |
| 1536 | struct ce_stats *stats = &adapter->stats; |
| 1537 | struct macstat_regs __iomem *macstat = |
| 1538 | &adapter->regs->macstat; |
| 1539 | |
| 1540 | stats->tx_collisions += readl(&macstat->tx_total_collisions); |
| 1541 | stats->tx_first_collisions += readl(&macstat->tx_single_collisions); |
| 1542 | stats->tx_deferred += readl(&macstat->tx_deferred); |
| 1543 | stats->tx_excessive_collisions += |
| 1544 | readl(&macstat->tx_multiple_collisions); |
| 1545 | stats->tx_late_collisions += readl(&macstat->tx_late_collisions); |
| 1546 | stats->tx_underflows += readl(&macstat->tx_undersize_frames); |
| 1547 | stats->tx_max_pkt_errs += readl(&macstat->tx_oversize_frames); |
| 1548 | |
| 1549 | stats->rx_align_errs += readl(&macstat->rx_align_errs); |
| 1550 | stats->rx_crc_errs += readl(&macstat->rx_code_errs); |
| 1551 | stats->rcvd_pkts_dropped += readl(&macstat->rx_drops); |
| 1552 | stats->rx_overflows += readl(&macstat->rx_oversize_packets); |
| 1553 | stats->rx_code_violations += readl(&macstat->rx_fcs_errs); |
| 1554 | stats->rx_length_errs += readl(&macstat->rx_frame_len_errs); |
| 1555 | stats->rx_other_errs += readl(&macstat->rx_fragment_packets); |
| 1556 | } |
| 1557 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 1558 | /* et1310_handle_macstat_interrupt |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1559 | * |
| 1560 | * One of the MACSTAT counters has wrapped. Update the local copy of |
| 1561 | * the statistics held in the adapter structure, checking the "wrap" |
| 1562 | * bit for each counter. |
| 1563 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1564 | static void et1310_handle_macstat_interrupt(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1565 | { |
| 1566 | u32 carry_reg1; |
| 1567 | u32 carry_reg2; |
| 1568 | |
| 1569 | /* Read the interrupt bits from the register(s). These are Clear On |
| 1570 | * Write. |
| 1571 | */ |
| 1572 | carry_reg1 = readl(&adapter->regs->macstat.carry_reg1); |
| 1573 | carry_reg2 = readl(&adapter->regs->macstat.carry_reg2); |
| 1574 | |
| 1575 | writel(carry_reg1, &adapter->regs->macstat.carry_reg1); |
| 1576 | writel(carry_reg2, &adapter->regs->macstat.carry_reg2); |
| 1577 | |
| 1578 | /* We need to do update the host copy of all the MAC_STAT counters. |
| 1579 | * For each counter, check it's overflow bit. If the overflow bit is |
| 1580 | * set, then increment the host version of the count by one complete |
| 1581 | * revolution of the counter. This routine is called when the counter |
| 1582 | * block indicates that one of the counters has wrapped. |
| 1583 | */ |
| 1584 | if (carry_reg1 & (1 << 14)) |
| 1585 | adapter->stats.rx_code_violations += COUNTER_WRAP_16_BIT; |
| 1586 | if (carry_reg1 & (1 << 8)) |
| 1587 | adapter->stats.rx_align_errs += COUNTER_WRAP_12_BIT; |
| 1588 | if (carry_reg1 & (1 << 7)) |
| 1589 | adapter->stats.rx_length_errs += COUNTER_WRAP_16_BIT; |
| 1590 | if (carry_reg1 & (1 << 2)) |
| 1591 | adapter->stats.rx_other_errs += COUNTER_WRAP_16_BIT; |
| 1592 | if (carry_reg1 & (1 << 6)) |
| 1593 | adapter->stats.rx_crc_errs += COUNTER_WRAP_16_BIT; |
| 1594 | if (carry_reg1 & (1 << 3)) |
| 1595 | adapter->stats.rx_overflows += COUNTER_WRAP_16_BIT; |
| 1596 | if (carry_reg1 & (1 << 0)) |
| 1597 | adapter->stats.rcvd_pkts_dropped += COUNTER_WRAP_16_BIT; |
| 1598 | if (carry_reg2 & (1 << 16)) |
| 1599 | adapter->stats.tx_max_pkt_errs += COUNTER_WRAP_12_BIT; |
| 1600 | if (carry_reg2 & (1 << 15)) |
| 1601 | adapter->stats.tx_underflows += COUNTER_WRAP_12_BIT; |
| 1602 | if (carry_reg2 & (1 << 6)) |
| 1603 | adapter->stats.tx_first_collisions += COUNTER_WRAP_12_BIT; |
| 1604 | if (carry_reg2 & (1 << 8)) |
| 1605 | adapter->stats.tx_deferred += COUNTER_WRAP_12_BIT; |
| 1606 | if (carry_reg2 & (1 << 5)) |
| 1607 | adapter->stats.tx_excessive_collisions += COUNTER_WRAP_12_BIT; |
| 1608 | if (carry_reg2 & (1 << 4)) |
| 1609 | adapter->stats.tx_late_collisions += COUNTER_WRAP_12_BIT; |
| 1610 | if (carry_reg2 & (1 << 2)) |
| 1611 | adapter->stats.tx_collisions += COUNTER_WRAP_12_BIT; |
| 1612 | } |
| 1613 | |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1614 | static int et131x_mdio_read(struct mii_bus *bus, int phy_addr, int reg) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1615 | { |
| 1616 | struct net_device *netdev = bus->priv; |
| 1617 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 1618 | u16 value; |
| 1619 | int ret; |
| 1620 | |
| 1621 | ret = et131x_phy_mii_read(adapter, phy_addr, reg, &value); |
| 1622 | |
| 1623 | if (ret < 0) |
| 1624 | return ret; |
| 1625 | else |
| 1626 | return value; |
| 1627 | } |
| 1628 | |
joseph daniel | bf3313a | 2012-05-01 00:30:34 +0600 | [diff] [blame] | 1629 | static int et131x_mdio_write(struct mii_bus *bus, int phy_addr, |
| 1630 | int reg, u16 value) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1631 | { |
| 1632 | struct net_device *netdev = bus->priv; |
| 1633 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 1634 | |
| 1635 | return et131x_mii_write(adapter, reg, value); |
| 1636 | } |
| 1637 | |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1638 | static int et131x_mdio_reset(struct mii_bus *bus) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1639 | { |
| 1640 | struct net_device *netdev = bus->priv; |
| 1641 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 1642 | |
| 1643 | et131x_mii_write(adapter, MII_BMCR, BMCR_RESET); |
| 1644 | |
| 1645 | return 0; |
| 1646 | } |
| 1647 | |
ZHAO Gang | 1ff70a7 | 2013-12-04 15:24:12 +0800 | [diff] [blame] | 1648 | /* et1310_phy_power_switch - PHY power control |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1649 | * @adapter: device to control |
| 1650 | * @down: true for off/false for back on |
| 1651 | * |
| 1652 | * one hundred, ten, one thousand megs |
| 1653 | * How would you like to have your LAN accessed |
| 1654 | * Can't you see that this code processed |
| 1655 | * Phy power, phy power.. |
| 1656 | */ |
ZHAO Gang | 1ff70a7 | 2013-12-04 15:24:12 +0800 | [diff] [blame] | 1657 | static void et1310_phy_power_switch(struct et131x_adapter *adapter, bool down) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1658 | { |
| 1659 | u16 data; |
| 1660 | |
| 1661 | et131x_mii_read(adapter, MII_BMCR, &data); |
| 1662 | data &= ~BMCR_PDOWN; |
| 1663 | if (down) |
| 1664 | data |= BMCR_PDOWN; |
| 1665 | et131x_mii_write(adapter, MII_BMCR, data); |
| 1666 | } |
| 1667 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 1668 | /* et131x_xcvr_init - Init the phy if we are setting it into force mode */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1669 | static void et131x_xcvr_init(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1670 | { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1671 | u16 lcr2; |
| 1672 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1673 | /* Set the LED behavior such that LED 1 indicates speed (off = |
| 1674 | * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates |
| 1675 | * link and activity (on for link, blink off for activity). |
| 1676 | * |
| 1677 | * NOTE: Some customizations have been added here for specific |
| 1678 | * vendors; The LED behavior is now determined by vendor data in the |
| 1679 | * EEPROM. However, the above description is the default. |
| 1680 | */ |
| 1681 | if ((adapter->eeprom_data[1] & 0x4) == 0) { |
| 1682 | et131x_mii_read(adapter, PHY_LED_2, &lcr2); |
| 1683 | |
Dan Carpenter | b5b86a4 | 2012-06-09 12:17:01 +0300 | [diff] [blame] | 1684 | lcr2 &= (ET_LED2_LED_100TX | ET_LED2_LED_1000T); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1685 | lcr2 |= (LED_VAL_LINKON_ACTIVE << LED_LINK_SHIFT); |
| 1686 | |
| 1687 | if ((adapter->eeprom_data[1] & 0x8) == 0) |
| 1688 | lcr2 |= (LED_VAL_1000BT_100BTX << LED_TXRX_SHIFT); |
| 1689 | else |
| 1690 | lcr2 |= (LED_VAL_LINKON << LED_TXRX_SHIFT); |
| 1691 | |
| 1692 | et131x_mii_write(adapter, PHY_LED_2, lcr2); |
| 1693 | } |
| 1694 | } |
| 1695 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 1696 | /* et131x_configure_global_regs - configure JAGCore global regs |
Mark Einon | 36f2771 | 2011-10-23 10:22:48 +0100 | [diff] [blame] | 1697 | * |
| 1698 | * Used to configure the global registers on the JAGCore |
| 1699 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1700 | static void et131x_configure_global_regs(struct et131x_adapter *adapter) |
Mark Einon | 36f2771 | 2011-10-23 10:22:48 +0100 | [diff] [blame] | 1701 | { |
| 1702 | struct global_regs __iomem *regs = &adapter->regs->global; |
| 1703 | |
| 1704 | writel(0, ®s->rxq_start_addr); |
| 1705 | writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr); |
| 1706 | |
| 1707 | if (adapter->registry_jumbo_packet < 2048) { |
| 1708 | /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word |
| 1709 | * block of RAM that the driver can split between Tx |
| 1710 | * and Rx as it desires. Our default is to split it |
| 1711 | * 50/50: |
| 1712 | */ |
| 1713 | writel(PARM_RX_MEM_END_DEF, ®s->rxq_end_addr); |
| 1714 | writel(PARM_RX_MEM_END_DEF + 1, ®s->txq_start_addr); |
| 1715 | } else if (adapter->registry_jumbo_packet < 8192) { |
| 1716 | /* For jumbo packets > 2k but < 8k, split 50-50. */ |
| 1717 | writel(INTERNAL_MEM_RX_OFFSET, ®s->rxq_end_addr); |
| 1718 | writel(INTERNAL_MEM_RX_OFFSET + 1, ®s->txq_start_addr); |
| 1719 | } else { |
| 1720 | /* 9216 is the only packet size greater than 8k that |
| 1721 | * is available. The Tx buffer has to be big enough |
| 1722 | * for one whole packet on the Tx side. We'll make |
| 1723 | * the Tx 9408, and give the rest to Rx |
| 1724 | */ |
| 1725 | writel(0x01b3, ®s->rxq_end_addr); |
| 1726 | writel(0x01b4, ®s->txq_start_addr); |
| 1727 | } |
| 1728 | |
| 1729 | /* Initialize the loopback register. Disable all loopbacks. */ |
| 1730 | writel(0, ®s->loopback); |
| 1731 | |
| 1732 | /* MSI Register */ |
| 1733 | writel(0, ®s->msi_config); |
| 1734 | |
| 1735 | /* By default, disable the watchdog timer. It will be enabled when |
| 1736 | * a packet is queued. |
| 1737 | */ |
| 1738 | writel(0, ®s->watchdog_timer); |
| 1739 | } |
| 1740 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 1741 | /* et131x_config_rx_dma_regs - Start of Rx_DMA init sequence */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1742 | static void et131x_config_rx_dma_regs(struct et131x_adapter *adapter) |
Mark Einon | 36f2771 | 2011-10-23 10:22:48 +0100 | [diff] [blame] | 1743 | { |
| 1744 | struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma; |
| 1745 | struct rx_ring *rx_local = &adapter->rx_ring; |
| 1746 | struct fbr_desc *fbr_entry; |
| 1747 | u32 entry; |
| 1748 | u32 psr_num_des; |
| 1749 | unsigned long flags; |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 1750 | u8 id; |
Mark Einon | 36f2771 | 2011-10-23 10:22:48 +0100 | [diff] [blame] | 1751 | |
| 1752 | /* Halt RXDMA to perform the reconfigure. */ |
| 1753 | et131x_rx_dma_disable(adapter); |
| 1754 | |
Mark Einon | 25e8e8a | 2012-10-19 23:08:15 +0100 | [diff] [blame] | 1755 | /* Load the completion writeback physical address */ |
| 1756 | writel(upper_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_hi); |
| 1757 | writel(lower_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_lo); |
Mark Einon | 36f2771 | 2011-10-23 10:22:48 +0100 | [diff] [blame] | 1758 | |
| 1759 | memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block)); |
| 1760 | |
| 1761 | /* Set the address and parameters of the packet status ring into the |
| 1762 | * 1310's registers |
| 1763 | */ |
Mark Einon | 25e8e8a | 2012-10-19 23:08:15 +0100 | [diff] [blame] | 1764 | writel(upper_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_hi); |
| 1765 | writel(lower_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_lo); |
Mark Einon | 36f2771 | 2011-10-23 10:22:48 +0100 | [diff] [blame] | 1766 | writel(rx_local->psr_num_entries - 1, &rx_dma->psr_num_des); |
| 1767 | writel(0, &rx_dma->psr_full_offset); |
| 1768 | |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1769 | psr_num_des = readl(&rx_dma->psr_num_des) & ET_RXDMA_PSR_NUM_DES_MASK; |
Mark Einon | 36f2771 | 2011-10-23 10:22:48 +0100 | [diff] [blame] | 1770 | writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100, |
| 1771 | &rx_dma->psr_min_des); |
| 1772 | |
| 1773 | spin_lock_irqsave(&adapter->rcv_lock, flags); |
| 1774 | |
| 1775 | /* These local variables track the PSR in the adapter structure */ |
| 1776 | rx_local->local_psr_full = 0; |
| 1777 | |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 1778 | for (id = 0; id < NUM_FBRS; id++) { |
Mark Einon | c0594ee | 2013-01-22 17:10:10 +0000 | [diff] [blame] | 1779 | u32 __iomem *num_des; |
| 1780 | u32 __iomem *full_offset; |
| 1781 | u32 __iomem *min_des; |
| 1782 | u32 __iomem *base_hi; |
| 1783 | u32 __iomem *base_lo; |
ZHAO Gang | efc5681 | 2013-12-09 19:38:24 +0800 | [diff] [blame] | 1784 | struct fbr_lookup *fbr = rx_local->fbr[id]; |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 1785 | |
| 1786 | if (id == 0) { |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 1787 | num_des = &rx_dma->fbr0_num_des; |
| 1788 | full_offset = &rx_dma->fbr0_full_offset; |
| 1789 | min_des = &rx_dma->fbr0_min_des; |
| 1790 | base_hi = &rx_dma->fbr0_base_hi; |
| 1791 | base_lo = &rx_dma->fbr0_base_lo; |
Mark Einon | f0ada67 | 2012-11-01 22:56:43 +0000 | [diff] [blame] | 1792 | } else { |
| 1793 | num_des = &rx_dma->fbr1_num_des; |
| 1794 | full_offset = &rx_dma->fbr1_full_offset; |
| 1795 | min_des = &rx_dma->fbr1_min_des; |
| 1796 | base_hi = &rx_dma->fbr1_base_hi; |
| 1797 | base_lo = &rx_dma->fbr1_base_lo; |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 1798 | } |
| 1799 | |
| 1800 | /* Now's the best time to initialize FBR contents */ |
ZHAO Gang | 57cc027 | 2013-12-09 19:38:30 +0800 | [diff] [blame] | 1801 | fbr_entry = fbr->ring_virtaddr; |
ZHAO Gang | efc5681 | 2013-12-09 19:38:24 +0800 | [diff] [blame] | 1802 | for (entry = 0; entry < fbr->num_entries; entry++) { |
| 1803 | fbr_entry->addr_hi = fbr->bus_high[entry]; |
| 1804 | fbr_entry->addr_lo = fbr->bus_low[entry]; |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 1805 | fbr_entry->word2 = entry; |
| 1806 | fbr_entry++; |
| 1807 | } |
| 1808 | |
| 1809 | /* Set the address and parameters of Free buffer ring 1 and 0 |
| 1810 | * into the 1310's registers |
| 1811 | */ |
ZHAO Gang | efc5681 | 2013-12-09 19:38:24 +0800 | [diff] [blame] | 1812 | writel(upper_32_bits(fbr->ring_physaddr), base_hi); |
| 1813 | writel(lower_32_bits(fbr->ring_physaddr), base_lo); |
| 1814 | writel(fbr->num_entries - 1, num_des); |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 1815 | writel(ET_DMA10_WRAP, full_offset); |
| 1816 | |
| 1817 | /* This variable tracks the free buffer ring 1 full position, |
| 1818 | * so it has to match the above. |
| 1819 | */ |
ZHAO Gang | efc5681 | 2013-12-09 19:38:24 +0800 | [diff] [blame] | 1820 | fbr->local_full = ET_DMA10_WRAP; |
| 1821 | writel(((fbr->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1, |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 1822 | min_des); |
Mark Einon | 36f2771 | 2011-10-23 10:22:48 +0100 | [diff] [blame] | 1823 | } |
| 1824 | |
Mark Einon | 36f2771 | 2011-10-23 10:22:48 +0100 | [diff] [blame] | 1825 | /* Program the number of packets we will receive before generating an |
| 1826 | * interrupt. |
| 1827 | * For version B silicon, this value gets updated once autoneg is |
| 1828 | *complete. |
| 1829 | */ |
| 1830 | writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done); |
| 1831 | |
| 1832 | /* The "time_done" is not working correctly to coalesce interrupts |
| 1833 | * after a given time period, but rather is giving us an interrupt |
| 1834 | * regardless of whether we have received packets. |
| 1835 | * This value gets updated once autoneg is complete. |
| 1836 | */ |
| 1837 | writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time); |
| 1838 | |
| 1839 | spin_unlock_irqrestore(&adapter->rcv_lock, flags); |
| 1840 | } |
| 1841 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 1842 | /* et131x_config_tx_dma_regs - Set up the tx dma section of the JAGCore. |
Mark Einon | 36f2771 | 2011-10-23 10:22:48 +0100 | [diff] [blame] | 1843 | * |
| 1844 | * Configure the transmit engine with the ring buffers we have created |
| 1845 | * and prepare it for use. |
| 1846 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1847 | static void et131x_config_tx_dma_regs(struct et131x_adapter *adapter) |
Mark Einon | 36f2771 | 2011-10-23 10:22:48 +0100 | [diff] [blame] | 1848 | { |
| 1849 | struct txdma_regs __iomem *txdma = &adapter->regs->txdma; |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 1850 | struct tx_ring *tx_ring = &adapter->tx_ring; |
Mark Einon | 36f2771 | 2011-10-23 10:22:48 +0100 | [diff] [blame] | 1851 | |
| 1852 | /* Load the hardware with the start of the transmit descriptor ring. */ |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 1853 | writel(upper_32_bits(tx_ring->tx_desc_ring_pa), &txdma->pr_base_hi); |
| 1854 | writel(lower_32_bits(tx_ring->tx_desc_ring_pa), &txdma->pr_base_lo); |
Mark Einon | 36f2771 | 2011-10-23 10:22:48 +0100 | [diff] [blame] | 1855 | |
| 1856 | /* Initialise the transmit DMA engine */ |
| 1857 | writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des); |
| 1858 | |
| 1859 | /* Load the completion writeback physical address */ |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 1860 | writel(upper_32_bits(tx_ring->tx_status_pa), &txdma->dma_wb_base_hi); |
| 1861 | writel(lower_32_bits(tx_ring->tx_status_pa), &txdma->dma_wb_base_lo); |
Mark Einon | 36f2771 | 2011-10-23 10:22:48 +0100 | [diff] [blame] | 1862 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 1863 | *tx_ring->tx_status = 0; |
Mark Einon | 36f2771 | 2011-10-23 10:22:48 +0100 | [diff] [blame] | 1864 | |
| 1865 | writel(0, &txdma->service_request); |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 1866 | tx_ring->send_idx = 0; |
Mark Einon | 36f2771 | 2011-10-23 10:22:48 +0100 | [diff] [blame] | 1867 | } |
| 1868 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 1869 | /* et131x_adapter_setup - Set the adapter up as per cassini+ documentation */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1870 | static void et131x_adapter_setup(struct et131x_adapter *adapter) |
Mark Einon | 36f2771 | 2011-10-23 10:22:48 +0100 | [diff] [blame] | 1871 | { |
| 1872 | /* Configure the JAGCore */ |
| 1873 | et131x_configure_global_regs(adapter); |
| 1874 | |
| 1875 | et1310_config_mac_regs1(adapter); |
| 1876 | |
| 1877 | /* Configure the MMC registers */ |
| 1878 | /* All we need to do is initialize the Memory Control Register */ |
| 1879 | writel(ET_MMC_ENABLE, &adapter->regs->mmc.mmc_ctrl); |
| 1880 | |
| 1881 | et1310_config_rxmac_regs(adapter); |
| 1882 | et1310_config_txmac_regs(adapter); |
| 1883 | |
| 1884 | et131x_config_rx_dma_regs(adapter); |
| 1885 | et131x_config_tx_dma_regs(adapter); |
| 1886 | |
| 1887 | et1310_config_macstat_regs(adapter); |
| 1888 | |
ZHAO Gang | 1ff70a7 | 2013-12-04 15:24:12 +0800 | [diff] [blame] | 1889 | et1310_phy_power_switch(adapter, 0); |
Mark Einon | 36f2771 | 2011-10-23 10:22:48 +0100 | [diff] [blame] | 1890 | et131x_xcvr_init(adapter); |
| 1891 | } |
| 1892 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 1893 | /* et131x_soft_reset - Issue soft reset to the hardware, complete for ET1310 */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1894 | static void et131x_soft_reset(struct et131x_adapter *adapter) |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 1895 | { |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1896 | u32 reg; |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 1897 | |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 1898 | /* Disable MAC Core */ |
| 1899 | reg = ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET | |
| 1900 | ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC | |
| 1901 | ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC; |
| 1902 | writel(reg, &adapter->regs->mac.cfg1); |
| 1903 | |
| 1904 | reg = ET_RESET_ALL; |
| 1905 | writel(reg, &adapter->regs->global.sw_reset); |
| 1906 | |
| 1907 | reg = ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC | |
| 1908 | ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC; |
| 1909 | writel(reg, &adapter->regs->mac.cfg1); |
| 1910 | writel(0, &adapter->regs->mac.cfg1); |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 1911 | } |
| 1912 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 1913 | /* et131x_enable_interrupts - enable interrupt |
Mark Einon | a4d444b | 2011-10-23 10:22:50 +0100 | [diff] [blame] | 1914 | * |
| 1915 | * Enable the appropriate interrupts on the ET131x according to our |
| 1916 | * configuration |
| 1917 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1918 | static void et131x_enable_interrupts(struct et131x_adapter *adapter) |
Mark Einon | a4d444b | 2011-10-23 10:22:50 +0100 | [diff] [blame] | 1919 | { |
| 1920 | u32 mask; |
| 1921 | |
| 1922 | /* Enable all global interrupts */ |
| 1923 | if (adapter->flowcontrol == FLOW_TXONLY || |
Mark Einon | 12a2f3f | 2013-12-05 22:37:46 +0000 | [diff] [blame] | 1924 | adapter->flowcontrol == FLOW_BOTH) |
Mark Einon | a4d444b | 2011-10-23 10:22:50 +0100 | [diff] [blame] | 1925 | mask = INT_MASK_ENABLE; |
| 1926 | else |
| 1927 | mask = INT_MASK_ENABLE_NO_FLOW; |
| 1928 | |
| 1929 | writel(mask, &adapter->regs->global.int_mask); |
| 1930 | } |
| 1931 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 1932 | /* et131x_disable_interrupts - interrupt disable |
Mark Einon | a4d444b | 2011-10-23 10:22:50 +0100 | [diff] [blame] | 1933 | * |
| 1934 | * Block all interrupts from the et131x device at the device itself |
| 1935 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1936 | static void et131x_disable_interrupts(struct et131x_adapter *adapter) |
Mark Einon | a4d444b | 2011-10-23 10:22:50 +0100 | [diff] [blame] | 1937 | { |
| 1938 | /* Disable all global interrupts */ |
| 1939 | writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask); |
| 1940 | } |
| 1941 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 1942 | /* et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310 */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1943 | static void et131x_tx_dma_disable(struct et131x_adapter *adapter) |
Mark Einon | a4d444b | 2011-10-23 10:22:50 +0100 | [diff] [blame] | 1944 | { |
| 1945 | /* Setup the tramsmit dma configuration register */ |
Mark Einon | 3040d05 | 2013-01-04 22:25:45 +0000 | [diff] [blame] | 1946 | writel(ET_TXDMA_CSR_HALT | ET_TXDMA_SNGL_EPKT, |
Mark Einon | a4d444b | 2011-10-23 10:22:50 +0100 | [diff] [blame] | 1947 | &adapter->regs->txdma.csr); |
| 1948 | } |
| 1949 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 1950 | /* et131x_enable_txrx - Enable tx/rx queues */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1951 | static void et131x_enable_txrx(struct net_device *netdev) |
Mark Einon | a4d444b | 2011-10-23 10:22:50 +0100 | [diff] [blame] | 1952 | { |
| 1953 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 1954 | |
| 1955 | /* Enable the Tx and Rx DMA engines (if not already enabled) */ |
| 1956 | et131x_rx_dma_enable(adapter); |
| 1957 | et131x_tx_dma_enable(adapter); |
| 1958 | |
| 1959 | /* Enable device interrupts */ |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 1960 | if (adapter->flags & FMP_ADAPTER_INTERRUPT_IN_USE) |
Mark Einon | a4d444b | 2011-10-23 10:22:50 +0100 | [diff] [blame] | 1961 | et131x_enable_interrupts(adapter); |
| 1962 | |
| 1963 | /* We're ready to move some data, so start the queue */ |
| 1964 | netif_start_queue(netdev); |
| 1965 | } |
| 1966 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 1967 | /* et131x_disable_txrx - Disable tx/rx queues */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1968 | static void et131x_disable_txrx(struct net_device *netdev) |
Mark Einon | a4d444b | 2011-10-23 10:22:50 +0100 | [diff] [blame] | 1969 | { |
| 1970 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 1971 | |
| 1972 | /* First thing is to stop the queue */ |
| 1973 | netif_stop_queue(netdev); |
| 1974 | |
| 1975 | /* Stop the Tx and Rx DMA engines */ |
| 1976 | et131x_rx_dma_disable(adapter); |
| 1977 | et131x_tx_dma_disable(adapter); |
| 1978 | |
| 1979 | /* Disable device interrupts */ |
| 1980 | et131x_disable_interrupts(adapter); |
| 1981 | } |
| 1982 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 1983 | /* et131x_init_send - Initialize send data structures */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 1984 | static void et131x_init_send(struct et131x_adapter *adapter) |
Mark Einon | 8310c60 | 2011-10-23 10:22:52 +0100 | [diff] [blame] | 1985 | { |
Mark Einon | 8310c60 | 2011-10-23 10:22:52 +0100 | [diff] [blame] | 1986 | u32 ct; |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 1987 | struct tx_ring *tx_ring = &adapter->tx_ring; |
| 1988 | struct tcb *tcb = tx_ring->tcb_ring; |
Mark Einon | 8310c60 | 2011-10-23 10:22:52 +0100 | [diff] [blame] | 1989 | |
| 1990 | tx_ring->tcb_qhead = tcb; |
| 1991 | |
| 1992 | memset(tcb, 0, sizeof(struct tcb) * NUM_TCB); |
| 1993 | |
| 1994 | /* Go through and set up each TCB */ |
| 1995 | for (ct = 0; ct++ < NUM_TCB; tcb++) |
| 1996 | /* Set the link pointer in HW TCB to the next TCB in the |
| 1997 | * chain |
| 1998 | */ |
| 1999 | tcb->next = tcb + 1; |
| 2000 | |
| 2001 | /* Set the tail pointer */ |
| 2002 | tcb--; |
| 2003 | tx_ring->tcb_qtail = tcb; |
| 2004 | tcb->next = NULL; |
| 2005 | /* Curr send queue should now be empty */ |
| 2006 | tx_ring->send_head = NULL; |
| 2007 | tx_ring->send_tail = NULL; |
| 2008 | } |
| 2009 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 2010 | /* et1310_enable_phy_coma - called when network cable is unplugged |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2011 | * |
| 2012 | * driver receive an phy status change interrupt while in D0 and check that |
| 2013 | * phy_status is down. |
| 2014 | * |
| 2015 | * -- gate off JAGCore; |
| 2016 | * -- set gigE PHY in Coma mode |
| 2017 | * -- wake on phy_interrupt; Perform software reset JAGCore, |
| 2018 | * re-initialize jagcore and gigE PHY |
| 2019 | * |
| 2020 | * Add D0-ASPM-PhyLinkDown Support: |
| 2021 | * -- while in D0, when there is a phy_interrupt indicating phy link |
| 2022 | * down status, call the MPSetPhyComa routine to enter this active |
| 2023 | * state power saving mode |
| 2024 | * -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt |
| 2025 | * indicating linkup status, call the MPDisablePhyComa routine to |
| 2026 | * restore JAGCore and gigE PHY |
| 2027 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 2028 | static void et1310_enable_phy_coma(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2029 | { |
| 2030 | unsigned long flags; |
| 2031 | u32 pmcsr; |
| 2032 | |
| 2033 | pmcsr = readl(&adapter->regs->global.pm_csr); |
| 2034 | |
| 2035 | /* Save the GbE PHY speed and duplex modes. Need to restore this |
| 2036 | * when cable is plugged back in |
| 2037 | */ |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2038 | |
| 2039 | /* Stop sending packets. */ |
| 2040 | spin_lock_irqsave(&adapter->send_hw_lock, flags); |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 2041 | adapter->flags |= FMP_ADAPTER_LOWER_POWER; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2042 | spin_unlock_irqrestore(&adapter->send_hw_lock, flags); |
| 2043 | |
| 2044 | /* Wait for outstanding Receive packets */ |
| 2045 | |
| 2046 | et131x_disable_txrx(adapter->netdev); |
| 2047 | |
| 2048 | /* Gate off JAGCore 3 clock domains */ |
| 2049 | pmcsr &= ~ET_PMCSR_INIT; |
| 2050 | writel(pmcsr, &adapter->regs->global.pm_csr); |
| 2051 | |
| 2052 | /* Program gigE PHY in to Coma mode */ |
| 2053 | pmcsr |= ET_PM_PHY_SW_COMA; |
| 2054 | writel(pmcsr, &adapter->regs->global.pm_csr); |
| 2055 | } |
| 2056 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 2057 | /* et1310_disable_phy_coma - Disable the Phy Coma Mode */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 2058 | static void et1310_disable_phy_coma(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2059 | { |
| 2060 | u32 pmcsr; |
| 2061 | |
| 2062 | pmcsr = readl(&adapter->regs->global.pm_csr); |
| 2063 | |
| 2064 | /* Disable phy_sw_coma register and re-enable JAGCore clocks */ |
| 2065 | pmcsr |= ET_PMCSR_INIT; |
| 2066 | pmcsr &= ~ET_PM_PHY_SW_COMA; |
| 2067 | writel(pmcsr, &adapter->regs->global.pm_csr); |
| 2068 | |
| 2069 | /* Restore the GbE PHY speed and duplex modes; |
| 2070 | * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY |
| 2071 | */ |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2072 | |
| 2073 | /* Re-initialize the send structures */ |
| 2074 | et131x_init_send(adapter); |
| 2075 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2076 | /* Bring the device back to the state it was during init prior to |
| 2077 | * autonegotiation being complete. This way, when we get the auto-neg |
| 2078 | * complete interrupt, we can complete init by calling ConfigMacREGS2. |
| 2079 | */ |
| 2080 | et131x_soft_reset(adapter); |
| 2081 | |
| 2082 | /* setup et1310 as per the documentation ?? */ |
| 2083 | et131x_adapter_setup(adapter); |
| 2084 | |
| 2085 | /* Allow Tx to restart */ |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 2086 | adapter->flags &= ~FMP_ADAPTER_LOWER_POWER; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2087 | |
| 2088 | et131x_enable_txrx(adapter->netdev); |
| 2089 | } |
| 2090 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2091 | static inline u32 bump_free_buff_ring(u32 *free_buff_ring, u32 limit) |
| 2092 | { |
| 2093 | u32 tmp_free_buff_ring = *free_buff_ring; |
| 2094 | tmp_free_buff_ring++; |
| 2095 | /* This works for all cases where limit < 1024. The 1023 case |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 2096 | * works because 1023++ is 1024 which means the if condition is not |
| 2097 | * taken but the carry of the bit into the wrap bit toggles the wrap |
| 2098 | * value correctly |
| 2099 | */ |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2100 | if ((tmp_free_buff_ring & ET_DMA10_MASK) > limit) { |
| 2101 | tmp_free_buff_ring &= ~ET_DMA10_MASK; |
| 2102 | tmp_free_buff_ring ^= ET_DMA10_WRAP; |
| 2103 | } |
| 2104 | /* For the 1023 case */ |
Mark Einon | 12a2f3f | 2013-12-05 22:37:46 +0000 | [diff] [blame] | 2105 | tmp_free_buff_ring &= (ET_DMA10_MASK | ET_DMA10_WRAP); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2106 | *free_buff_ring = tmp_free_buff_ring; |
| 2107 | return tmp_free_buff_ring; |
| 2108 | } |
| 2109 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 2110 | /* et131x_rx_dma_memory_alloc |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2111 | * |
| 2112 | * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required, |
| 2113 | * and the Packet Status Ring. |
| 2114 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 2115 | static int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2116 | { |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2117 | u8 id; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2118 | u32 i, j; |
| 2119 | u32 bufsize; |
Mark Einon | 8764893 | 2012-11-12 21:16:28 +0000 | [diff] [blame] | 2120 | u32 pktstat_ringsize; |
| 2121 | u32 fbr_chunksize; |
ZHAO Gang | 8f7fa96 | 2013-12-08 11:01:06 +0800 | [diff] [blame] | 2122 | struct rx_ring *rx_ring = &adapter->rx_ring; |
ZHAO Gang | bad5d26 | 2013-12-09 19:38:25 +0800 | [diff] [blame] | 2123 | struct fbr_lookup *fbr; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2124 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2125 | /* Alloc memory for the lookup table */ |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2126 | rx_ring->fbr[0] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL); |
Mark Einon | f0ada67 | 2012-11-01 22:56:43 +0000 | [diff] [blame] | 2127 | rx_ring->fbr[1] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2128 | |
| 2129 | /* The first thing we will do is configure the sizes of the buffer |
| 2130 | * rings. These will change based on jumbo packet support. Larger |
| 2131 | * jumbo packets increases the size of each entry in FBR0, and the |
| 2132 | * number of entries in FBR0, while at the same time decreasing the |
| 2133 | * number of entries in FBR1. |
| 2134 | * |
| 2135 | * FBR1 holds "large" frames, FBR0 holds "small" frames. If FBR1 |
| 2136 | * entries are huge in order to accommodate a "jumbo" frame, then it |
| 2137 | * will have less entries. Conversely, FBR1 will now be relied upon |
| 2138 | * to carry more "normal" frames, thus it's entry size also increases |
| 2139 | * and the number of entries goes up too (since it now carries |
| 2140 | * "small" + "regular" packets. |
| 2141 | * |
| 2142 | * In this scheme, we try to maintain 512 entries between the two |
| 2143 | * rings. Also, FBR1 remains a constant size - when it's size doubles |
| 2144 | * the number of entries halves. FBR0 increases in size, however. |
| 2145 | */ |
| 2146 | |
| 2147 | if (adapter->registry_jumbo_packet < 2048) { |
Mark Einon | f0ada67 | 2012-11-01 22:56:43 +0000 | [diff] [blame] | 2148 | rx_ring->fbr[0]->buffsize = 256; |
| 2149 | rx_ring->fbr[0]->num_entries = 512; |
| 2150 | rx_ring->fbr[1]->buffsize = 2048; |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 2151 | rx_ring->fbr[1]->num_entries = 512; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2152 | } else if (adapter->registry_jumbo_packet < 4096) { |
Mark Einon | f0ada67 | 2012-11-01 22:56:43 +0000 | [diff] [blame] | 2153 | rx_ring->fbr[0]->buffsize = 512; |
| 2154 | rx_ring->fbr[0]->num_entries = 1024; |
| 2155 | rx_ring->fbr[1]->buffsize = 4096; |
| 2156 | rx_ring->fbr[1]->num_entries = 512; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2157 | } else { |
Mark Einon | f0ada67 | 2012-11-01 22:56:43 +0000 | [diff] [blame] | 2158 | rx_ring->fbr[0]->buffsize = 1024; |
| 2159 | rx_ring->fbr[0]->num_entries = 768; |
| 2160 | rx_ring->fbr[1]->buffsize = 16384; |
| 2161 | rx_ring->fbr[1]->num_entries = 128; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2162 | } |
| 2163 | |
ZHAO Gang | bad5d26 | 2013-12-09 19:38:25 +0800 | [diff] [blame] | 2164 | rx_ring->psr_num_entries = rx_ring->fbr[0]->num_entries + |
| 2165 | rx_ring->fbr[1]->num_entries; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2166 | |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2167 | for (id = 0; id < NUM_FBRS; id++) { |
ZHAO Gang | bad5d26 | 2013-12-09 19:38:25 +0800 | [diff] [blame] | 2168 | fbr = rx_ring->fbr[id]; |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2169 | /* Allocate an area of memory for Free Buffer Ring */ |
ZHAO Gang | bad5d26 | 2013-12-09 19:38:25 +0800 | [diff] [blame] | 2170 | bufsize = sizeof(struct fbr_desc) * fbr->num_entries; |
| 2171 | fbr->ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev, |
| 2172 | bufsize, |
| 2173 | &fbr->ring_physaddr, |
| 2174 | GFP_KERNEL); |
| 2175 | if (!fbr->ring_virtaddr) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2176 | dev_err(&adapter->pdev->dev, |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2177 | "Cannot alloc memory for Free Buffer Ring %d\n", id); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2178 | return -ENOMEM; |
| 2179 | } |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2180 | } |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2181 | |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2182 | for (id = 0; id < NUM_FBRS; id++) { |
ZHAO Gang | bad5d26 | 2013-12-09 19:38:25 +0800 | [diff] [blame] | 2183 | fbr = rx_ring->fbr[id]; |
| 2184 | fbr_chunksize = (FBR_CHUNKS * fbr->buffsize); |
Mark Einon | 8764893 | 2012-11-12 21:16:28 +0000 | [diff] [blame] | 2185 | |
ZHAO Gang | bad5d26 | 2013-12-09 19:38:25 +0800 | [diff] [blame] | 2186 | for (i = 0; i < fbr->num_entries / FBR_CHUNKS; i++) { |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2187 | dma_addr_t fbr_tmp_physaddr; |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2188 | |
ZHAO Gang | bad5d26 | 2013-12-09 19:38:25 +0800 | [diff] [blame] | 2189 | fbr->mem_virtaddrs[i] = dma_alloc_coherent( |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2190 | &adapter->pdev->dev, fbr_chunksize, |
ZHAO Gang | bad5d26 | 2013-12-09 19:38:25 +0800 | [diff] [blame] | 2191 | &fbr->mem_physaddrs[i], |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2192 | GFP_KERNEL); |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2193 | |
ZHAO Gang | bad5d26 | 2013-12-09 19:38:25 +0800 | [diff] [blame] | 2194 | if (!fbr->mem_virtaddrs[i]) { |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2195 | dev_err(&adapter->pdev->dev, |
| 2196 | "Could not alloc memory\n"); |
| 2197 | return -ENOMEM; |
| 2198 | } |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2199 | |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2200 | /* See NOTE in "Save Physical Address" comment above */ |
ZHAO Gang | bad5d26 | 2013-12-09 19:38:25 +0800 | [diff] [blame] | 2201 | fbr_tmp_physaddr = fbr->mem_physaddrs[i]; |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2202 | |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2203 | for (j = 0; j < FBR_CHUNKS; j++) { |
| 2204 | u32 index = (i * FBR_CHUNKS) + j; |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2205 | |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2206 | /* Save the Virtual address of this index for |
| 2207 | * quick access later |
| 2208 | */ |
ZHAO Gang | bad5d26 | 2013-12-09 19:38:25 +0800 | [diff] [blame] | 2209 | fbr->virt[index] = (u8 *)fbr->mem_virtaddrs[i] + |
| 2210 | (j * fbr->buffsize); |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2211 | |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2212 | /* now store the physical address in the |
| 2213 | * descriptor so the device can access it |
| 2214 | */ |
ZHAO Gang | bad5d26 | 2013-12-09 19:38:25 +0800 | [diff] [blame] | 2215 | fbr->bus_high[index] = |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2216 | upper_32_bits(fbr_tmp_physaddr); |
ZHAO Gang | bad5d26 | 2013-12-09 19:38:25 +0800 | [diff] [blame] | 2217 | fbr->bus_low[index] = |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2218 | lower_32_bits(fbr_tmp_physaddr); |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2219 | |
ZHAO Gang | bad5d26 | 2013-12-09 19:38:25 +0800 | [diff] [blame] | 2220 | fbr_tmp_physaddr += fbr->buffsize; |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2221 | } |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2222 | } |
| 2223 | } |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2224 | |
| 2225 | /* Allocate an area of memory for FIFO of Packet Status ring entries */ |
| 2226 | pktstat_ringsize = |
ZHAO Gang | bad5d26 | 2013-12-09 19:38:25 +0800 | [diff] [blame] | 2227 | sizeof(struct pkt_stat_desc) * rx_ring->psr_num_entries; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2228 | |
Mark Einon | 0d1b7a8 | 2011-10-20 01:18:43 +0100 | [diff] [blame] | 2229 | rx_ring->ps_ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev, |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2230 | pktstat_ringsize, |
Mark Einon | 0d1b7a8 | 2011-10-20 01:18:43 +0100 | [diff] [blame] | 2231 | &rx_ring->ps_ring_physaddr, |
| 2232 | GFP_KERNEL); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2233 | |
| 2234 | if (!rx_ring->ps_ring_virtaddr) { |
| 2235 | dev_err(&adapter->pdev->dev, |
| 2236 | "Cannot alloc memory for Packet Status Ring\n"); |
| 2237 | return -ENOMEM; |
| 2238 | } |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2239 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 2240 | /* NOTE : dma_alloc_coherent(), used above to alloc DMA regions, |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2241 | * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses |
| 2242 | * are ever returned, make sure the high part is retrieved here before |
| 2243 | * storing the adjusted address. |
| 2244 | */ |
| 2245 | |
| 2246 | /* Allocate an area of memory for writeback of status information */ |
Mark Einon | 0d1b7a8 | 2011-10-20 01:18:43 +0100 | [diff] [blame] | 2247 | rx_ring->rx_status_block = dma_alloc_coherent(&adapter->pdev->dev, |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2248 | sizeof(struct rx_status_block), |
Mark Einon | 0d1b7a8 | 2011-10-20 01:18:43 +0100 | [diff] [blame] | 2249 | &rx_ring->rx_status_bus, |
| 2250 | GFP_KERNEL); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2251 | if (!rx_ring->rx_status_block) { |
| 2252 | dev_err(&adapter->pdev->dev, |
| 2253 | "Cannot alloc memory for Status Block\n"); |
| 2254 | return -ENOMEM; |
| 2255 | } |
| 2256 | rx_ring->num_rfd = NIC_DEFAULT_NUM_RFD; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2257 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2258 | /* The RFDs are going to be put on lists later on, so initialize the |
| 2259 | * lists now. |
| 2260 | */ |
| 2261 | INIT_LIST_HEAD(&rx_ring->recv_list); |
| 2262 | return 0; |
| 2263 | } |
| 2264 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 2265 | /* et131x_rx_dma_memory_free - Free all memory allocated within this module */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 2266 | static void et131x_rx_dma_memory_free(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2267 | { |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2268 | u8 id; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2269 | u32 index; |
| 2270 | u32 bufsize; |
| 2271 | u32 pktstat_ringsize; |
| 2272 | struct rfd *rfd; |
ZHAO Gang | 8f7fa96 | 2013-12-08 11:01:06 +0800 | [diff] [blame] | 2273 | struct rx_ring *rx_ring = &adapter->rx_ring; |
ZHAO Gang | f876f59 | 2013-12-09 19:38:26 +0800 | [diff] [blame] | 2274 | struct fbr_lookup *fbr; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2275 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2276 | /* Free RFDs and associated packet descriptors */ |
| 2277 | WARN_ON(rx_ring->num_ready_recv != rx_ring->num_rfd); |
| 2278 | |
| 2279 | while (!list_empty(&rx_ring->recv_list)) { |
ZHAO Gang | 57cc027 | 2013-12-09 19:38:30 +0800 | [diff] [blame] | 2280 | rfd = list_entry(rx_ring->recv_list.next, |
| 2281 | struct rfd, list_node); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2282 | |
| 2283 | list_del(&rfd->list_node); |
| 2284 | rfd->skb = NULL; |
Mark Einon | d959df0 | 2012-11-16 10:47:41 +0000 | [diff] [blame] | 2285 | kfree(rfd); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2286 | } |
| 2287 | |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2288 | /* Free Free Buffer Rings */ |
| 2289 | for (id = 0; id < NUM_FBRS; id++) { |
ZHAO Gang | f876f59 | 2013-12-09 19:38:26 +0800 | [diff] [blame] | 2290 | fbr = rx_ring->fbr[id]; |
| 2291 | |
| 2292 | if (!fbr->ring_virtaddr) |
Mark Einon | 823bb2e | 2012-11-16 10:47:39 +0000 | [diff] [blame] | 2293 | continue; |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2294 | |
Mark Einon | 823bb2e | 2012-11-16 10:47:39 +0000 | [diff] [blame] | 2295 | /* First the packet memory */ |
| 2296 | for (index = 0; |
ZHAO Gang | f876f59 | 2013-12-09 19:38:26 +0800 | [diff] [blame] | 2297 | index < fbr->num_entries / FBR_CHUNKS; |
Mark Einon | 823bb2e | 2012-11-16 10:47:39 +0000 | [diff] [blame] | 2298 | index++) { |
ZHAO Gang | f876f59 | 2013-12-09 19:38:26 +0800 | [diff] [blame] | 2299 | if (fbr->mem_virtaddrs[index]) { |
| 2300 | bufsize = fbr->buffsize * FBR_CHUNKS; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2301 | |
Mark Einon | 823bb2e | 2012-11-16 10:47:39 +0000 | [diff] [blame] | 2302 | dma_free_coherent(&adapter->pdev->dev, |
ZHAO Gang | f876f59 | 2013-12-09 19:38:26 +0800 | [diff] [blame] | 2303 | bufsize, |
| 2304 | fbr->mem_virtaddrs[index], |
| 2305 | fbr->mem_physaddrs[index]); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2306 | |
ZHAO Gang | f876f59 | 2013-12-09 19:38:26 +0800 | [diff] [blame] | 2307 | fbr->mem_virtaddrs[index] = NULL; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2308 | } |
| 2309 | } |
Mark Einon | 823bb2e | 2012-11-16 10:47:39 +0000 | [diff] [blame] | 2310 | |
ZHAO Gang | f876f59 | 2013-12-09 19:38:26 +0800 | [diff] [blame] | 2311 | bufsize = sizeof(struct fbr_desc) * fbr->num_entries; |
Mark Einon | 823bb2e | 2012-11-16 10:47:39 +0000 | [diff] [blame] | 2312 | |
ZHAO Gang | f876f59 | 2013-12-09 19:38:26 +0800 | [diff] [blame] | 2313 | dma_free_coherent(&adapter->pdev->dev, |
| 2314 | bufsize, |
| 2315 | fbr->ring_virtaddr, |
| 2316 | fbr->ring_physaddr); |
Mark Einon | 823bb2e | 2012-11-16 10:47:39 +0000 | [diff] [blame] | 2317 | |
ZHAO Gang | f876f59 | 2013-12-09 19:38:26 +0800 | [diff] [blame] | 2318 | fbr->ring_virtaddr = NULL; |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2319 | } |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2320 | |
| 2321 | /* Free Packet Status Ring */ |
| 2322 | if (rx_ring->ps_ring_virtaddr) { |
Mark Einon | 242187a | 2012-10-30 18:38:55 +0000 | [diff] [blame] | 2323 | pktstat_ringsize = sizeof(struct pkt_stat_desc) * |
ZHAO Gang | 8f7fa96 | 2013-12-08 11:01:06 +0800 | [diff] [blame] | 2324 | rx_ring->psr_num_entries; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2325 | |
Mark Einon | 675c8f6 | 2011-10-20 01:18:44 +0100 | [diff] [blame] | 2326 | dma_free_coherent(&adapter->pdev->dev, pktstat_ringsize, |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2327 | rx_ring->ps_ring_virtaddr, |
| 2328 | rx_ring->ps_ring_physaddr); |
| 2329 | |
| 2330 | rx_ring->ps_ring_virtaddr = NULL; |
| 2331 | } |
| 2332 | |
| 2333 | /* Free area of memory for the writeback of status information */ |
| 2334 | if (rx_ring->rx_status_block) { |
Mark Einon | 675c8f6 | 2011-10-20 01:18:44 +0100 | [diff] [blame] | 2335 | dma_free_coherent(&adapter->pdev->dev, |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2336 | sizeof(struct rx_status_block), |
| 2337 | rx_ring->rx_status_block, rx_ring->rx_status_bus); |
| 2338 | rx_ring->rx_status_block = NULL; |
| 2339 | } |
| 2340 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2341 | /* Free the FBR Lookup Table */ |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2342 | kfree(rx_ring->fbr[0]); |
Mark Einon | f0ada67 | 2012-11-01 22:56:43 +0000 | [diff] [blame] | 2343 | kfree(rx_ring->fbr[1]); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2344 | |
| 2345 | /* Reset Counters */ |
| 2346 | rx_ring->num_ready_recv = 0; |
| 2347 | } |
| 2348 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 2349 | /* et131x_init_recv - Initialize receive data structures */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 2350 | static int et131x_init_recv(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2351 | { |
Mark Einon | d959df0 | 2012-11-16 10:47:41 +0000 | [diff] [blame] | 2352 | struct rfd *rfd; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2353 | u32 rfdct; |
ZHAO Gang | 8f7fa96 | 2013-12-08 11:01:06 +0800 | [diff] [blame] | 2354 | struct rx_ring *rx_ring = &adapter->rx_ring; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2355 | |
| 2356 | /* Setup each RFD */ |
| 2357 | for (rfdct = 0; rfdct < rx_ring->num_rfd; rfdct++) { |
Mark Einon | d959df0 | 2012-11-16 10:47:41 +0000 | [diff] [blame] | 2358 | rfd = kzalloc(sizeof(struct rfd), GFP_ATOMIC | GFP_DMA); |
Joe Perches | 78110bb | 2013-02-11 09:41:29 -0800 | [diff] [blame] | 2359 | if (!rfd) |
Mark Einon | d959df0 | 2012-11-16 10:47:41 +0000 | [diff] [blame] | 2360 | return -ENOMEM; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2361 | |
| 2362 | rfd->skb = NULL; |
| 2363 | |
| 2364 | /* Add this RFD to the recv_list */ |
| 2365 | list_add_tail(&rfd->list_node, &rx_ring->recv_list); |
| 2366 | |
ZHAO Gang | 4eb9462 | 2013-12-04 15:24:13 +0800 | [diff] [blame] | 2367 | /* Increment the available RFD's */ |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2368 | rx_ring->num_ready_recv++; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2369 | } |
| 2370 | |
Mark Einon | d959df0 | 2012-11-16 10:47:41 +0000 | [diff] [blame] | 2371 | return 0; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2372 | } |
| 2373 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 2374 | /* et131x_set_rx_dma_timer - Set the heartbeat timer according to line rate */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 2375 | static void et131x_set_rx_dma_timer(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2376 | { |
| 2377 | struct phy_device *phydev = adapter->phydev; |
| 2378 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2379 | /* For version B silicon, we do not use the RxDMA timer for 10 and 100 |
| 2380 | * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing. |
| 2381 | */ |
| 2382 | if ((phydev->speed == SPEED_100) || (phydev->speed == SPEED_10)) { |
| 2383 | writel(0, &adapter->regs->rxdma.max_pkt_time); |
| 2384 | writel(1, &adapter->regs->rxdma.num_pkt_done); |
| 2385 | } |
| 2386 | } |
| 2387 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 2388 | /* NICReturnRFD - Recycle a RFD and put it back onto the receive list |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2389 | * @adapter: pointer to our adapter |
| 2390 | * @rfd: pointer to the RFD |
| 2391 | */ |
| 2392 | static void nic_return_rfd(struct et131x_adapter *adapter, struct rfd *rfd) |
| 2393 | { |
| 2394 | struct rx_ring *rx_local = &adapter->rx_ring; |
| 2395 | struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma; |
| 2396 | u16 buff_index = rfd->bufferindex; |
| 2397 | u8 ring_index = rfd->ringindex; |
| 2398 | unsigned long flags; |
ZHAO Gang | 39bdb4a | 2013-12-09 19:38:27 +0800 | [diff] [blame] | 2399 | struct fbr_lookup *fbr = rx_local->fbr[ring_index]; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2400 | |
| 2401 | /* We don't use any of the OOB data besides status. Otherwise, we |
| 2402 | * need to clean up OOB data |
| 2403 | */ |
ZHAO Gang | 39bdb4a | 2013-12-09 19:38:27 +0800 | [diff] [blame] | 2404 | if (buff_index < fbr->num_entries) { |
| 2405 | u32 free_buff_ring; |
Mark Einon | c0594ee | 2013-01-22 17:10:10 +0000 | [diff] [blame] | 2406 | u32 __iomem *offset; |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2407 | struct fbr_desc *next; |
| 2408 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2409 | spin_lock_irqsave(&adapter->fbr_lock, flags); |
| 2410 | |
Mark Einon | f0ada67 | 2012-11-01 22:56:43 +0000 | [diff] [blame] | 2411 | if (ring_index == 0) |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2412 | offset = &rx_dma->fbr0_full_offset; |
Mark Einon | f0ada67 | 2012-11-01 22:56:43 +0000 | [diff] [blame] | 2413 | else |
| 2414 | offset = &rx_dma->fbr1_full_offset; |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2415 | |
ZHAO Gang | 39bdb4a | 2013-12-09 19:38:27 +0800 | [diff] [blame] | 2416 | next = (struct fbr_desc *)(fbr->ring_virtaddr) + |
| 2417 | INDEX10(fbr->local_full); |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2418 | |
| 2419 | /* Handle the Free Buffer Ring advancement here. Write |
| 2420 | * the PA / Buffer Index for the returned buffer into |
| 2421 | * the oldest (next to be freed)FBR entry |
| 2422 | */ |
ZHAO Gang | 39bdb4a | 2013-12-09 19:38:27 +0800 | [diff] [blame] | 2423 | next->addr_hi = fbr->bus_high[buff_index]; |
| 2424 | next->addr_lo = fbr->bus_low[buff_index]; |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2425 | next->word2 = buff_index; |
| 2426 | |
ZHAO Gang | 39bdb4a | 2013-12-09 19:38:27 +0800 | [diff] [blame] | 2427 | free_buff_ring = bump_free_buff_ring(&fbr->local_full, |
| 2428 | fbr->num_entries - 1); |
| 2429 | writel(free_buff_ring, offset); |
Mark Einon | 788ca84 | 2012-10-30 18:38:54 +0000 | [diff] [blame] | 2430 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2431 | spin_unlock_irqrestore(&adapter->fbr_lock, flags); |
| 2432 | } else { |
| 2433 | dev_err(&adapter->pdev->dev, |
| 2434 | "%s illegal Buffer Index returned\n", __func__); |
| 2435 | } |
| 2436 | |
| 2437 | /* The processing on this RFD is done, so put it back on the tail of |
| 2438 | * our list |
| 2439 | */ |
| 2440 | spin_lock_irqsave(&adapter->rcv_lock, flags); |
| 2441 | list_add_tail(&rfd->list_node, &rx_local->recv_list); |
| 2442 | rx_local->num_ready_recv++; |
| 2443 | spin_unlock_irqrestore(&adapter->rcv_lock, flags); |
| 2444 | |
| 2445 | WARN_ON(rx_local->num_ready_recv > rx_local->num_rfd); |
| 2446 | } |
| 2447 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 2448 | /* nic_rx_pkts - Checks the hardware for available packets |
Mark Einon | 54dbf04 | 2011-11-13 19:43:39 +0000 | [diff] [blame] | 2449 | * |
| 2450 | * Returns rfd, a pointer to our MPRFD. |
| 2451 | * |
| 2452 | * Checks the hardware for available packets, using completion ring |
| 2453 | * If packets are available, it gets an RFD from the recv_list, attaches |
| 2454 | * the packet to it, puts the RFD in the RecvPendList, and also returns |
| 2455 | * the pointer to the RFD. |
| 2456 | */ |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2457 | static struct rfd *nic_rx_pkts(struct et131x_adapter *adapter) |
| 2458 | { |
| 2459 | struct rx_ring *rx_local = &adapter->rx_ring; |
| 2460 | struct rx_status_block *status; |
| 2461 | struct pkt_stat_desc *psr; |
Mark Einon | 186c426 | 2012-10-30 18:38:57 +0000 | [diff] [blame] | 2462 | struct rfd *rfd; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2463 | u32 i; |
| 2464 | u8 *buf; |
| 2465 | unsigned long flags; |
| 2466 | struct list_head *element; |
| 2467 | u8 ring_index; |
| 2468 | u16 buff_index; |
| 2469 | u32 len; |
| 2470 | u32 word0; |
| 2471 | u32 word1; |
Mark Einon | 186c426 | 2012-10-30 18:38:57 +0000 | [diff] [blame] | 2472 | struct sk_buff *skb; |
ZHAO Gang | 297bb9d | 2013-12-09 19:38:28 +0800 | [diff] [blame] | 2473 | struct fbr_lookup *fbr; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2474 | |
| 2475 | /* RX Status block is written by the DMA engine prior to every |
| 2476 | * interrupt. It contains the next to be used entry in the Packet |
| 2477 | * Status Ring, and also the two Free Buffer rings. |
| 2478 | */ |
| 2479 | status = rx_local->rx_status_block; |
| 2480 | word1 = status->word1 >> 16; /* Get the useful bits */ |
| 2481 | |
| 2482 | /* Check the PSR and wrap bits do not match */ |
| 2483 | if ((word1 & 0x1FFF) == (rx_local->local_psr_full & 0x1FFF)) |
Mark Einon | 242187a | 2012-10-30 18:38:55 +0000 | [diff] [blame] | 2484 | return NULL; /* Looks like this ring is not updated yet */ |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2485 | |
| 2486 | /* The packet status ring indicates that data is available. */ |
| 2487 | psr = (struct pkt_stat_desc *) (rx_local->ps_ring_virtaddr) + |
| 2488 | (rx_local->local_psr_full & 0xFFF); |
| 2489 | |
Mark Einon | 242187a | 2012-10-30 18:38:55 +0000 | [diff] [blame] | 2490 | /* Grab any information that is required once the PSR is advanced, |
| 2491 | * since we can no longer rely on the memory being accurate |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2492 | */ |
| 2493 | len = psr->word1 & 0xFFFF; |
| 2494 | ring_index = (psr->word1 >> 26) & 0x03; |
ZHAO Gang | 297bb9d | 2013-12-09 19:38:28 +0800 | [diff] [blame] | 2495 | fbr = rx_local->fbr[ring_index]; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2496 | buff_index = (psr->word1 >> 16) & 0x3FF; |
| 2497 | word0 = psr->word0; |
| 2498 | |
| 2499 | /* Indicate that we have used this PSR entry. */ |
| 2500 | /* FIXME wrap 12 */ |
| 2501 | add_12bit(&rx_local->local_psr_full, 1); |
| 2502 | if ( |
| 2503 | (rx_local->local_psr_full & 0xFFF) > rx_local->psr_num_entries - 1) { |
| 2504 | /* Clear psr full and toggle the wrap bit */ |
| 2505 | rx_local->local_psr_full &= ~0xFFF; |
| 2506 | rx_local->local_psr_full ^= 0x1000; |
| 2507 | } |
| 2508 | |
Mark Einon | 242187a | 2012-10-30 18:38:55 +0000 | [diff] [blame] | 2509 | writel(rx_local->local_psr_full, &adapter->regs->rxdma.psr_full_offset); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2510 | |
ZHAO Gang | 297bb9d | 2013-12-09 19:38:28 +0800 | [diff] [blame] | 2511 | if (ring_index > 1 || buff_index > fbr->num_entries - 1) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2512 | /* Illegal buffer or ring index cannot be used by S/W*/ |
| 2513 | dev_err(&adapter->pdev->dev, |
Mark Einon | 242187a | 2012-10-30 18:38:55 +0000 | [diff] [blame] | 2514 | "NICRxPkts PSR Entry %d indicates length of %d and/or bad bi(%d)\n", |
| 2515 | rx_local->local_psr_full & 0xFFF, len, buff_index); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2516 | return NULL; |
| 2517 | } |
| 2518 | |
| 2519 | /* Get and fill the RFD. */ |
| 2520 | spin_lock_irqsave(&adapter->rcv_lock, flags); |
| 2521 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2522 | element = rx_local->recv_list.next; |
ZHAO Gang | 57cc027 | 2013-12-09 19:38:30 +0800 | [diff] [blame] | 2523 | rfd = list_entry(element, struct rfd, list_node); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2524 | |
Mark Einon | 242187a | 2012-10-30 18:38:55 +0000 | [diff] [blame] | 2525 | if (!rfd) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2526 | spin_unlock_irqrestore(&adapter->rcv_lock, flags); |
| 2527 | return NULL; |
| 2528 | } |
| 2529 | |
| 2530 | list_del(&rfd->list_node); |
| 2531 | rx_local->num_ready_recv--; |
| 2532 | |
| 2533 | spin_unlock_irqrestore(&adapter->rcv_lock, flags); |
| 2534 | |
| 2535 | rfd->bufferindex = buff_index; |
| 2536 | rfd->ringindex = ring_index; |
| 2537 | |
Mark Einon | 242187a | 2012-10-30 18:38:55 +0000 | [diff] [blame] | 2538 | /* In V1 silicon, there is a bug which screws up filtering of runt |
| 2539 | * packets. Therefore runt packet filtering is disabled in the MAC and |
| 2540 | * the packets are dropped here. They are also counted here. |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2541 | */ |
| 2542 | if (len < (NIC_MIN_PACKET_SIZE + 4)) { |
| 2543 | adapter->stats.rx_other_errs++; |
| 2544 | len = 0; |
| 2545 | } |
| 2546 | |
Mark Einon | 242187a | 2012-10-30 18:38:55 +0000 | [diff] [blame] | 2547 | if (len == 0) { |
| 2548 | rfd->len = 0; |
| 2549 | goto out; |
| 2550 | } |
| 2551 | |
| 2552 | /* Determine if this is a multicast packet coming in */ |
| 2553 | if ((word0 & ALCATEL_MULTICAST_PKT) && |
| 2554 | !(word0 & ALCATEL_BROADCAST_PKT)) { |
| 2555 | /* Promiscuous mode and Multicast mode are not mutually |
| 2556 | * exclusive as was first thought. I guess Promiscuous is just |
| 2557 | * considered a super-set of the other filters. Generally filter |
| 2558 | * is 0x2b when in promiscuous mode. |
| 2559 | */ |
| 2560 | if ((adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST) |
| 2561 | && !(adapter->packet_filter & ET131X_PACKET_TYPE_PROMISCUOUS) |
| 2562 | && !(adapter->packet_filter & |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2563 | ET131X_PACKET_TYPE_ALL_MULTICAST)) { |
ZHAO Gang | 297bb9d | 2013-12-09 19:38:28 +0800 | [diff] [blame] | 2564 | buf = fbr->virt[buff_index]; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2565 | |
Mark Einon | 242187a | 2012-10-30 18:38:55 +0000 | [diff] [blame] | 2566 | /* Loop through our list to see if the destination |
| 2567 | * address of this packet matches one in our list. |
| 2568 | */ |
| 2569 | for (i = 0; i < adapter->multicast_addr_count; i++) { |
| 2570 | if (buf[0] == adapter->multicast_list[i][0] |
| 2571 | && buf[1] == adapter->multicast_list[i][1] |
| 2572 | && buf[2] == adapter->multicast_list[i][2] |
| 2573 | && buf[3] == adapter->multicast_list[i][3] |
| 2574 | && buf[4] == adapter->multicast_list[i][4] |
| 2575 | && buf[5] == adapter->multicast_list[i][5]) { |
| 2576 | break; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2577 | } |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2578 | } |
| 2579 | |
Mark Einon | 242187a | 2012-10-30 18:38:55 +0000 | [diff] [blame] | 2580 | /* If our index is equal to the number of Multicast |
| 2581 | * address we have, then this means we did not find this |
| 2582 | * packet's matching address in our list. Set the len to |
| 2583 | * zero, so we free our RFD when we return from this |
| 2584 | * function. |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2585 | */ |
Mark Einon | 242187a | 2012-10-30 18:38:55 +0000 | [diff] [blame] | 2586 | if (i == adapter->multicast_addr_count) |
| 2587 | len = 0; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2588 | } |
| 2589 | |
Mark Einon | 242187a | 2012-10-30 18:38:55 +0000 | [diff] [blame] | 2590 | if (len > 0) |
| 2591 | adapter->stats.multicast_pkts_rcvd++; |
| 2592 | } else if (word0 & ALCATEL_BROADCAST_PKT) { |
| 2593 | adapter->stats.broadcast_pkts_rcvd++; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2594 | } else { |
Mark Einon | 242187a | 2012-10-30 18:38:55 +0000 | [diff] [blame] | 2595 | /* Not sure what this counter measures in promiscuous mode. |
| 2596 | * Perhaps we should check the MAC address to see if it is |
| 2597 | * directed to us in promiscuous mode. |
| 2598 | */ |
| 2599 | adapter->stats.unicast_pkts_rcvd++; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2600 | } |
| 2601 | |
Mark Einon | 12a2f3f | 2013-12-05 22:37:46 +0000 | [diff] [blame] | 2602 | if (!len) { |
Mark Einon | 242187a | 2012-10-30 18:38:55 +0000 | [diff] [blame] | 2603 | rfd->len = 0; |
| 2604 | goto out; |
| 2605 | } |
| 2606 | |
| 2607 | rfd->len = len; |
| 2608 | |
| 2609 | skb = dev_alloc_skb(rfd->len + 2); |
| 2610 | if (!skb) { |
| 2611 | dev_err(&adapter->pdev->dev, "Couldn't alloc an SKB for Rx\n"); |
| 2612 | return NULL; |
| 2613 | } |
| 2614 | |
| 2615 | adapter->net_stats.rx_bytes += rfd->len; |
| 2616 | |
ZHAO Gang | 297bb9d | 2013-12-09 19:38:28 +0800 | [diff] [blame] | 2617 | memcpy(skb_put(skb, rfd->len), fbr->virt[buff_index], rfd->len); |
Mark Einon | 242187a | 2012-10-30 18:38:55 +0000 | [diff] [blame] | 2618 | |
Mark Einon | 242187a | 2012-10-30 18:38:55 +0000 | [diff] [blame] | 2619 | skb->protocol = eth_type_trans(skb, adapter->netdev); |
| 2620 | skb->ip_summed = CHECKSUM_NONE; |
| 2621 | netif_rx_ni(skb); |
| 2622 | |
| 2623 | out: |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2624 | nic_return_rfd(adapter, rfd); |
| 2625 | return rfd; |
| 2626 | } |
| 2627 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 2628 | /* et131x_handle_recv_interrupt - Interrupt handler for receive processing |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2629 | * |
| 2630 | * Assumption, Rcv spinlock has been acquired. |
| 2631 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 2632 | static void et131x_handle_recv_interrupt(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2633 | { |
| 2634 | struct rfd *rfd = NULL; |
| 2635 | u32 count = 0; |
| 2636 | bool done = true; |
ZHAO Gang | 8f7fa96 | 2013-12-08 11:01:06 +0800 | [diff] [blame] | 2637 | struct rx_ring *rx_ring = &adapter->rx_ring; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2638 | |
| 2639 | /* Process up to available RFD's */ |
| 2640 | while (count < NUM_PACKETS_HANDLED) { |
ZHAO Gang | 8f7fa96 | 2013-12-08 11:01:06 +0800 | [diff] [blame] | 2641 | if (list_empty(&rx_ring->recv_list)) { |
| 2642 | WARN_ON(rx_ring->num_ready_recv != 0); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2643 | done = false; |
| 2644 | break; |
| 2645 | } |
| 2646 | |
| 2647 | rfd = nic_rx_pkts(adapter); |
| 2648 | |
| 2649 | if (rfd == NULL) |
| 2650 | break; |
| 2651 | |
| 2652 | /* Do not receive any packets until a filter has been set. |
| 2653 | * Do not receive any packets until we have link. |
| 2654 | * If length is zero, return the RFD in order to advance the |
| 2655 | * Free buffer ring. |
| 2656 | */ |
| 2657 | if (!adapter->packet_filter || |
| 2658 | !netif_carrier_ok(adapter->netdev) || |
| 2659 | rfd->len == 0) |
| 2660 | continue; |
| 2661 | |
| 2662 | /* Increment the number of packets we received */ |
| 2663 | adapter->net_stats.rx_packets++; |
| 2664 | |
| 2665 | /* Set the status on the packet, either resources or success */ |
ZHAO Gang | 8f7fa96 | 2013-12-08 11:01:06 +0800 | [diff] [blame] | 2666 | if (rx_ring->num_ready_recv < RFD_LOW_WATER_MARK) |
Mark Einon | 0cdc6ee | 2013-09-11 14:14:45 +0100 | [diff] [blame] | 2667 | dev_warn(&adapter->pdev->dev, "RFD's are running out\n"); |
| 2668 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2669 | count++; |
| 2670 | } |
| 2671 | |
| 2672 | if (count == NUM_PACKETS_HANDLED || !done) { |
ZHAO Gang | 8f7fa96 | 2013-12-08 11:01:06 +0800 | [diff] [blame] | 2673 | rx_ring->unfinished_receives = true; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2674 | writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO, |
| 2675 | &adapter->regs->global.watchdog_timer); |
| 2676 | } else |
| 2677 | /* Watchdog timer will disable itself if appropriate. */ |
ZHAO Gang | 8f7fa96 | 2013-12-08 11:01:06 +0800 | [diff] [blame] | 2678 | rx_ring->unfinished_receives = false; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2679 | } |
| 2680 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 2681 | /* et131x_tx_dma_memory_alloc |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2682 | * |
| 2683 | * Allocates memory that will be visible both to the device and to the CPU. |
| 2684 | * The OS will pass us packets, pointers to which we will insert in the Tx |
| 2685 | * Descriptor queue. The device will read this queue to find the packets in |
| 2686 | * memory. The device will update the "status" in memory each time it xmits a |
| 2687 | * packet. |
| 2688 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 2689 | static int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2690 | { |
| 2691 | int desc_size = 0; |
| 2692 | struct tx_ring *tx_ring = &adapter->tx_ring; |
| 2693 | |
| 2694 | /* Allocate memory for the TCB's (Transmit Control Block) */ |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2695 | tx_ring->tcb_ring = kcalloc(NUM_TCB, sizeof(struct tcb), |
| 2696 | GFP_ATOMIC | GFP_DMA); |
| 2697 | if (!tx_ring->tcb_ring) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2698 | return -ENOMEM; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2699 | |
Mark Einon | d3c75e8 | 2012-11-12 21:16:29 +0000 | [diff] [blame] | 2700 | desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX); |
ZHAO Gang | 57cc027 | 2013-12-09 19:38:30 +0800 | [diff] [blame] | 2701 | tx_ring->tx_desc_ring = dma_alloc_coherent(&adapter->pdev->dev, |
| 2702 | desc_size, |
| 2703 | &tx_ring->tx_desc_ring_pa, |
| 2704 | GFP_KERNEL); |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2705 | if (!tx_ring->tx_desc_ring) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2706 | dev_err(&adapter->pdev->dev, |
Mark Einon | 09a3fc2 | 2011-10-23 10:22:53 +0100 | [diff] [blame] | 2707 | "Cannot alloc memory for Tx Ring\n"); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2708 | return -ENOMEM; |
| 2709 | } |
| 2710 | |
| 2711 | /* Save physical address |
| 2712 | * |
Mark Einon | 26dc751 | 2011-10-20 01:18:47 +0100 | [diff] [blame] | 2713 | * NOTE: dma_alloc_coherent(), used above to alloc DMA regions, |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2714 | * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses |
| 2715 | * are ever returned, make sure the high part is retrieved here before |
| 2716 | * storing the adjusted address. |
| 2717 | */ |
| 2718 | /* Allocate memory for the Tx status block */ |
Mark Einon | 0d1b7a8 | 2011-10-20 01:18:43 +0100 | [diff] [blame] | 2719 | tx_ring->tx_status = dma_alloc_coherent(&adapter->pdev->dev, |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2720 | sizeof(u32), |
Mark Einon | 0d1b7a8 | 2011-10-20 01:18:43 +0100 | [diff] [blame] | 2721 | &tx_ring->tx_status_pa, |
| 2722 | GFP_KERNEL); |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2723 | if (!tx_ring->tx_status_pa) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2724 | dev_err(&adapter->pdev->dev, |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2725 | "Cannot alloc memory for Tx status block\n"); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2726 | return -ENOMEM; |
| 2727 | } |
| 2728 | return 0; |
| 2729 | } |
| 2730 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 2731 | /* et131x_tx_dma_memory_free - Free all memory allocated within this module */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 2732 | static void et131x_tx_dma_memory_free(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2733 | { |
| 2734 | int desc_size = 0; |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2735 | struct tx_ring *tx_ring = &adapter->tx_ring; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2736 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2737 | if (tx_ring->tx_desc_ring) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2738 | /* Free memory relating to Tx rings here */ |
Mark Einon | d3c75e8 | 2012-11-12 21:16:29 +0000 | [diff] [blame] | 2739 | desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX); |
Mark Einon | 675c8f6 | 2011-10-20 01:18:44 +0100 | [diff] [blame] | 2740 | dma_free_coherent(&adapter->pdev->dev, |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2741 | desc_size, |
| 2742 | tx_ring->tx_desc_ring, |
| 2743 | tx_ring->tx_desc_ring_pa); |
| 2744 | tx_ring->tx_desc_ring = NULL; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2745 | } |
| 2746 | |
| 2747 | /* Free memory for the Tx status block */ |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2748 | if (tx_ring->tx_status) { |
Mark Einon | 675c8f6 | 2011-10-20 01:18:44 +0100 | [diff] [blame] | 2749 | dma_free_coherent(&adapter->pdev->dev, |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2750 | sizeof(u32), |
| 2751 | tx_ring->tx_status, |
| 2752 | tx_ring->tx_status_pa); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2753 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2754 | tx_ring->tx_status = NULL; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2755 | } |
| 2756 | /* Free the memory for the tcb structures */ |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2757 | kfree(tx_ring->tcb_ring); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2758 | } |
| 2759 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 2760 | /* nic_send_packet - NIC specific send handler for version B silicon. |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2761 | * @adapter: pointer to our adapter |
| 2762 | * @tcb: pointer to struct tcb |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2763 | */ |
| 2764 | static int nic_send_packet(struct et131x_adapter *adapter, struct tcb *tcb) |
| 2765 | { |
| 2766 | u32 i; |
| 2767 | struct tx_desc desc[24]; /* 24 x 16 byte */ |
| 2768 | u32 frag = 0; |
| 2769 | u32 thiscopy, remainder; |
| 2770 | struct sk_buff *skb = tcb->skb; |
| 2771 | u32 nr_frags = skb_shinfo(skb)->nr_frags + 1; |
| 2772 | struct skb_frag_struct *frags = &skb_shinfo(skb)->frags[0]; |
| 2773 | unsigned long flags; |
| 2774 | struct phy_device *phydev = adapter->phydev; |
Mark Einon | 998f6df | 2012-10-18 21:34:22 +0100 | [diff] [blame] | 2775 | dma_addr_t dma_addr; |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2776 | struct tx_ring *tx_ring = &adapter->tx_ring; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2777 | |
| 2778 | /* Part of the optimizations of this send routine restrict us to |
| 2779 | * sending 24 fragments at a pass. In practice we should never see |
| 2780 | * more than 5 fragments. |
| 2781 | * |
| 2782 | * NOTE: The older version of this function (below) can handle any |
| 2783 | * number of fragments. If needed, we can call this function, |
| 2784 | * although it is less efficient. |
| 2785 | */ |
Rashika Kheria | 9c7bc37 | 2013-10-24 16:24:51 +0530 | [diff] [blame] | 2786 | |
| 2787 | /* nr_frags should be no more than 18. */ |
| 2788 | BUILD_BUG_ON(MAX_SKB_FRAGS + 1 > 23); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2789 | |
| 2790 | memset(desc, 0, sizeof(struct tx_desc) * (nr_frags + 1)); |
| 2791 | |
| 2792 | for (i = 0; i < nr_frags; i++) { |
| 2793 | /* If there is something in this element, lets get a |
| 2794 | * descriptor from the ring and get the necessary data |
| 2795 | */ |
| 2796 | if (i == 0) { |
| 2797 | /* If the fragments are smaller than a standard MTU, |
| 2798 | * then map them to a single descriptor in the Tx |
| 2799 | * Desc ring. However, if they're larger, as is |
| 2800 | * possible with support for jumbo packets, then |
| 2801 | * split them each across 2 descriptors. |
| 2802 | * |
| 2803 | * This will work until we determine why the hardware |
| 2804 | * doesn't seem to like large fragments. |
| 2805 | */ |
Mark Einon | f1b540b | 2012-10-17 22:15:11 +0100 | [diff] [blame] | 2806 | if (skb_headlen(skb) <= 1514) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2807 | /* Low 16bits are length, high is vlan and |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 2808 | * unused currently so zero |
| 2809 | */ |
Mark Einon | f1b540b | 2012-10-17 22:15:11 +0100 | [diff] [blame] | 2810 | desc[frag].len_vlan = skb_headlen(skb); |
Mark Einon | 998f6df | 2012-10-18 21:34:22 +0100 | [diff] [blame] | 2811 | dma_addr = dma_map_single(&adapter->pdev->dev, |
| 2812 | skb->data, |
| 2813 | skb_headlen(skb), |
| 2814 | DMA_TO_DEVICE); |
| 2815 | desc[frag].addr_lo = lower_32_bits(dma_addr); |
| 2816 | desc[frag].addr_hi = upper_32_bits(dma_addr); |
| 2817 | frag++; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2818 | } else { |
Mark Einon | f1b540b | 2012-10-17 22:15:11 +0100 | [diff] [blame] | 2819 | desc[frag].len_vlan = skb_headlen(skb) / 2; |
Mark Einon | 998f6df | 2012-10-18 21:34:22 +0100 | [diff] [blame] | 2820 | dma_addr = dma_map_single(&adapter->pdev->dev, |
Mark Einon | 3781683 | 2012-11-16 10:47:42 +0000 | [diff] [blame] | 2821 | skb->data, |
| 2822 | (skb_headlen(skb) / 2), |
| 2823 | DMA_TO_DEVICE); |
Mark Einon | 998f6df | 2012-10-18 21:34:22 +0100 | [diff] [blame] | 2824 | desc[frag].addr_lo = lower_32_bits(dma_addr); |
| 2825 | desc[frag].addr_hi = upper_32_bits(dma_addr); |
| 2826 | frag++; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2827 | |
Mark Einon | f1b540b | 2012-10-17 22:15:11 +0100 | [diff] [blame] | 2828 | desc[frag].len_vlan = skb_headlen(skb) / 2; |
Mark Einon | 998f6df | 2012-10-18 21:34:22 +0100 | [diff] [blame] | 2829 | dma_addr = dma_map_single(&adapter->pdev->dev, |
Mark Einon | 3781683 | 2012-11-16 10:47:42 +0000 | [diff] [blame] | 2830 | skb->data + |
| 2831 | (skb_headlen(skb) / 2), |
| 2832 | (skb_headlen(skb) / 2), |
| 2833 | DMA_TO_DEVICE); |
Mark Einon | 998f6df | 2012-10-18 21:34:22 +0100 | [diff] [blame] | 2834 | desc[frag].addr_lo = lower_32_bits(dma_addr); |
| 2835 | desc[frag].addr_hi = upper_32_bits(dma_addr); |
| 2836 | frag++; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2837 | } |
| 2838 | } else { |
Mark Einon | 998f6df | 2012-10-18 21:34:22 +0100 | [diff] [blame] | 2839 | desc[frag].len_vlan = frags[i - 1].size; |
| 2840 | dma_addr = skb_frag_dma_map(&adapter->pdev->dev, |
| 2841 | &frags[i - 1], |
| 2842 | 0, |
| 2843 | frags[i - 1].size, |
| 2844 | DMA_TO_DEVICE); |
| 2845 | desc[frag].addr_lo = lower_32_bits(dma_addr); |
| 2846 | desc[frag].addr_hi = upper_32_bits(dma_addr); |
| 2847 | frag++; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2848 | } |
| 2849 | } |
| 2850 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2851 | if (phydev && phydev->speed == SPEED_1000) { |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2852 | if (++tx_ring->since_irq == PARM_TX_NUM_BUFS_DEF) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2853 | /* Last element & Interrupt flag */ |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 2854 | desc[frag - 1].flags = |
| 2855 | TXDESC_FLAG_INTPROC | TXDESC_FLAG_LASTPKT; |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2856 | tx_ring->since_irq = 0; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2857 | } else { /* Last element */ |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 2858 | desc[frag - 1].flags = TXDESC_FLAG_LASTPKT; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2859 | } |
| 2860 | } else |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 2861 | desc[frag - 1].flags = |
| 2862 | TXDESC_FLAG_INTPROC | TXDESC_FLAG_LASTPKT; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2863 | |
Mark Einon | a129be8 | 2013-01-04 22:25:46 +0000 | [diff] [blame] | 2864 | desc[0].flags |= TXDESC_FLAG_FIRSTPKT; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2865 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2866 | tcb->index_start = tx_ring->send_idx; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2867 | tcb->stale = 0; |
| 2868 | |
| 2869 | spin_lock_irqsave(&adapter->send_hw_lock, flags); |
| 2870 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2871 | thiscopy = NUM_DESC_PER_RING_TX - INDEX10(tx_ring->send_idx); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2872 | |
| 2873 | if (thiscopy >= frag) { |
| 2874 | remainder = 0; |
| 2875 | thiscopy = frag; |
| 2876 | } else { |
| 2877 | remainder = frag - thiscopy; |
| 2878 | } |
| 2879 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2880 | memcpy(tx_ring->tx_desc_ring + INDEX10(tx_ring->send_idx), |
| 2881 | desc, |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2882 | sizeof(struct tx_desc) * thiscopy); |
| 2883 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2884 | add_10bit(&tx_ring->send_idx, thiscopy); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2885 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2886 | if (INDEX10(tx_ring->send_idx) == 0 || |
| 2887 | INDEX10(tx_ring->send_idx) == NUM_DESC_PER_RING_TX) { |
| 2888 | tx_ring->send_idx &= ~ET_DMA10_MASK; |
| 2889 | tx_ring->send_idx ^= ET_DMA10_WRAP; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2890 | } |
| 2891 | |
| 2892 | if (remainder) { |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2893 | memcpy(tx_ring->tx_desc_ring, |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2894 | desc + thiscopy, |
| 2895 | sizeof(struct tx_desc) * remainder); |
| 2896 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2897 | add_10bit(&tx_ring->send_idx, remainder); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2898 | } |
| 2899 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2900 | if (INDEX10(tx_ring->send_idx) == 0) { |
| 2901 | if (tx_ring->send_idx) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2902 | tcb->index = NUM_DESC_PER_RING_TX - 1; |
| 2903 | else |
| 2904 | tcb->index = ET_DMA10_WRAP|(NUM_DESC_PER_RING_TX - 1); |
| 2905 | } else |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2906 | tcb->index = tx_ring->send_idx - 1; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2907 | |
| 2908 | spin_lock(&adapter->tcb_send_qlock); |
| 2909 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2910 | if (tx_ring->send_tail) |
| 2911 | tx_ring->send_tail->next = tcb; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2912 | else |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2913 | tx_ring->send_head = tcb; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2914 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2915 | tx_ring->send_tail = tcb; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2916 | |
| 2917 | WARN_ON(tcb->next != NULL); |
| 2918 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2919 | tx_ring->used++; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2920 | |
| 2921 | spin_unlock(&adapter->tcb_send_qlock); |
| 2922 | |
| 2923 | /* Write the new write pointer back to the device. */ |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2924 | writel(tx_ring->send_idx, &adapter->regs->txdma.service_request); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2925 | |
| 2926 | /* For Gig only, we use Tx Interrupt coalescing. Enable the software |
| 2927 | * timer to wake us up if this packet isn't followed by N more. |
| 2928 | */ |
| 2929 | if (phydev && phydev->speed == SPEED_1000) { |
| 2930 | writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO, |
| 2931 | &adapter->regs->global.watchdog_timer); |
| 2932 | } |
| 2933 | spin_unlock_irqrestore(&adapter->send_hw_lock, flags); |
| 2934 | |
| 2935 | return 0; |
| 2936 | } |
| 2937 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 2938 | /* send_packet - Do the work to send a packet |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2939 | * |
| 2940 | * Assumption: Send spinlock has been acquired |
| 2941 | */ |
| 2942 | static int send_packet(struct sk_buff *skb, struct et131x_adapter *adapter) |
| 2943 | { |
| 2944 | int status; |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2945 | struct tcb *tcb; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2946 | u16 *shbufva; |
| 2947 | unsigned long flags; |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2948 | struct tx_ring *tx_ring = &adapter->tx_ring; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2949 | |
| 2950 | /* All packets must have at least a MAC address and a protocol type */ |
| 2951 | if (skb->len < ETH_HLEN) |
| 2952 | return -EIO; |
| 2953 | |
| 2954 | /* Get a TCB for this packet */ |
| 2955 | spin_lock_irqsave(&adapter->tcb_ready_qlock, flags); |
| 2956 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2957 | tcb = tx_ring->tcb_qhead; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2958 | |
| 2959 | if (tcb == NULL) { |
| 2960 | spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags); |
| 2961 | return -ENOMEM; |
| 2962 | } |
| 2963 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2964 | tx_ring->tcb_qhead = tcb->next; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2965 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2966 | if (tx_ring->tcb_qhead == NULL) |
| 2967 | tx_ring->tcb_qtail = NULL; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2968 | |
| 2969 | spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags); |
| 2970 | |
| 2971 | tcb->skb = skb; |
| 2972 | |
Mark Einon | f1b540b | 2012-10-17 22:15:11 +0100 | [diff] [blame] | 2973 | if (skb->data != NULL && skb_headlen(skb) >= 6) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2974 | shbufva = (u16 *) skb->data; |
| 2975 | |
| 2976 | if ((shbufva[0] == 0xffff) && |
Mark Einon | 0cdc6ee | 2013-09-11 14:14:45 +0100 | [diff] [blame] | 2977 | (shbufva[1] == 0xffff) && (shbufva[2] == 0xffff)) |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 2978 | tcb->flags |= FMP_DEST_BROAD; |
Mark Einon | 0cdc6ee | 2013-09-11 14:14:45 +0100 | [diff] [blame] | 2979 | else if ((shbufva[0] & 0x3) == 0x0001) |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 2980 | tcb->flags |= FMP_DEST_MULTI; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2981 | } |
| 2982 | |
| 2983 | tcb->next = NULL; |
| 2984 | |
| 2985 | /* Call the NIC specific send handler. */ |
| 2986 | status = nic_send_packet(adapter, tcb); |
| 2987 | |
| 2988 | if (status != 0) { |
| 2989 | spin_lock_irqsave(&adapter->tcb_ready_qlock, flags); |
| 2990 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2991 | if (tx_ring->tcb_qtail) |
| 2992 | tx_ring->tcb_qtail->next = tcb; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2993 | else |
| 2994 | /* Apparently ready Q is empty. */ |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2995 | tx_ring->tcb_qhead = tcb; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2996 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 2997 | tx_ring->tcb_qtail = tcb; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2998 | spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags); |
| 2999 | return status; |
| 3000 | } |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3001 | WARN_ON(tx_ring->used > NUM_TCB); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3002 | return 0; |
| 3003 | } |
| 3004 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 3005 | /* et131x_send_packets - This function is called by the OS to send packets */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 3006 | static int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3007 | { |
| 3008 | int status = 0; |
Mark Einon | 06709e9 | 2011-10-20 01:18:46 +0100 | [diff] [blame] | 3009 | struct et131x_adapter *adapter = netdev_priv(netdev); |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3010 | struct tx_ring *tx_ring = &adapter->tx_ring; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3011 | |
| 3012 | /* Send these packets |
| 3013 | * |
| 3014 | * NOTE: The Linux Tx entry point is only given one packet at a time |
| 3015 | * to Tx, so the PacketCount and it's array used makes no sense here |
| 3016 | */ |
| 3017 | |
| 3018 | /* TCB is not available */ |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3019 | if (tx_ring->used >= NUM_TCB) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3020 | /* NOTE: If there's an error on send, no need to queue the |
| 3021 | * packet under Linux; if we just send an error up to the |
| 3022 | * netif layer, it will resend the skb to us. |
| 3023 | */ |
| 3024 | status = -ENOMEM; |
| 3025 | } else { |
| 3026 | /* We need to see if the link is up; if it's not, make the |
| 3027 | * netif layer think we're good and drop the packet |
| 3028 | */ |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 3029 | if ((adapter->flags & FMP_ADAPTER_FAIL_SEND_MASK) || |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3030 | !netif_carrier_ok(netdev)) { |
| 3031 | dev_kfree_skb_any(skb); |
| 3032 | skb = NULL; |
| 3033 | |
| 3034 | adapter->net_stats.tx_dropped++; |
| 3035 | } else { |
| 3036 | status = send_packet(skb, adapter); |
| 3037 | if (status != 0 && status != -ENOMEM) { |
| 3038 | /* On any other error, make netif think we're |
| 3039 | * OK and drop the packet |
| 3040 | */ |
| 3041 | dev_kfree_skb_any(skb); |
| 3042 | skb = NULL; |
| 3043 | adapter->net_stats.tx_dropped++; |
| 3044 | } |
| 3045 | } |
| 3046 | } |
| 3047 | return status; |
| 3048 | } |
| 3049 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 3050 | /* free_send_packet - Recycle a struct tcb |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3051 | * @adapter: pointer to our adapter |
| 3052 | * @tcb: pointer to struct tcb |
| 3053 | * |
| 3054 | * Complete the packet if necessary |
| 3055 | * Assumption - Send spinlock has been acquired |
| 3056 | */ |
| 3057 | static inline void free_send_packet(struct et131x_adapter *adapter, |
| 3058 | struct tcb *tcb) |
| 3059 | { |
| 3060 | unsigned long flags; |
| 3061 | struct tx_desc *desc = NULL; |
| 3062 | struct net_device_stats *stats = &adapter->net_stats; |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3063 | struct tx_ring *tx_ring = &adapter->tx_ring; |
Mark Einon | 983e4b3 | 2012-10-23 23:34:15 +0100 | [diff] [blame] | 3064 | u64 dma_addr; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3065 | |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 3066 | if (tcb->flags & FMP_DEST_BROAD) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3067 | atomic_inc(&adapter->stats.broadcast_pkts_xmtd); |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 3068 | else if (tcb->flags & FMP_DEST_MULTI) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3069 | atomic_inc(&adapter->stats.multicast_pkts_xmtd); |
| 3070 | else |
| 3071 | atomic_inc(&adapter->stats.unicast_pkts_xmtd); |
| 3072 | |
| 3073 | if (tcb->skb) { |
| 3074 | stats->tx_bytes += tcb->skb->len; |
| 3075 | |
| 3076 | /* Iterate through the TX descriptors on the ring |
| 3077 | * corresponding to this packet and umap the fragments |
| 3078 | * they point to |
| 3079 | */ |
| 3080 | do { |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3081 | desc = tx_ring->tx_desc_ring + |
ZHAO Gang | 57cc027 | 2013-12-09 19:38:30 +0800 | [diff] [blame] | 3082 | INDEX10(tcb->index_start); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3083 | |
Mark Einon | 998f6df | 2012-10-18 21:34:22 +0100 | [diff] [blame] | 3084 | dma_addr = desc->addr_lo; |
Mark Einon | 983e4b3 | 2012-10-23 23:34:15 +0100 | [diff] [blame] | 3085 | dma_addr |= (u64)desc->addr_hi << 32; |
Mark Einon | 998f6df | 2012-10-18 21:34:22 +0100 | [diff] [blame] | 3086 | |
Mark Einon | 26dc751 | 2011-10-20 01:18:47 +0100 | [diff] [blame] | 3087 | dma_unmap_single(&adapter->pdev->dev, |
Mark Einon | 998f6df | 2012-10-18 21:34:22 +0100 | [diff] [blame] | 3088 | dma_addr, |
Mark Einon | 26dc751 | 2011-10-20 01:18:47 +0100 | [diff] [blame] | 3089 | desc->len_vlan, DMA_TO_DEVICE); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3090 | |
| 3091 | add_10bit(&tcb->index_start, 1); |
| 3092 | if (INDEX10(tcb->index_start) >= |
| 3093 | NUM_DESC_PER_RING_TX) { |
| 3094 | tcb->index_start &= ~ET_DMA10_MASK; |
| 3095 | tcb->index_start ^= ET_DMA10_WRAP; |
| 3096 | } |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3097 | } while (desc != tx_ring->tx_desc_ring + INDEX10(tcb->index)); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3098 | |
| 3099 | dev_kfree_skb_any(tcb->skb); |
| 3100 | } |
| 3101 | |
| 3102 | memset(tcb, 0, sizeof(struct tcb)); |
| 3103 | |
| 3104 | /* Add the TCB to the Ready Q */ |
| 3105 | spin_lock_irqsave(&adapter->tcb_ready_qlock, flags); |
| 3106 | |
| 3107 | adapter->net_stats.tx_packets++; |
| 3108 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3109 | if (tx_ring->tcb_qtail) |
| 3110 | tx_ring->tcb_qtail->next = tcb; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3111 | else |
| 3112 | /* Apparently ready Q is empty. */ |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3113 | tx_ring->tcb_qhead = tcb; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3114 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3115 | tx_ring->tcb_qtail = tcb; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3116 | |
| 3117 | spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags); |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3118 | WARN_ON(tx_ring->used < 0); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3119 | } |
| 3120 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 3121 | /* et131x_free_busy_send_packets - Free and complete the stopped active sends |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3122 | * |
| 3123 | * Assumption - Send spinlock has been acquired |
| 3124 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 3125 | static void et131x_free_busy_send_packets(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3126 | { |
| 3127 | struct tcb *tcb; |
| 3128 | unsigned long flags; |
| 3129 | u32 freed = 0; |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3130 | struct tx_ring *tx_ring = &adapter->tx_ring; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3131 | |
| 3132 | /* Any packets being sent? Check the first TCB on the send list */ |
| 3133 | spin_lock_irqsave(&adapter->tcb_send_qlock, flags); |
| 3134 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3135 | tcb = tx_ring->send_head; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3136 | |
| 3137 | while (tcb != NULL && freed < NUM_TCB) { |
| 3138 | struct tcb *next = tcb->next; |
| 3139 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3140 | tx_ring->send_head = next; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3141 | |
| 3142 | if (next == NULL) |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3143 | tx_ring->send_tail = NULL; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3144 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3145 | tx_ring->used--; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3146 | |
| 3147 | spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags); |
| 3148 | |
| 3149 | freed++; |
| 3150 | free_send_packet(adapter, tcb); |
| 3151 | |
| 3152 | spin_lock_irqsave(&adapter->tcb_send_qlock, flags); |
| 3153 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3154 | tcb = tx_ring->send_head; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3155 | } |
| 3156 | |
| 3157 | WARN_ON(freed == NUM_TCB); |
| 3158 | |
| 3159 | spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags); |
| 3160 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3161 | tx_ring->used = 0; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3162 | } |
| 3163 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 3164 | /* et131x_handle_send_interrupt - Interrupt handler for sending processing |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3165 | * |
| 3166 | * Re-claim the send resources, complete sends and get more to send from |
| 3167 | * the send wait queue. |
| 3168 | * |
| 3169 | * Assumption - Send spinlock has been acquired |
| 3170 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 3171 | static void et131x_handle_send_interrupt(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3172 | { |
| 3173 | unsigned long flags; |
| 3174 | u32 serviced; |
| 3175 | struct tcb *tcb; |
| 3176 | u32 index; |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3177 | struct tx_ring *tx_ring = &adapter->tx_ring; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3178 | |
| 3179 | serviced = readl(&adapter->regs->txdma.new_service_complete); |
| 3180 | index = INDEX10(serviced); |
| 3181 | |
| 3182 | /* Has the ring wrapped? Process any descriptors that do not have |
| 3183 | * the same "wrap" indicator as the current completion indicator |
| 3184 | */ |
| 3185 | spin_lock_irqsave(&adapter->tcb_send_qlock, flags); |
| 3186 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3187 | tcb = tx_ring->send_head; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3188 | |
| 3189 | while (tcb && |
| 3190 | ((serviced ^ tcb->index) & ET_DMA10_WRAP) && |
| 3191 | index < INDEX10(tcb->index)) { |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3192 | tx_ring->used--; |
| 3193 | tx_ring->send_head = tcb->next; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3194 | if (tcb->next == NULL) |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3195 | tx_ring->send_tail = NULL; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3196 | |
| 3197 | spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags); |
| 3198 | free_send_packet(adapter, tcb); |
| 3199 | spin_lock_irqsave(&adapter->tcb_send_qlock, flags); |
| 3200 | |
| 3201 | /* Goto the next packet */ |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3202 | tcb = tx_ring->send_head; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3203 | } |
| 3204 | while (tcb && |
| 3205 | !((serviced ^ tcb->index) & ET_DMA10_WRAP) |
| 3206 | && index > (tcb->index & ET_DMA10_MASK)) { |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3207 | tx_ring->used--; |
| 3208 | tx_ring->send_head = tcb->next; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3209 | if (tcb->next == NULL) |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3210 | tx_ring->send_tail = NULL; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3211 | |
| 3212 | spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags); |
| 3213 | free_send_packet(adapter, tcb); |
| 3214 | spin_lock_irqsave(&adapter->tcb_send_qlock, flags); |
| 3215 | |
| 3216 | /* Goto the next packet */ |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3217 | tcb = tx_ring->send_head; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3218 | } |
| 3219 | |
| 3220 | /* Wake up the queue when we hit a low-water mark */ |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3221 | if (tx_ring->used <= NUM_TCB / 3) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3222 | netif_wake_queue(adapter->netdev); |
| 3223 | |
| 3224 | spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags); |
| 3225 | } |
| 3226 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3227 | static int et131x_get_settings(struct net_device *netdev, |
| 3228 | struct ethtool_cmd *cmd) |
| 3229 | { |
| 3230 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 3231 | |
| 3232 | return phy_ethtool_gset(adapter->phydev, cmd); |
| 3233 | } |
| 3234 | |
| 3235 | static int et131x_set_settings(struct net_device *netdev, |
| 3236 | struct ethtool_cmd *cmd) |
| 3237 | { |
| 3238 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 3239 | |
| 3240 | return phy_ethtool_sset(adapter->phydev, cmd); |
| 3241 | } |
| 3242 | |
| 3243 | static int et131x_get_regs_len(struct net_device *netdev) |
| 3244 | { |
| 3245 | #define ET131X_REGS_LEN 256 |
| 3246 | return ET131X_REGS_LEN * sizeof(u32); |
| 3247 | } |
| 3248 | |
| 3249 | static void et131x_get_regs(struct net_device *netdev, |
| 3250 | struct ethtool_regs *regs, void *regs_data) |
| 3251 | { |
| 3252 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 3253 | struct address_map __iomem *aregs = adapter->regs; |
| 3254 | u32 *regs_buff = regs_data; |
| 3255 | u32 num = 0; |
Mark Einon | c8b0a48 | 2013-01-22 14:29:47 +0000 | [diff] [blame] | 3256 | u16 tmp; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3257 | |
| 3258 | memset(regs_data, 0, et131x_get_regs_len(netdev)); |
| 3259 | |
| 3260 | regs->version = (1 << 24) | (adapter->pdev->revision << 16) | |
| 3261 | adapter->pdev->device; |
| 3262 | |
| 3263 | /* PHY regs */ |
Mark Einon | c8b0a48 | 2013-01-22 14:29:47 +0000 | [diff] [blame] | 3264 | et131x_mii_read(adapter, MII_BMCR, &tmp); |
| 3265 | regs_buff[num++] = tmp; |
| 3266 | et131x_mii_read(adapter, MII_BMSR, &tmp); |
| 3267 | regs_buff[num++] = tmp; |
| 3268 | et131x_mii_read(adapter, MII_PHYSID1, &tmp); |
| 3269 | regs_buff[num++] = tmp; |
| 3270 | et131x_mii_read(adapter, MII_PHYSID2, &tmp); |
| 3271 | regs_buff[num++] = tmp; |
| 3272 | et131x_mii_read(adapter, MII_ADVERTISE, &tmp); |
| 3273 | regs_buff[num++] = tmp; |
| 3274 | et131x_mii_read(adapter, MII_LPA, &tmp); |
| 3275 | regs_buff[num++] = tmp; |
| 3276 | et131x_mii_read(adapter, MII_EXPANSION, &tmp); |
| 3277 | regs_buff[num++] = tmp; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3278 | /* Autoneg next page transmit reg */ |
Mark Einon | c8b0a48 | 2013-01-22 14:29:47 +0000 | [diff] [blame] | 3279 | et131x_mii_read(adapter, 0x07, &tmp); |
| 3280 | regs_buff[num++] = tmp; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3281 | /* Link partner next page reg */ |
Mark Einon | c8b0a48 | 2013-01-22 14:29:47 +0000 | [diff] [blame] | 3282 | et131x_mii_read(adapter, 0x08, &tmp); |
| 3283 | regs_buff[num++] = tmp; |
| 3284 | et131x_mii_read(adapter, MII_CTRL1000, &tmp); |
| 3285 | regs_buff[num++] = tmp; |
| 3286 | et131x_mii_read(adapter, MII_STAT1000, &tmp); |
| 3287 | regs_buff[num++] = tmp; |
| 3288 | et131x_mii_read(adapter, 0x0b, &tmp); |
| 3289 | regs_buff[num++] = tmp; |
| 3290 | et131x_mii_read(adapter, 0x0c, &tmp); |
| 3291 | regs_buff[num++] = tmp; |
| 3292 | et131x_mii_read(adapter, MII_MMD_CTRL, &tmp); |
| 3293 | regs_buff[num++] = tmp; |
| 3294 | et131x_mii_read(adapter, MII_MMD_DATA, &tmp); |
| 3295 | regs_buff[num++] = tmp; |
| 3296 | et131x_mii_read(adapter, MII_ESTATUS, &tmp); |
| 3297 | regs_buff[num++] = tmp; |
Mark Einon | 01e14a4 | 2012-10-30 21:23:29 +0000 | [diff] [blame] | 3298 | |
Mark Einon | c8b0a48 | 2013-01-22 14:29:47 +0000 | [diff] [blame] | 3299 | et131x_mii_read(adapter, PHY_INDEX_REG, &tmp); |
| 3300 | regs_buff[num++] = tmp; |
| 3301 | et131x_mii_read(adapter, PHY_DATA_REG, &tmp); |
| 3302 | regs_buff[num++] = tmp; |
| 3303 | et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, &tmp); |
| 3304 | regs_buff[num++] = tmp; |
| 3305 | et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL, &tmp); |
| 3306 | regs_buff[num++] = tmp; |
| 3307 | et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL + 1, &tmp); |
| 3308 | regs_buff[num++] = tmp; |
Mark Einon | 01e14a4 | 2012-10-30 21:23:29 +0000 | [diff] [blame] | 3309 | |
Mark Einon | c8b0a48 | 2013-01-22 14:29:47 +0000 | [diff] [blame] | 3310 | et131x_mii_read(adapter, PHY_REGISTER_MGMT_CONTROL, &tmp); |
| 3311 | regs_buff[num++] = tmp; |
| 3312 | et131x_mii_read(adapter, PHY_CONFIG, &tmp); |
| 3313 | regs_buff[num++] = tmp; |
| 3314 | et131x_mii_read(adapter, PHY_PHY_CONTROL, &tmp); |
| 3315 | regs_buff[num++] = tmp; |
| 3316 | et131x_mii_read(adapter, PHY_INTERRUPT_MASK, &tmp); |
| 3317 | regs_buff[num++] = tmp; |
| 3318 | et131x_mii_read(adapter, PHY_INTERRUPT_STATUS, &tmp); |
| 3319 | regs_buff[num++] = tmp; |
| 3320 | et131x_mii_read(adapter, PHY_PHY_STATUS, &tmp); |
| 3321 | regs_buff[num++] = tmp; |
| 3322 | et131x_mii_read(adapter, PHY_LED_1, &tmp); |
| 3323 | regs_buff[num++] = tmp; |
| 3324 | et131x_mii_read(adapter, PHY_LED_2, &tmp); |
| 3325 | regs_buff[num++] = tmp; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3326 | |
| 3327 | /* Global regs */ |
| 3328 | regs_buff[num++] = readl(&aregs->global.txq_start_addr); |
| 3329 | regs_buff[num++] = readl(&aregs->global.txq_end_addr); |
| 3330 | regs_buff[num++] = readl(&aregs->global.rxq_start_addr); |
| 3331 | regs_buff[num++] = readl(&aregs->global.rxq_end_addr); |
| 3332 | regs_buff[num++] = readl(&aregs->global.pm_csr); |
| 3333 | regs_buff[num++] = adapter->stats.interrupt_status; |
| 3334 | regs_buff[num++] = readl(&aregs->global.int_mask); |
| 3335 | regs_buff[num++] = readl(&aregs->global.int_alias_clr_en); |
| 3336 | regs_buff[num++] = readl(&aregs->global.int_status_alias); |
| 3337 | regs_buff[num++] = readl(&aregs->global.sw_reset); |
| 3338 | regs_buff[num++] = readl(&aregs->global.slv_timer); |
| 3339 | regs_buff[num++] = readl(&aregs->global.msi_config); |
| 3340 | regs_buff[num++] = readl(&aregs->global.loopback); |
| 3341 | regs_buff[num++] = readl(&aregs->global.watchdog_timer); |
| 3342 | |
| 3343 | /* TXDMA regs */ |
| 3344 | regs_buff[num++] = readl(&aregs->txdma.csr); |
| 3345 | regs_buff[num++] = readl(&aregs->txdma.pr_base_hi); |
| 3346 | regs_buff[num++] = readl(&aregs->txdma.pr_base_lo); |
| 3347 | regs_buff[num++] = readl(&aregs->txdma.pr_num_des); |
| 3348 | regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr); |
| 3349 | regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext); |
| 3350 | regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr); |
| 3351 | regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi); |
| 3352 | regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo); |
| 3353 | regs_buff[num++] = readl(&aregs->txdma.service_request); |
| 3354 | regs_buff[num++] = readl(&aregs->txdma.service_complete); |
| 3355 | regs_buff[num++] = readl(&aregs->txdma.cache_rd_index); |
| 3356 | regs_buff[num++] = readl(&aregs->txdma.cache_wr_index); |
| 3357 | regs_buff[num++] = readl(&aregs->txdma.tx_dma_error); |
| 3358 | regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt); |
| 3359 | regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt); |
| 3360 | regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt); |
| 3361 | regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt); |
| 3362 | regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt); |
| 3363 | regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt); |
| 3364 | regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt); |
| 3365 | regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt); |
| 3366 | regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt); |
| 3367 | regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt); |
| 3368 | regs_buff[num++] = readl(&aregs->txdma.new_service_complete); |
| 3369 | regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt); |
| 3370 | |
| 3371 | /* RXDMA regs */ |
| 3372 | regs_buff[num++] = readl(&aregs->rxdma.csr); |
| 3373 | regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi); |
| 3374 | regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo); |
| 3375 | regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done); |
| 3376 | regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time); |
| 3377 | regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr); |
| 3378 | regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext); |
| 3379 | regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr); |
| 3380 | regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi); |
| 3381 | regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo); |
| 3382 | regs_buff[num++] = readl(&aregs->rxdma.psr_num_des); |
| 3383 | regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset); |
| 3384 | regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset); |
| 3385 | regs_buff[num++] = readl(&aregs->rxdma.psr_access_index); |
| 3386 | regs_buff[num++] = readl(&aregs->rxdma.psr_min_des); |
| 3387 | regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo); |
| 3388 | regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi); |
| 3389 | regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des); |
| 3390 | regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset); |
| 3391 | regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset); |
| 3392 | regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index); |
| 3393 | regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des); |
| 3394 | regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo); |
| 3395 | regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi); |
| 3396 | regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des); |
| 3397 | regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset); |
| 3398 | regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset); |
| 3399 | regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index); |
| 3400 | regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des); |
| 3401 | } |
| 3402 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3403 | static void et131x_get_drvinfo(struct net_device *netdev, |
| 3404 | struct ethtool_drvinfo *info) |
| 3405 | { |
| 3406 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 3407 | |
Jiri Pirko | 7826d43 | 2013-01-06 00:44:26 +0000 | [diff] [blame] | 3408 | strlcpy(info->driver, DRIVER_NAME, sizeof(info->driver)); |
| 3409 | strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); |
| 3410 | strlcpy(info->bus_info, pci_name(adapter->pdev), |
| 3411 | sizeof(info->bus_info)); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3412 | } |
| 3413 | |
| 3414 | static struct ethtool_ops et131x_ethtool_ops = { |
| 3415 | .get_settings = et131x_get_settings, |
| 3416 | .set_settings = et131x_set_settings, |
| 3417 | .get_drvinfo = et131x_get_drvinfo, |
| 3418 | .get_regs_len = et131x_get_regs_len, |
| 3419 | .get_regs = et131x_get_regs, |
Mark Einon | 242187a | 2012-10-30 18:38:55 +0000 | [diff] [blame] | 3420 | .get_link = ethtool_op_get_link, |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3421 | }; |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 3422 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 3423 | /* et131x_hwaddr_init - set up the MAC Address on the ET1310 */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 3424 | static void et131x_hwaddr_init(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3425 | { |
| 3426 | /* If have our default mac from init and no mac address from |
| 3427 | * EEPROM then we need to generate the last octet and set it on the |
| 3428 | * device |
| 3429 | */ |
Wei Yongjun | c14d01b | 2012-08-26 08:55:15 +0800 | [diff] [blame] | 3430 | if (is_zero_ether_addr(adapter->rom_addr)) { |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 3431 | /* We need to randomly generate the last octet so we |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3432 | * decrease our chances of setting the mac address to |
| 3433 | * same as another one of our cards in the system |
| 3434 | */ |
| 3435 | get_random_bytes(&adapter->addr[5], 1); |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 3436 | /* We have the default value in the register we are |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3437 | * working with so we need to copy the current |
| 3438 | * address into the permanent address |
| 3439 | */ |
| 3440 | memcpy(adapter->rom_addr, |
| 3441 | adapter->addr, ETH_ALEN); |
| 3442 | } else { |
| 3443 | /* We do not have an override address, so set the |
| 3444 | * current address to the permanent address and add |
| 3445 | * it to the device |
| 3446 | */ |
| 3447 | memcpy(adapter->addr, |
| 3448 | adapter->rom_addr, ETH_ALEN); |
| 3449 | } |
| 3450 | } |
| 3451 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 3452 | /* et131x_pci_init - initial PCI setup |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3453 | * |
| 3454 | * Perform the initial setup of PCI registers and if possible initialise |
| 3455 | * the MAC address. At this point the I/O registers have yet to be mapped |
| 3456 | */ |
| 3457 | static int et131x_pci_init(struct et131x_adapter *adapter, |
Mark Einon | 12a2f3f | 2013-12-05 22:37:46 +0000 | [diff] [blame] | 3458 | struct pci_dev *pdev) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3459 | { |
Francois Romieu | d14e3d0 | 2011-10-23 19:12:14 +0200 | [diff] [blame] | 3460 | u16 max_payload; |
Francois Romieu | d14e3d0 | 2011-10-23 19:12:14 +0200 | [diff] [blame] | 3461 | int i, rc; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3462 | |
Francois Romieu | d14e3d0 | 2011-10-23 19:12:14 +0200 | [diff] [blame] | 3463 | rc = et131x_init_eeprom(adapter); |
| 3464 | if (rc < 0) |
| 3465 | goto out; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3466 | |
Jiang Liu | 532c5f6 | 2012-07-24 17:20:32 +0800 | [diff] [blame] | 3467 | if (!pci_is_pcie(pdev)) { |
Francois Romieu | d14e3d0 | 2011-10-23 19:12:14 +0200 | [diff] [blame] | 3468 | dev_err(&pdev->dev, "Missing PCIe capabilities\n"); |
| 3469 | goto err_out; |
| 3470 | } |
joseph daniel | bf3313a | 2012-05-01 00:30:34 +0600 | [diff] [blame] | 3471 | |
Yijing Wang | 9db008d | 2013-09-09 21:13:07 +0800 | [diff] [blame] | 3472 | /* Let's set up the PORT LOGIC Register. */ |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3473 | |
| 3474 | /* Program the Ack/Nak latency and replay timers */ |
Yijing Wang | 9db008d | 2013-09-09 21:13:07 +0800 | [diff] [blame] | 3475 | max_payload = pdev->pcie_mpss; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3476 | |
| 3477 | if (max_payload < 2) { |
| 3478 | static const u16 acknak[2] = { 0x76, 0xD0 }; |
| 3479 | static const u16 replay[2] = { 0x1E0, 0x2ED }; |
| 3480 | |
| 3481 | if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK, |
| 3482 | acknak[max_payload])) { |
| 3483 | dev_err(&pdev->dev, |
| 3484 | "Could not write PCI config space for ACK/NAK\n"); |
Francois Romieu | d14e3d0 | 2011-10-23 19:12:14 +0200 | [diff] [blame] | 3485 | goto err_out; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3486 | } |
| 3487 | if (pci_write_config_word(pdev, ET1310_PCI_REPLAY, |
| 3488 | replay[max_payload])) { |
| 3489 | dev_err(&pdev->dev, |
| 3490 | "Could not write PCI config space for Replay Timer\n"); |
Francois Romieu | d14e3d0 | 2011-10-23 19:12:14 +0200 | [diff] [blame] | 3491 | goto err_out; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3492 | } |
| 3493 | } |
| 3494 | |
| 3495 | /* l0s and l1 latency timers. We are using default values. |
| 3496 | * Representing 001 for L0s and 010 for L1 |
| 3497 | */ |
| 3498 | if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) { |
| 3499 | dev_err(&pdev->dev, |
| 3500 | "Could not write PCI config space for Latency Timers\n"); |
Francois Romieu | d14e3d0 | 2011-10-23 19:12:14 +0200 | [diff] [blame] | 3501 | goto err_out; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3502 | } |
| 3503 | |
| 3504 | /* Change the max read size to 2k */ |
Yijing Wang | 9db008d | 2013-09-09 21:13:07 +0800 | [diff] [blame] | 3505 | if (pcie_set_readrq(pdev, 2048)) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3506 | dev_err(&pdev->dev, |
Jiang Liu | 532c5f6 | 2012-07-24 17:20:32 +0800 | [diff] [blame] | 3507 | "Couldn't change PCI config space for Max read size\n"); |
Francois Romieu | d14e3d0 | 2011-10-23 19:12:14 +0200 | [diff] [blame] | 3508 | goto err_out; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3509 | } |
| 3510 | |
| 3511 | /* Get MAC address from config space if an eeprom exists, otherwise |
| 3512 | * the MAC address there will not be valid |
| 3513 | */ |
| 3514 | if (!adapter->has_eeprom) { |
| 3515 | et131x_hwaddr_init(adapter); |
| 3516 | return 0; |
| 3517 | } |
| 3518 | |
| 3519 | for (i = 0; i < ETH_ALEN; i++) { |
| 3520 | if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i, |
| 3521 | adapter->rom_addr + i)) { |
| 3522 | dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n"); |
Francois Romieu | d14e3d0 | 2011-10-23 19:12:14 +0200 | [diff] [blame] | 3523 | goto err_out; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3524 | } |
| 3525 | } |
| 3526 | memcpy(adapter->addr, adapter->rom_addr, ETH_ALEN); |
Francois Romieu | d14e3d0 | 2011-10-23 19:12:14 +0200 | [diff] [blame] | 3527 | out: |
| 3528 | return rc; |
| 3529 | err_out: |
| 3530 | rc = -EIO; |
| 3531 | goto out; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3532 | } |
| 3533 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 3534 | /* et131x_error_timer_handler |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3535 | * @data: timer-specific variable; here a pointer to our adapter structure |
| 3536 | * |
| 3537 | * The routine called when the error timer expires, to track the number of |
| 3538 | * recurring errors. |
| 3539 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 3540 | static void et131x_error_timer_handler(unsigned long data) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3541 | { |
| 3542 | struct et131x_adapter *adapter = (struct et131x_adapter *) data; |
| 3543 | struct phy_device *phydev = adapter->phydev; |
| 3544 | |
| 3545 | if (et1310_in_phy_coma(adapter)) { |
| 3546 | /* Bring the device immediately out of coma, to |
| 3547 | * prevent it from sleeping indefinitely, this |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 3548 | * mechanism could be improved! |
| 3549 | */ |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3550 | et1310_disable_phy_coma(adapter); |
| 3551 | adapter->boot_coma = 20; |
| 3552 | } else { |
| 3553 | et1310_update_macstat_host_counters(adapter); |
| 3554 | } |
| 3555 | |
| 3556 | if (!phydev->link && adapter->boot_coma < 11) |
| 3557 | adapter->boot_coma++; |
| 3558 | |
| 3559 | if (adapter->boot_coma == 10) { |
| 3560 | if (!phydev->link) { |
| 3561 | if (!et1310_in_phy_coma(adapter)) { |
| 3562 | /* NOTE - This was originally a 'sync with |
| 3563 | * interrupt'. How to do that under Linux? |
| 3564 | */ |
| 3565 | et131x_enable_interrupts(adapter); |
| 3566 | et1310_enable_phy_coma(adapter); |
| 3567 | } |
| 3568 | } |
| 3569 | } |
| 3570 | |
| 3571 | /* This is a periodic timer, so reschedule */ |
Mark Einon | 242187a | 2012-10-30 18:38:55 +0000 | [diff] [blame] | 3572 | mod_timer(&adapter->error_timer, jiffies + TX_ERROR_PERIOD * HZ / 1000); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3573 | } |
| 3574 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 3575 | /* et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx */ |
Mark Einon | d959df0 | 2012-11-16 10:47:41 +0000 | [diff] [blame] | 3576 | static void et131x_adapter_memory_free(struct et131x_adapter *adapter) |
| 3577 | { |
Mark Einon | d959df0 | 2012-11-16 10:47:41 +0000 | [diff] [blame] | 3578 | et131x_tx_dma_memory_free(adapter); |
| 3579 | et131x_rx_dma_memory_free(adapter); |
| 3580 | } |
| 3581 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 3582 | /* et131x_adapter_memory_alloc |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3583 | * Allocate all the memory blocks for send, receive and others. |
| 3584 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 3585 | static int et131x_adapter_memory_alloc(struct et131x_adapter *adapter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3586 | { |
| 3587 | int status; |
| 3588 | |
| 3589 | /* Allocate memory for the Tx Ring */ |
| 3590 | status = et131x_tx_dma_memory_alloc(adapter); |
Mark Einon | 12a2f3f | 2013-12-05 22:37:46 +0000 | [diff] [blame] | 3591 | if (status) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3592 | dev_err(&adapter->pdev->dev, |
| 3593 | "et131x_tx_dma_memory_alloc FAILED\n"); |
| 3594 | return status; |
| 3595 | } |
| 3596 | /* Receive buffer memory allocation */ |
| 3597 | status = et131x_rx_dma_memory_alloc(adapter); |
Mark Einon | 12a2f3f | 2013-12-05 22:37:46 +0000 | [diff] [blame] | 3598 | if (status) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3599 | dev_err(&adapter->pdev->dev, |
| 3600 | "et131x_rx_dma_memory_alloc FAILED\n"); |
| 3601 | et131x_tx_dma_memory_free(adapter); |
| 3602 | return status; |
| 3603 | } |
| 3604 | |
| 3605 | /* Init receive data structures */ |
| 3606 | status = et131x_init_recv(adapter); |
Mark Einon | d959df0 | 2012-11-16 10:47:41 +0000 | [diff] [blame] | 3607 | if (status) { |
Mark Einon | 12a2f3f | 2013-12-05 22:37:46 +0000 | [diff] [blame] | 3608 | dev_err(&adapter->pdev->dev, "et131x_init_recv FAILED\n"); |
Mark Einon | d959df0 | 2012-11-16 10:47:41 +0000 | [diff] [blame] | 3609 | et131x_adapter_memory_free(adapter); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3610 | } |
| 3611 | return status; |
| 3612 | } |
| 3613 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3614 | static void et131x_adjust_link(struct net_device *netdev) |
| 3615 | { |
| 3616 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 3617 | struct phy_device *phydev = adapter->phydev; |
| 3618 | |
Mark Einon | b96ab7c | 2013-12-05 22:37:40 +0000 | [diff] [blame] | 3619 | if (!phydev) |
| 3620 | return; |
| 3621 | if (phydev->link == adapter->link) |
| 3622 | return; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3623 | |
Mark Einon | b96ab7c | 2013-12-05 22:37:40 +0000 | [diff] [blame] | 3624 | /* Check to see if we are in coma mode and if |
| 3625 | * so, disable it because we will not be able |
| 3626 | * to read PHY values until we are out. |
| 3627 | */ |
| 3628 | if (et1310_in_phy_coma(adapter)) |
| 3629 | et1310_disable_phy_coma(adapter); |
Mark Einon | 6903098 | 2013-01-13 20:31:16 +0000 | [diff] [blame] | 3630 | |
Mark Einon | b96ab7c | 2013-12-05 22:37:40 +0000 | [diff] [blame] | 3631 | adapter->link = phydev->link; |
| 3632 | phy_print_status(phydev); |
Mark Einon | 6903098 | 2013-01-13 20:31:16 +0000 | [diff] [blame] | 3633 | |
Mark Einon | b96ab7c | 2013-12-05 22:37:40 +0000 | [diff] [blame] | 3634 | if (phydev->link) { |
| 3635 | adapter->boot_coma = 20; |
Mark Einon | 76af014 | 2013-12-05 22:37:41 +0000 | [diff] [blame] | 3636 | if (phydev->speed == SPEED_10) { |
Mark Einon | b96ab7c | 2013-12-05 22:37:40 +0000 | [diff] [blame] | 3637 | u16 register18; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3638 | |
Mark Einon | b96ab7c | 2013-12-05 22:37:40 +0000 | [diff] [blame] | 3639 | et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, |
| 3640 | ®ister18); |
| 3641 | et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG, |
| 3642 | register18 | 0x4); |
| 3643 | et131x_mii_write(adapter, PHY_INDEX_REG, |
| 3644 | register18 | 0x8402); |
| 3645 | et131x_mii_write(adapter, PHY_DATA_REG, |
| 3646 | register18 | 511); |
| 3647 | et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG, |
| 3648 | register18); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3649 | } |
| 3650 | |
Mark Einon | b96ab7c | 2013-12-05 22:37:40 +0000 | [diff] [blame] | 3651 | et1310_config_flow_control(adapter); |
| 3652 | |
Mark Einon | 76af014 | 2013-12-05 22:37:41 +0000 | [diff] [blame] | 3653 | if (phydev->speed == SPEED_1000 && |
Mark Einon | b96ab7c | 2013-12-05 22:37:40 +0000 | [diff] [blame] | 3654 | adapter->registry_jumbo_packet > 2048) { |
| 3655 | u16 reg; |
| 3656 | |
| 3657 | et131x_mii_read(adapter, PHY_CONFIG, ®); |
| 3658 | reg &= ~ET_PHY_CONFIG_TX_FIFO_DEPTH; |
| 3659 | reg |= ET_PHY_CONFIG_FIFO_DEPTH_32; |
| 3660 | et131x_mii_write(adapter, PHY_CONFIG, reg); |
| 3661 | } |
| 3662 | |
| 3663 | et131x_set_rx_dma_timer(adapter); |
| 3664 | et1310_config_mac_regs2(adapter); |
| 3665 | } else { |
| 3666 | adapter->boot_coma = 0; |
| 3667 | |
| 3668 | if (phydev->speed == SPEED_10) { |
Mark Einon | b96ab7c | 2013-12-05 22:37:40 +0000 | [diff] [blame] | 3669 | u16 register18; |
| 3670 | |
| 3671 | et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, |
| 3672 | ®ister18); |
| 3673 | et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG, |
| 3674 | register18 | 0x4); |
| 3675 | et131x_mii_write(adapter, PHY_INDEX_REG, |
| 3676 | register18 | 0x8402); |
| 3677 | et131x_mii_write(adapter, PHY_DATA_REG, |
| 3678 | register18 | 511); |
| 3679 | et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG, |
| 3680 | register18); |
| 3681 | } |
| 3682 | |
| 3683 | /* Free the packets being actively sent & stopped */ |
| 3684 | et131x_free_busy_send_packets(adapter); |
| 3685 | |
| 3686 | /* Re-initialize the send structures */ |
| 3687 | et131x_init_send(adapter); |
| 3688 | |
| 3689 | /* Bring the device back to the state it was during |
| 3690 | * init prior to autonegotiation being complete. This |
| 3691 | * way, when we get the auto-neg complete interrupt, |
| 3692 | * we can complete init by calling config_mac_regs2. |
| 3693 | */ |
| 3694 | et131x_soft_reset(adapter); |
| 3695 | |
| 3696 | /* Setup ET1310 as per the documentation */ |
| 3697 | et131x_adapter_setup(adapter); |
| 3698 | |
| 3699 | /* perform reset of tx/rx */ |
| 3700 | et131x_disable_txrx(netdev); |
| 3701 | et131x_enable_txrx(netdev); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3702 | } |
| 3703 | } |
| 3704 | |
| 3705 | static int et131x_mii_probe(struct net_device *netdev) |
| 3706 | { |
| 3707 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 3708 | struct phy_device *phydev = NULL; |
| 3709 | |
| 3710 | phydev = phy_find_first(adapter->mii_bus); |
| 3711 | if (!phydev) { |
| 3712 | dev_err(&adapter->pdev->dev, "no PHY found\n"); |
| 3713 | return -ENODEV; |
| 3714 | } |
| 3715 | |
| 3716 | phydev = phy_connect(netdev, dev_name(&phydev->dev), |
Florian Fainelli | f9a8f83 | 2013-01-14 00:52:52 +0000 | [diff] [blame] | 3717 | &et131x_adjust_link, PHY_INTERFACE_MODE_MII); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3718 | |
| 3719 | if (IS_ERR(phydev)) { |
| 3720 | dev_err(&adapter->pdev->dev, "Could not attach to PHY\n"); |
| 3721 | return PTR_ERR(phydev); |
| 3722 | } |
| 3723 | |
| 3724 | phydev->supported &= (SUPPORTED_10baseT_Half |
| 3725 | | SUPPORTED_10baseT_Full |
| 3726 | | SUPPORTED_100baseT_Half |
| 3727 | | SUPPORTED_100baseT_Full |
| 3728 | | SUPPORTED_Autoneg |
| 3729 | | SUPPORTED_MII |
| 3730 | | SUPPORTED_TP); |
| 3731 | |
| 3732 | if (adapter->pdev->device != ET131X_PCI_DEVICE_ID_FAST) |
| 3733 | phydev->supported |= SUPPORTED_1000baseT_Full; |
| 3734 | |
| 3735 | phydev->advertising = phydev->supported; |
| 3736 | adapter->phydev = phydev; |
| 3737 | |
Mark Einon | 12a2f3f | 2013-12-05 22:37:46 +0000 | [diff] [blame] | 3738 | dev_info(&adapter->pdev->dev, |
| 3739 | "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3740 | phydev->drv->name, dev_name(&phydev->dev)); |
| 3741 | |
| 3742 | return 0; |
| 3743 | } |
| 3744 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 3745 | /* et131x_adapter_init |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3746 | * |
| 3747 | * Initialize the data structures for the et131x_adapter object and link |
| 3748 | * them together with the platform provided device structures. |
| 3749 | */ |
| 3750 | static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev, |
Mark Einon | 12a2f3f | 2013-12-05 22:37:46 +0000 | [diff] [blame] | 3751 | struct pci_dev *pdev) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3752 | { |
| 3753 | static const u8 default_mac[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 }; |
| 3754 | |
| 3755 | struct et131x_adapter *adapter; |
| 3756 | |
| 3757 | /* Allocate private adapter struct and copy in relevant information */ |
| 3758 | adapter = netdev_priv(netdev); |
| 3759 | adapter->pdev = pci_dev_get(pdev); |
| 3760 | adapter->netdev = netdev; |
| 3761 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3762 | /* Initialize spinlocks here */ |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3763 | spin_lock_init(&adapter->tcb_send_qlock); |
| 3764 | spin_lock_init(&adapter->tcb_ready_qlock); |
| 3765 | spin_lock_init(&adapter->send_hw_lock); |
| 3766 | spin_lock_init(&adapter->rcv_lock); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3767 | spin_lock_init(&adapter->fbr_lock); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3768 | |
| 3769 | adapter->registry_jumbo_packet = 1514; /* 1514-9216 */ |
| 3770 | |
| 3771 | /* Set the MAC address to a default */ |
| 3772 | memcpy(adapter->addr, default_mac, ETH_ALEN); |
| 3773 | |
| 3774 | return adapter; |
| 3775 | } |
| 3776 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 3777 | /* et131x_pci_remove |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3778 | * |
| 3779 | * Registered in the pci_driver structure, this function is called when the |
| 3780 | * PCI subsystem detects that a PCI device which matches the information |
| 3781 | * contained in the pci_device_id table has been removed. |
| 3782 | */ |
Bill Pemberton | 596c5dd | 2012-11-19 13:26:57 -0500 | [diff] [blame] | 3783 | static void et131x_pci_remove(struct pci_dev *pdev) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3784 | { |
| 3785 | struct net_device *netdev = pci_get_drvdata(pdev); |
| 3786 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 3787 | |
| 3788 | unregister_netdev(netdev); |
Francois Romieu | fa9f0a6 | 2011-10-23 19:11:35 +0200 | [diff] [blame] | 3789 | phy_disconnect(adapter->phydev); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3790 | mdiobus_unregister(adapter->mii_bus); |
Devendra Naga | ddd4bd3 | 2013-04-10 12:34:00 +0530 | [diff] [blame] | 3791 | cancel_work_sync(&adapter->task); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3792 | kfree(adapter->mii_bus->irq); |
| 3793 | mdiobus_free(adapter->mii_bus); |
| 3794 | |
| 3795 | et131x_adapter_memory_free(adapter); |
| 3796 | iounmap(adapter->regs); |
| 3797 | pci_dev_put(pdev); |
| 3798 | |
| 3799 | free_netdev(netdev); |
| 3800 | pci_release_regions(pdev); |
| 3801 | pci_disable_device(pdev); |
| 3802 | } |
| 3803 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 3804 | /* et131x_up - Bring up a device for use. */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 3805 | static void et131x_up(struct net_device *netdev) |
Mark Einon | a4d444b | 2011-10-23 10:22:50 +0100 | [diff] [blame] | 3806 | { |
| 3807 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 3808 | |
| 3809 | et131x_enable_txrx(netdev); |
| 3810 | phy_start(adapter->phydev); |
| 3811 | } |
| 3812 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 3813 | /* et131x_down - Bring down the device */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 3814 | static void et131x_down(struct net_device *netdev) |
Mark Einon | a4d444b | 2011-10-23 10:22:50 +0100 | [diff] [blame] | 3815 | { |
| 3816 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 3817 | |
| 3818 | /* Save the timestamp for the TX watchdog, prevent a timeout */ |
| 3819 | netdev->trans_start = jiffies; |
| 3820 | |
| 3821 | phy_stop(adapter->phydev); |
| 3822 | et131x_disable_txrx(netdev); |
| 3823 | } |
| 3824 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3825 | #ifdef CONFIG_PM_SLEEP |
| 3826 | static int et131x_suspend(struct device *dev) |
| 3827 | { |
| 3828 | struct pci_dev *pdev = to_pci_dev(dev); |
| 3829 | struct net_device *netdev = pci_get_drvdata(pdev); |
| 3830 | |
| 3831 | if (netif_running(netdev)) { |
| 3832 | netif_device_detach(netdev); |
| 3833 | et131x_down(netdev); |
| 3834 | pci_save_state(pdev); |
| 3835 | } |
| 3836 | |
| 3837 | return 0; |
| 3838 | } |
| 3839 | |
| 3840 | static int et131x_resume(struct device *dev) |
| 3841 | { |
| 3842 | struct pci_dev *pdev = to_pci_dev(dev); |
| 3843 | struct net_device *netdev = pci_get_drvdata(pdev); |
| 3844 | |
| 3845 | if (netif_running(netdev)) { |
| 3846 | pci_restore_state(pdev); |
| 3847 | et131x_up(netdev); |
| 3848 | netif_device_attach(netdev); |
| 3849 | } |
| 3850 | |
| 3851 | return 0; |
| 3852 | } |
| 3853 | |
Mark Einon | 2e9ff8d | 2011-11-04 17:58:02 +0000 | [diff] [blame] | 3854 | static SIMPLE_DEV_PM_OPS(et131x_pm_ops, et131x_suspend, et131x_resume); |
| 3855 | #define ET131X_PM_OPS (&et131x_pm_ops) |
| 3856 | #else |
| 3857 | #define ET131X_PM_OPS NULL |
| 3858 | #endif |
| 3859 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 3860 | /* et131x_isr - The Interrupt Service Routine for the driver. |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3861 | * @irq: the IRQ on which the interrupt was received. |
| 3862 | * @dev_id: device-specific info (here a pointer to a net_device struct) |
| 3863 | * |
| 3864 | * Returns a value indicating if the interrupt was handled. |
| 3865 | */ |
Mark Einon | c0594ee | 2013-01-22 17:10:10 +0000 | [diff] [blame] | 3866 | static irqreturn_t et131x_isr(int irq, void *dev_id) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3867 | { |
| 3868 | bool handled = true; |
| 3869 | struct net_device *netdev = (struct net_device *)dev_id; |
ZHAO Gang | 8f7fa96 | 2013-12-08 11:01:06 +0800 | [diff] [blame] | 3870 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 3871 | struct rx_ring *rx_ring = &adapter->rx_ring; |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3872 | struct tx_ring *tx_ring = &adapter->tx_ring; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3873 | u32 status; |
| 3874 | |
| 3875 | if (!netif_device_present(netdev)) { |
| 3876 | handled = false; |
| 3877 | goto out; |
| 3878 | } |
| 3879 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3880 | /* If the adapter is in low power state, then it should not |
| 3881 | * recognize any interrupt |
| 3882 | */ |
| 3883 | |
| 3884 | /* Disable Device Interrupts */ |
| 3885 | et131x_disable_interrupts(adapter); |
| 3886 | |
| 3887 | /* Get a copy of the value in the interrupt status register |
| 3888 | * so we can process the interrupting section |
| 3889 | */ |
| 3890 | status = readl(&adapter->regs->global.int_status); |
| 3891 | |
| 3892 | if (adapter->flowcontrol == FLOW_TXONLY || |
| 3893 | adapter->flowcontrol == FLOW_BOTH) { |
| 3894 | status &= ~INT_MASK_ENABLE; |
| 3895 | } else { |
| 3896 | status &= ~INT_MASK_ENABLE_NO_FLOW; |
| 3897 | } |
| 3898 | |
| 3899 | /* Make sure this is our interrupt */ |
| 3900 | if (!status) { |
| 3901 | handled = false; |
| 3902 | et131x_enable_interrupts(adapter); |
| 3903 | goto out; |
| 3904 | } |
| 3905 | |
| 3906 | /* This is our interrupt, so process accordingly */ |
| 3907 | |
| 3908 | if (status & ET_INTR_WATCHDOG) { |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 3909 | struct tcb *tcb = tx_ring->send_head; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3910 | |
| 3911 | if (tcb) |
| 3912 | if (++tcb->stale > 1) |
| 3913 | status |= ET_INTR_TXDMA_ISR; |
| 3914 | |
ZHAO Gang | 8f7fa96 | 2013-12-08 11:01:06 +0800 | [diff] [blame] | 3915 | if (rx_ring->unfinished_receives) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3916 | status |= ET_INTR_RXDMA_XFR_DONE; |
| 3917 | else if (tcb == NULL) |
| 3918 | writel(0, &adapter->regs->global.watchdog_timer); |
| 3919 | |
| 3920 | status &= ~ET_INTR_WATCHDOG; |
| 3921 | } |
| 3922 | |
Mark Einon | 12a2f3f | 2013-12-05 22:37:46 +0000 | [diff] [blame] | 3923 | if (!status) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3924 | /* This interrupt has in some way been "handled" by |
| 3925 | * the ISR. Either it was a spurious Rx interrupt, or |
| 3926 | * it was a Tx interrupt that has been filtered by |
| 3927 | * the ISR. |
| 3928 | */ |
| 3929 | et131x_enable_interrupts(adapter); |
| 3930 | goto out; |
| 3931 | } |
| 3932 | |
| 3933 | /* We need to save the interrupt status value for use in our |
| 3934 | * DPC. We will clear the software copy of that in that |
| 3935 | * routine. |
| 3936 | */ |
| 3937 | adapter->stats.interrupt_status = status; |
| 3938 | |
| 3939 | /* Schedule the ISR handler as a bottom-half task in the |
| 3940 | * kernel's tq_immediate queue, and mark the queue for |
| 3941 | * execution |
| 3942 | */ |
| 3943 | schedule_work(&adapter->task); |
| 3944 | out: |
| 3945 | return IRQ_RETVAL(handled); |
| 3946 | } |
| 3947 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 3948 | /* et131x_isr_handler - The ISR handler |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3949 | * |
| 3950 | * scheduled to run in a deferred context by the ISR. This is where the ISR's |
| 3951 | * work actually gets done. |
| 3952 | */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 3953 | static void et131x_isr_handler(struct work_struct *work) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3954 | { |
| 3955 | struct et131x_adapter *adapter = |
| 3956 | container_of(work, struct et131x_adapter, task); |
| 3957 | u32 status = adapter->stats.interrupt_status; |
| 3958 | struct address_map __iomem *iomem = adapter->regs; |
| 3959 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 3960 | /* These first two are by far the most common. Once handled, we clear |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3961 | * their two bits in the status word. If the word is now zero, we |
| 3962 | * exit. |
| 3963 | */ |
| 3964 | /* Handle all the completed Transmit interrupts */ |
| 3965 | if (status & ET_INTR_TXDMA_ISR) |
| 3966 | et131x_handle_send_interrupt(adapter); |
| 3967 | |
| 3968 | /* Handle all the completed Receives interrupts */ |
| 3969 | if (status & ET_INTR_RXDMA_XFR_DONE) |
| 3970 | et131x_handle_recv_interrupt(adapter); |
| 3971 | |
Mark Einon | 6ff6280 | 2013-12-05 22:55:49 +0000 | [diff] [blame] | 3972 | status &= ~(ET_INTR_TXDMA_ERR | ET_INTR_RXDMA_XFR_DONE); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3973 | |
Mark Einon | 15ffde4 | 2012-11-16 10:47:37 +0000 | [diff] [blame] | 3974 | if (!status) |
| 3975 | goto out; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3976 | |
Mark Einon | 15ffde4 | 2012-11-16 10:47:37 +0000 | [diff] [blame] | 3977 | /* Handle the TXDMA Error interrupt */ |
| 3978 | if (status & ET_INTR_TXDMA_ERR) { |
Mark Einon | 15ffde4 | 2012-11-16 10:47:37 +0000 | [diff] [blame] | 3979 | /* Following read also clears the register (COR) */ |
Mark Einon | 12a2f3f | 2013-12-05 22:37:46 +0000 | [diff] [blame] | 3980 | u32 txdma_err = readl(&iomem->txdma.tx_dma_error); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3981 | |
Mark Einon | 15ffde4 | 2012-11-16 10:47:37 +0000 | [diff] [blame] | 3982 | dev_warn(&adapter->pdev->dev, |
| 3983 | "TXDMA_ERR interrupt, error = %d\n", |
| 3984 | txdma_err); |
| 3985 | } |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3986 | |
Mark Einon | 15ffde4 | 2012-11-16 10:47:37 +0000 | [diff] [blame] | 3987 | /* Handle Free Buffer Ring 0 and 1 Low interrupt */ |
| 3988 | if (status & (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) { |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 3989 | /* This indicates the number of unused buffers in RXDMA free |
Mark Einon | 15ffde4 | 2012-11-16 10:47:37 +0000 | [diff] [blame] | 3990 | * buffer ring 0 is <= the limit you programmed. Free buffer |
| 3991 | * resources need to be returned. Free buffers are consumed as |
| 3992 | * packets are passed from the network to the host. The host |
| 3993 | * becomes aware of the packets from the contents of the packet |
| 3994 | * status ring. This ring is queried when the packet done |
| 3995 | * interrupt occurs. Packets are then passed to the OS. When |
| 3996 | * the OS is done with the packets the resources can be |
| 3997 | * returned to the ET1310 for re-use. This interrupt is one |
| 3998 | * method of returning resources. |
| 3999 | */ |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4000 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 4001 | /* If the user has flow control on, then we will |
Mark Einon | 15ffde4 | 2012-11-16 10:47:37 +0000 | [diff] [blame] | 4002 | * send a pause packet, otherwise just exit |
| 4003 | */ |
| 4004 | if (adapter->flowcontrol == FLOW_TXONLY || |
| 4005 | adapter->flowcontrol == FLOW_BOTH) { |
| 4006 | u32 pm_csr; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4007 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 4008 | /* Tell the device to send a pause packet via the back |
Mark Einon | 15ffde4 | 2012-11-16 10:47:37 +0000 | [diff] [blame] | 4009 | * pressure register (bp req and bp xon/xoff) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4010 | */ |
Mark Einon | 15ffde4 | 2012-11-16 10:47:37 +0000 | [diff] [blame] | 4011 | pm_csr = readl(&iomem->global.pm_csr); |
| 4012 | if (!et1310_in_phy_coma(adapter)) |
| 4013 | writel(3, &iomem->txmac.bp_ctrl); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4014 | } |
| 4015 | } |
Mark Einon | 15ffde4 | 2012-11-16 10:47:37 +0000 | [diff] [blame] | 4016 | |
| 4017 | /* Handle Packet Status Ring Low Interrupt */ |
| 4018 | if (status & ET_INTR_RXDMA_STAT_LOW) { |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 4019 | /* Same idea as with the two Free Buffer Rings. Packets going |
Mark Einon | 15ffde4 | 2012-11-16 10:47:37 +0000 | [diff] [blame] | 4020 | * from the network to the host each consume a free buffer |
| 4021 | * resource and a packet status resource. These resoures are |
| 4022 | * passed to the OS. When the OS is done with the resources, |
| 4023 | * they need to be returned to the ET1310. This is one method |
| 4024 | * of returning the resources. |
| 4025 | */ |
| 4026 | } |
| 4027 | |
| 4028 | /* Handle RXDMA Error Interrupt */ |
| 4029 | if (status & ET_INTR_RXDMA_ERR) { |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 4030 | /* The rxdma_error interrupt is sent when a time-out on a |
Mark Einon | 15ffde4 | 2012-11-16 10:47:37 +0000 | [diff] [blame] | 4031 | * request issued by the JAGCore has occurred or a completion is |
| 4032 | * returned with an un-successful status. In both cases the |
| 4033 | * request is considered complete. The JAGCore will |
| 4034 | * automatically re-try the request in question. Normally |
| 4035 | * information on events like these are sent to the host using |
| 4036 | * the "Advanced Error Reporting" capability. This interrupt is |
| 4037 | * another way of getting similar information. The only thing |
| 4038 | * required is to clear the interrupt by reading the ISR in the |
| 4039 | * global resources. The JAGCore will do a re-try on the |
| 4040 | * request. Normally you should never see this interrupt. If |
| 4041 | * you start to see this interrupt occurring frequently then |
| 4042 | * something bad has occurred. A reset might be the thing to do. |
| 4043 | */ |
| 4044 | /* TRAP();*/ |
| 4045 | |
| 4046 | dev_warn(&adapter->pdev->dev, |
| 4047 | "RxDMA_ERR interrupt, error %x\n", |
| 4048 | readl(&iomem->txmac.tx_test)); |
| 4049 | } |
| 4050 | |
| 4051 | /* Handle the Wake on LAN Event */ |
| 4052 | if (status & ET_INTR_WOL) { |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 4053 | /* This is a secondary interrupt for wake on LAN. The driver |
Mark Einon | 15ffde4 | 2012-11-16 10:47:37 +0000 | [diff] [blame] | 4054 | * should never see this, if it does, something serious is |
| 4055 | * wrong. We will TRAP the message when we are in DBG mode, |
| 4056 | * otherwise we will ignore it. |
| 4057 | */ |
| 4058 | dev_err(&adapter->pdev->dev, "WAKE_ON_LAN interrupt\n"); |
| 4059 | } |
| 4060 | |
| 4061 | /* Let's move on to the TxMac */ |
| 4062 | if (status & ET_INTR_TXMAC) { |
| 4063 | u32 err = readl(&iomem->txmac.err); |
| 4064 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 4065 | /* When any of the errors occur and TXMAC generates an |
Mark Einon | 15ffde4 | 2012-11-16 10:47:37 +0000 | [diff] [blame] | 4066 | * interrupt to report these errors, it usually means that |
| 4067 | * TXMAC has detected an error in the data stream retrieved |
| 4068 | * from the on-chip Tx Q. All of these errors are catastrophic |
| 4069 | * and TXMAC won't be able to recover data when these errors |
| 4070 | * occur. In a nutshell, the whole Tx path will have to be reset |
| 4071 | * and re-configured afterwards. |
| 4072 | */ |
| 4073 | dev_warn(&adapter->pdev->dev, |
| 4074 | "TXMAC interrupt, error 0x%08x\n", |
| 4075 | err); |
| 4076 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 4077 | /* If we are debugging, we want to see this error, otherwise we |
Mark Einon | 15ffde4 | 2012-11-16 10:47:37 +0000 | [diff] [blame] | 4078 | * just want the device to be reset and continue |
| 4079 | */ |
| 4080 | } |
| 4081 | |
| 4082 | /* Handle RXMAC Interrupt */ |
| 4083 | if (status & ET_INTR_RXMAC) { |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 4084 | /* These interrupts are catastrophic to the device, what we need |
Mark Einon | 15ffde4 | 2012-11-16 10:47:37 +0000 | [diff] [blame] | 4085 | * to do is disable the interrupts and set the flag to cause us |
| 4086 | * to reset so we can solve this issue. |
| 4087 | */ |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 4088 | /* MP_SET_FLAG( adapter, FMP_ADAPTER_HARDWARE_ERROR); */ |
Mark Einon | 15ffde4 | 2012-11-16 10:47:37 +0000 | [diff] [blame] | 4089 | |
| 4090 | dev_warn(&adapter->pdev->dev, |
| 4091 | "RXMAC interrupt, error 0x%08x. Requesting reset\n", |
| 4092 | readl(&iomem->rxmac.err_reg)); |
| 4093 | |
| 4094 | dev_warn(&adapter->pdev->dev, |
| 4095 | "Enable 0x%08x, Diag 0x%08x\n", |
| 4096 | readl(&iomem->rxmac.ctrl), |
| 4097 | readl(&iomem->rxmac.rxq_diag)); |
| 4098 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 4099 | /* If we are debugging, we want to see this error, otherwise we |
Mark Einon | 15ffde4 | 2012-11-16 10:47:37 +0000 | [diff] [blame] | 4100 | * just want the device to be reset and continue |
| 4101 | */ |
| 4102 | } |
| 4103 | |
| 4104 | /* Handle MAC_STAT Interrupt */ |
| 4105 | if (status & ET_INTR_MAC_STAT) { |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 4106 | /* This means at least one of the un-masked counters in the |
Mark Einon | 15ffde4 | 2012-11-16 10:47:37 +0000 | [diff] [blame] | 4107 | * MAC_STAT block has rolled over. Use this to maintain the top, |
| 4108 | * software managed bits of the counter(s). |
| 4109 | */ |
| 4110 | et1310_handle_macstat_interrupt(adapter); |
| 4111 | } |
| 4112 | |
| 4113 | /* Handle SLV Timeout Interrupt */ |
| 4114 | if (status & ET_INTR_SLV_TIMEOUT) { |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 4115 | /* This means a timeout has occurred on a read or write request |
Mark Einon | 15ffde4 | 2012-11-16 10:47:37 +0000 | [diff] [blame] | 4116 | * to one of the JAGCore registers. The Global Resources block |
| 4117 | * has terminated the request and on a read request, returned a |
| 4118 | * "fake" value. The most likely reasons are: Bad Address or the |
| 4119 | * addressed module is in a power-down state and can't respond. |
| 4120 | */ |
| 4121 | } |
| 4122 | out: |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4123 | et131x_enable_interrupts(adapter); |
| 4124 | } |
| 4125 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 4126 | /* et131x_stats - Return the current device statistics */ |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4127 | static struct net_device_stats *et131x_stats(struct net_device *netdev) |
| 4128 | { |
| 4129 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 4130 | struct net_device_stats *stats = &adapter->net_stats; |
| 4131 | struct ce_stats *devstat = &adapter->stats; |
| 4132 | |
| 4133 | stats->rx_errors = devstat->rx_length_errs + |
| 4134 | devstat->rx_align_errs + |
| 4135 | devstat->rx_crc_errs + |
| 4136 | devstat->rx_code_violations + |
| 4137 | devstat->rx_other_errs; |
| 4138 | stats->tx_errors = devstat->tx_max_pkt_errs; |
| 4139 | stats->multicast = devstat->multicast_pkts_rcvd; |
| 4140 | stats->collisions = devstat->tx_collisions; |
| 4141 | |
| 4142 | stats->rx_length_errors = devstat->rx_length_errs; |
| 4143 | stats->rx_over_errors = devstat->rx_overflows; |
| 4144 | stats->rx_crc_errors = devstat->rx_crc_errs; |
| 4145 | |
| 4146 | /* NOTE: These stats don't have corresponding values in CE_STATS, |
| 4147 | * so we're going to have to update these directly from within the |
| 4148 | * TX/RX code |
| 4149 | */ |
| 4150 | /* stats->rx_bytes = 20; devstat->; */ |
| 4151 | /* stats->tx_bytes = 20; devstat->; */ |
| 4152 | /* stats->rx_dropped = devstat->; */ |
| 4153 | /* stats->tx_dropped = devstat->; */ |
| 4154 | |
| 4155 | /* NOTE: Not used, can't find analogous statistics */ |
| 4156 | /* stats->rx_frame_errors = devstat->; */ |
| 4157 | /* stats->rx_fifo_errors = devstat->; */ |
| 4158 | /* stats->rx_missed_errors = devstat->; */ |
| 4159 | |
| 4160 | /* stats->tx_aborted_errors = devstat->; */ |
| 4161 | /* stats->tx_carrier_errors = devstat->; */ |
| 4162 | /* stats->tx_fifo_errors = devstat->; */ |
| 4163 | /* stats->tx_heartbeat_errors = devstat->; */ |
| 4164 | /* stats->tx_window_errors = devstat->; */ |
| 4165 | return stats; |
| 4166 | } |
| 4167 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 4168 | /* et131x_open - Open the device for use. */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 4169 | static int et131x_open(struct net_device *netdev) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4170 | { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4171 | struct et131x_adapter *adapter = netdev_priv(netdev); |
Francois Romieu | 5f3eb88 | 2011-10-23 19:12:01 +0200 | [diff] [blame] | 4172 | struct pci_dev *pdev = adapter->pdev; |
| 4173 | unsigned int irq = pdev->irq; |
| 4174 | int result; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4175 | |
| 4176 | /* Start the timer to track NIC errors */ |
| 4177 | init_timer(&adapter->error_timer); |
| 4178 | adapter->error_timer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000; |
| 4179 | adapter->error_timer.function = et131x_error_timer_handler; |
| 4180 | adapter->error_timer.data = (unsigned long)adapter; |
| 4181 | add_timer(&adapter->error_timer); |
| 4182 | |
joseph daniel | bf3313a | 2012-05-01 00:30:34 +0600 | [diff] [blame] | 4183 | result = request_irq(irq, et131x_isr, |
| 4184 | IRQF_SHARED, netdev->name, netdev); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4185 | if (result) { |
Francois Romieu | 5f3eb88 | 2011-10-23 19:12:01 +0200 | [diff] [blame] | 4186 | dev_err(&pdev->dev, "could not register IRQ %d\n", irq); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4187 | return result; |
| 4188 | } |
| 4189 | |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 4190 | adapter->flags |= FMP_ADAPTER_INTERRUPT_IN_USE; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4191 | |
| 4192 | et131x_up(netdev); |
| 4193 | |
| 4194 | return result; |
| 4195 | } |
| 4196 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 4197 | /* et131x_close - Close the device */ |
Francois Romieu | eb7a6ca | 2011-10-23 19:11:02 +0200 | [diff] [blame] | 4198 | static int et131x_close(struct net_device *netdev) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4199 | { |
| 4200 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 4201 | |
| 4202 | et131x_down(netdev); |
| 4203 | |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 4204 | adapter->flags &= ~FMP_ADAPTER_INTERRUPT_IN_USE; |
Francois Romieu | 5f3eb88 | 2011-10-23 19:12:01 +0200 | [diff] [blame] | 4205 | free_irq(adapter->pdev->irq, netdev); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4206 | |
| 4207 | /* Stop the error timer */ |
| 4208 | return del_timer_sync(&adapter->error_timer); |
| 4209 | } |
| 4210 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 4211 | /* et131x_ioctl - The I/O Control handler for the driver |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4212 | * @netdev: device on which the control request is being made |
| 4213 | * @reqbuf: a pointer to the IOCTL request buffer |
| 4214 | * @cmd: the IOCTL command code |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4215 | */ |
Mark Einon | 09a3fc2 | 2011-10-23 10:22:53 +0100 | [diff] [blame] | 4216 | static int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf, |
| 4217 | int cmd) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4218 | { |
| 4219 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 4220 | |
| 4221 | if (!adapter->phydev) |
| 4222 | return -EINVAL; |
| 4223 | |
| 4224 | return phy_mii_ioctl(adapter->phydev, reqbuf, cmd); |
| 4225 | } |
| 4226 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 4227 | /* et131x_set_packet_filter - Configures the Rx Packet filtering on the device |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4228 | * @adapter: pointer to our private adapter structure |
| 4229 | * |
| 4230 | * FIXME: lot of dups with MAC code |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4231 | */ |
| 4232 | static int et131x_set_packet_filter(struct et131x_adapter *adapter) |
| 4233 | { |
Francois Romieu | 834d0ee | 2011-10-23 19:11:19 +0200 | [diff] [blame] | 4234 | int filter = adapter->packet_filter; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4235 | int status = 0; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4236 | u32 ctrl; |
| 4237 | u32 pf_ctrl; |
| 4238 | |
| 4239 | ctrl = readl(&adapter->regs->rxmac.ctrl); |
| 4240 | pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl); |
| 4241 | |
| 4242 | /* Default to disabled packet filtering. Enable it in the individual |
| 4243 | * case statements that require the device to filter something |
| 4244 | */ |
| 4245 | ctrl |= 0x04; |
| 4246 | |
| 4247 | /* Set us to be in promiscuous mode so we receive everything, this |
| 4248 | * is also true when we get a packet filter of 0 |
| 4249 | */ |
| 4250 | if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0) |
| 4251 | pf_ctrl &= ~7; /* Clear filter bits */ |
| 4252 | else { |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 4253 | /* Set us up with Multicast packet filtering. Three cases are |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4254 | * possible - (1) we have a multi-cast list, (2) we receive ALL |
| 4255 | * multicast entries or (3) we receive none. |
| 4256 | */ |
| 4257 | if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST) |
| 4258 | pf_ctrl &= ~2; /* Multicast filter bit */ |
| 4259 | else { |
| 4260 | et1310_setup_device_for_multicast(adapter); |
| 4261 | pf_ctrl |= 2; |
| 4262 | ctrl &= ~0x04; |
| 4263 | } |
| 4264 | |
| 4265 | /* Set us up with Unicast packet filtering */ |
| 4266 | if (filter & ET131X_PACKET_TYPE_DIRECTED) { |
| 4267 | et1310_setup_device_for_unicast(adapter); |
| 4268 | pf_ctrl |= 4; |
| 4269 | ctrl &= ~0x04; |
| 4270 | } |
| 4271 | |
| 4272 | /* Set us up with Broadcast packet filtering */ |
| 4273 | if (filter & ET131X_PACKET_TYPE_BROADCAST) { |
| 4274 | pf_ctrl |= 1; /* Broadcast filter bit */ |
| 4275 | ctrl &= ~0x04; |
| 4276 | } else |
| 4277 | pf_ctrl &= ~1; |
| 4278 | |
| 4279 | /* Setup the receive mac configuration registers - Packet |
| 4280 | * Filter control + the enable / disable for packet filter |
| 4281 | * in the control reg. |
| 4282 | */ |
| 4283 | writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl); |
| 4284 | writel(ctrl, &adapter->regs->rxmac.ctrl); |
| 4285 | } |
| 4286 | return status; |
| 4287 | } |
| 4288 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 4289 | /* et131x_multicast - The handler to configure multicasting on the interface */ |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4290 | static void et131x_multicast(struct net_device *netdev) |
| 4291 | { |
| 4292 | struct et131x_adapter *adapter = netdev_priv(netdev); |
Francois Romieu | 834d0ee | 2011-10-23 19:11:19 +0200 | [diff] [blame] | 4293 | int packet_filter; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4294 | struct netdev_hw_addr *ha; |
| 4295 | int i; |
| 4296 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4297 | /* Before we modify the platform-independent filter flags, store them |
| 4298 | * locally. This allows us to determine if anything's changed and if |
| 4299 | * we even need to bother the hardware |
| 4300 | */ |
| 4301 | packet_filter = adapter->packet_filter; |
| 4302 | |
| 4303 | /* Clear the 'multicast' flag locally; because we only have a single |
| 4304 | * flag to check multicast, and multiple multicast addresses can be |
| 4305 | * set, this is the easiest way to determine if more than one |
| 4306 | * multicast address is being set. |
| 4307 | */ |
| 4308 | packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST; |
| 4309 | |
| 4310 | /* Check the net_device flags and set the device independent flags |
| 4311 | * accordingly |
| 4312 | */ |
| 4313 | |
| 4314 | if (netdev->flags & IFF_PROMISC) |
| 4315 | adapter->packet_filter |= ET131X_PACKET_TYPE_PROMISCUOUS; |
| 4316 | else |
| 4317 | adapter->packet_filter &= ~ET131X_PACKET_TYPE_PROMISCUOUS; |
| 4318 | |
| 4319 | if (netdev->flags & IFF_ALLMULTI) |
| 4320 | adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST; |
| 4321 | |
| 4322 | if (netdev_mc_count(netdev) > NIC_MAX_MCAST_LIST) |
| 4323 | adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST; |
| 4324 | |
| 4325 | if (netdev_mc_count(netdev) < 1) { |
| 4326 | adapter->packet_filter &= ~ET131X_PACKET_TYPE_ALL_MULTICAST; |
| 4327 | adapter->packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST; |
| 4328 | } else |
| 4329 | adapter->packet_filter |= ET131X_PACKET_TYPE_MULTICAST; |
| 4330 | |
| 4331 | /* Set values in the private adapter struct */ |
| 4332 | i = 0; |
| 4333 | netdev_for_each_mc_addr(ha, netdev) { |
| 4334 | if (i == NIC_MAX_MCAST_LIST) |
| 4335 | break; |
| 4336 | memcpy(adapter->multicast_list[i++], ha->addr, ETH_ALEN); |
| 4337 | } |
| 4338 | adapter->multicast_addr_count = i; |
| 4339 | |
| 4340 | /* Are the new flags different from the previous ones? If not, then no |
| 4341 | * action is required |
| 4342 | * |
| 4343 | * NOTE - This block will always update the multicast_list with the |
| 4344 | * hardware, even if the addresses aren't the same. |
| 4345 | */ |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 4346 | if (packet_filter != adapter->packet_filter) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4347 | et131x_set_packet_filter(adapter); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4348 | } |
| 4349 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 4350 | /* et131x_tx - The handler to tx a packet on the device */ |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4351 | static int et131x_tx(struct sk_buff *skb, struct net_device *netdev) |
| 4352 | { |
| 4353 | int status = 0; |
Mark Einon | 06709e9 | 2011-10-20 01:18:46 +0100 | [diff] [blame] | 4354 | struct et131x_adapter *adapter = netdev_priv(netdev); |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 4355 | struct tx_ring *tx_ring = &adapter->tx_ring; |
Mark Einon | 06709e9 | 2011-10-20 01:18:46 +0100 | [diff] [blame] | 4356 | |
| 4357 | /* stop the queue if it's getting full */ |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 4358 | if (tx_ring->used >= NUM_TCB - 1 && !netif_queue_stopped(netdev)) |
Mark Einon | 06709e9 | 2011-10-20 01:18:46 +0100 | [diff] [blame] | 4359 | netif_stop_queue(netdev); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4360 | |
| 4361 | /* Save the timestamp for the TX timeout watchdog */ |
| 4362 | netdev->trans_start = jiffies; |
| 4363 | |
| 4364 | /* Call the device-specific data Tx routine */ |
| 4365 | status = et131x_send_packets(skb, netdev); |
| 4366 | |
| 4367 | /* Check status and manage the netif queue if necessary */ |
| 4368 | if (status != 0) { |
Mark Einon | 09a3fc2 | 2011-10-23 10:22:53 +0100 | [diff] [blame] | 4369 | if (status == -ENOMEM) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4370 | status = NETDEV_TX_BUSY; |
Mark Einon | 09a3fc2 | 2011-10-23 10:22:53 +0100 | [diff] [blame] | 4371 | else |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4372 | status = NETDEV_TX_OK; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4373 | } |
| 4374 | return status; |
| 4375 | } |
| 4376 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 4377 | /* et131x_tx_timeout - Timeout handler |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4378 | * |
| 4379 | * The handler called when a Tx request times out. The timeout period is |
| 4380 | * specified by the 'tx_timeo" element in the net_device structure (see |
| 4381 | * et131x_alloc_device() to see how this value is set). |
| 4382 | */ |
| 4383 | static void et131x_tx_timeout(struct net_device *netdev) |
| 4384 | { |
| 4385 | struct et131x_adapter *adapter = netdev_priv(netdev); |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 4386 | struct tx_ring *tx_ring = &adapter->tx_ring; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4387 | struct tcb *tcb; |
| 4388 | unsigned long flags; |
| 4389 | |
| 4390 | /* If the device is closed, ignore the timeout */ |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 4391 | if (~(adapter->flags & FMP_ADAPTER_INTERRUPT_IN_USE)) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4392 | return; |
| 4393 | |
| 4394 | /* Any nonrecoverable hardware error? |
| 4395 | * Checks adapter->flags for any failure in phy reading |
| 4396 | */ |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 4397 | if (adapter->flags & FMP_ADAPTER_NON_RECOVER_ERROR) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4398 | return; |
| 4399 | |
| 4400 | /* Hardware failure? */ |
Mark Einon | c655dee | 2013-01-22 14:29:48 +0000 | [diff] [blame] | 4401 | if (adapter->flags & FMP_ADAPTER_HARDWARE_ERROR) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4402 | dev_err(&adapter->pdev->dev, "hardware error - reset\n"); |
| 4403 | return; |
| 4404 | } |
| 4405 | |
| 4406 | /* Is send stuck? */ |
| 4407 | spin_lock_irqsave(&adapter->tcb_send_qlock, flags); |
| 4408 | |
ZHAO Gang | 76981cf | 2013-12-08 11:01:07 +0800 | [diff] [blame] | 4409 | tcb = tx_ring->send_head; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4410 | |
| 4411 | if (tcb != NULL) { |
| 4412 | tcb->count++; |
| 4413 | |
| 4414 | if (tcb->count > NIC_SEND_HANG_THRESHOLD) { |
| 4415 | spin_unlock_irqrestore(&adapter->tcb_send_qlock, |
| 4416 | flags); |
| 4417 | |
| 4418 | dev_warn(&adapter->pdev->dev, |
| 4419 | "Send stuck - reset. tcb->WrIndex %x, flags 0x%08x\n", |
| 4420 | tcb->index, |
| 4421 | tcb->flags); |
| 4422 | |
| 4423 | adapter->net_stats.tx_errors++; |
| 4424 | |
| 4425 | /* perform reset of tx/rx */ |
| 4426 | et131x_disable_txrx(netdev); |
| 4427 | et131x_enable_txrx(netdev); |
| 4428 | return; |
| 4429 | } |
| 4430 | } |
| 4431 | |
| 4432 | spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags); |
| 4433 | } |
| 4434 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 4435 | /* et131x_change_mtu - The handler called to change the MTU for the device */ |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4436 | static int et131x_change_mtu(struct net_device *netdev, int new_mtu) |
| 4437 | { |
| 4438 | int result = 0; |
| 4439 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 4440 | |
| 4441 | /* Make sure the requested MTU is valid */ |
| 4442 | if (new_mtu < 64 || new_mtu > 9216) |
| 4443 | return -EINVAL; |
| 4444 | |
| 4445 | et131x_disable_txrx(netdev); |
| 4446 | et131x_handle_send_interrupt(adapter); |
| 4447 | et131x_handle_recv_interrupt(adapter); |
| 4448 | |
| 4449 | /* Set the new MTU */ |
| 4450 | netdev->mtu = new_mtu; |
| 4451 | |
| 4452 | /* Free Rx DMA memory */ |
| 4453 | et131x_adapter_memory_free(adapter); |
| 4454 | |
| 4455 | /* Set the config parameter for Jumbo Packet support */ |
| 4456 | adapter->registry_jumbo_packet = new_mtu + 14; |
| 4457 | et131x_soft_reset(adapter); |
| 4458 | |
| 4459 | /* Alloc and init Rx DMA memory */ |
| 4460 | result = et131x_adapter_memory_alloc(adapter); |
| 4461 | if (result != 0) { |
| 4462 | dev_warn(&adapter->pdev->dev, |
| 4463 | "Change MTU failed; couldn't re-alloc DMA memory\n"); |
| 4464 | return result; |
| 4465 | } |
| 4466 | |
| 4467 | et131x_init_send(adapter); |
| 4468 | |
| 4469 | et131x_hwaddr_init(adapter); |
| 4470 | memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN); |
| 4471 | |
| 4472 | /* Init the device with the new settings */ |
| 4473 | et131x_adapter_setup(adapter); |
| 4474 | |
| 4475 | et131x_enable_txrx(netdev); |
| 4476 | |
| 4477 | return result; |
| 4478 | } |
| 4479 | |
Mark Einon | 15ae239 | 2013-12-05 22:37:45 +0000 | [diff] [blame] | 4480 | /* et131x_set_mac_addr - handler to change the MAC address for the device */ |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4481 | static int et131x_set_mac_addr(struct net_device *netdev, void *new_mac) |
| 4482 | { |
| 4483 | int result = 0; |
| 4484 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 4485 | struct sockaddr *address = new_mac; |
| 4486 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4487 | if (adapter == NULL) |
| 4488 | return -ENODEV; |
| 4489 | |
| 4490 | /* Make sure the requested MAC is valid */ |
| 4491 | if (!is_valid_ether_addr(address->sa_data)) |
Danny Kukawka | d8aa3e2 | 2012-02-21 13:07:51 +0100 | [diff] [blame] | 4492 | return -EADDRNOTAVAIL; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4493 | |
| 4494 | et131x_disable_txrx(netdev); |
| 4495 | et131x_handle_send_interrupt(adapter); |
| 4496 | et131x_handle_recv_interrupt(adapter); |
| 4497 | |
| 4498 | /* Set the new MAC */ |
| 4499 | /* netdev->set_mac_address = &new_mac; */ |
| 4500 | |
| 4501 | memcpy(netdev->dev_addr, address->sa_data, netdev->addr_len); |
| 4502 | |
Toshiaki Yamane | e58b89d | 2012-07-19 10:34:32 +0900 | [diff] [blame] | 4503 | netdev_info(netdev, "Setting MAC address to %pM\n", |
| 4504 | netdev->dev_addr); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4505 | |
| 4506 | /* Free Rx DMA memory */ |
| 4507 | et131x_adapter_memory_free(adapter); |
| 4508 | |
| 4509 | et131x_soft_reset(adapter); |
| 4510 | |
| 4511 | /* Alloc and init Rx DMA memory */ |
| 4512 | result = et131x_adapter_memory_alloc(adapter); |
| 4513 | if (result != 0) { |
| 4514 | dev_err(&adapter->pdev->dev, |
| 4515 | "Change MAC failed; couldn't re-alloc DMA memory\n"); |
| 4516 | return result; |
| 4517 | } |
| 4518 | |
| 4519 | et131x_init_send(adapter); |
| 4520 | |
| 4521 | et131x_hwaddr_init(adapter); |
| 4522 | |
| 4523 | /* Init the device with the new settings */ |
| 4524 | et131x_adapter_setup(adapter); |
| 4525 | |
| 4526 | et131x_enable_txrx(netdev); |
| 4527 | |
| 4528 | return result; |
| 4529 | } |
| 4530 | |
| 4531 | static const struct net_device_ops et131x_netdev_ops = { |
| 4532 | .ndo_open = et131x_open, |
| 4533 | .ndo_stop = et131x_close, |
| 4534 | .ndo_start_xmit = et131x_tx, |
Linus Torvalds | aa77677 | 2011-10-26 15:39:02 +0200 | [diff] [blame] | 4535 | .ndo_set_rx_mode = et131x_multicast, |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 4536 | .ndo_tx_timeout = et131x_tx_timeout, |
| 4537 | .ndo_change_mtu = et131x_change_mtu, |
| 4538 | .ndo_set_mac_address = et131x_set_mac_addr, |
| 4539 | .ndo_validate_addr = eth_validate_addr, |
| 4540 | .ndo_get_stats = et131x_stats, |
| 4541 | .ndo_do_ioctl = et131x_ioctl, |
| 4542 | }; |
| 4543 | |
Mark Einon | 26ef102 | 2013-01-22 14:29:49 +0000 | [diff] [blame] | 4544 | /* et131x_pci_setup - Perform device initialization |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4545 | * @pdev: a pointer to the device's pci_dev structure |
| 4546 | * @ent: this device's entry in the pci_device_id table |
| 4547 | * |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4548 | * Registered in the pci_driver structure, this function is called when the |
| 4549 | * PCI subsystem finds a new PCI device which matches the information |
| 4550 | * contained in the pci_device_id table. This routine is the equivalent to |
| 4551 | * a device insertion routine. |
| 4552 | */ |
Bill Pemberton | fe5c49b | 2012-11-19 13:22:12 -0500 | [diff] [blame] | 4553 | static int et131x_pci_setup(struct pci_dev *pdev, |
Mark Einon | 12a2f3f | 2013-12-05 22:37:46 +0000 | [diff] [blame] | 4554 | const struct pci_device_id *ent) |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4555 | { |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4556 | struct net_device *netdev; |
| 4557 | struct et131x_adapter *adapter; |
Francois Romieu | fa9f0a6 | 2011-10-23 19:11:35 +0200 | [diff] [blame] | 4558 | int rc; |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4559 | int ii; |
| 4560 | |
Francois Romieu | fa9f0a6 | 2011-10-23 19:11:35 +0200 | [diff] [blame] | 4561 | rc = pci_enable_device(pdev); |
| 4562 | if (rc < 0) { |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4563 | dev_err(&pdev->dev, "pci_enable_device() failed\n"); |
Francois Romieu | fa9f0a6 | 2011-10-23 19:11:35 +0200 | [diff] [blame] | 4564 | goto out; |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4565 | } |
| 4566 | |
| 4567 | /* Perform some basic PCI checks */ |
| 4568 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { |
| 4569 | dev_err(&pdev->dev, "Can't find PCI device's base address\n"); |
Francois Romieu | fa9f0a6 | 2011-10-23 19:11:35 +0200 | [diff] [blame] | 4570 | rc = -ENODEV; |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4571 | goto err_disable; |
| 4572 | } |
| 4573 | |
Francois Romieu | fa9f0a6 | 2011-10-23 19:11:35 +0200 | [diff] [blame] | 4574 | rc = pci_request_regions(pdev, DRIVER_NAME); |
| 4575 | if (rc < 0) { |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4576 | dev_err(&pdev->dev, "Can't get PCI resources\n"); |
| 4577 | goto err_disable; |
| 4578 | } |
| 4579 | |
| 4580 | pci_set_master(pdev); |
| 4581 | |
| 4582 | /* Check the DMA addressing support of this device */ |
Russell King | e22f0e3 | 2013-06-26 23:49:11 +0100 | [diff] [blame] | 4583 | if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) && |
| 4584 | dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) { |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4585 | dev_err(&pdev->dev, "No usable DMA addressing method\n"); |
Francois Romieu | fa9f0a6 | 2011-10-23 19:11:35 +0200 | [diff] [blame] | 4586 | rc = -EIO; |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4587 | goto err_release_res; |
| 4588 | } |
| 4589 | |
| 4590 | /* Allocate netdev and private adapter structs */ |
Francois Romieu | fa9f0a6 | 2011-10-23 19:11:35 +0200 | [diff] [blame] | 4591 | netdev = alloc_etherdev(sizeof(struct et131x_adapter)); |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4592 | if (!netdev) { |
| 4593 | dev_err(&pdev->dev, "Couldn't alloc netdev struct\n"); |
Francois Romieu | fa9f0a6 | 2011-10-23 19:11:35 +0200 | [diff] [blame] | 4594 | rc = -ENOMEM; |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4595 | goto err_release_res; |
| 4596 | } |
| 4597 | |
Francois Romieu | fa9f0a6 | 2011-10-23 19:11:35 +0200 | [diff] [blame] | 4598 | netdev->watchdog_timeo = ET131X_TX_TIMEOUT; |
| 4599 | netdev->netdev_ops = &et131x_netdev_ops; |
| 4600 | |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4601 | SET_NETDEV_DEV(netdev, &pdev->dev); |
Devendra Naga | a6e28b3 | 2012-07-12 11:53:17 +0545 | [diff] [blame] | 4602 | SET_ETHTOOL_OPS(netdev, &et131x_ethtool_ops); |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4603 | |
| 4604 | adapter = et131x_adapter_init(netdev, pdev); |
| 4605 | |
Francois Romieu | fa9f0a6 | 2011-10-23 19:11:35 +0200 | [diff] [blame] | 4606 | rc = et131x_pci_init(adapter, pdev); |
| 4607 | if (rc < 0) |
| 4608 | goto err_free_dev; |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4609 | |
| 4610 | /* Map the bus-relative registers to system virtual memory */ |
| 4611 | adapter->regs = pci_ioremap_bar(pdev, 0); |
| 4612 | if (!adapter->regs) { |
| 4613 | dev_err(&pdev->dev, "Cannot map device registers\n"); |
Francois Romieu | fa9f0a6 | 2011-10-23 19:11:35 +0200 | [diff] [blame] | 4614 | rc = -ENOMEM; |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4615 | goto err_free_dev; |
| 4616 | } |
| 4617 | |
| 4618 | /* If Phy COMA mode was enabled when we went down, disable it here. */ |
| 4619 | writel(ET_PMCSR_INIT, &adapter->regs->global.pm_csr); |
| 4620 | |
| 4621 | /* Issue a global reset to the et1310 */ |
| 4622 | et131x_soft_reset(adapter); |
| 4623 | |
| 4624 | /* Disable all interrupts (paranoid) */ |
| 4625 | et131x_disable_interrupts(adapter); |
| 4626 | |
| 4627 | /* Allocate DMA memory */ |
Francois Romieu | fa9f0a6 | 2011-10-23 19:11:35 +0200 | [diff] [blame] | 4628 | rc = et131x_adapter_memory_alloc(adapter); |
| 4629 | if (rc < 0) { |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4630 | dev_err(&pdev->dev, "Could not alloc adapater memory (DMA)\n"); |
| 4631 | goto err_iounmap; |
| 4632 | } |
| 4633 | |
| 4634 | /* Init send data structures */ |
| 4635 | et131x_init_send(adapter); |
| 4636 | |
| 4637 | /* Set up the task structure for the ISR's deferred handler */ |
| 4638 | INIT_WORK(&adapter->task, et131x_isr_handler); |
| 4639 | |
| 4640 | /* Copy address into the net_device struct */ |
| 4641 | memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN); |
| 4642 | |
| 4643 | /* Init variable for counting how long we do not have link status */ |
| 4644 | adapter->boot_coma = 0; |
| 4645 | et1310_disable_phy_coma(adapter); |
| 4646 | |
Francois Romieu | fa9f0a6 | 2011-10-23 19:11:35 +0200 | [diff] [blame] | 4647 | rc = -ENOMEM; |
| 4648 | |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4649 | /* Setup the mii_bus struct */ |
| 4650 | adapter->mii_bus = mdiobus_alloc(); |
| 4651 | if (!adapter->mii_bus) { |
| 4652 | dev_err(&pdev->dev, "Alloc of mii_bus struct failed\n"); |
| 4653 | goto err_mem_free; |
| 4654 | } |
| 4655 | |
| 4656 | adapter->mii_bus->name = "et131x_eth_mii"; |
| 4657 | snprintf(adapter->mii_bus->id, MII_BUS_ID_SIZE, "%x", |
| 4658 | (adapter->pdev->bus->number << 8) | adapter->pdev->devfn); |
| 4659 | adapter->mii_bus->priv = netdev; |
| 4660 | adapter->mii_bus->read = et131x_mdio_read; |
| 4661 | adapter->mii_bus->write = et131x_mdio_write; |
| 4662 | adapter->mii_bus->reset = et131x_mdio_reset; |
Joe Perches | 78110bb | 2013-02-11 09:41:29 -0800 | [diff] [blame] | 4663 | adapter->mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), |
| 4664 | GFP_KERNEL); |
| 4665 | if (!adapter->mii_bus->irq) |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4666 | goto err_mdio_free; |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4667 | |
| 4668 | for (ii = 0; ii < PHY_MAX_ADDR; ii++) |
| 4669 | adapter->mii_bus->irq[ii] = PHY_POLL; |
| 4670 | |
Francois Romieu | fa9f0a6 | 2011-10-23 19:11:35 +0200 | [diff] [blame] | 4671 | rc = mdiobus_register(adapter->mii_bus); |
| 4672 | if (rc < 0) { |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4673 | dev_err(&pdev->dev, "failed to register MII bus\n"); |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4674 | goto err_mdio_free_irq; |
| 4675 | } |
| 4676 | |
Francois Romieu | fa9f0a6 | 2011-10-23 19:11:35 +0200 | [diff] [blame] | 4677 | rc = et131x_mii_probe(netdev); |
| 4678 | if (rc < 0) { |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4679 | dev_err(&pdev->dev, "failed to probe MII bus\n"); |
| 4680 | goto err_mdio_unregister; |
| 4681 | } |
| 4682 | |
| 4683 | /* Setup et1310 as per the documentation */ |
| 4684 | et131x_adapter_setup(adapter); |
| 4685 | |
| 4686 | /* We can enable interrupts now |
| 4687 | * |
| 4688 | * NOTE - Because registration of interrupt handler is done in the |
| 4689 | * device's open(), defer enabling device interrupts to that |
| 4690 | * point |
| 4691 | */ |
| 4692 | |
| 4693 | /* Register the net_device struct with the Linux network layer */ |
Francois Romieu | fa9f0a6 | 2011-10-23 19:11:35 +0200 | [diff] [blame] | 4694 | rc = register_netdev(netdev); |
| 4695 | if (rc < 0) { |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4696 | dev_err(&pdev->dev, "register_netdev() failed\n"); |
Francois Romieu | fa9f0a6 | 2011-10-23 19:11:35 +0200 | [diff] [blame] | 4697 | goto err_phy_disconnect; |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4698 | } |
| 4699 | |
| 4700 | /* Register the net_device struct with the PCI subsystem. Save a copy |
| 4701 | * of the PCI config space for this device now that the device has |
| 4702 | * been initialized, just in case it needs to be quickly restored. |
| 4703 | */ |
| 4704 | pci_set_drvdata(pdev, netdev); |
Francois Romieu | fa9f0a6 | 2011-10-23 19:11:35 +0200 | [diff] [blame] | 4705 | out: |
| 4706 | return rc; |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4707 | |
Francois Romieu | fa9f0a6 | 2011-10-23 19:11:35 +0200 | [diff] [blame] | 4708 | err_phy_disconnect: |
| 4709 | phy_disconnect(adapter->phydev); |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4710 | err_mdio_unregister: |
| 4711 | mdiobus_unregister(adapter->mii_bus); |
| 4712 | err_mdio_free_irq: |
| 4713 | kfree(adapter->mii_bus->irq); |
| 4714 | err_mdio_free: |
| 4715 | mdiobus_free(adapter->mii_bus); |
| 4716 | err_mem_free: |
| 4717 | et131x_adapter_memory_free(adapter); |
| 4718 | err_iounmap: |
| 4719 | iounmap(adapter->regs); |
| 4720 | err_free_dev: |
| 4721 | pci_dev_put(pdev); |
| 4722 | free_netdev(netdev); |
| 4723 | err_release_res: |
| 4724 | pci_release_regions(pdev); |
| 4725 | err_disable: |
| 4726 | pci_disable_device(pdev); |
Francois Romieu | fa9f0a6 | 2011-10-23 19:11:35 +0200 | [diff] [blame] | 4727 | goto out; |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4728 | } |
| 4729 | |
Jingoo Han | 41e043f | 2013-12-03 08:26:00 +0900 | [diff] [blame] | 4730 | static const struct pci_device_id et131x_pci_table[] = { |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4731 | { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_GIG), 0UL}, |
| 4732 | { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_FAST), 0UL}, |
| 4733 | {0,} |
| 4734 | }; |
| 4735 | MODULE_DEVICE_TABLE(pci, et131x_pci_table); |
| 4736 | |
| 4737 | static struct pci_driver et131x_driver = { |
| 4738 | .name = DRIVER_NAME, |
| 4739 | .id_table = et131x_pci_table, |
| 4740 | .probe = et131x_pci_setup, |
Bill Pemberton | 0b5e409 | 2012-11-19 13:20:50 -0500 | [diff] [blame] | 4741 | .remove = et131x_pci_remove, |
Mark Einon | 5da2b15 | 2011-10-23 10:22:49 +0100 | [diff] [blame] | 4742 | .driver.pm = ET131X_PM_OPS, |
| 4743 | }; |
| 4744 | |
Devendra Naga | 89812b1 | 2012-07-10 12:11:03 +0530 | [diff] [blame] | 4745 | module_pci_driver(et131x_driver); |