Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1 | /* |
| 2 | * SH RSPI driver |
| 3 | * |
Geert Uytterhoeven | 9372220 | 2014-01-24 09:43:58 +0100 | [diff] [blame] | 4 | * Copyright (C) 2012, 2013 Renesas Solutions Corp. |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 5 | * Copyright (C) 2014 Glider bvba |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 6 | * |
| 7 | * Based on spi-sh.c: |
| 8 | * Copyright (C) 2011 Renesas Solutions Corp. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | #include <linux/module.h> |
| 26 | #include <linux/kernel.h> |
| 27 | #include <linux/sched.h> |
| 28 | #include <linux/errno.h> |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 29 | #include <linux/interrupt.h> |
| 30 | #include <linux/platform_device.h> |
| 31 | #include <linux/io.h> |
| 32 | #include <linux/clk.h> |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 33 | #include <linux/dmaengine.h> |
| 34 | #include <linux/dma-mapping.h> |
Geert Uytterhoeven | 426ef76 | 2014-01-28 10:21:38 +0100 | [diff] [blame] | 35 | #include <linux/of_device.h> |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 36 | #include <linux/sh_dma.h> |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 37 | #include <linux/spi/spi.h> |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 38 | #include <linux/spi/rspi.h> |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 39 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 40 | #define RSPI_SPCR 0x00 /* Control Register */ |
| 41 | #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */ |
| 42 | #define RSPI_SPPCR 0x02 /* Pin Control Register */ |
| 43 | #define RSPI_SPSR 0x03 /* Status Register */ |
| 44 | #define RSPI_SPDR 0x04 /* Data Register */ |
| 45 | #define RSPI_SPSCR 0x08 /* Sequence Control Register */ |
| 46 | #define RSPI_SPSSR 0x09 /* Sequence Status Register */ |
| 47 | #define RSPI_SPBR 0x0a /* Bit Rate Register */ |
| 48 | #define RSPI_SPDCR 0x0b /* Data Control Register */ |
| 49 | #define RSPI_SPCKD 0x0c /* Clock Delay Register */ |
| 50 | #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */ |
| 51 | #define RSPI_SPND 0x0e /* Next-Access Delay Register */ |
Geert Uytterhoeven | 862d357 | 2014-01-24 09:43:59 +0100 | [diff] [blame] | 52 | #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */ |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 53 | #define RSPI_SPCMD0 0x10 /* Command Register 0 */ |
| 54 | #define RSPI_SPCMD1 0x12 /* Command Register 1 */ |
| 55 | #define RSPI_SPCMD2 0x14 /* Command Register 2 */ |
| 56 | #define RSPI_SPCMD3 0x16 /* Command Register 3 */ |
| 57 | #define RSPI_SPCMD4 0x18 /* Command Register 4 */ |
| 58 | #define RSPI_SPCMD5 0x1a /* Command Register 5 */ |
| 59 | #define RSPI_SPCMD6 0x1c /* Command Register 6 */ |
| 60 | #define RSPI_SPCMD7 0x1e /* Command Register 7 */ |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 61 | #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2) |
| 62 | #define RSPI_NUM_SPCMD 8 |
| 63 | #define RSPI_RZ_NUM_SPCMD 4 |
| 64 | #define QSPI_NUM_SPCMD 4 |
Geert Uytterhoeven | 862d357 | 2014-01-24 09:43:59 +0100 | [diff] [blame] | 65 | |
| 66 | /* RSPI on RZ only */ |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 67 | #define RSPI_SPBFCR 0x20 /* Buffer Control Register */ |
| 68 | #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 69 | |
Geert Uytterhoeven | 862d357 | 2014-01-24 09:43:59 +0100 | [diff] [blame] | 70 | /* QSPI only */ |
Geert Uytterhoeven | fbe5072 | 2014-01-12 11:27:38 +0100 | [diff] [blame] | 71 | #define QSPI_SPBFCR 0x18 /* Buffer Control Register */ |
| 72 | #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ |
| 73 | #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ |
| 74 | #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ |
| 75 | #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ |
| 76 | #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 77 | #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4) |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 78 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 79 | /* SPCR - Control Register */ |
| 80 | #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ |
| 81 | #define SPCR_SPE 0x40 /* Function Enable */ |
| 82 | #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */ |
| 83 | #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */ |
| 84 | #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */ |
| 85 | #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */ |
| 86 | /* RSPI on SH only */ |
| 87 | #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */ |
| 88 | #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */ |
Geert Uytterhoeven | fbe5072 | 2014-01-12 11:27:38 +0100 | [diff] [blame] | 89 | /* QSPI on R-Car M2 only */ |
| 90 | #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */ |
| 91 | #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 92 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 93 | /* SSLP - Slave Select Polarity Register */ |
| 94 | #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */ |
| 95 | #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 96 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 97 | /* SPPCR - Pin Control Register */ |
| 98 | #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */ |
| 99 | #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 100 | #define SPPCR_SPOM 0x04 |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 101 | #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */ |
| 102 | #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 103 | |
Geert Uytterhoeven | fbe5072 | 2014-01-12 11:27:38 +0100 | [diff] [blame] | 104 | #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */ |
| 105 | #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */ |
| 106 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 107 | /* SPSR - Status Register */ |
| 108 | #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */ |
| 109 | #define SPSR_TEND 0x40 /* Transmit End */ |
| 110 | #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */ |
| 111 | #define SPSR_PERF 0x08 /* Parity Error Flag */ |
| 112 | #define SPSR_MODF 0x04 /* Mode Fault Error Flag */ |
| 113 | #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */ |
Geert Uytterhoeven | 862d357 | 2014-01-24 09:43:59 +0100 | [diff] [blame] | 114 | #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 115 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 116 | /* SPSCR - Sequence Control Register */ |
| 117 | #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 118 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 119 | /* SPSSR - Sequence Status Register */ |
| 120 | #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */ |
| 121 | #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 122 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 123 | /* SPDCR - Data Control Register */ |
| 124 | #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */ |
| 125 | #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */ |
| 126 | #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */ |
| 127 | #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0) |
| 128 | #define SPDCR_SPLWORD SPDCR_SPLW1 |
| 129 | #define SPDCR_SPLBYTE SPDCR_SPLW0 |
| 130 | #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */ |
Geert Uytterhoeven | 862d357 | 2014-01-24 09:43:59 +0100 | [diff] [blame] | 131 | #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 132 | #define SPDCR_SLSEL1 0x08 |
| 133 | #define SPDCR_SLSEL0 0x04 |
Geert Uytterhoeven | 862d357 | 2014-01-24 09:43:59 +0100 | [diff] [blame] | 134 | #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 135 | #define SPDCR_SPFC1 0x02 |
| 136 | #define SPDCR_SPFC0 0x01 |
Geert Uytterhoeven | 862d357 | 2014-01-24 09:43:59 +0100 | [diff] [blame] | 137 | #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 138 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 139 | /* SPCKD - Clock Delay Register */ |
| 140 | #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 141 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 142 | /* SSLND - Slave Select Negation Delay Register */ |
| 143 | #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 144 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 145 | /* SPND - Next-Access Delay Register */ |
| 146 | #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 147 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 148 | /* SPCR2 - Control Register 2 */ |
| 149 | #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */ |
| 150 | #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */ |
| 151 | #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */ |
| 152 | #define SPCR2_SPPE 0x01 /* Parity Enable */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 153 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 154 | /* SPCMDn - Command Registers */ |
| 155 | #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */ |
| 156 | #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */ |
| 157 | #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */ |
| 158 | #define SPCMD_LSBF 0x1000 /* LSB First */ |
| 159 | #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 160 | #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 161 | #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */ |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 162 | #define SPCMD_SPB_16BIT 0x0100 |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 163 | #define SPCMD_SPB_20BIT 0x0000 |
| 164 | #define SPCMD_SPB_24BIT 0x0100 |
| 165 | #define SPCMD_SPB_32BIT 0x0200 |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 166 | #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */ |
Geert Uytterhoeven | fbe5072 | 2014-01-12 11:27:38 +0100 | [diff] [blame] | 167 | #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */ |
| 168 | #define SPCMD_SPIMOD1 0x0040 |
| 169 | #define SPCMD_SPIMOD0 0x0020 |
| 170 | #define SPCMD_SPIMOD_SINGLE 0 |
| 171 | #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0 |
| 172 | #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1 |
| 173 | #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */ |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 174 | #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */ |
| 175 | #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */ |
| 176 | #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */ |
| 177 | #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 178 | |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 179 | /* SPBFCR - Buffer Control Register */ |
Geert Uytterhoeven | 862d357 | 2014-01-24 09:43:59 +0100 | [diff] [blame] | 180 | #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */ |
| 181 | #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */ |
Geert Uytterhoeven | 6ab4865 | 2014-01-12 11:27:37 +0100 | [diff] [blame] | 182 | #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ |
| 183 | #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 184 | |
Geert Uytterhoeven | 2aae80b | 2013-12-24 10:49:33 +0100 | [diff] [blame] | 185 | #define DUMMY_DATA 0x00 |
| 186 | |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 187 | struct rspi_data { |
| 188 | void __iomem *addr; |
| 189 | u32 max_speed_hz; |
| 190 | struct spi_master *master; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 191 | wait_queue_head_t wait; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 192 | struct clk *clk; |
Geert Uytterhoeven | 348e515 | 2014-01-12 11:27:43 +0100 | [diff] [blame] | 193 | u16 spcmd; |
Geert Uytterhoeven | 06a7a3c | 2014-01-24 09:44:00 +0100 | [diff] [blame] | 194 | u8 spsr; |
| 195 | u8 sppcr; |
Geert Uytterhoeven | 9372220 | 2014-01-24 09:43:58 +0100 | [diff] [blame] | 196 | int rx_irq, tx_irq; |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 197 | const struct spi_ops *ops; |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 198 | |
| 199 | /* for dmaengine */ |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 200 | struct dma_chan *chan_tx; |
| 201 | struct dma_chan *chan_rx; |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 202 | |
| 203 | unsigned dma_width_16bit:1; |
| 204 | unsigned dma_callbacked:1; |
Geert Uytterhoeven | 74da768 | 2014-01-24 09:43:53 +0100 | [diff] [blame] | 205 | unsigned byte_access:1; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 206 | }; |
| 207 | |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 208 | static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 209 | { |
| 210 | iowrite8(data, rspi->addr + offset); |
| 211 | } |
| 212 | |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 213 | static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 214 | { |
| 215 | iowrite16(data, rspi->addr + offset); |
| 216 | } |
| 217 | |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 218 | static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset) |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 219 | { |
| 220 | iowrite32(data, rspi->addr + offset); |
| 221 | } |
| 222 | |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 223 | static u8 rspi_read8(const struct rspi_data *rspi, u16 offset) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 224 | { |
| 225 | return ioread8(rspi->addr + offset); |
| 226 | } |
| 227 | |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 228 | static u16 rspi_read16(const struct rspi_data *rspi, u16 offset) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 229 | { |
| 230 | return ioread16(rspi->addr + offset); |
| 231 | } |
| 232 | |
Geert Uytterhoeven | 74da768 | 2014-01-24 09:43:53 +0100 | [diff] [blame] | 233 | static void rspi_write_data(const struct rspi_data *rspi, u16 data) |
| 234 | { |
| 235 | if (rspi->byte_access) |
| 236 | rspi_write8(rspi, data, RSPI_SPDR); |
| 237 | else /* 16 bit */ |
| 238 | rspi_write16(rspi, data, RSPI_SPDR); |
| 239 | } |
| 240 | |
| 241 | static u16 rspi_read_data(const struct rspi_data *rspi) |
| 242 | { |
| 243 | if (rspi->byte_access) |
| 244 | return rspi_read8(rspi, RSPI_SPDR); |
| 245 | else /* 16 bit */ |
| 246 | return rspi_read16(rspi, RSPI_SPDR); |
| 247 | } |
| 248 | |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 249 | /* optional functions */ |
| 250 | struct spi_ops { |
Geert Uytterhoeven | 74da768 | 2014-01-24 09:43:53 +0100 | [diff] [blame] | 251 | int (*set_config_register)(struct rspi_data *rspi, int access_size); |
Geert Uytterhoeven | eb557f7 | 2014-01-24 09:43:55 +0100 | [diff] [blame] | 252 | int (*transfer_one)(struct spi_master *master, struct spi_device *spi, |
| 253 | struct spi_transfer *xfer); |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 254 | u16 mode_bits; |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 255 | }; |
| 256 | |
| 257 | /* |
Geert Uytterhoeven | 862d357 | 2014-01-24 09:43:59 +0100 | [diff] [blame] | 258 | * functions for RSPI on legacy SH |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 259 | */ |
Geert Uytterhoeven | 74da768 | 2014-01-24 09:43:53 +0100 | [diff] [blame] | 260 | static int rspi_set_config_register(struct rspi_data *rspi, int access_size) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 261 | { |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 262 | int spbr; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 263 | |
Geert Uytterhoeven | 06a7a3c | 2014-01-24 09:44:00 +0100 | [diff] [blame] | 264 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
| 265 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 266 | |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 267 | /* Sets transfer bit rate */ |
| 268 | spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1; |
| 269 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); |
| 270 | |
Geert Uytterhoeven | 74da768 | 2014-01-24 09:43:53 +0100 | [diff] [blame] | 271 | /* Disable dummy transmission, set 16-bit word access, 1 frame */ |
| 272 | rspi_write8(rspi, 0, RSPI_SPDCR); |
| 273 | rspi->byte_access = 0; |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 274 | |
| 275 | /* Sets RSPCK, SSL, next-access delay value */ |
| 276 | rspi_write8(rspi, 0x00, RSPI_SPCKD); |
| 277 | rspi_write8(rspi, 0x00, RSPI_SSLND); |
| 278 | rspi_write8(rspi, 0x00, RSPI_SPND); |
| 279 | |
| 280 | /* Sets parity, interrupt mask */ |
| 281 | rspi_write8(rspi, 0x00, RSPI_SPCR2); |
| 282 | |
| 283 | /* Sets SPCMD */ |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 284 | rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); |
| 285 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 286 | |
| 287 | /* Sets RSPI mode */ |
| 288 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); |
| 289 | |
| 290 | return 0; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 291 | } |
| 292 | |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 293 | /* |
Geert Uytterhoeven | 862d357 | 2014-01-24 09:43:59 +0100 | [diff] [blame] | 294 | * functions for RSPI on RZ |
| 295 | */ |
| 296 | static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size) |
| 297 | { |
| 298 | int spbr; |
| 299 | |
Geert Uytterhoeven | 06a7a3c | 2014-01-24 09:44:00 +0100 | [diff] [blame] | 300 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
| 301 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); |
Geert Uytterhoeven | 862d357 | 2014-01-24 09:43:59 +0100 | [diff] [blame] | 302 | |
| 303 | /* Sets transfer bit rate */ |
| 304 | spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1; |
| 305 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); |
| 306 | |
| 307 | /* Disable dummy transmission, set byte access */ |
| 308 | rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR); |
| 309 | rspi->byte_access = 1; |
| 310 | |
| 311 | /* Sets RSPCK, SSL, next-access delay value */ |
| 312 | rspi_write8(rspi, 0x00, RSPI_SPCKD); |
| 313 | rspi_write8(rspi, 0x00, RSPI_SSLND); |
| 314 | rspi_write8(rspi, 0x00, RSPI_SPND); |
| 315 | |
| 316 | /* Sets SPCMD */ |
| 317 | rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); |
| 318 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); |
| 319 | |
| 320 | /* Sets RSPI mode */ |
| 321 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); |
| 322 | |
| 323 | return 0; |
| 324 | } |
| 325 | |
| 326 | /* |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 327 | * functions for QSPI |
| 328 | */ |
Geert Uytterhoeven | 74da768 | 2014-01-24 09:43:53 +0100 | [diff] [blame] | 329 | static int qspi_set_config_register(struct rspi_data *rspi, int access_size) |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 330 | { |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 331 | int spbr; |
| 332 | |
Geert Uytterhoeven | 06a7a3c | 2014-01-24 09:44:00 +0100 | [diff] [blame] | 333 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
| 334 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 335 | |
| 336 | /* Sets transfer bit rate */ |
| 337 | spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz); |
| 338 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); |
| 339 | |
Geert Uytterhoeven | 74da768 | 2014-01-24 09:43:53 +0100 | [diff] [blame] | 340 | /* Disable dummy transmission, set byte access */ |
| 341 | rspi_write8(rspi, 0, RSPI_SPDCR); |
| 342 | rspi->byte_access = 1; |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 343 | |
| 344 | /* Sets RSPCK, SSL, next-access delay value */ |
| 345 | rspi_write8(rspi, 0x00, RSPI_SPCKD); |
| 346 | rspi_write8(rspi, 0x00, RSPI_SSLND); |
| 347 | rspi_write8(rspi, 0x00, RSPI_SPND); |
| 348 | |
| 349 | /* Data Length Setting */ |
| 350 | if (access_size == 8) |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 351 | rspi->spcmd |= SPCMD_SPB_8BIT; |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 352 | else if (access_size == 16) |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 353 | rspi->spcmd |= SPCMD_SPB_16BIT; |
Laurent Pinchart | 8e1c809 | 2013-11-27 01:41:44 +0100 | [diff] [blame] | 354 | else |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 355 | rspi->spcmd |= SPCMD_SPB_32BIT; |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 356 | |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 357 | rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN; |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 358 | |
| 359 | /* Resets transfer data length */ |
| 360 | rspi_write32(rspi, 0, QSPI_SPBMUL0); |
| 361 | |
| 362 | /* Resets transmit and receive buffer */ |
| 363 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); |
| 364 | /* Sets buffer to allow normal operation */ |
| 365 | rspi_write8(rspi, 0x00, QSPI_SPBFCR); |
| 366 | |
| 367 | /* Sets SPCMD */ |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 368 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 369 | |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 370 | /* Enables SPI function in master mode */ |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 371 | rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR); |
| 372 | |
| 373 | return 0; |
| 374 | } |
| 375 | |
| 376 | #define set_config_register(spi, n) spi->ops->set_config_register(spi, n) |
| 377 | |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 378 | static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 379 | { |
| 380 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); |
| 381 | } |
| 382 | |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 383 | static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 384 | { |
| 385 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); |
| 386 | } |
| 387 | |
| 388 | static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask, |
| 389 | u8 enable_bit) |
| 390 | { |
| 391 | int ret; |
| 392 | |
| 393 | rspi->spsr = rspi_read8(rspi, RSPI_SPSR); |
| 394 | rspi_enable_irq(rspi, enable_bit); |
| 395 | ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); |
| 396 | if (ret == 0 && !(rspi->spsr & wait_mask)) |
| 397 | return -ETIMEDOUT; |
| 398 | |
| 399 | return 0; |
| 400 | } |
| 401 | |
Geert Uytterhoeven | 35301c9 | 2014-01-24 09:43:54 +0100 | [diff] [blame] | 402 | static int rspi_data_out(struct rspi_data *rspi, u8 data) |
| 403 | { |
| 404 | if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { |
| 405 | dev_err(&rspi->master->dev, "transmit timeout\n"); |
| 406 | return -ETIMEDOUT; |
| 407 | } |
| 408 | rspi_write_data(rspi, data); |
| 409 | return 0; |
| 410 | } |
| 411 | |
| 412 | static int rspi_data_in(struct rspi_data *rspi) |
| 413 | { |
| 414 | u8 data; |
| 415 | |
| 416 | if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) { |
| 417 | dev_err(&rspi->master->dev, "receive timeout\n"); |
| 418 | return -ETIMEDOUT; |
| 419 | } |
| 420 | data = rspi_read_data(rspi); |
| 421 | return data; |
| 422 | } |
| 423 | |
| 424 | static int rspi_data_out_in(struct rspi_data *rspi, u8 data) |
| 425 | { |
| 426 | int ret; |
| 427 | |
| 428 | ret = rspi_data_out(rspi, data); |
| 429 | if (ret < 0) |
| 430 | return ret; |
| 431 | |
| 432 | return rspi_data_in(rspi); |
| 433 | } |
| 434 | |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 435 | static void rspi_dma_complete(void *arg) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 436 | { |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 437 | struct rspi_data *rspi = arg; |
| 438 | |
| 439 | rspi->dma_callbacked = 1; |
| 440 | wake_up_interruptible(&rspi->wait); |
| 441 | } |
| 442 | |
Geert Uytterhoeven | c132f09 | 2013-12-24 10:49:31 +0100 | [diff] [blame] | 443 | static int rspi_dma_map_sg(struct scatterlist *sg, const void *buf, |
| 444 | unsigned len, struct dma_chan *chan, |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 445 | enum dma_transfer_direction dir) |
| 446 | { |
| 447 | sg_init_table(sg, 1); |
| 448 | sg_set_buf(sg, buf, len); |
| 449 | sg_dma_len(sg) = len; |
| 450 | return dma_map_sg(chan->device->dev, sg, 1, dir); |
| 451 | } |
| 452 | |
| 453 | static void rspi_dma_unmap_sg(struct scatterlist *sg, struct dma_chan *chan, |
| 454 | enum dma_transfer_direction dir) |
| 455 | { |
| 456 | dma_unmap_sg(chan->device->dev, sg, 1, dir); |
| 457 | } |
| 458 | |
| 459 | static void rspi_memory_to_8bit(void *buf, const void *data, unsigned len) |
| 460 | { |
| 461 | u16 *dst = buf; |
| 462 | const u8 *src = data; |
| 463 | |
| 464 | while (len) { |
| 465 | *dst++ = (u16)(*src++); |
| 466 | len--; |
| 467 | } |
| 468 | } |
| 469 | |
| 470 | static void rspi_memory_from_8bit(void *buf, const void *data, unsigned len) |
| 471 | { |
| 472 | u8 *dst = buf; |
| 473 | const u16 *src = data; |
| 474 | |
| 475 | while (len) { |
| 476 | *dst++ = (u8)*src++; |
| 477 | len--; |
| 478 | } |
| 479 | } |
| 480 | |
| 481 | static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t) |
| 482 | { |
| 483 | struct scatterlist sg; |
Geert Uytterhoeven | c132f09 | 2013-12-24 10:49:31 +0100 | [diff] [blame] | 484 | const void *buf = NULL; |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 485 | struct dma_async_tx_descriptor *desc; |
Geert Uytterhoeven | 9372220 | 2014-01-24 09:43:58 +0100 | [diff] [blame] | 486 | unsigned int len; |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 487 | int ret = 0; |
| 488 | |
| 489 | if (rspi->dma_width_16bit) { |
Geert Uytterhoeven | c132f09 | 2013-12-24 10:49:31 +0100 | [diff] [blame] | 490 | void *tmp; |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 491 | /* |
| 492 | * If DMAC bus width is 16-bit, the driver allocates a dummy |
| 493 | * buffer. And, the driver converts original data into the |
| 494 | * DMAC data as the following format: |
| 495 | * original data: 1st byte, 2nd byte ... |
| 496 | * DMAC data: 1st byte, dummy, 2nd byte, dummy ... |
| 497 | */ |
| 498 | len = t->len * 2; |
Geert Uytterhoeven | c132f09 | 2013-12-24 10:49:31 +0100 | [diff] [blame] | 499 | tmp = kmalloc(len, GFP_KERNEL); |
| 500 | if (!tmp) |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 501 | return -ENOMEM; |
Geert Uytterhoeven | c132f09 | 2013-12-24 10:49:31 +0100 | [diff] [blame] | 502 | rspi_memory_to_8bit(tmp, t->tx_buf, t->len); |
| 503 | buf = tmp; |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 504 | } else { |
| 505 | len = t->len; |
Geert Uytterhoeven | c132f09 | 2013-12-24 10:49:31 +0100 | [diff] [blame] | 506 | buf = t->tx_buf; |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 507 | } |
| 508 | |
| 509 | if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) { |
| 510 | ret = -EFAULT; |
| 511 | goto end_nomap; |
| 512 | } |
| 513 | desc = dmaengine_prep_slave_sg(rspi->chan_tx, &sg, 1, DMA_TO_DEVICE, |
| 514 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 515 | if (!desc) { |
| 516 | ret = -EIO; |
| 517 | goto end; |
| 518 | } |
| 519 | |
| 520 | /* |
| 521 | * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be |
| 522 | * called. So, this driver disables the IRQ while DMA transfer. |
| 523 | */ |
Geert Uytterhoeven | 9372220 | 2014-01-24 09:43:58 +0100 | [diff] [blame] | 524 | disable_irq(rspi->tx_irq); |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 525 | |
| 526 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR); |
| 527 | rspi_enable_irq(rspi, SPCR_SPTIE); |
| 528 | rspi->dma_callbacked = 0; |
| 529 | |
| 530 | desc->callback = rspi_dma_complete; |
| 531 | desc->callback_param = rspi; |
| 532 | dmaengine_submit(desc); |
| 533 | dma_async_issue_pending(rspi->chan_tx); |
| 534 | |
| 535 | ret = wait_event_interruptible_timeout(rspi->wait, |
| 536 | rspi->dma_callbacked, HZ); |
| 537 | if (ret > 0 && rspi->dma_callbacked) |
| 538 | ret = 0; |
| 539 | else if (!ret) |
| 540 | ret = -ETIMEDOUT; |
| 541 | rspi_disable_irq(rspi, SPCR_SPTIE); |
| 542 | |
Geert Uytterhoeven | 9372220 | 2014-01-24 09:43:58 +0100 | [diff] [blame] | 543 | enable_irq(rspi->tx_irq); |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 544 | |
| 545 | end: |
| 546 | rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE); |
| 547 | end_nomap: |
| 548 | if (rspi->dma_width_16bit) |
| 549 | kfree(buf); |
| 550 | |
| 551 | return ret; |
| 552 | } |
| 553 | |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 554 | static void rspi_receive_init(const struct rspi_data *rspi) |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 555 | { |
Geert Uytterhoeven | 97b95c1 | 2013-12-24 10:49:34 +0100 | [diff] [blame] | 556 | u8 spsr; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 557 | |
| 558 | spsr = rspi_read8(rspi, RSPI_SPSR); |
| 559 | if (spsr & SPSR_SPRF) |
Geert Uytterhoeven | 74da768 | 2014-01-24 09:43:53 +0100 | [diff] [blame] | 560 | rspi_read_data(rspi); /* dummy read */ |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 561 | if (spsr & SPSR_OVRF) |
| 562 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, |
Geert Uytterhoeven | df900e6 | 2013-12-23 19:34:24 +0100 | [diff] [blame] | 563 | RSPI_SPSR); |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 564 | } |
| 565 | |
Geert Uytterhoeven | 862d357 | 2014-01-24 09:43:59 +0100 | [diff] [blame] | 566 | static void rspi_rz_receive_init(const struct rspi_data *rspi) |
| 567 | { |
| 568 | rspi_receive_init(rspi); |
| 569 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR); |
| 570 | rspi_write8(rspi, 0, RSPI_SPBFCR); |
| 571 | } |
| 572 | |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 573 | static void qspi_receive_init(const struct rspi_data *rspi) |
Hiep Cao Minh | cb52c67 | 2013-10-10 17:14:03 +0900 | [diff] [blame] | 574 | { |
Geert Uytterhoeven | 97b95c1 | 2013-12-24 10:49:34 +0100 | [diff] [blame] | 575 | u8 spsr; |
Hiep Cao Minh | cb52c67 | 2013-10-10 17:14:03 +0900 | [diff] [blame] | 576 | |
| 577 | spsr = rspi_read8(rspi, RSPI_SPSR); |
| 578 | if (spsr & SPSR_SPRF) |
Geert Uytterhoeven | 74da768 | 2014-01-24 09:43:53 +0100 | [diff] [blame] | 579 | rspi_read_data(rspi); /* dummy read */ |
Hiep Cao Minh | cb52c67 | 2013-10-10 17:14:03 +0900 | [diff] [blame] | 580 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); |
Geert Uytterhoeven | 340a15e | 2014-01-24 09:43:57 +0100 | [diff] [blame] | 581 | rspi_write8(rspi, 0, QSPI_SPBFCR); |
Hiep Cao Minh | cb52c67 | 2013-10-10 17:14:03 +0900 | [diff] [blame] | 582 | } |
| 583 | |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 584 | static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t) |
| 585 | { |
| 586 | struct scatterlist sg, sg_dummy; |
| 587 | void *dummy = NULL, *rx_buf = NULL; |
| 588 | struct dma_async_tx_descriptor *desc, *desc_dummy; |
Geert Uytterhoeven | 9372220 | 2014-01-24 09:43:58 +0100 | [diff] [blame] | 589 | unsigned int len; |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 590 | int ret = 0; |
| 591 | |
| 592 | if (rspi->dma_width_16bit) { |
| 593 | /* |
| 594 | * If DMAC bus width is 16-bit, the driver allocates a dummy |
| 595 | * buffer. And, finally the driver converts the DMAC data into |
| 596 | * actual data as the following format: |
| 597 | * DMAC data: 1st byte, dummy, 2nd byte, dummy ... |
| 598 | * actual data: 1st byte, 2nd byte ... |
| 599 | */ |
| 600 | len = t->len * 2; |
| 601 | rx_buf = kmalloc(len, GFP_KERNEL); |
| 602 | if (!rx_buf) |
| 603 | return -ENOMEM; |
| 604 | } else { |
| 605 | len = t->len; |
| 606 | rx_buf = t->rx_buf; |
| 607 | } |
| 608 | |
| 609 | /* prepare dummy transfer to generate SPI clocks */ |
| 610 | dummy = kzalloc(len, GFP_KERNEL); |
| 611 | if (!dummy) { |
| 612 | ret = -ENOMEM; |
| 613 | goto end_nomap; |
| 614 | } |
| 615 | if (!rspi_dma_map_sg(&sg_dummy, dummy, len, rspi->chan_tx, |
| 616 | DMA_TO_DEVICE)) { |
| 617 | ret = -EFAULT; |
| 618 | goto end_nomap; |
| 619 | } |
| 620 | desc_dummy = dmaengine_prep_slave_sg(rspi->chan_tx, &sg_dummy, 1, |
| 621 | DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 622 | if (!desc_dummy) { |
| 623 | ret = -EIO; |
| 624 | goto end_dummy_mapped; |
| 625 | } |
| 626 | |
| 627 | /* prepare receive transfer */ |
| 628 | if (!rspi_dma_map_sg(&sg, rx_buf, len, rspi->chan_rx, |
| 629 | DMA_FROM_DEVICE)) { |
| 630 | ret = -EFAULT; |
| 631 | goto end_dummy_mapped; |
| 632 | |
| 633 | } |
| 634 | desc = dmaengine_prep_slave_sg(rspi->chan_rx, &sg, 1, DMA_FROM_DEVICE, |
| 635 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 636 | if (!desc) { |
| 637 | ret = -EIO; |
| 638 | goto end; |
| 639 | } |
| 640 | |
| 641 | rspi_receive_init(rspi); |
| 642 | |
| 643 | /* |
| 644 | * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be |
| 645 | * called. So, this driver disables the IRQ while DMA transfer. |
| 646 | */ |
Geert Uytterhoeven | 9372220 | 2014-01-24 09:43:58 +0100 | [diff] [blame] | 647 | disable_irq(rspi->tx_irq); |
| 648 | if (rspi->rx_irq != rspi->tx_irq) |
| 649 | disable_irq(rspi->rx_irq); |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 650 | |
| 651 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR); |
| 652 | rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); |
| 653 | rspi->dma_callbacked = 0; |
| 654 | |
| 655 | desc->callback = rspi_dma_complete; |
| 656 | desc->callback_param = rspi; |
| 657 | dmaengine_submit(desc); |
| 658 | dma_async_issue_pending(rspi->chan_rx); |
| 659 | |
| 660 | desc_dummy->callback = NULL; /* No callback */ |
| 661 | dmaengine_submit(desc_dummy); |
| 662 | dma_async_issue_pending(rspi->chan_tx); |
| 663 | |
| 664 | ret = wait_event_interruptible_timeout(rspi->wait, |
| 665 | rspi->dma_callbacked, HZ); |
| 666 | if (ret > 0 && rspi->dma_callbacked) |
| 667 | ret = 0; |
| 668 | else if (!ret) |
| 669 | ret = -ETIMEDOUT; |
| 670 | rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); |
| 671 | |
Geert Uytterhoeven | 9372220 | 2014-01-24 09:43:58 +0100 | [diff] [blame] | 672 | enable_irq(rspi->tx_irq); |
| 673 | if (rspi->rx_irq != rspi->tx_irq) |
| 674 | enable_irq(rspi->rx_irq); |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 675 | |
| 676 | end: |
| 677 | rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE); |
| 678 | end_dummy_mapped: |
| 679 | rspi_dma_unmap_sg(&sg_dummy, rspi->chan_tx, DMA_TO_DEVICE); |
| 680 | end_nomap: |
| 681 | if (rspi->dma_width_16bit) { |
| 682 | if (!ret) |
| 683 | rspi_memory_from_8bit(t->rx_buf, rx_buf, t->len); |
| 684 | kfree(rx_buf); |
| 685 | } |
| 686 | kfree(dummy); |
| 687 | |
| 688 | return ret; |
| 689 | } |
| 690 | |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 691 | static int rspi_is_dma(const struct rspi_data *rspi, struct spi_transfer *t) |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 692 | { |
| 693 | if (t->tx_buf && rspi->chan_tx) |
| 694 | return 1; |
| 695 | /* If the module receives data by DMAC, it also needs TX DMAC */ |
| 696 | if (t->rx_buf && rspi->chan_tx && rspi->chan_rx) |
| 697 | return 1; |
| 698 | |
| 699 | return 0; |
| 700 | } |
| 701 | |
Geert Uytterhoeven | 8449fd7 | 2014-01-24 09:43:56 +0100 | [diff] [blame] | 702 | static int rspi_transfer_out_in(struct rspi_data *rspi, |
| 703 | struct spi_transfer *xfer) |
| 704 | { |
| 705 | int remain = xfer->len, ret; |
| 706 | const u8 *tx_buf = xfer->tx_buf; |
| 707 | u8 *rx_buf = xfer->rx_buf; |
| 708 | u8 spcr, data; |
| 709 | |
| 710 | rspi_receive_init(rspi); |
| 711 | |
| 712 | spcr = rspi_read8(rspi, RSPI_SPCR); |
| 713 | if (rx_buf) |
| 714 | spcr &= ~SPCR_TXMD; |
| 715 | else |
| 716 | spcr |= SPCR_TXMD; |
| 717 | rspi_write8(rspi, spcr, RSPI_SPCR); |
| 718 | |
| 719 | while (remain > 0) { |
| 720 | data = tx_buf ? *tx_buf++ : DUMMY_DATA; |
| 721 | ret = rspi_data_out(rspi, data); |
| 722 | if (ret < 0) |
| 723 | return ret; |
| 724 | if (rx_buf) { |
| 725 | ret = rspi_data_in(rspi); |
| 726 | if (ret < 0) |
| 727 | return ret; |
| 728 | *rx_buf++ = ret; |
| 729 | } |
| 730 | remain--; |
| 731 | } |
| 732 | |
| 733 | /* Wait for the last transmission */ |
| 734 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); |
| 735 | |
| 736 | return 0; |
| 737 | } |
| 738 | |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 739 | static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi, |
| 740 | struct spi_transfer *xfer) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 741 | { |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 742 | struct rspi_data *rspi = spi_master_get_devdata(master); |
Geert Uytterhoeven | 8449fd7 | 2014-01-24 09:43:56 +0100 | [diff] [blame] | 743 | int ret; |
| 744 | |
| 745 | if (!rspi_is_dma(rspi, xfer)) |
| 746 | return rspi_transfer_out_in(rspi, xfer); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 747 | |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 748 | if (xfer->tx_buf) { |
Geert Uytterhoeven | 8449fd7 | 2014-01-24 09:43:56 +0100 | [diff] [blame] | 749 | ret = rspi_send_dma(rspi, xfer); |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 750 | if (ret < 0) |
| 751 | return ret; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 752 | } |
Geert Uytterhoeven | 8449fd7 | 2014-01-24 09:43:56 +0100 | [diff] [blame] | 753 | if (xfer->rx_buf) |
| 754 | return rspi_receive_dma(rspi, xfer); |
| 755 | |
| 756 | return 0; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 757 | } |
| 758 | |
Geert Uytterhoeven | 862d357 | 2014-01-24 09:43:59 +0100 | [diff] [blame] | 759 | static int rspi_rz_transfer_out_in(struct rspi_data *rspi, |
| 760 | struct spi_transfer *xfer) |
| 761 | { |
| 762 | int remain = xfer->len, ret; |
| 763 | const u8 *tx_buf = xfer->tx_buf; |
| 764 | u8 *rx_buf = xfer->rx_buf; |
| 765 | u8 data; |
| 766 | |
| 767 | rspi_rz_receive_init(rspi); |
| 768 | |
| 769 | while (remain > 0) { |
| 770 | data = tx_buf ? *tx_buf++ : DUMMY_DATA; |
| 771 | ret = rspi_data_out_in(rspi, data); |
| 772 | if (ret < 0) |
| 773 | return ret; |
| 774 | if (rx_buf) |
| 775 | *rx_buf++ = ret; |
| 776 | remain--; |
| 777 | } |
| 778 | |
| 779 | /* Wait for the last transmission */ |
| 780 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); |
| 781 | |
| 782 | return 0; |
| 783 | } |
| 784 | |
| 785 | static int rspi_rz_transfer_one(struct spi_master *master, |
| 786 | struct spi_device *spi, |
| 787 | struct spi_transfer *xfer) |
| 788 | { |
| 789 | struct rspi_data *rspi = spi_master_get_devdata(master); |
| 790 | |
| 791 | return rspi_rz_transfer_out_in(rspi, xfer); |
| 792 | } |
| 793 | |
Geert Uytterhoeven | 340a15e | 2014-01-24 09:43:57 +0100 | [diff] [blame] | 794 | static int qspi_transfer_out_in(struct rspi_data *rspi, |
| 795 | struct spi_transfer *xfer) |
| 796 | { |
| 797 | int remain = xfer->len, ret; |
| 798 | const u8 *tx_buf = xfer->tx_buf; |
| 799 | u8 *rx_buf = xfer->rx_buf; |
| 800 | u8 data; |
| 801 | |
| 802 | qspi_receive_init(rspi); |
| 803 | |
| 804 | while (remain > 0) { |
| 805 | data = tx_buf ? *tx_buf++ : DUMMY_DATA; |
| 806 | ret = rspi_data_out_in(rspi, data); |
| 807 | if (ret < 0) |
| 808 | return ret; |
| 809 | if (rx_buf) |
| 810 | *rx_buf++ = ret; |
| 811 | remain--; |
| 812 | } |
| 813 | |
| 814 | /* Wait for the last transmission */ |
| 815 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); |
| 816 | |
| 817 | return 0; |
| 818 | } |
| 819 | |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 820 | static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer) |
| 821 | { |
| 822 | const u8 *buf = xfer->tx_buf; |
| 823 | unsigned int i; |
| 824 | int ret; |
| 825 | |
| 826 | for (i = 0; i < xfer->len; i++) { |
| 827 | ret = rspi_data_out(rspi, *buf++); |
| 828 | if (ret < 0) |
| 829 | return ret; |
| 830 | } |
| 831 | |
| 832 | /* Wait for the last transmission */ |
| 833 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); |
| 834 | |
| 835 | return 0; |
| 836 | } |
| 837 | |
| 838 | static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer) |
| 839 | { |
| 840 | u8 *buf = xfer->rx_buf; |
| 841 | unsigned int i; |
| 842 | int ret; |
| 843 | |
| 844 | for (i = 0; i < xfer->len; i++) { |
| 845 | ret = rspi_data_in(rspi); |
| 846 | if (ret < 0) |
| 847 | return ret; |
| 848 | *buf++ = ret; |
| 849 | } |
| 850 | |
| 851 | return 0; |
| 852 | } |
| 853 | |
Geert Uytterhoeven | eb557f7 | 2014-01-24 09:43:55 +0100 | [diff] [blame] | 854 | static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi, |
| 855 | struct spi_transfer *xfer) |
| 856 | { |
| 857 | struct rspi_data *rspi = spi_master_get_devdata(master); |
Geert Uytterhoeven | eb557f7 | 2014-01-24 09:43:55 +0100 | [diff] [blame] | 858 | |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 859 | if (xfer->tx_buf && xfer->tx_nbits > SPI_NBITS_SINGLE) { |
| 860 | /* Quad or Dual SPI Write */ |
| 861 | return qspi_transfer_out(rspi, xfer); |
| 862 | } else if (xfer->rx_buf && xfer->rx_nbits > SPI_NBITS_SINGLE) { |
| 863 | /* Quad or Dual SPI Read */ |
| 864 | return qspi_transfer_in(rspi, xfer); |
| 865 | } else { |
| 866 | /* Single SPI Transfer */ |
| 867 | return qspi_transfer_out_in(rspi, xfer); |
| 868 | } |
Geert Uytterhoeven | eb557f7 | 2014-01-24 09:43:55 +0100 | [diff] [blame] | 869 | } |
| 870 | |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 871 | static int rspi_setup(struct spi_device *spi) |
| 872 | { |
| 873 | struct rspi_data *rspi = spi_master_get_devdata(spi->master); |
| 874 | |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 875 | rspi->max_speed_hz = spi->max_speed_hz; |
| 876 | |
Geert Uytterhoeven | 348e515 | 2014-01-12 11:27:43 +0100 | [diff] [blame] | 877 | rspi->spcmd = SPCMD_SSLKP; |
| 878 | if (spi->mode & SPI_CPOL) |
| 879 | rspi->spcmd |= SPCMD_CPOL; |
| 880 | if (spi->mode & SPI_CPHA) |
| 881 | rspi->spcmd |= SPCMD_CPHA; |
| 882 | |
Geert Uytterhoeven | 06a7a3c | 2014-01-24 09:44:00 +0100 | [diff] [blame] | 883 | /* CMOS output mode and MOSI signal from previous transfer */ |
| 884 | rspi->sppcr = 0; |
| 885 | if (spi->mode & SPI_LOOP) |
| 886 | rspi->sppcr |= SPPCR_SPLP; |
| 887 | |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 888 | set_config_register(rspi, 8); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 889 | |
| 890 | return 0; |
| 891 | } |
| 892 | |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 893 | static void rspi_cleanup(struct spi_device *spi) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 894 | { |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 895 | } |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 896 | |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 897 | static u16 qspi_transfer_mode(const struct spi_transfer *xfer) |
| 898 | { |
| 899 | if (xfer->tx_buf) |
| 900 | switch (xfer->tx_nbits) { |
| 901 | case SPI_NBITS_QUAD: |
| 902 | return SPCMD_SPIMOD_QUAD; |
| 903 | case SPI_NBITS_DUAL: |
| 904 | return SPCMD_SPIMOD_DUAL; |
| 905 | default: |
| 906 | return 0; |
| 907 | } |
| 908 | if (xfer->rx_buf) |
| 909 | switch (xfer->rx_nbits) { |
| 910 | case SPI_NBITS_QUAD: |
| 911 | return SPCMD_SPIMOD_QUAD | SPCMD_SPRW; |
| 912 | case SPI_NBITS_DUAL: |
| 913 | return SPCMD_SPIMOD_DUAL | SPCMD_SPRW; |
| 914 | default: |
| 915 | return 0; |
| 916 | } |
| 917 | |
| 918 | return 0; |
| 919 | } |
| 920 | |
| 921 | static int qspi_setup_sequencer(struct rspi_data *rspi, |
| 922 | const struct spi_message *msg) |
| 923 | { |
| 924 | const struct spi_transfer *xfer; |
| 925 | unsigned int i = 0, len = 0; |
| 926 | u16 current_mode = 0xffff, mode; |
| 927 | |
| 928 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
| 929 | mode = qspi_transfer_mode(xfer); |
| 930 | if (mode == current_mode) { |
| 931 | len += xfer->len; |
| 932 | continue; |
| 933 | } |
| 934 | |
| 935 | /* Transfer mode change */ |
| 936 | if (i) { |
| 937 | /* Set transfer data length of previous transfer */ |
| 938 | rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); |
| 939 | } |
| 940 | |
| 941 | if (i >= QSPI_NUM_SPCMD) { |
| 942 | dev_err(&msg->spi->dev, |
| 943 | "Too many different transfer modes"); |
| 944 | return -EINVAL; |
| 945 | } |
| 946 | |
| 947 | /* Program transfer mode for this transfer */ |
| 948 | rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i)); |
| 949 | current_mode = mode; |
| 950 | len = xfer->len; |
| 951 | i++; |
| 952 | } |
| 953 | if (i) { |
| 954 | /* Set final transfer data length and sequence length */ |
| 955 | rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); |
| 956 | rspi_write8(rspi, i - 1, RSPI_SPSCR); |
| 957 | } |
| 958 | |
| 959 | return 0; |
| 960 | } |
| 961 | |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 962 | static int rspi_prepare_message(struct spi_master *master, |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 963 | struct spi_message *msg) |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 964 | { |
| 965 | struct rspi_data *rspi = spi_master_get_devdata(master); |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 966 | int ret; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 967 | |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 968 | if (msg->spi->mode & |
| 969 | (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) { |
| 970 | /* Setup sequencer for messages with multiple transfer modes */ |
| 971 | ret = qspi_setup_sequencer(rspi, msg); |
| 972 | if (ret < 0) |
| 973 | return ret; |
| 974 | } |
| 975 | |
| 976 | /* Enable SPI function in master mode */ |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 977 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 978 | return 0; |
| 979 | } |
| 980 | |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 981 | static int rspi_unprepare_message(struct spi_master *master, |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 982 | struct spi_message *msg) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 983 | { |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 984 | struct rspi_data *rspi = spi_master_get_devdata(master); |
| 985 | |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 986 | /* Disable SPI function */ |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 987 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 988 | |
| 989 | /* Reset sequencer for Single SPI Transfers */ |
| 990 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); |
| 991 | rspi_write8(rspi, 0, RSPI_SPSCR); |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 992 | return 0; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 993 | } |
| 994 | |
Geert Uytterhoeven | 9372220 | 2014-01-24 09:43:58 +0100 | [diff] [blame] | 995 | static irqreturn_t rspi_irq_mux(int irq, void *_sr) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 996 | { |
Geert Uytterhoeven | c132f09 | 2013-12-24 10:49:31 +0100 | [diff] [blame] | 997 | struct rspi_data *rspi = _sr; |
Geert Uytterhoeven | 97b95c1 | 2013-12-24 10:49:34 +0100 | [diff] [blame] | 998 | u8 spsr; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 999 | irqreturn_t ret = IRQ_NONE; |
Geert Uytterhoeven | 97b95c1 | 2013-12-24 10:49:34 +0100 | [diff] [blame] | 1000 | u8 disable_irq = 0; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1001 | |
| 1002 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); |
| 1003 | if (spsr & SPSR_SPRF) |
| 1004 | disable_irq |= SPCR_SPRIE; |
| 1005 | if (spsr & SPSR_SPTEF) |
| 1006 | disable_irq |= SPCR_SPTIE; |
| 1007 | |
| 1008 | if (disable_irq) { |
| 1009 | ret = IRQ_HANDLED; |
| 1010 | rspi_disable_irq(rspi, disable_irq); |
| 1011 | wake_up(&rspi->wait); |
| 1012 | } |
| 1013 | |
| 1014 | return ret; |
| 1015 | } |
| 1016 | |
Geert Uytterhoeven | 9372220 | 2014-01-24 09:43:58 +0100 | [diff] [blame] | 1017 | static irqreturn_t rspi_irq_rx(int irq, void *_sr) |
| 1018 | { |
| 1019 | struct rspi_data *rspi = _sr; |
| 1020 | u8 spsr; |
| 1021 | |
| 1022 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); |
| 1023 | if (spsr & SPSR_SPRF) { |
| 1024 | rspi_disable_irq(rspi, SPCR_SPRIE); |
| 1025 | wake_up(&rspi->wait); |
| 1026 | return IRQ_HANDLED; |
| 1027 | } |
| 1028 | |
| 1029 | return 0; |
| 1030 | } |
| 1031 | |
| 1032 | static irqreturn_t rspi_irq_tx(int irq, void *_sr) |
| 1033 | { |
| 1034 | struct rspi_data *rspi = _sr; |
| 1035 | u8 spsr; |
| 1036 | |
| 1037 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); |
| 1038 | if (spsr & SPSR_SPTEF) { |
| 1039 | rspi_disable_irq(rspi, SPCR_SPTIE); |
| 1040 | wake_up(&rspi->wait); |
| 1041 | return IRQ_HANDLED; |
| 1042 | } |
| 1043 | |
| 1044 | return 0; |
| 1045 | } |
| 1046 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1047 | static int rspi_request_dma(struct rspi_data *rspi, |
Shimoda, Yoshihiro | 0243c53 | 2012-08-02 17:17:33 +0900 | [diff] [blame] | 1048 | struct platform_device *pdev) |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 1049 | { |
Geert Uytterhoeven | baf588f | 2013-12-24 10:49:32 +0100 | [diff] [blame] | 1050 | const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev); |
Guennadi Liakhovetski | e2b0509 | 2013-08-02 15:03:42 +0200 | [diff] [blame] | 1051 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 1052 | dma_cap_mask_t mask; |
Shimoda, Yoshihiro | 0243c53 | 2012-08-02 17:17:33 +0900 | [diff] [blame] | 1053 | struct dma_slave_config cfg; |
| 1054 | int ret; |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 1055 | |
Guennadi Liakhovetski | e2b0509 | 2013-08-02 15:03:42 +0200 | [diff] [blame] | 1056 | if (!res || !rspi_pd) |
Shimoda, Yoshihiro | 0243c53 | 2012-08-02 17:17:33 +0900 | [diff] [blame] | 1057 | return 0; /* The driver assumes no error. */ |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 1058 | |
| 1059 | rspi->dma_width_16bit = rspi_pd->dma_width_16bit; |
| 1060 | |
| 1061 | /* If the module receives data by DMAC, it also needs TX DMAC */ |
| 1062 | if (rspi_pd->dma_rx_id && rspi_pd->dma_tx_id) { |
| 1063 | dma_cap_zero(mask); |
| 1064 | dma_cap_set(DMA_SLAVE, mask); |
Shimoda, Yoshihiro | 0243c53 | 2012-08-02 17:17:33 +0900 | [diff] [blame] | 1065 | rspi->chan_rx = dma_request_channel(mask, shdma_chan_filter, |
| 1066 | (void *)rspi_pd->dma_rx_id); |
| 1067 | if (rspi->chan_rx) { |
| 1068 | cfg.slave_id = rspi_pd->dma_rx_id; |
| 1069 | cfg.direction = DMA_DEV_TO_MEM; |
Guennadi Liakhovetski | e2b0509 | 2013-08-02 15:03:42 +0200 | [diff] [blame] | 1070 | cfg.dst_addr = 0; |
| 1071 | cfg.src_addr = res->start + RSPI_SPDR; |
Shimoda, Yoshihiro | 0243c53 | 2012-08-02 17:17:33 +0900 | [diff] [blame] | 1072 | ret = dmaengine_slave_config(rspi->chan_rx, &cfg); |
| 1073 | if (!ret) |
| 1074 | dev_info(&pdev->dev, "Use DMA when rx.\n"); |
| 1075 | else |
| 1076 | return ret; |
| 1077 | } |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 1078 | } |
| 1079 | if (rspi_pd->dma_tx_id) { |
| 1080 | dma_cap_zero(mask); |
| 1081 | dma_cap_set(DMA_SLAVE, mask); |
Shimoda, Yoshihiro | 0243c53 | 2012-08-02 17:17:33 +0900 | [diff] [blame] | 1082 | rspi->chan_tx = dma_request_channel(mask, shdma_chan_filter, |
| 1083 | (void *)rspi_pd->dma_tx_id); |
| 1084 | if (rspi->chan_tx) { |
| 1085 | cfg.slave_id = rspi_pd->dma_tx_id; |
| 1086 | cfg.direction = DMA_MEM_TO_DEV; |
Guennadi Liakhovetski | e2b0509 | 2013-08-02 15:03:42 +0200 | [diff] [blame] | 1087 | cfg.dst_addr = res->start + RSPI_SPDR; |
| 1088 | cfg.src_addr = 0; |
Shimoda, Yoshihiro | 0243c53 | 2012-08-02 17:17:33 +0900 | [diff] [blame] | 1089 | ret = dmaengine_slave_config(rspi->chan_tx, &cfg); |
| 1090 | if (!ret) |
| 1091 | dev_info(&pdev->dev, "Use DMA when tx\n"); |
| 1092 | else |
| 1093 | return ret; |
| 1094 | } |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 1095 | } |
Shimoda, Yoshihiro | 0243c53 | 2012-08-02 17:17:33 +0900 | [diff] [blame] | 1096 | |
| 1097 | return 0; |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 1098 | } |
| 1099 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1100 | static void rspi_release_dma(struct rspi_data *rspi) |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 1101 | { |
| 1102 | if (rspi->chan_tx) |
| 1103 | dma_release_channel(rspi->chan_tx); |
| 1104 | if (rspi->chan_rx) |
| 1105 | dma_release_channel(rspi->chan_rx); |
| 1106 | } |
| 1107 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1108 | static int rspi_remove(struct platform_device *pdev) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1109 | { |
Laurent Pinchart | 5ffbe2d | 2013-11-27 01:41:45 +0100 | [diff] [blame] | 1110 | struct rspi_data *rspi = platform_get_drvdata(pdev); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1111 | |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 1112 | rspi_release_dma(rspi); |
Geert Uytterhoeven | 17fe0d9 | 2014-01-24 09:44:01 +0100 | [diff] [blame] | 1113 | clk_disable_unprepare(rspi->clk); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1114 | |
| 1115 | return 0; |
| 1116 | } |
| 1117 | |
Geert Uytterhoeven | 426ef76 | 2014-01-28 10:21:38 +0100 | [diff] [blame] | 1118 | static const struct spi_ops rspi_ops = { |
| 1119 | .set_config_register = rspi_set_config_register, |
| 1120 | .transfer_one = rspi_transfer_one, |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 1121 | .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, |
Geert Uytterhoeven | 426ef76 | 2014-01-28 10:21:38 +0100 | [diff] [blame] | 1122 | }; |
| 1123 | |
| 1124 | static const struct spi_ops rspi_rz_ops = { |
| 1125 | .set_config_register = rspi_rz_set_config_register, |
| 1126 | .transfer_one = rspi_rz_transfer_one, |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 1127 | .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, |
Geert Uytterhoeven | 426ef76 | 2014-01-28 10:21:38 +0100 | [diff] [blame] | 1128 | }; |
| 1129 | |
| 1130 | static const struct spi_ops qspi_ops = { |
| 1131 | .set_config_register = qspi_set_config_register, |
| 1132 | .transfer_one = qspi_transfer_one, |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 1133 | .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP | |
| 1134 | SPI_TX_DUAL | SPI_TX_QUAD | |
| 1135 | SPI_RX_DUAL | SPI_RX_QUAD, |
Geert Uytterhoeven | 426ef76 | 2014-01-28 10:21:38 +0100 | [diff] [blame] | 1136 | }; |
| 1137 | |
| 1138 | #ifdef CONFIG_OF |
| 1139 | static const struct of_device_id rspi_of_match[] = { |
| 1140 | /* RSPI on legacy SH */ |
| 1141 | { .compatible = "renesas,rspi", .data = &rspi_ops }, |
| 1142 | /* RSPI on RZ/A1H */ |
| 1143 | { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops }, |
| 1144 | /* QSPI on R-Car Gen2 */ |
| 1145 | { .compatible = "renesas,qspi", .data = &qspi_ops }, |
| 1146 | { /* sentinel */ } |
| 1147 | }; |
| 1148 | |
| 1149 | MODULE_DEVICE_TABLE(of, rspi_of_match); |
| 1150 | |
| 1151 | static int rspi_parse_dt(struct device *dev, struct spi_master *master) |
| 1152 | { |
| 1153 | u32 num_cs; |
| 1154 | int error; |
| 1155 | |
| 1156 | /* Parse DT properties */ |
| 1157 | error = of_property_read_u32(dev->of_node, "num-cs", &num_cs); |
| 1158 | if (error) { |
| 1159 | dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error); |
| 1160 | return error; |
| 1161 | } |
| 1162 | |
| 1163 | master->num_chipselect = num_cs; |
| 1164 | return 0; |
| 1165 | } |
| 1166 | #else |
Shimoda, Yoshihiro | 64b67de | 2014-02-03 10:43:46 +0900 | [diff] [blame^] | 1167 | #define rspi_of_match NULL |
Geert Uytterhoeven | 426ef76 | 2014-01-28 10:21:38 +0100 | [diff] [blame] | 1168 | static inline int rspi_parse_dt(struct device *dev, struct spi_master *master) |
| 1169 | { |
| 1170 | return -EINVAL; |
| 1171 | } |
| 1172 | #endif /* CONFIG_OF */ |
| 1173 | |
Geert Uytterhoeven | 9372220 | 2014-01-24 09:43:58 +0100 | [diff] [blame] | 1174 | static int rspi_request_irq(struct device *dev, unsigned int irq, |
| 1175 | irq_handler_t handler, const char *suffix, |
| 1176 | void *dev_id) |
| 1177 | { |
| 1178 | const char *base = dev_name(dev); |
| 1179 | size_t len = strlen(base) + strlen(suffix) + 2; |
| 1180 | char *name = devm_kzalloc(dev, len, GFP_KERNEL); |
| 1181 | if (!name) |
| 1182 | return -ENOMEM; |
| 1183 | snprintf(name, len, "%s:%s", base, suffix); |
| 1184 | return devm_request_irq(dev, irq, handler, 0, name, dev_id); |
| 1185 | } |
| 1186 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1187 | static int rspi_probe(struct platform_device *pdev) |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1188 | { |
| 1189 | struct resource *res; |
| 1190 | struct spi_master *master; |
| 1191 | struct rspi_data *rspi; |
Geert Uytterhoeven | 9372220 | 2014-01-24 09:43:58 +0100 | [diff] [blame] | 1192 | int ret; |
Geert Uytterhoeven | 426ef76 | 2014-01-28 10:21:38 +0100 | [diff] [blame] | 1193 | const struct of_device_id *of_id; |
| 1194 | const struct rspi_plat_data *rspi_pd; |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 1195 | const struct spi_ops *ops; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1196 | |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1197 | master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); |
| 1198 | if (master == NULL) { |
| 1199 | dev_err(&pdev->dev, "spi_alloc_master error.\n"); |
| 1200 | return -ENOMEM; |
| 1201 | } |
| 1202 | |
Geert Uytterhoeven | 426ef76 | 2014-01-28 10:21:38 +0100 | [diff] [blame] | 1203 | of_id = of_match_device(rspi_of_match, &pdev->dev); |
| 1204 | if (of_id) { |
| 1205 | ops = of_id->data; |
| 1206 | ret = rspi_parse_dt(&pdev->dev, master); |
| 1207 | if (ret) |
| 1208 | goto error1; |
| 1209 | } else { |
| 1210 | ops = (struct spi_ops *)pdev->id_entry->driver_data; |
| 1211 | rspi_pd = dev_get_platdata(&pdev->dev); |
| 1212 | if (rspi_pd && rspi_pd->num_chipselect) |
| 1213 | master->num_chipselect = rspi_pd->num_chipselect; |
| 1214 | else |
| 1215 | master->num_chipselect = 2; /* default */ |
| 1216 | }; |
| 1217 | |
| 1218 | /* ops parameter check */ |
| 1219 | if (!ops->set_config_register) { |
| 1220 | dev_err(&pdev->dev, "there is no set_config_register\n"); |
| 1221 | ret = -ENODEV; |
| 1222 | goto error1; |
| 1223 | } |
| 1224 | |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1225 | rspi = spi_master_get_devdata(master); |
Jingoo Han | 24b5a82 | 2013-05-23 19:20:40 +0900 | [diff] [blame] | 1226 | platform_set_drvdata(pdev, rspi); |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 1227 | rspi->ops = ops; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1228 | rspi->master = master; |
Laurent Pinchart | 5d79e9a | 2013-11-27 01:41:46 +0100 | [diff] [blame] | 1229 | |
| 1230 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1231 | rspi->addr = devm_ioremap_resource(&pdev->dev, res); |
| 1232 | if (IS_ERR(rspi->addr)) { |
| 1233 | ret = PTR_ERR(rspi->addr); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1234 | goto error1; |
| 1235 | } |
| 1236 | |
Geert Uytterhoeven | 29f397b | 2014-01-24 09:44:02 +0100 | [diff] [blame] | 1237 | rspi->clk = devm_clk_get(&pdev->dev, NULL); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1238 | if (IS_ERR(rspi->clk)) { |
| 1239 | dev_err(&pdev->dev, "cannot get clock\n"); |
| 1240 | ret = PTR_ERR(rspi->clk); |
Laurent Pinchart | 5d79e9a | 2013-11-27 01:41:46 +0100 | [diff] [blame] | 1241 | goto error1; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1242 | } |
Geert Uytterhoeven | 17fe0d9 | 2014-01-24 09:44:01 +0100 | [diff] [blame] | 1243 | |
| 1244 | ret = clk_prepare_enable(rspi->clk); |
| 1245 | if (ret < 0) { |
| 1246 | dev_err(&pdev->dev, "unable to prepare/enable clock\n"); |
| 1247 | goto error1; |
| 1248 | } |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1249 | |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1250 | init_waitqueue_head(&rspi->wait); |
| 1251 | |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1252 | master->bus_num = pdev->id; |
| 1253 | master->setup = rspi_setup; |
Geert Uytterhoeven | eb557f7 | 2014-01-24 09:43:55 +0100 | [diff] [blame] | 1254 | master->transfer_one = ops->transfer_one; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1255 | master->cleanup = rspi_cleanup; |
Geert Uytterhoeven | 79d2349 | 2014-01-24 09:43:52 +0100 | [diff] [blame] | 1256 | master->prepare_message = rspi_prepare_message; |
| 1257 | master->unprepare_message = rspi_unprepare_message; |
Geert Uytterhoeven | 880c6d1 | 2014-01-30 09:43:50 +0100 | [diff] [blame] | 1258 | master->mode_bits = ops->mode_bits; |
Geert Uytterhoeven | 426ef76 | 2014-01-28 10:21:38 +0100 | [diff] [blame] | 1259 | master->dev.of_node = pdev->dev.of_node; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1260 | |
Geert Uytterhoeven | 9372220 | 2014-01-24 09:43:58 +0100 | [diff] [blame] | 1261 | ret = platform_get_irq_byname(pdev, "rx"); |
| 1262 | if (ret < 0) { |
| 1263 | ret = platform_get_irq_byname(pdev, "mux"); |
| 1264 | if (ret < 0) |
| 1265 | ret = platform_get_irq(pdev, 0); |
| 1266 | if (ret >= 0) |
| 1267 | rspi->rx_irq = rspi->tx_irq = ret; |
| 1268 | } else { |
| 1269 | rspi->rx_irq = ret; |
| 1270 | ret = platform_get_irq_byname(pdev, "tx"); |
| 1271 | if (ret >= 0) |
| 1272 | rspi->tx_irq = ret; |
| 1273 | } |
| 1274 | if (ret < 0) { |
| 1275 | dev_err(&pdev->dev, "platform_get_irq error\n"); |
| 1276 | goto error2; |
| 1277 | } |
| 1278 | |
| 1279 | if (rspi->rx_irq == rspi->tx_irq) { |
| 1280 | /* Single multiplexed interrupt */ |
| 1281 | ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux, |
| 1282 | "mux", rspi); |
| 1283 | } else { |
| 1284 | /* Multi-interrupt mode, only SPRI and SPTI are used */ |
| 1285 | ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx, |
| 1286 | "rx", rspi); |
| 1287 | if (!ret) |
| 1288 | ret = rspi_request_irq(&pdev->dev, rspi->tx_irq, |
| 1289 | rspi_irq_tx, "tx", rspi); |
| 1290 | } |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1291 | if (ret < 0) { |
| 1292 | dev_err(&pdev->dev, "request_irq error\n"); |
Geert Uytterhoeven | fcb4ed7 | 2014-01-14 10:20:33 +0100 | [diff] [blame] | 1293 | goto error2; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1294 | } |
| 1295 | |
Shimoda, Yoshihiro | 0243c53 | 2012-08-02 17:17:33 +0900 | [diff] [blame] | 1296 | ret = rspi_request_dma(rspi, pdev); |
| 1297 | if (ret < 0) { |
| 1298 | dev_err(&pdev->dev, "rspi_request_dma failed.\n"); |
Geert Uytterhoeven | fcb4ed7 | 2014-01-14 10:20:33 +0100 | [diff] [blame] | 1299 | goto error3; |
Shimoda, Yoshihiro | 0243c53 | 2012-08-02 17:17:33 +0900 | [diff] [blame] | 1300 | } |
Shimoda, Yoshihiro | a3633fe | 2012-04-20 14:50:36 +0900 | [diff] [blame] | 1301 | |
Jingoo Han | 9e03d05 | 2013-12-04 14:13:50 +0900 | [diff] [blame] | 1302 | ret = devm_spi_register_master(&pdev->dev, master); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1303 | if (ret < 0) { |
| 1304 | dev_err(&pdev->dev, "spi_register_master error.\n"); |
Geert Uytterhoeven | fcb4ed7 | 2014-01-14 10:20:33 +0100 | [diff] [blame] | 1305 | goto error3; |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1306 | } |
| 1307 | |
| 1308 | dev_info(&pdev->dev, "probed\n"); |
| 1309 | |
| 1310 | return 0; |
| 1311 | |
Geert Uytterhoeven | fcb4ed7 | 2014-01-14 10:20:33 +0100 | [diff] [blame] | 1312 | error3: |
Laurent Pinchart | 5d79e9a | 2013-11-27 01:41:46 +0100 | [diff] [blame] | 1313 | rspi_release_dma(rspi); |
Geert Uytterhoeven | fcb4ed7 | 2014-01-14 10:20:33 +0100 | [diff] [blame] | 1314 | error2: |
Geert Uytterhoeven | 17fe0d9 | 2014-01-24 09:44:01 +0100 | [diff] [blame] | 1315 | clk_disable_unprepare(rspi->clk); |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1316 | error1: |
| 1317 | spi_master_put(master); |
| 1318 | |
| 1319 | return ret; |
| 1320 | } |
| 1321 | |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 1322 | static struct platform_device_id spi_driver_ids[] = { |
| 1323 | { "rspi", (kernel_ulong_t)&rspi_ops }, |
Geert Uytterhoeven | 862d357 | 2014-01-24 09:43:59 +0100 | [diff] [blame] | 1324 | { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops }, |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 1325 | { "qspi", (kernel_ulong_t)&qspi_ops }, |
| 1326 | {}, |
| 1327 | }; |
| 1328 | |
| 1329 | MODULE_DEVICE_TABLE(platform, spi_driver_ids); |
| 1330 | |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1331 | static struct platform_driver rspi_driver = { |
| 1332 | .probe = rspi_probe, |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1333 | .remove = rspi_remove, |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 1334 | .id_table = spi_driver_ids, |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1335 | .driver = { |
Hiep Cao Minh | 5ce0ba8 | 2013-09-03 13:10:26 +0900 | [diff] [blame] | 1336 | .name = "renesas_spi", |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1337 | .owner = THIS_MODULE, |
Geert Uytterhoeven | 426ef76 | 2014-01-28 10:21:38 +0100 | [diff] [blame] | 1338 | .of_match_table = of_match_ptr(rspi_of_match), |
Shimoda, Yoshihiro | 0b2182d | 2012-03-07 14:46:25 +0900 | [diff] [blame] | 1339 | }, |
| 1340 | }; |
| 1341 | module_platform_driver(rspi_driver); |
| 1342 | |
| 1343 | MODULE_DESCRIPTION("Renesas RSPI bus driver"); |
| 1344 | MODULE_LICENSE("GPL v2"); |
| 1345 | MODULE_AUTHOR("Yoshihiro Shimoda"); |
| 1346 | MODULE_ALIAS("platform:rspi"); |