Paul Gortmaker | 69c60c8 | 2011-05-26 12:22:53 -0400 | [diff] [blame] | 1 | #include <linux/export.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | #include <linux/init.h> |
| 3 | #include <linux/bitops.h> |
Stephen Rothwell | 5cdd174 | 2011-08-10 11:49:56 +1000 | [diff] [blame] | 4 | #include <linux/elf.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | #include <linux/mm.h> |
Yinghai Lu | 8d71a2e | 2008-09-07 17:58:53 -0700 | [diff] [blame] | 6 | |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 7 | #include <linux/io.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | #include <asm/processor.h> |
Andi Kleen | d3f7eae | 2007-08-10 22:31:07 +0200 | [diff] [blame] | 9 | #include <asm/apic.h> |
Yinghai Lu | 1f442d7 | 2009-03-07 23:46:26 -0800 | [diff] [blame] | 10 | #include <asm/cpu.h> |
Andreas Herrmann | 42937e8 | 2009-06-08 15:55:09 +0200 | [diff] [blame] | 11 | #include <asm/pci-direct.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12 | |
Yinghai Lu | 8d71a2e | 2008-09-07 17:58:53 -0700 | [diff] [blame] | 13 | #ifdef CONFIG_X86_64 |
| 14 | # include <asm/numa_64.h> |
| 15 | # include <asm/mmconfig.h> |
| 16 | # include <asm/cacheflush.h> |
| 17 | #endif |
| 18 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 19 | #include "cpu.h" |
| 20 | |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 21 | #ifdef CONFIG_X86_32 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | /* |
| 23 | * B step AMD K6 before B 9730xxxx have hardware bugs that can cause |
| 24 | * misexecution of code under Linux. Owners of such processors should |
| 25 | * contact AMD for precise details and a CPU swap. |
| 26 | * |
| 27 | * See http://www.multimania.com/poulot/k6bug.html |
| 28 | * http://www.amd.com/K6/k6docs/revgd.html |
| 29 | * |
| 30 | * The following test is erm.. interesting. AMD neglected to up |
| 31 | * the chip setting when fixing the bug but they also tweaked some |
| 32 | * performance at the same time.. |
| 33 | */ |
Paolo Ciarrocchi | fb87a29 | 2008-02-22 23:10:33 +0100 | [diff] [blame] | 34 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | extern void vide(void); |
| 36 | __asm__(".align 4\nvide: ret"); |
| 37 | |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 38 | static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c) |
| 39 | { |
| 40 | /* |
| 41 | * General Systems BIOSen alias the cpu frequency registers |
| 42 | * of the Elan at 0x000df000. Unfortuantly, one of the Linux |
| 43 | * drivers subsequently pokes it, and changes the CPU speed. |
| 44 | * Workaround : Remove the unneeded alias. |
| 45 | */ |
| 46 | #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ |
| 47 | #define CBAR_ENB (0x80000000) |
| 48 | #define CBAR_KEY (0X000000CB) |
| 49 | if (c->x86_model == 9 || c->x86_model == 10) { |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 50 | if (inl(CBAR) & CBAR_ENB) |
| 51 | outl(0 | CBAR_KEY, CBAR); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 52 | } |
| 53 | } |
| 54 | |
| 55 | |
| 56 | static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c) |
| 57 | { |
| 58 | u32 l, h; |
| 59 | int mbytes = num_physpages >> (20-PAGE_SHIFT); |
| 60 | |
| 61 | if (c->x86_model < 6) { |
| 62 | /* Based on AMD doc 20734R - June 2000 */ |
| 63 | if (c->x86_model == 0) { |
| 64 | clear_cpu_cap(c, X86_FEATURE_APIC); |
| 65 | set_cpu_cap(c, X86_FEATURE_PGE); |
| 66 | } |
| 67 | return; |
| 68 | } |
| 69 | |
| 70 | if (c->x86_model == 6 && c->x86_mask == 1) { |
| 71 | const int K6_BUG_LOOP = 1000000; |
| 72 | int n; |
| 73 | void (*f_vide)(void); |
| 74 | unsigned long d, d2; |
| 75 | |
| 76 | printk(KERN_INFO "AMD K6 stepping B detected - "); |
| 77 | |
| 78 | /* |
| 79 | * It looks like AMD fixed the 2.6.2 bug and improved indirect |
| 80 | * calls at the same time. |
| 81 | */ |
| 82 | |
| 83 | n = K6_BUG_LOOP; |
| 84 | f_vide = vide; |
| 85 | rdtscl(d); |
| 86 | while (n--) |
| 87 | f_vide(); |
| 88 | rdtscl(d2); |
| 89 | d = d2-d; |
| 90 | |
| 91 | if (d > 20*K6_BUG_LOOP) |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 92 | printk(KERN_CONT |
| 93 | "system stability may be impaired when more than 32 MB are used.\n"); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 94 | else |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 95 | printk(KERN_CONT "probably OK (after B9730xxxx).\n"); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 96 | printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n"); |
| 97 | } |
| 98 | |
| 99 | /* K6 with old style WHCR */ |
| 100 | if (c->x86_model < 8 || |
| 101 | (c->x86_model == 8 && c->x86_mask < 8)) { |
| 102 | /* We can only write allocate on the low 508Mb */ |
| 103 | if (mbytes > 508) |
| 104 | mbytes = 508; |
| 105 | |
| 106 | rdmsr(MSR_K6_WHCR, l, h); |
| 107 | if ((l&0x0000FFFF) == 0) { |
| 108 | unsigned long flags; |
| 109 | l = (1<<0)|((mbytes/4)<<1); |
| 110 | local_irq_save(flags); |
| 111 | wbinvd(); |
| 112 | wrmsr(MSR_K6_WHCR, l, h); |
| 113 | local_irq_restore(flags); |
| 114 | printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", |
| 115 | mbytes); |
| 116 | } |
| 117 | return; |
| 118 | } |
| 119 | |
| 120 | if ((c->x86_model == 8 && c->x86_mask > 7) || |
| 121 | c->x86_model == 9 || c->x86_model == 13) { |
| 122 | /* The more serious chips .. */ |
| 123 | |
| 124 | if (mbytes > 4092) |
| 125 | mbytes = 4092; |
| 126 | |
| 127 | rdmsr(MSR_K6_WHCR, l, h); |
| 128 | if ((l&0xFFFF0000) == 0) { |
| 129 | unsigned long flags; |
| 130 | l = ((mbytes>>2)<<22)|(1<<16); |
| 131 | local_irq_save(flags); |
| 132 | wbinvd(); |
| 133 | wrmsr(MSR_K6_WHCR, l, h); |
| 134 | local_irq_restore(flags); |
| 135 | printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", |
| 136 | mbytes); |
| 137 | } |
| 138 | |
| 139 | return; |
| 140 | } |
| 141 | |
| 142 | if (c->x86_model == 10) { |
| 143 | /* AMD Geode LX is model 10 */ |
| 144 | /* placeholder for any needed mods */ |
| 145 | return; |
| 146 | } |
| 147 | } |
| 148 | |
Yinghai Lu | 1f442d7 | 2009-03-07 23:46:26 -0800 | [diff] [blame] | 149 | static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c) |
| 150 | { |
| 151 | #ifdef CONFIG_SMP |
| 152 | /* calling is from identify_secondary_cpu() ? */ |
Robert Richter | f6e9456c | 2010-07-21 19:03:58 +0200 | [diff] [blame] | 153 | if (!c->cpu_index) |
Yinghai Lu | 1f442d7 | 2009-03-07 23:46:26 -0800 | [diff] [blame] | 154 | return; |
| 155 | |
| 156 | /* |
| 157 | * Certain Athlons might work (for various values of 'work') in SMP |
| 158 | * but they are not certified as MP capable. |
| 159 | */ |
| 160 | /* Athlon 660/661 is valid. */ |
| 161 | if ((c->x86_model == 6) && ((c->x86_mask == 0) || |
| 162 | (c->x86_mask == 1))) |
| 163 | goto valid_k7; |
| 164 | |
| 165 | /* Duron 670 is valid */ |
| 166 | if ((c->x86_model == 7) && (c->x86_mask == 0)) |
| 167 | goto valid_k7; |
| 168 | |
| 169 | /* |
| 170 | * Athlon 662, Duron 671, and Athlon >model 7 have capability |
| 171 | * bit. It's worth noting that the A5 stepping (662) of some |
| 172 | * Athlon XP's have the MP bit set. |
| 173 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for |
| 174 | * more. |
| 175 | */ |
| 176 | if (((c->x86_model == 6) && (c->x86_mask >= 2)) || |
| 177 | ((c->x86_model == 7) && (c->x86_mask >= 1)) || |
| 178 | (c->x86_model > 7)) |
| 179 | if (cpu_has_mp) |
| 180 | goto valid_k7; |
| 181 | |
| 182 | /* If we get here, not a certified SMP capable AMD system. */ |
| 183 | |
| 184 | /* |
| 185 | * Don't taint if we are running SMP kernel on a single non-MP |
| 186 | * approved Athlon |
| 187 | */ |
| 188 | WARN_ONCE(1, "WARNING: This combination of AMD" |
Michael Tokarev | 7da8b6d | 2009-07-22 17:50:23 +0400 | [diff] [blame] | 189 | " processors is not suitable for SMP.\n"); |
Yinghai Lu | 1f442d7 | 2009-03-07 23:46:26 -0800 | [diff] [blame] | 190 | if (!test_taint(TAINT_UNSAFE_SMP)) |
| 191 | add_taint(TAINT_UNSAFE_SMP); |
| 192 | |
| 193 | valid_k7: |
| 194 | ; |
| 195 | #endif |
| 196 | } |
| 197 | |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 198 | static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c) |
| 199 | { |
| 200 | u32 l, h; |
| 201 | |
| 202 | /* |
| 203 | * Bit 15 of Athlon specific MSR 15, needs to be 0 |
| 204 | * to enable SSE on Palomino/Morgan/Barton CPU's. |
| 205 | * If the BIOS didn't enable it already, enable it here. |
| 206 | */ |
| 207 | if (c->x86_model >= 6 && c->x86_model <= 10) { |
| 208 | if (!cpu_has(c, X86_FEATURE_XMM)) { |
| 209 | printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); |
| 210 | rdmsr(MSR_K7_HWCR, l, h); |
| 211 | l &= ~0x00008000; |
| 212 | wrmsr(MSR_K7_HWCR, l, h); |
| 213 | set_cpu_cap(c, X86_FEATURE_XMM); |
| 214 | } |
| 215 | } |
| 216 | |
| 217 | /* |
| 218 | * It's been determined by AMD that Athlons since model 8 stepping 1 |
| 219 | * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx |
| 220 | * As per AMD technical note 27212 0.2 |
| 221 | */ |
| 222 | if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { |
| 223 | rdmsr(MSR_K7_CLK_CTL, l, h); |
| 224 | if ((l & 0xfff00000) != 0x20000000) { |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 225 | printk(KERN_INFO |
| 226 | "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", |
| 227 | l, ((l & 0x000fffff)|0x20000000)); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 228 | wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); |
| 229 | } |
| 230 | } |
| 231 | |
| 232 | set_cpu_cap(c, X86_FEATURE_K7); |
Yinghai Lu | 1f442d7 | 2009-03-07 23:46:26 -0800 | [diff] [blame] | 233 | |
| 234 | amd_k7_smp_check(c); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 235 | } |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 236 | #endif |
| 237 | |
Tejun Heo | 645a791 | 2011-01-23 14:37:40 +0100 | [diff] [blame] | 238 | #ifdef CONFIG_NUMA |
Tejun Heo | bbc9e2f | 2011-01-23 14:37:39 +0100 | [diff] [blame] | 239 | /* |
| 240 | * To workaround broken NUMA config. Read the comment in |
| 241 | * srat_detect_node(). |
| 242 | */ |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 243 | static int __cpuinit nearby_node(int apicid) |
| 244 | { |
| 245 | int i, node; |
| 246 | |
| 247 | for (i = apicid - 1; i >= 0; i--) { |
Tejun Heo | bbc9e2f | 2011-01-23 14:37:39 +0100 | [diff] [blame] | 248 | node = __apicid_to_node[i]; |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 249 | if (node != NUMA_NO_NODE && node_online(node)) |
| 250 | return node; |
| 251 | } |
| 252 | for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { |
Tejun Heo | bbc9e2f | 2011-01-23 14:37:39 +0100 | [diff] [blame] | 253 | node = __apicid_to_node[i]; |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 254 | if (node != NUMA_NO_NODE && node_online(node)) |
| 255 | return node; |
| 256 | } |
| 257 | return first_node(node_online_map); /* Shouldn't happen */ |
| 258 | } |
| 259 | #endif |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 260 | |
| 261 | /* |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 262 | * Fixup core topology information for |
| 263 | * (1) AMD multi-node processors |
| 264 | * Assumption: Number of cores in each internal node is the same. |
Andreas Herrmann | 6057b4d | 2010-09-30 14:38:57 +0200 | [diff] [blame] | 265 | * (2) AMD processors supporting compute units |
Andreas Herrmann | 4a376ec | 2009-09-03 09:40:21 +0200 | [diff] [blame] | 266 | */ |
| 267 | #ifdef CONFIG_X86_HT |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 268 | static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) |
Andreas Herrmann | 4a376ec | 2009-09-03 09:40:21 +0200 | [diff] [blame] | 269 | { |
Borislav Petkov | 9e81509 | 2011-02-14 18:14:51 +0100 | [diff] [blame] | 270 | u32 nodes, cores_per_cu = 1; |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 271 | u8 node_id; |
Andreas Herrmann | 4a376ec | 2009-09-03 09:40:21 +0200 | [diff] [blame] | 272 | int cpu = smp_processor_id(); |
| 273 | |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 274 | /* get information required for multi-node processors */ |
| 275 | if (cpu_has(c, X86_FEATURE_TOPOEXT)) { |
Andreas Herrmann | 6057b4d | 2010-09-30 14:38:57 +0200 | [diff] [blame] | 276 | u32 eax, ebx, ecx, edx; |
| 277 | |
| 278 | cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); |
| 279 | nodes = ((ecx >> 8) & 7) + 1; |
| 280 | node_id = ecx & 7; |
| 281 | |
| 282 | /* get compute unit information */ |
| 283 | smp_num_siblings = ((ebx >> 8) & 3) + 1; |
| 284 | c->compute_unit_id = ebx & 0xff; |
Borislav Petkov | 9e81509 | 2011-02-14 18:14:51 +0100 | [diff] [blame] | 285 | cores_per_cu += ((ebx >> 8) & 3); |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 286 | } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { |
Andreas Herrmann | 6057b4d | 2010-09-30 14:38:57 +0200 | [diff] [blame] | 287 | u64 value; |
| 288 | |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 289 | rdmsrl(MSR_FAM10H_NODE_ID, value); |
| 290 | nodes = ((value >> 3) & 7) + 1; |
| 291 | node_id = value & 7; |
| 292 | } else |
Andreas Herrmann | 9d260eb | 2009-12-16 15:43:55 +0100 | [diff] [blame] | 293 | return; |
| 294 | |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 295 | /* fixup multi-node processor information */ |
| 296 | if (nodes > 1) { |
Andreas Herrmann | 6057b4d | 2010-09-30 14:38:57 +0200 | [diff] [blame] | 297 | u32 cores_per_node; |
Andreas Herrmann | d518573 | 2011-01-24 16:05:40 +0100 | [diff] [blame] | 298 | u32 cus_per_node; |
Andreas Herrmann | 6057b4d | 2010-09-30 14:38:57 +0200 | [diff] [blame] | 299 | |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 300 | set_cpu_cap(c, X86_FEATURE_AMD_DCM); |
| 301 | cores_per_node = c->x86_max_cores / nodes; |
Andreas Herrmann | d518573 | 2011-01-24 16:05:40 +0100 | [diff] [blame] | 302 | cus_per_node = cores_per_node / cores_per_cu; |
Andreas Herrmann | 4a376ec | 2009-09-03 09:40:21 +0200 | [diff] [blame] | 303 | |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 304 | /* store NodeID, use llc_shared_map to store sibling info */ |
| 305 | per_cpu(cpu_llc_id, cpu) = node_id; |
Andreas Herrmann | 9d260eb | 2009-12-16 15:43:55 +0100 | [diff] [blame] | 306 | |
Borislav Petkov | 9e81509 | 2011-02-14 18:14:51 +0100 | [diff] [blame] | 307 | /* core id has to be in the [0 .. cores_per_node - 1] range */ |
Andreas Herrmann | d518573 | 2011-01-24 16:05:40 +0100 | [diff] [blame] | 308 | c->cpu_core_id %= cores_per_node; |
| 309 | c->compute_unit_id %= cus_per_node; |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 310 | } |
Andreas Herrmann | 4a376ec | 2009-09-03 09:40:21 +0200 | [diff] [blame] | 311 | } |
| 312 | #endif |
| 313 | |
| 314 | /* |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 315 | * On a AMD dual core setup the lower bits of the APIC id distingush the cores. |
| 316 | * Assumes number of cores is a power of two. |
| 317 | */ |
| 318 | static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c) |
| 319 | { |
| 320 | #ifdef CONFIG_X86_HT |
| 321 | unsigned bits; |
Andreas Herrmann | 99bd0c0 | 2009-06-19 10:59:09 +0200 | [diff] [blame] | 322 | int cpu = smp_processor_id(); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 323 | |
| 324 | bits = c->x86_coreid_bits; |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 325 | /* Low order bits define the core id (index of core in socket) */ |
| 326 | c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); |
| 327 | /* Convert the initial APIC ID into the socket ID */ |
| 328 | c->phys_proc_id = c->initial_apicid >> bits; |
Andreas Herrmann | 99bd0c0 | 2009-06-19 10:59:09 +0200 | [diff] [blame] | 329 | /* use socket ID also for last level cache */ |
| 330 | per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 331 | amd_get_topology(c); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 332 | #endif |
| 333 | } |
| 334 | |
Andreas Herrmann | 6a81269 | 2009-09-16 11:33:40 +0200 | [diff] [blame] | 335 | int amd_get_nb_id(int cpu) |
| 336 | { |
| 337 | int id = 0; |
| 338 | #ifdef CONFIG_SMP |
| 339 | id = per_cpu(cpu_llc_id, cpu); |
| 340 | #endif |
| 341 | return id; |
| 342 | } |
| 343 | EXPORT_SYMBOL_GPL(amd_get_nb_id); |
| 344 | |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 345 | static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c) |
| 346 | { |
Tejun Heo | 645a791 | 2011-01-23 14:37:40 +0100 | [diff] [blame] | 347 | #ifdef CONFIG_NUMA |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 348 | int cpu = smp_processor_id(); |
| 349 | int node; |
Yinghai Lu | 0d96b9f | 2009-08-29 13:17:14 -0700 | [diff] [blame] | 350 | unsigned apicid = c->apicid; |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 351 | |
Tejun Heo | bbc9e2f | 2011-01-23 14:37:39 +0100 | [diff] [blame] | 352 | node = numa_cpu_node(cpu); |
| 353 | if (node == NUMA_NO_NODE) |
| 354 | node = per_cpu(cpu_llc_id, cpu); |
Andreas Herrmann | 4a376ec | 2009-09-03 09:40:21 +0200 | [diff] [blame] | 355 | |
Daniel J Blueman | 64be4c1 | 2011-12-05 16:20:37 +0800 | [diff] [blame^] | 356 | /* |
| 357 | * If core numbers are inconsistent, it's likely a multi-fabric platform, |
| 358 | * so invoke platform-specific handler |
| 359 | */ |
| 360 | if (c->phys_proc_id != node) |
| 361 | x86_cpuinit.fixup_cpu_id(c, node); |
| 362 | |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 363 | if (!node_online(node)) { |
Tejun Heo | bbc9e2f | 2011-01-23 14:37:39 +0100 | [diff] [blame] | 364 | /* |
| 365 | * Two possibilities here: |
| 366 | * |
| 367 | * - The CPU is missing memory and no node was created. In |
| 368 | * that case try picking one from a nearby CPU. |
| 369 | * |
| 370 | * - The APIC IDs differ from the HyperTransport node IDs |
| 371 | * which the K8 northbridge parsing fills in. Assume |
| 372 | * they are all increased by a constant offset, but in |
| 373 | * the same order as the HT nodeids. If that doesn't |
| 374 | * result in a usable node fall back to the path for the |
| 375 | * previous case. |
| 376 | * |
| 377 | * This workaround operates directly on the mapping between |
| 378 | * APIC ID and NUMA node, assuming certain relationship |
| 379 | * between APIC ID, HT node ID and NUMA topology. As going |
| 380 | * through CPU mapping may alter the outcome, directly |
| 381 | * access __apicid_to_node[]. |
| 382 | */ |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 383 | int ht_nodeid = c->initial_apicid; |
| 384 | |
| 385 | if (ht_nodeid >= 0 && |
Tejun Heo | bbc9e2f | 2011-01-23 14:37:39 +0100 | [diff] [blame] | 386 | __apicid_to_node[ht_nodeid] != NUMA_NO_NODE) |
| 387 | node = __apicid_to_node[ht_nodeid]; |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 388 | /* Pick a nearby node */ |
| 389 | if (!node_online(node)) |
| 390 | node = nearby_node(apicid); |
| 391 | } |
| 392 | numa_set_node(cpu, node); |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 393 | #endif |
| 394 | } |
| 395 | |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 396 | static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c) |
| 397 | { |
| 398 | #ifdef CONFIG_X86_HT |
| 399 | unsigned bits, ecx; |
| 400 | |
| 401 | /* Multi core CPU? */ |
| 402 | if (c->extended_cpuid_level < 0x80000008) |
| 403 | return; |
| 404 | |
| 405 | ecx = cpuid_ecx(0x80000008); |
| 406 | |
| 407 | c->x86_max_cores = (ecx & 0xff) + 1; |
| 408 | |
| 409 | /* CPU telling us the core id bits shift? */ |
| 410 | bits = (ecx >> 12) & 0xF; |
| 411 | |
| 412 | /* Otherwise recompute */ |
| 413 | if (bits == 0) { |
| 414 | while ((1 << bits) < c->x86_max_cores) |
| 415 | bits++; |
| 416 | } |
| 417 | |
| 418 | c->x86_coreid_bits = bits; |
| 419 | #endif |
| 420 | } |
| 421 | |
Borislav Petkov | 8fa8b03 | 2011-08-05 20:04:09 +0200 | [diff] [blame] | 422 | static void __cpuinit bsp_init_amd(struct cpuinfo_x86 *c) |
| 423 | { |
| 424 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { |
| 425 | |
| 426 | if (c->x86 > 0x10 || |
| 427 | (c->x86 == 0x10 && c->x86_model >= 0x2)) { |
| 428 | u64 val; |
| 429 | |
| 430 | rdmsrl(MSR_K7_HWCR, val); |
| 431 | if (!(val & BIT(24))) |
| 432 | printk(KERN_WARNING FW_BUG "TSC doesn't count " |
| 433 | "with P0 frequency!\n"); |
| 434 | } |
| 435 | } |
| 436 | |
| 437 | if (c->x86 == 0x15) { |
| 438 | unsigned long upperbit; |
| 439 | u32 cpuid, assoc; |
| 440 | |
| 441 | cpuid = cpuid_edx(0x80000005); |
| 442 | assoc = cpuid >> 16 & 0xff; |
| 443 | upperbit = ((cpuid >> 24) << 10) / assoc; |
| 444 | |
| 445 | va_align.mask = (upperbit - 1) & PAGE_MASK; |
| 446 | va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; |
| 447 | } |
| 448 | } |
| 449 | |
Thomas Petazzoni | 03ae576 | 2008-02-15 12:00:23 +0100 | [diff] [blame] | 450 | static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) |
Andi Kleen | 2b16a23 | 2008-01-30 13:32:40 +0100 | [diff] [blame] | 451 | { |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 452 | early_init_amd_mc(c); |
| 453 | |
Venki Pallipadi | 40fb171 | 2008-11-17 16:11:37 -0800 | [diff] [blame] | 454 | /* |
| 455 | * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate |
| 456 | * with P/T states and does not stop in deep C-states |
| 457 | */ |
| 458 | if (c->x86_power & (1 << 8)) { |
Yinghai Lu | e322423 | 2008-09-06 01:52:28 -0700 | [diff] [blame] | 459 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); |
Venki Pallipadi | 40fb171 | 2008-11-17 16:11:37 -0800 | [diff] [blame] | 460 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); |
| 461 | } |
Yinghai Lu | 5fef55f | 2008-09-04 21:09:43 +0200 | [diff] [blame] | 462 | |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 463 | #ifdef CONFIG_X86_64 |
| 464 | set_cpu_cap(c, X86_FEATURE_SYSCALL32); |
| 465 | #else |
Yinghai Lu | 5fef55f | 2008-09-04 21:09:43 +0200 | [diff] [blame] | 466 | /* Set MTRR capability flag if appropriate */ |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 467 | if (c->x86 == 5) |
| 468 | if (c->x86_model == 13 || c->x86_model == 9 || |
| 469 | (c->x86_model == 8 && c->x86_mask >= 8)) |
| 470 | set_cpu_cap(c, X86_FEATURE_K6_MTRR); |
| 471 | #endif |
Andreas Herrmann | 42937e8 | 2009-06-08 15:55:09 +0200 | [diff] [blame] | 472 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) |
| 473 | /* check CPU config space for extended APIC ID */ |
Jeremy Fitzhardinge | 2cb0786 | 2009-07-22 09:59:35 -0700 | [diff] [blame] | 474 | if (cpu_has_apic && c->x86 >= 0xf) { |
Andreas Herrmann | 42937e8 | 2009-06-08 15:55:09 +0200 | [diff] [blame] | 475 | unsigned int val; |
| 476 | val = read_pci_config(0, 24, 0, 0x68); |
| 477 | if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18))) |
| 478 | set_cpu_cap(c, X86_FEATURE_EXTD_APICID); |
| 479 | } |
| 480 | #endif |
Andi Kleen | 2b16a23 | 2008-01-30 13:32:40 +0100 | [diff] [blame] | 481 | } |
| 482 | |
Magnus Damm | b4af3f7 | 2006-09-26 10:52:36 +0200 | [diff] [blame] | 483 | static void __cpuinit init_amd(struct cpuinfo_x86 *c) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 484 | { |
Linus Torvalds | 8e8da02 | 2011-12-04 11:57:09 -0800 | [diff] [blame] | 485 | u32 dummy; |
| 486 | |
Andi Kleen | 7d318d7 | 2005-09-29 22:05:55 +0200 | [diff] [blame] | 487 | #ifdef CONFIG_SMP |
Andi Kleen | 3c92c2b | 2005-10-11 01:28:33 +0200 | [diff] [blame] | 488 | unsigned long long value; |
Andi Kleen | 7d318d7 | 2005-09-29 22:05:55 +0200 | [diff] [blame] | 489 | |
Paolo Ciarrocchi | fb87a29 | 2008-02-22 23:10:33 +0100 | [diff] [blame] | 490 | /* |
| 491 | * Disable TLB flush filter by setting HWCR.FFDIS on K8 |
Andi Kleen | 7d318d7 | 2005-09-29 22:05:55 +0200 | [diff] [blame] | 492 | * bit 6 of msr C001_0015 |
| 493 | * |
| 494 | * Errata 63 for SH-B3 steppings |
| 495 | * Errata 122 for all steppings (F+ have it disabled by default) |
| 496 | */ |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 497 | if (c->x86 == 0xf) { |
Andi Kleen | 7d318d7 | 2005-09-29 22:05:55 +0200 | [diff] [blame] | 498 | rdmsrl(MSR_K7_HWCR, value); |
| 499 | value |= 1 << 6; |
| 500 | wrmsrl(MSR_K7_HWCR, value); |
| 501 | } |
| 502 | #endif |
| 503 | |
Andi Kleen | 2b16a23 | 2008-01-30 13:32:40 +0100 | [diff] [blame] | 504 | early_init_amd(c); |
| 505 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 506 | /* |
Paolo Ciarrocchi | fb87a29 | 2008-02-22 23:10:33 +0100 | [diff] [blame] | 507 | * Bit 31 in normal CPUID used for nonstandard 3DNow ID; |
Ingo Molnar | 16282a8 | 2008-02-26 08:49:57 +0100 | [diff] [blame] | 508 | * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway |
Paolo Ciarrocchi | fb87a29 | 2008-02-22 23:10:33 +0100 | [diff] [blame] | 509 | */ |
Ingo Molnar | 16282a8 | 2008-02-26 08:49:57 +0100 | [diff] [blame] | 510 | clear_cpu_cap(c, 0*32+31); |
Paolo Ciarrocchi | fb87a29 | 2008-02-22 23:10:33 +0100 | [diff] [blame] | 511 | |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 512 | #ifdef CONFIG_X86_64 |
| 513 | /* On C+ stepping K8 rep microcode works well for copy/memset */ |
| 514 | if (c->x86 == 0xf) { |
| 515 | u32 level; |
| 516 | |
| 517 | level = cpuid_eax(1); |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 518 | if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 519 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
Kevin Winchester | fbd8b18 | 2009-08-10 19:56:45 -0300 | [diff] [blame] | 520 | |
| 521 | /* |
| 522 | * Some BIOSes incorrectly force this feature, but only K8 |
| 523 | * revision D (model = 0x14) and later actually support it. |
Borislav Petkov | 6b0f43d | 2009-08-31 09:50:11 +0200 | [diff] [blame] | 524 | * (AMD Erratum #110, docId: 25759). |
Kevin Winchester | fbd8b18 | 2009-08-10 19:56:45 -0300 | [diff] [blame] | 525 | */ |
Borislav Petkov | 6b0f43d | 2009-08-31 09:50:11 +0200 | [diff] [blame] | 526 | if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { |
| 527 | u64 val; |
| 528 | |
Kevin Winchester | fbd8b18 | 2009-08-10 19:56:45 -0300 | [diff] [blame] | 529 | clear_cpu_cap(c, X86_FEATURE_LAHF_LM); |
Borislav Petkov | 6b0f43d | 2009-08-31 09:50:11 +0200 | [diff] [blame] | 530 | if (!rdmsrl_amd_safe(0xc001100d, &val)) { |
| 531 | val &= ~(1ULL << 32); |
| 532 | wrmsrl_amd_safe(0xc001100d, val); |
| 533 | } |
| 534 | } |
| 535 | |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 536 | } |
Borislav Petkov | 12d8a96 | 2010-06-02 20:29:21 +0200 | [diff] [blame] | 537 | if (c->x86 >= 0x10) |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 538 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
Yinghai Lu | 0d96b9f | 2009-08-29 13:17:14 -0700 | [diff] [blame] | 539 | |
| 540 | /* get apicid instead of initial apic id from cpuid */ |
| 541 | c->apicid = hard_smp_processor_id(); |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 542 | #else |
| 543 | |
| 544 | /* |
| 545 | * FIXME: We should handle the K5 here. Set up the write |
| 546 | * range and also turn on MSR 83 bits 4 and 31 (write alloc, |
| 547 | * no bus pipeline) |
| 548 | */ |
| 549 | |
Paolo Ciarrocchi | fb87a29 | 2008-02-22 23:10:33 +0100 | [diff] [blame] | 550 | switch (c->x86) { |
| 551 | case 4: |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 552 | init_amd_k5(c); |
| 553 | break; |
Paolo Ciarrocchi | fb87a29 | 2008-02-22 23:10:33 +0100 | [diff] [blame] | 554 | case 5: |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 555 | init_amd_k6(c); |
| 556 | break; |
Paolo Ciarrocchi | fb87a29 | 2008-02-22 23:10:33 +0100 | [diff] [blame] | 557 | case 6: /* An Athlon/Duron */ |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 558 | init_amd_k7(c); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 559 | break; |
Andi Kleen | 67cddd9 | 2007-07-21 17:10:03 +0200 | [diff] [blame] | 560 | } |
Andi Kleen | 3556ddf | 2007-04-02 12:14:12 +0200 | [diff] [blame] | 561 | |
Andi Kleen | c12ceb7 | 2007-05-21 14:31:47 +0200 | [diff] [blame] | 562 | /* K6s reports MCEs but don't actually have all the MSRs */ |
| 563 | if (c->x86 < 6) |
Ingo Molnar | 16282a8 | 2008-02-26 08:49:57 +0100 | [diff] [blame] | 564 | clear_cpu_cap(c, X86_FEATURE_MCE); |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 565 | #endif |
Andi Kleen | de42186 | 2008-01-30 13:32:37 +0100 | [diff] [blame] | 566 | |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 567 | /* Enable workaround for FXSAVE leak */ |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 568 | if (c->x86 >= 6) |
| 569 | set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK); |
| 570 | |
| 571 | if (!c->x86_model_id[0]) { |
| 572 | switch (c->x86) { |
| 573 | case 0xf: |
| 574 | /* Should distinguish Models here, but this is only |
| 575 | a fallback anyways. */ |
| 576 | strcpy(c->x86_model_id, "Hammer"); |
| 577 | break; |
| 578 | } |
| 579 | } |
| 580 | |
Borislav Petkov | 27c13ec | 2009-11-21 14:01:45 +0100 | [diff] [blame] | 581 | cpu_detect_cache_sizes(c); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 582 | |
| 583 | /* Multi core CPU? */ |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 584 | if (c->extended_cpuid_level >= 0x80000008) { |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 585 | amd_detect_cmp(c); |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 586 | srat_detect_node(c); |
| 587 | } |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 588 | |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 589 | #ifdef CONFIG_X86_32 |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 590 | detect_ht(c); |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 591 | #endif |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 592 | |
| 593 | if (c->extended_cpuid_level >= 0x80000006) { |
Andreas Herrmann | d9fadd7 | 2010-09-02 15:37:10 +0200 | [diff] [blame] | 594 | if (cpuid_edx(0x80000006) & 0xf000) |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 595 | num_cache_leaves = 4; |
| 596 | else |
| 597 | num_cache_leaves = 3; |
| 598 | } |
| 599 | |
Borislav Petkov | 12d8a96 | 2010-06-02 20:29:21 +0200 | [diff] [blame] | 600 | if (c->x86 >= 0xf) |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 601 | set_cpu_cap(c, X86_FEATURE_K8); |
| 602 | |
| 603 | if (cpu_has_xmm2) { |
| 604 | /* MFENCE stops RDTSC speculation */ |
Ingo Molnar | 16282a8 | 2008-02-26 08:49:57 +0100 | [diff] [blame] | 605 | set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 606 | } |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 607 | |
| 608 | #ifdef CONFIG_X86_64 |
| 609 | if (c->x86 == 0x10) { |
| 610 | /* do this for boot cpu */ |
| 611 | if (c == &boot_cpu_data) |
| 612 | check_enable_amd_mmconf_dmi(); |
| 613 | |
| 614 | fam10h_check_enable_mmcfg(); |
| 615 | } |
| 616 | |
Borislav Petkov | 12d8a96 | 2010-06-02 20:29:21 +0200 | [diff] [blame] | 617 | if (c == &boot_cpu_data && c->x86 >= 0xf) { |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 618 | unsigned long long tseg; |
| 619 | |
| 620 | /* |
| 621 | * Split up direct mapping around the TSEG SMM area. |
| 622 | * Don't do it for gbpages because there seems very little |
| 623 | * benefit in doing so. |
| 624 | */ |
| 625 | if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 626 | printk(KERN_DEBUG "tseg: %010llx\n", tseg); |
| 627 | if ((tseg>>PMD_SHIFT) < |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 628 | (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) || |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 629 | ((tseg>>PMD_SHIFT) < |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 630 | (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) && |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 631 | (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT)))) |
| 632 | set_memory_4k((unsigned long)__va(tseg), 1); |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 633 | } |
| 634 | } |
| 635 | #endif |
Boris Ostrovsky | b87cf80 | 2011-03-15 12:13:44 -0400 | [diff] [blame] | 636 | |
Boris Ostrovsky | e9cdd34 | 2011-05-26 11:19:52 -0400 | [diff] [blame] | 637 | /* |
| 638 | * Family 0x12 and above processors have APIC timer |
| 639 | * running in deep C states. |
| 640 | */ |
| 641 | if (c->x86 > 0x11) |
Boris Ostrovsky | b87cf80 | 2011-03-15 12:13:44 -0400 | [diff] [blame] | 642 | set_cpu_cap(c, X86_FEATURE_ARAT); |
Joerg Roedel | 5bbc097 | 2011-04-15 14:47:40 +0200 | [diff] [blame] | 643 | |
| 644 | /* |
| 645 | * Disable GART TLB Walk Errors on Fam10h. We do this here |
| 646 | * because this is always needed when GART is enabled, even in a |
| 647 | * kernel which has no MCE support built in. |
| 648 | */ |
| 649 | if (c->x86 == 0x10) { |
| 650 | /* |
| 651 | * BIOS should disable GartTlbWlk Errors themself. If |
| 652 | * it doesn't do it here as suggested by the BKDG. |
| 653 | * |
| 654 | * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 |
| 655 | */ |
| 656 | u64 mask; |
Roedel, Joerg | d47cc0d | 2011-05-19 11:13:39 +0200 | [diff] [blame] | 657 | int err; |
Joerg Roedel | 5bbc097 | 2011-04-15 14:47:40 +0200 | [diff] [blame] | 658 | |
Roedel, Joerg | d47cc0d | 2011-05-19 11:13:39 +0200 | [diff] [blame] | 659 | err = rdmsrl_safe(MSR_AMD64_MCx_MASK(4), &mask); |
| 660 | if (err == 0) { |
| 661 | mask |= (1 << 10); |
| 662 | checking_wrmsrl(MSR_AMD64_MCx_MASK(4), mask); |
| 663 | } |
Joerg Roedel | 5bbc097 | 2011-04-15 14:47:40 +0200 | [diff] [blame] | 664 | } |
Linus Torvalds | 8e8da02 | 2011-12-04 11:57:09 -0800 | [diff] [blame] | 665 | |
| 666 | rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 667 | } |
| 668 | |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 669 | #ifdef CONFIG_X86_32 |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 670 | static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, |
| 671 | unsigned int size) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 672 | { |
| 673 | /* AMD errata T13 (order #21922) */ |
| 674 | if ((c->x86 == 6)) { |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 675 | /* Duron Rev A0 */ |
| 676 | if (c->x86_model == 3 && c->x86_mask == 0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 677 | size = 64; |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 678 | /* Tbird rev A1/A2 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 679 | if (c->x86_model == 4 && |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 680 | (c->x86_mask == 0 || c->x86_mask == 1)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 681 | size = 256; |
| 682 | } |
| 683 | return size; |
| 684 | } |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 685 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 686 | |
Jan Beulich | 02dde8b | 2009-03-12 12:08:49 +0000 | [diff] [blame] | 687 | static const struct cpu_dev __cpuinitconst amd_cpu_dev = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 688 | .c_vendor = "AMD", |
Paolo Ciarrocchi | fb87a29 | 2008-02-22 23:10:33 +0100 | [diff] [blame] | 689 | .c_ident = { "AuthenticAMD" }, |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 690 | #ifdef CONFIG_X86_32 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 691 | .c_models = { |
| 692 | { .vendor = X86_VENDOR_AMD, .family = 4, .model_names = |
| 693 | { |
| 694 | [3] = "486 DX/2", |
| 695 | [7] = "486 DX/2-WB", |
Paolo Ciarrocchi | fb87a29 | 2008-02-22 23:10:33 +0100 | [diff] [blame] | 696 | [8] = "486 DX/4", |
| 697 | [9] = "486 DX/4-WB", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 698 | [14] = "Am5x86-WT", |
Paolo Ciarrocchi | fb87a29 | 2008-02-22 23:10:33 +0100 | [diff] [blame] | 699 | [15] = "Am5x86-WB" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 700 | } |
| 701 | }, |
| 702 | }, |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 703 | .c_size_cache = amd_size_cache, |
| 704 | #endif |
Thomas Petazzoni | 03ae576 | 2008-02-15 12:00:23 +0100 | [diff] [blame] | 705 | .c_early_init = early_init_amd, |
Borislav Petkov | 8fa8b03 | 2011-08-05 20:04:09 +0200 | [diff] [blame] | 706 | .c_bsp_init = bsp_init_amd, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 707 | .c_init = init_amd, |
Yinghai Lu | 10a434f | 2008-09-04 21:09:45 +0200 | [diff] [blame] | 708 | .c_x86_vendor = X86_VENDOR_AMD, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 709 | }; |
| 710 | |
Yinghai Lu | 10a434f | 2008-09-04 21:09:45 +0200 | [diff] [blame] | 711 | cpu_dev_register(amd_cpu_dev); |
Hans Rosenfeld | d78d671 | 2010-07-28 19:09:30 +0200 | [diff] [blame] | 712 | |
| 713 | /* |
| 714 | * AMD errata checking |
| 715 | * |
| 716 | * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or |
| 717 | * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that |
| 718 | * have an OSVW id assigned, which it takes as first argument. Both take a |
| 719 | * variable number of family-specific model-stepping ranges created by |
| 720 | * AMD_MODEL_RANGE(). Each erratum also has to be declared as extern const |
| 721 | * int[] in arch/x86/include/asm/processor.h. |
| 722 | * |
| 723 | * Example: |
| 724 | * |
| 725 | * const int amd_erratum_319[] = |
| 726 | * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), |
| 727 | * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), |
| 728 | * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); |
| 729 | */ |
| 730 | |
Hans Rosenfeld | 9d8888c | 2010-07-28 19:09:31 +0200 | [diff] [blame] | 731 | const int amd_erratum_400[] = |
Borislav Petkov | 328935e | 2011-05-17 14:55:18 +0200 | [diff] [blame] | 732 | AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), |
Hans Rosenfeld | 9d8888c | 2010-07-28 19:09:31 +0200 | [diff] [blame] | 733 | AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); |
H. Peter Anvin | a5b9160 | 2010-07-28 16:23:20 -0700 | [diff] [blame] | 734 | EXPORT_SYMBOL_GPL(amd_erratum_400); |
Hans Rosenfeld | 9d8888c | 2010-07-28 19:09:31 +0200 | [diff] [blame] | 735 | |
Hans Rosenfeld | 1be85a6 | 2010-07-28 19:09:32 +0200 | [diff] [blame] | 736 | const int amd_erratum_383[] = |
| 737 | AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); |
H. Peter Anvin | a5b9160 | 2010-07-28 16:23:20 -0700 | [diff] [blame] | 738 | EXPORT_SYMBOL_GPL(amd_erratum_383); |
Hans Rosenfeld | 9d8888c | 2010-07-28 19:09:31 +0200 | [diff] [blame] | 739 | |
Hans Rosenfeld | d78d671 | 2010-07-28 19:09:30 +0200 | [diff] [blame] | 740 | bool cpu_has_amd_erratum(const int *erratum) |
| 741 | { |
Tejun Heo | 7b543a5 | 2010-12-18 16:30:05 +0100 | [diff] [blame] | 742 | struct cpuinfo_x86 *cpu = __this_cpu_ptr(&cpu_info); |
Hans Rosenfeld | d78d671 | 2010-07-28 19:09:30 +0200 | [diff] [blame] | 743 | int osvw_id = *erratum++; |
| 744 | u32 range; |
| 745 | u32 ms; |
| 746 | |
| 747 | /* |
| 748 | * If called early enough that current_cpu_data hasn't been initialized |
| 749 | * yet, fall back to boot_cpu_data. |
| 750 | */ |
| 751 | if (cpu->x86 == 0) |
| 752 | cpu = &boot_cpu_data; |
| 753 | |
| 754 | if (cpu->x86_vendor != X86_VENDOR_AMD) |
| 755 | return false; |
| 756 | |
| 757 | if (osvw_id >= 0 && osvw_id < 65536 && |
| 758 | cpu_has(cpu, X86_FEATURE_OSVW)) { |
| 759 | u64 osvw_len; |
| 760 | |
| 761 | rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); |
| 762 | if (osvw_id < osvw_len) { |
| 763 | u64 osvw_bits; |
| 764 | |
| 765 | rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), |
| 766 | osvw_bits); |
| 767 | return osvw_bits & (1ULL << (osvw_id & 0x3f)); |
| 768 | } |
| 769 | } |
| 770 | |
| 771 | /* OSVW unavailable or ID unknown, match family-model-stepping range */ |
Hans Rosenfeld | 07a7795 | 2010-08-18 16:19:50 +0200 | [diff] [blame] | 772 | ms = (cpu->x86_model << 4) | cpu->x86_mask; |
Hans Rosenfeld | d78d671 | 2010-07-28 19:09:30 +0200 | [diff] [blame] | 773 | while ((range = *erratum++)) |
| 774 | if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && |
| 775 | (ms >= AMD_MODEL_RANGE_START(range)) && |
| 776 | (ms <= AMD_MODEL_RANGE_END(range))) |
| 777 | return true; |
| 778 | |
| 779 | return false; |
| 780 | } |
H. Peter Anvin | a5b9160 | 2010-07-28 16:23:20 -0700 | [diff] [blame] | 781 | |
| 782 | EXPORT_SYMBOL_GPL(cpu_has_amd_erratum); |