Mian Yousaf Kaukab | 64ddba4 | 2013-04-29 14:07:48 +0200 | [diff] [blame^] | 1 | ST Microelectronics Flexible Static Memory Controller (FSMC) |
| 2 | NAND Interface |
Stefan Roese | eea6281 | 2012-03-16 10:19:31 +0100 | [diff] [blame] | 3 | |
| 4 | Required properties: |
Linus Walleij | ba78520 | 2013-01-05 22:28:32 +0100 | [diff] [blame] | 5 | - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand" |
Stefan Roese | eea6281 | 2012-03-16 10:19:31 +0100 | [diff] [blame] | 6 | - reg : Address range of the mtd chip |
Jean-Christophe PLAGNIOL-VILLARD | 6d7b42a | 2012-10-04 15:14:16 +0200 | [diff] [blame] | 7 | - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd" |
Stefan Roese | eea6281 | 2012-03-16 10:19:31 +0100 | [diff] [blame] | 8 | |
| 9 | Optional properties: |
| 10 | - bank-width : Width (in bytes) of the device. If not present, the width |
| 11 | defaults to 1 byte |
| 12 | - nand-skip-bbtscan: Indicates the the BBT scanning should be skipped |
Mian Yousaf Kaukab | 64ddba4 | 2013-04-29 14:07:48 +0200 | [diff] [blame^] | 13 | - timings: array of 6 bytes for NAND timings. The meanings of these bytes |
| 14 | are: |
| 15 | byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits |
| 16 | are valid. Zero means one clockcycle, 15 means 16 clock |
| 17 | cycles. |
| 18 | byte 1 TAR : ALE to RE delay, 4 bits are valid. Same format as TCLR. |
| 19 | byte 2 THIZ : number of HCLK clock cycles during which the data bus is |
| 20 | kept in Hi-Z (tristate) after the start of a write access. |
| 21 | Only valid for write transactions. Zero means zero cycles, |
| 22 | 255 means 255 cycles. |
| 23 | byte 3 THOLD : number of HCLK clock cycles to hold the address (and data |
| 24 | when writing) after the command deassertation. Zero means |
| 25 | one cycle, 255 means 256 cycles. |
| 26 | byte 4 TWAIT : number of HCLK clock cycles to assert the command to the |
| 27 | NAND flash in response to SMWAITn. Zero means 1 cycle, |
| 28 | 255 means 256 cycles. |
| 29 | byte 5 TSET : number of HCLK clock cycles to assert the address before the |
| 30 | command is asserted. Zero means one cycle, 255 means 256 |
| 31 | cycles. |
| 32 | - bank: default NAND bank to use (0-3 are valid, 0 is the default). |
Stefan Roese | eea6281 | 2012-03-16 10:19:31 +0100 | [diff] [blame] | 33 | |
| 34 | Example: |
| 35 | |
| 36 | fsmc: flash@d1800000 { |
| 37 | compatible = "st,spear600-fsmc-nand"; |
| 38 | #address-cells = <1>; |
| 39 | #size-cells = <1>; |
| 40 | reg = <0xd1800000 0x1000 /* FSMC Register */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d7b42a | 2012-10-04 15:14:16 +0200 | [diff] [blame] | 41 | 0xd2000000 0x0010 /* NAND Base DATA */ |
| 42 | 0xd2020000 0x0010 /* NAND Base ADDR */ |
| 43 | 0xd2010000 0x0010>; /* NAND Base CMD */ |
| 44 | reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; |
Stefan Roese | eea6281 | 2012-03-16 10:19:31 +0100 | [diff] [blame] | 45 | |
| 46 | bank-width = <1>; |
| 47 | nand-skip-bbtscan; |
Mian Yousaf Kaukab | 64ddba4 | 2013-04-29 14:07:48 +0200 | [diff] [blame^] | 48 | timings = /bits/ 8 <0 0 0 2 3 0>; |
| 49 | bank = <1>; |
Stefan Roese | eea6281 | 2012-03-16 10:19:31 +0100 | [diff] [blame] | 50 | |
| 51 | partition@0 { |
| 52 | ... |
| 53 | }; |
| 54 | }; |