Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Rafael Micro R820T driver |
| 3 | * |
| 4 | * Copyright (C) 2013 Mauro Carvalho Chehab <mchehab@redhat.com> |
| 5 | * |
| 6 | * This driver was written from scratch, based on an existing driver |
| 7 | * that it is part of rtl-sdr git tree, released under GPLv2: |
| 8 | * https://groups.google.com/forum/#!topic/ultra-cheap-sdr/Y3rBEOFtHug |
| 9 | * https://github.com/n1gp/gr-baz |
| 10 | * |
| 11 | * From what I understood from the threads, the original driver was converted |
| 12 | * to userspace from a Realtek tree. I couldn't find the original tree. |
| 13 | * However, the original driver look awkward on my eyes. So, I decided to |
| 14 | * write a new version from it from the scratch, while trying to reproduce |
| 15 | * everything found there. |
| 16 | * |
| 17 | * TODO: |
| 18 | * After locking, the original driver seems to have some routines to |
| 19 | * improve reception. This was not implemented here yet. |
| 20 | * |
| 21 | * RF Gain set/get is not implemented. |
| 22 | * |
| 23 | * This program is free software; you can redistribute it and/or modify |
| 24 | * it under the terms of the GNU General Public License as published by |
| 25 | * the Free Software Foundation; either version 2 of the License, or |
| 26 | * (at your option) any later version. |
| 27 | * |
| 28 | * This program is distributed in the hope that it will be useful, |
| 29 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 30 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 31 | * GNU General Public License for more details. |
| 32 | * |
| 33 | */ |
| 34 | |
| 35 | #include <linux/videodev2.h> |
| 36 | #include <linux/mutex.h> |
| 37 | #include <linux/slab.h> |
Mauro Carvalho Chehab | 103fe2f | 2013-04-10 07:08:17 -0300 | [diff] [blame] | 38 | #include <linux/bitrev.h> |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 39 | #include <asm/div64.h> |
Mauro Carvalho Chehab | 103fe2f | 2013-04-10 07:08:17 -0300 | [diff] [blame] | 40 | |
| 41 | #include "tuner-i2c.h" |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 42 | #include "r820t.h" |
| 43 | |
| 44 | /* |
| 45 | * FIXME: I think that there are only 32 registers, but better safe than |
| 46 | * sorry. After finishing the driver, we may review it. |
| 47 | */ |
| 48 | #define REG_SHADOW_START 5 |
| 49 | #define NUM_REGS 27 |
Mauro Carvalho Chehab | 25cf4d4 | 2013-04-10 15:55:48 -0300 | [diff] [blame^] | 50 | #define NUM_IMR 5 |
| 51 | #define IMR_TRIAL 9 |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 52 | |
| 53 | #define VER_NUM 49 |
| 54 | |
| 55 | static int debug; |
| 56 | module_param(debug, int, 0644); |
| 57 | MODULE_PARM_DESC(debug, "enable verbose debug messages"); |
| 58 | |
| 59 | /* |
| 60 | * enums and structures |
| 61 | */ |
| 62 | |
| 63 | enum xtal_cap_value { |
| 64 | XTAL_LOW_CAP_30P = 0, |
| 65 | XTAL_LOW_CAP_20P, |
| 66 | XTAL_LOW_CAP_10P, |
| 67 | XTAL_LOW_CAP_0P, |
| 68 | XTAL_HIGH_CAP_0P |
| 69 | }; |
| 70 | |
Mauro Carvalho Chehab | 25cf4d4 | 2013-04-10 15:55:48 -0300 | [diff] [blame^] | 71 | struct r820t_sect_type { |
| 72 | u8 phase_y; |
| 73 | u8 gain_x; |
| 74 | u16 value; |
| 75 | }; |
| 76 | |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 77 | struct r820t_priv { |
| 78 | struct list_head hybrid_tuner_instance_list; |
| 79 | const struct r820t_config *cfg; |
| 80 | struct tuner_i2c_props i2c_props; |
| 81 | struct mutex lock; |
| 82 | |
| 83 | u8 regs[NUM_REGS]; |
| 84 | u8 buf[NUM_REGS + 1]; |
| 85 | enum xtal_cap_value xtal_cap_sel; |
| 86 | u16 pll; /* kHz */ |
| 87 | u32 int_freq; |
| 88 | u8 fil_cal_code; |
| 89 | bool imr_done; |
| 90 | |
Mauro Carvalho Chehab | 25cf4d4 | 2013-04-10 15:55:48 -0300 | [diff] [blame^] | 91 | struct r820t_sect_type imr_data[NUM_IMR]; |
| 92 | |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 93 | /* Store current mode */ |
| 94 | u32 delsys; |
| 95 | enum v4l2_tuner_type type; |
| 96 | v4l2_std_id std; |
| 97 | u32 bw; /* in MHz */ |
| 98 | |
| 99 | bool has_lock; |
| 100 | }; |
| 101 | |
| 102 | struct r820t_freq_range { |
| 103 | u32 freq; |
| 104 | u8 open_d; |
| 105 | u8 rf_mux_ploy; |
| 106 | u8 tf_c; |
| 107 | u8 xtal_cap20p; |
| 108 | u8 xtal_cap10p; |
| 109 | u8 xtal_cap0p; |
| 110 | u8 imr_mem; /* Not used, currently */ |
| 111 | }; |
| 112 | |
| 113 | #define VCO_POWER_REF 0x02 |
Mauro Carvalho Chehab | 84ddc33 | 2013-04-10 08:51:45 -0300 | [diff] [blame] | 114 | #define DIP_FREQ 32000000 |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 115 | |
| 116 | /* |
| 117 | * Static constants |
| 118 | */ |
| 119 | |
| 120 | static LIST_HEAD(hybrid_tuner_instance_list); |
| 121 | static DEFINE_MUTEX(r820t_list_mutex); |
| 122 | |
| 123 | /* Those initial values start from REG_SHADOW_START */ |
| 124 | static const u8 r820t_init_array[NUM_REGS] = { |
| 125 | 0x83, 0x32, 0x75, /* 05 to 07 */ |
| 126 | 0xc0, 0x40, 0xd6, 0x6c, /* 08 to 0b */ |
| 127 | 0xf5, 0x63, 0x75, 0x68, /* 0c to 0f */ |
| 128 | 0x6c, 0x83, 0x80, 0x00, /* 10 to 13 */ |
| 129 | 0x0f, 0x00, 0xc0, 0x30, /* 14 to 17 */ |
| 130 | 0x48, 0xcc, 0x60, 0x00, /* 18 to 1b */ |
| 131 | 0x54, 0xae, 0x4a, 0xc0 /* 1c to 1f */ |
| 132 | }; |
| 133 | |
| 134 | /* Tuner frequency ranges */ |
| 135 | static const struct r820t_freq_range freq_ranges[] = { |
| 136 | { |
| 137 | .freq = 0, |
| 138 | .open_d = 0x08, /* low */ |
| 139 | .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ |
| 140 | .tf_c = 0xdf, /* R27[7:0] band2,band0 */ |
| 141 | .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ |
| 142 | .xtal_cap10p = 0x01, |
| 143 | .xtal_cap0p = 0x00, |
| 144 | .imr_mem = 0, |
| 145 | }, { |
| 146 | .freq = 50, /* Start freq, in MHz */ |
| 147 | .open_d = 0x08, /* low */ |
| 148 | .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ |
| 149 | .tf_c = 0xbe, /* R27[7:0] band4,band1 */ |
| 150 | .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ |
| 151 | .xtal_cap10p = 0x01, |
| 152 | .xtal_cap0p = 0x00, |
| 153 | .imr_mem = 0, |
| 154 | }, { |
| 155 | .freq = 55, /* Start freq, in MHz */ |
| 156 | .open_d = 0x08, /* low */ |
| 157 | .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ |
| 158 | .tf_c = 0x8b, /* R27[7:0] band7,band4 */ |
| 159 | .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ |
| 160 | .xtal_cap10p = 0x01, |
| 161 | .xtal_cap0p = 0x00, |
| 162 | .imr_mem = 0, |
| 163 | }, { |
| 164 | .freq = 60, /* Start freq, in MHz */ |
| 165 | .open_d = 0x08, /* low */ |
| 166 | .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ |
| 167 | .tf_c = 0x7b, /* R27[7:0] band8,band4 */ |
| 168 | .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ |
| 169 | .xtal_cap10p = 0x01, |
| 170 | .xtal_cap0p = 0x00, |
| 171 | .imr_mem = 0, |
| 172 | }, { |
| 173 | .freq = 65, /* Start freq, in MHz */ |
| 174 | .open_d = 0x08, /* low */ |
| 175 | .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ |
| 176 | .tf_c = 0x69, /* R27[7:0] band9,band6 */ |
| 177 | .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ |
| 178 | .xtal_cap10p = 0x01, |
| 179 | .xtal_cap0p = 0x00, |
| 180 | .imr_mem = 0, |
| 181 | }, { |
| 182 | .freq = 70, /* Start freq, in MHz */ |
| 183 | .open_d = 0x08, /* low */ |
| 184 | .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ |
| 185 | .tf_c = 0x58, /* R27[7:0] band10,band7 */ |
| 186 | .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ |
| 187 | .xtal_cap10p = 0x01, |
| 188 | .xtal_cap0p = 0x00, |
| 189 | .imr_mem = 0, |
| 190 | }, { |
| 191 | .freq = 75, /* Start freq, in MHz */ |
| 192 | .open_d = 0x00, /* high */ |
| 193 | .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ |
| 194 | .tf_c = 0x44, /* R27[7:0] band11,band11 */ |
| 195 | .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ |
| 196 | .xtal_cap10p = 0x01, |
| 197 | .xtal_cap0p = 0x00, |
| 198 | .imr_mem = 0, |
| 199 | }, { |
| 200 | .freq = 80, /* Start freq, in MHz */ |
| 201 | .open_d = 0x00, /* high */ |
| 202 | .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ |
| 203 | .tf_c = 0x44, /* R27[7:0] band11,band11 */ |
| 204 | .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ |
| 205 | .xtal_cap10p = 0x01, |
| 206 | .xtal_cap0p = 0x00, |
| 207 | .imr_mem = 0, |
| 208 | }, { |
| 209 | .freq = 90, /* Start freq, in MHz */ |
| 210 | .open_d = 0x00, /* high */ |
| 211 | .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ |
| 212 | .tf_c = 0x34, /* R27[7:0] band12,band11 */ |
| 213 | .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */ |
| 214 | .xtal_cap10p = 0x01, |
| 215 | .xtal_cap0p = 0x00, |
| 216 | .imr_mem = 0, |
| 217 | }, { |
| 218 | .freq = 100, /* Start freq, in MHz */ |
| 219 | .open_d = 0x00, /* high */ |
| 220 | .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ |
| 221 | .tf_c = 0x34, /* R27[7:0] band12,band11 */ |
| 222 | .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */ |
| 223 | .xtal_cap10p = 0x01, |
| 224 | .xtal_cap0p = 0x00, |
| 225 | .imr_mem = 0, |
| 226 | }, { |
| 227 | .freq = 110, /* Start freq, in MHz */ |
| 228 | .open_d = 0x00, /* high */ |
| 229 | .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ |
| 230 | .tf_c = 0x24, /* R27[7:0] band13,band11 */ |
| 231 | .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */ |
| 232 | .xtal_cap10p = 0x01, |
| 233 | .xtal_cap0p = 0x00, |
| 234 | .imr_mem = 1, |
| 235 | }, { |
| 236 | .freq = 120, /* Start freq, in MHz */ |
| 237 | .open_d = 0x00, /* high */ |
| 238 | .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ |
| 239 | .tf_c = 0x24, /* R27[7:0] band13,band11 */ |
| 240 | .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */ |
| 241 | .xtal_cap10p = 0x01, |
| 242 | .xtal_cap0p = 0x00, |
| 243 | .imr_mem = 1, |
| 244 | }, { |
| 245 | .freq = 140, /* Start freq, in MHz */ |
| 246 | .open_d = 0x00, /* high */ |
| 247 | .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ |
| 248 | .tf_c = 0x14, /* R27[7:0] band14,band11 */ |
| 249 | .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */ |
| 250 | .xtal_cap10p = 0x01, |
| 251 | .xtal_cap0p = 0x00, |
| 252 | .imr_mem = 1, |
| 253 | }, { |
| 254 | .freq = 180, /* Start freq, in MHz */ |
| 255 | .open_d = 0x00, /* high */ |
| 256 | .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ |
| 257 | .tf_c = 0x13, /* R27[7:0] band14,band12 */ |
| 258 | .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ |
| 259 | .xtal_cap10p = 0x00, |
| 260 | .xtal_cap0p = 0x00, |
| 261 | .imr_mem = 1, |
| 262 | }, { |
| 263 | .freq = 220, /* Start freq, in MHz */ |
| 264 | .open_d = 0x00, /* high */ |
| 265 | .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ |
| 266 | .tf_c = 0x13, /* R27[7:0] band14,band12 */ |
| 267 | .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ |
| 268 | .xtal_cap10p = 0x00, |
| 269 | .xtal_cap0p = 0x00, |
| 270 | .imr_mem = 2, |
| 271 | }, { |
| 272 | .freq = 250, /* Start freq, in MHz */ |
| 273 | .open_d = 0x00, /* high */ |
| 274 | .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ |
| 275 | .tf_c = 0x11, /* R27[7:0] highest,highest */ |
| 276 | .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ |
| 277 | .xtal_cap10p = 0x00, |
| 278 | .xtal_cap0p = 0x00, |
| 279 | .imr_mem = 2, |
| 280 | }, { |
| 281 | .freq = 280, /* Start freq, in MHz */ |
| 282 | .open_d = 0x00, /* high */ |
| 283 | .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ |
| 284 | .tf_c = 0x00, /* R27[7:0] highest,highest */ |
| 285 | .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ |
| 286 | .xtal_cap10p = 0x00, |
| 287 | .xtal_cap0p = 0x00, |
| 288 | .imr_mem = 2, |
| 289 | }, { |
| 290 | .freq = 310, /* Start freq, in MHz */ |
| 291 | .open_d = 0x00, /* high */ |
| 292 | .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */ |
| 293 | .tf_c = 0x00, /* R27[7:0] highest,highest */ |
| 294 | .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ |
| 295 | .xtal_cap10p = 0x00, |
| 296 | .xtal_cap0p = 0x00, |
| 297 | .imr_mem = 2, |
| 298 | }, { |
| 299 | .freq = 450, /* Start freq, in MHz */ |
| 300 | .open_d = 0x00, /* high */ |
| 301 | .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */ |
| 302 | .tf_c = 0x00, /* R27[7:0] highest,highest */ |
| 303 | .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ |
| 304 | .xtal_cap10p = 0x00, |
| 305 | .xtal_cap0p = 0x00, |
| 306 | .imr_mem = 3, |
| 307 | }, { |
| 308 | .freq = 588, /* Start freq, in MHz */ |
| 309 | .open_d = 0x00, /* high */ |
| 310 | .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */ |
| 311 | .tf_c = 0x00, /* R27[7:0] highest,highest */ |
| 312 | .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ |
| 313 | .xtal_cap10p = 0x00, |
| 314 | .xtal_cap0p = 0x00, |
| 315 | .imr_mem = 3, |
| 316 | }, { |
| 317 | .freq = 650, /* Start freq, in MHz */ |
| 318 | .open_d = 0x00, /* high */ |
| 319 | .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */ |
| 320 | .tf_c = 0x00, /* R27[7:0] highest,highest */ |
| 321 | .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ |
| 322 | .xtal_cap10p = 0x00, |
| 323 | .xtal_cap0p = 0x00, |
| 324 | .imr_mem = 4, |
| 325 | } |
| 326 | }; |
| 327 | |
| 328 | static int r820t_xtal_capacitor[][2] = { |
| 329 | { 0x0b, XTAL_LOW_CAP_30P }, |
| 330 | { 0x02, XTAL_LOW_CAP_20P }, |
| 331 | { 0x01, XTAL_LOW_CAP_10P }, |
| 332 | { 0x00, XTAL_LOW_CAP_0P }, |
| 333 | { 0x10, XTAL_HIGH_CAP_0P }, |
| 334 | }; |
| 335 | |
| 336 | /* |
Mauro Carvalho Chehab | 50786dd | 2013-04-07 18:33:13 -0300 | [diff] [blame] | 337 | * measured with a Racal 6103E GSM test set at 928 MHz with -60 dBm |
| 338 | * input power, for raw results see: |
| 339 | * http://steve-m.de/projects/rtl-sdr/gain_measurement/r820t/ |
| 340 | */ |
| 341 | |
| 342 | static const int r820t_lna_gain_steps[] = { |
| 343 | 0, 9, 13, 40, 38, 13, 31, 22, 26, 31, 26, 14, 19, 5, 35, 13 |
| 344 | }; |
| 345 | |
| 346 | static const int r820t_mixer_gain_steps[] = { |
| 347 | 0, 5, 10, 10, 19, 9, 10, 25, 17, 10, 8, 16, 13, 6, 3, -8 |
| 348 | }; |
| 349 | |
| 350 | /* |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 351 | * I2C read/write code and shadow registers logic |
| 352 | */ |
| 353 | static void shadow_store(struct r820t_priv *priv, u8 reg, const u8 *val, |
| 354 | int len) |
| 355 | { |
| 356 | int r = reg - REG_SHADOW_START; |
| 357 | |
| 358 | if (r < 0) { |
| 359 | len += r; |
| 360 | r = 0; |
| 361 | } |
| 362 | if (len <= 0) |
| 363 | return; |
| 364 | if (len > NUM_REGS) |
| 365 | len = NUM_REGS; |
| 366 | |
| 367 | tuner_dbg("%s: prev reg=%02x len=%d: %*ph\n", |
| 368 | __func__, r + REG_SHADOW_START, len, len, val); |
| 369 | |
| 370 | memcpy(&priv->regs[r], val, len); |
| 371 | } |
| 372 | |
| 373 | static int r820t_write(struct r820t_priv *priv, u8 reg, const u8 *val, |
| 374 | int len) |
| 375 | { |
| 376 | int rc, size, pos = 0; |
| 377 | |
| 378 | /* Store the shadow registers */ |
| 379 | shadow_store(priv, reg, val, len); |
| 380 | |
| 381 | do { |
| 382 | if (len > priv->cfg->max_i2c_msg_len - 1) |
| 383 | size = priv->cfg->max_i2c_msg_len - 1; |
| 384 | else |
| 385 | size = len; |
| 386 | |
| 387 | /* Fill I2C buffer */ |
| 388 | priv->buf[0] = reg; |
| 389 | memcpy(&priv->buf[1], &val[pos], size); |
| 390 | |
| 391 | rc = tuner_i2c_xfer_send(&priv->i2c_props, priv->buf, size + 1); |
| 392 | if (rc != size + 1) { |
| 393 | tuner_info("%s: i2c wr failed=%d reg=%02x len=%d: %*ph\n", |
| 394 | __func__, rc, reg, size, size, &priv->buf[1]); |
| 395 | if (rc < 0) |
| 396 | return rc; |
| 397 | return -EREMOTEIO; |
| 398 | } |
| 399 | tuner_dbg("%s: i2c wr reg=%02x len=%d: %*ph\n", |
| 400 | __func__, reg, size, size, &priv->buf[1]); |
| 401 | |
| 402 | reg += size; |
| 403 | len -= size; |
| 404 | pos += size; |
| 405 | } while (len > 0); |
| 406 | |
| 407 | return 0; |
| 408 | } |
| 409 | |
| 410 | static int r820t_write_reg(struct r820t_priv *priv, u8 reg, u8 val) |
| 411 | { |
| 412 | return r820t_write(priv, reg, &val, 1); |
| 413 | } |
| 414 | |
Mauro Carvalho Chehab | 8678b03 | 2013-04-10 10:50:50 -0300 | [diff] [blame] | 415 | static int r820t_read_cache_reg(struct r820t_priv *priv, int reg) |
| 416 | { |
| 417 | reg -= REG_SHADOW_START; |
| 418 | |
| 419 | if (reg >= 0 && reg < NUM_REGS) |
| 420 | return priv->regs[reg]; |
| 421 | else |
| 422 | return -EINVAL; |
| 423 | } |
| 424 | |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 425 | static int r820t_write_reg_mask(struct r820t_priv *priv, u8 reg, u8 val, |
| 426 | u8 bit_mask) |
| 427 | { |
Mauro Carvalho Chehab | 8678b03 | 2013-04-10 10:50:50 -0300 | [diff] [blame] | 428 | int rc = r820t_read_cache_reg(priv, reg); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 429 | |
Mauro Carvalho Chehab | 8678b03 | 2013-04-10 10:50:50 -0300 | [diff] [blame] | 430 | if (rc < 0) |
| 431 | return rc; |
| 432 | |
| 433 | val = (rc & ~bit_mask) | (val & bit_mask); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 434 | |
| 435 | return r820t_write(priv, reg, &val, 1); |
| 436 | } |
| 437 | |
Mauro Carvalho Chehab | 226471a | 2013-04-10 10:53:35 -0300 | [diff] [blame] | 438 | static int r820t_read(struct r820t_priv *priv, u8 reg, u8 *val, int len) |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 439 | { |
Mauro Carvalho Chehab | 103fe2f | 2013-04-10 07:08:17 -0300 | [diff] [blame] | 440 | int rc, i; |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 441 | u8 *p = &priv->buf[1]; |
| 442 | |
| 443 | priv->buf[0] = reg; |
| 444 | |
| 445 | rc = tuner_i2c_xfer_send_recv(&priv->i2c_props, priv->buf, 1, p, len); |
| 446 | if (rc != len) { |
| 447 | tuner_info("%s: i2c rd failed=%d reg=%02x len=%d: %*ph\n", |
| 448 | __func__, rc, reg, len, len, p); |
| 449 | if (rc < 0) |
| 450 | return rc; |
| 451 | return -EREMOTEIO; |
| 452 | } |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 453 | |
| 454 | /* Copy data to the output buffer */ |
Mauro Carvalho Chehab | 103fe2f | 2013-04-10 07:08:17 -0300 | [diff] [blame] | 455 | for (i = 0; i < len; i++) |
| 456 | val[i] = bitrev8(p[i]); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 457 | |
Mauro Carvalho Chehab | 6b8c230 | 2013-04-10 07:43:10 -0300 | [diff] [blame] | 458 | tuner_dbg("%s: i2c rd reg=%02x len=%d: %*ph\n", |
| 459 | __func__, reg, len, len, val); |
| 460 | |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 461 | return 0; |
| 462 | } |
| 463 | |
| 464 | /* |
| 465 | * r820t tuning logic |
| 466 | */ |
| 467 | |
| 468 | static int r820t_set_mux(struct r820t_priv *priv, u32 freq) |
| 469 | { |
| 470 | const struct r820t_freq_range *range; |
| 471 | int i, rc; |
Mauro Carvalho Chehab | 25cf4d4 | 2013-04-10 15:55:48 -0300 | [diff] [blame^] | 472 | u8 val, reg08, reg09; |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 473 | |
| 474 | /* Get the proper frequency range */ |
| 475 | freq = freq / 1000000; |
| 476 | for (i = 0; i < ARRAY_SIZE(freq_ranges) - 1; i++) { |
| 477 | if (freq < freq_ranges[i + 1].freq) |
| 478 | break; |
| 479 | } |
| 480 | range = &freq_ranges[i]; |
| 481 | |
| 482 | tuner_dbg("set r820t range#%d for frequency %d MHz\n", i, freq); |
| 483 | |
| 484 | /* Open Drain */ |
| 485 | rc = r820t_write_reg_mask(priv, 0x17, range->open_d, 0x08); |
| 486 | if (rc < 0) |
| 487 | return rc; |
| 488 | |
| 489 | /* RF_MUX,Polymux */ |
| 490 | rc = r820t_write_reg_mask(priv, 0x1a, range->rf_mux_ploy, 0xc3); |
| 491 | if (rc < 0) |
| 492 | return rc; |
| 493 | |
| 494 | /* TF BAND */ |
| 495 | rc = r820t_write_reg(priv, 0x1b, range->tf_c); |
| 496 | if (rc < 0) |
| 497 | return rc; |
| 498 | |
| 499 | /* XTAL CAP & Drive */ |
| 500 | switch (priv->xtal_cap_sel) { |
| 501 | case XTAL_LOW_CAP_30P: |
| 502 | case XTAL_LOW_CAP_20P: |
| 503 | val = range->xtal_cap20p | 0x08; |
| 504 | break; |
| 505 | case XTAL_LOW_CAP_10P: |
| 506 | val = range->xtal_cap10p | 0x08; |
| 507 | break; |
| 508 | case XTAL_HIGH_CAP_0P: |
| 509 | val = range->xtal_cap0p | 0x00; |
| 510 | break; |
| 511 | default: |
| 512 | case XTAL_LOW_CAP_0P: |
| 513 | val = range->xtal_cap0p | 0x08; |
| 514 | break; |
| 515 | } |
| 516 | rc = r820t_write_reg_mask(priv, 0x10, val, 0x0b); |
| 517 | if (rc < 0) |
| 518 | return rc; |
| 519 | |
Mauro Carvalho Chehab | 25cf4d4 | 2013-04-10 15:55:48 -0300 | [diff] [blame^] | 520 | if (priv->imr_done) { |
| 521 | reg08 = priv->imr_data[range->imr_mem].gain_x; |
| 522 | reg09 = priv->imr_data[range->imr_mem].phase_y; |
| 523 | } else { |
| 524 | reg08 = 0; |
| 525 | reg09 = 0; |
| 526 | } |
| 527 | rc = r820t_write_reg_mask(priv, 0x08, reg08, 0x3f); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 528 | if (rc < 0) |
| 529 | return rc; |
| 530 | |
Mauro Carvalho Chehab | 25cf4d4 | 2013-04-10 15:55:48 -0300 | [diff] [blame^] | 531 | rc = r820t_write_reg_mask(priv, 0x09, reg09, 0x3f); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 532 | |
| 533 | return rc; |
| 534 | } |
| 535 | |
Mauro Carvalho Chehab | d75d538 | 2013-04-10 15:54:46 -0300 | [diff] [blame] | 536 | static int r820t_set_pll(struct r820t_priv *priv, enum v4l2_tuner_type type, |
| 537 | u32 freq) |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 538 | { |
| 539 | u64 tmp64, vco_freq; |
| 540 | int rc, i; |
Mauro Carvalho Chehab | d75d538 | 2013-04-10 15:54:46 -0300 | [diff] [blame] | 541 | unsigned sleep_time = 10000; |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 542 | u32 vco_fra; /* VCO contribution by SDM (kHz) */ |
| 543 | u32 vco_min = 1770000; |
| 544 | u32 vco_max = vco_min * 2; |
| 545 | u32 pll_ref; |
| 546 | u16 n_sdm = 2; |
| 547 | u16 sdm = 0; |
| 548 | u8 mix_div = 2; |
| 549 | u8 div_buf = 0; |
| 550 | u8 div_num = 0; |
Mauro Carvalho Chehab | d75d538 | 2013-04-10 15:54:46 -0300 | [diff] [blame] | 551 | u8 refdiv2 = 0; |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 552 | u8 ni, si, nint, vco_fine_tune, val; |
| 553 | u8 data[5]; |
| 554 | |
Mauro Carvalho Chehab | d75d538 | 2013-04-10 15:54:46 -0300 | [diff] [blame] | 555 | /* Frequency in kHz */ |
| 556 | freq = freq / 1000; |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 557 | pll_ref = priv->cfg->xtal / 1000; |
| 558 | |
Mauro Carvalho Chehab | d75d538 | 2013-04-10 15:54:46 -0300 | [diff] [blame] | 559 | if ((priv->cfg->rafael_chip == CHIP_R620D) || |
| 560 | (priv->cfg->rafael_chip == CHIP_R828D) || |
| 561 | (priv->cfg->rafael_chip == CHIP_R828)) { |
| 562 | /* ref set refdiv2, reffreq = Xtal/2 on ATV application */ |
| 563 | if (type != V4L2_TUNER_DIGITAL_TV) { |
| 564 | pll_ref /= 2; |
| 565 | refdiv2 = 0x10; |
| 566 | sleep_time = 20000; |
| 567 | } |
| 568 | } else { |
| 569 | if (priv->cfg->xtal > 24000000) { |
| 570 | pll_ref /= 2; |
| 571 | refdiv2 = 0x10; |
| 572 | } |
| 573 | } |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 574 | |
Mauro Carvalho Chehab | d75d538 | 2013-04-10 15:54:46 -0300 | [diff] [blame] | 575 | tuner_dbg("set r820t pll for frequency %d kHz = %d%s\n", |
| 576 | freq, pll_ref, refdiv2 ? " / 2" : ""); |
| 577 | |
| 578 | rc = r820t_write_reg_mask(priv, 0x10, refdiv2, 0x10); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 579 | if (rc < 0) |
| 580 | return rc; |
| 581 | |
| 582 | /* set pll autotune = 128kHz */ |
| 583 | rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c); |
| 584 | if (rc < 0) |
| 585 | return rc; |
| 586 | |
| 587 | /* set VCO current = 100 */ |
| 588 | rc = r820t_write_reg_mask(priv, 0x12, 0x80, 0xe0); |
| 589 | if (rc < 0) |
| 590 | return rc; |
| 591 | |
| 592 | /* Calculate divider */ |
| 593 | while (mix_div <= 64) { |
| 594 | if (((freq * mix_div) >= vco_min) && |
| 595 | ((freq * mix_div) < vco_max)) { |
| 596 | div_buf = mix_div; |
| 597 | while (div_buf > 2) { |
| 598 | div_buf = div_buf >> 1; |
| 599 | div_num++; |
| 600 | } |
| 601 | break; |
| 602 | } |
| 603 | mix_div = mix_div << 1; |
| 604 | } |
| 605 | |
Mauro Carvalho Chehab | 226471a | 2013-04-10 10:53:35 -0300 | [diff] [blame] | 606 | rc = r820t_read(priv, 0x00, data, sizeof(data)); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 607 | if (rc < 0) |
| 608 | return rc; |
| 609 | |
| 610 | vco_fine_tune = (data[4] & 0x30) >> 4; |
| 611 | |
| 612 | if (vco_fine_tune > VCO_POWER_REF) |
| 613 | div_num = div_num - 1; |
| 614 | else if (vco_fine_tune < VCO_POWER_REF) |
| 615 | div_num = div_num + 1; |
| 616 | |
| 617 | rc = r820t_write_reg_mask(priv, 0x10, div_num << 5, 0xe0); |
| 618 | if (rc < 0) |
| 619 | return rc; |
| 620 | |
| 621 | vco_freq = (u64)(freq * (u64)mix_div); |
| 622 | |
| 623 | tmp64 = vco_freq; |
| 624 | do_div(tmp64, 2 * pll_ref); |
| 625 | nint = (u8)tmp64; |
| 626 | |
| 627 | tmp64 = vco_freq - ((u64)2) * pll_ref * nint; |
| 628 | do_div(tmp64, 1000); |
| 629 | vco_fra = (u16)(tmp64); |
| 630 | |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 631 | /* boundary spur prevention */ |
| 632 | if (vco_fra < pll_ref / 64) { |
| 633 | vco_fra = 0; |
| 634 | } else if (vco_fra > pll_ref * 127 / 64) { |
| 635 | vco_fra = 0; |
| 636 | nint++; |
| 637 | } else if ((vco_fra > pll_ref * 127 / 128) && (vco_fra < pll_ref)) { |
| 638 | vco_fra = pll_ref * 127 / 128; |
| 639 | } else if ((vco_fra > pll_ref) && (vco_fra < pll_ref * 129 / 128)) { |
| 640 | vco_fra = pll_ref * 129 / 128; |
| 641 | } |
| 642 | |
| 643 | if (nint > 63) { |
| 644 | tuner_info("No valid PLL values for %u kHz!\n", freq); |
| 645 | return -EINVAL; |
| 646 | } |
| 647 | |
| 648 | ni = (nint - 13) / 4; |
| 649 | si = nint - 4 * ni - 13; |
| 650 | |
| 651 | rc = r820t_write_reg(priv, 0x14, ni + (si << 6)); |
| 652 | if (rc < 0) |
| 653 | return rc; |
| 654 | |
| 655 | /* pw_sdm */ |
| 656 | if (!vco_fra) |
| 657 | val = 0x08; |
| 658 | else |
| 659 | val = 0x00; |
| 660 | |
| 661 | rc = r820t_write_reg_mask(priv, 0x12, val, 0x08); |
| 662 | if (rc < 0) |
| 663 | return rc; |
| 664 | |
| 665 | /* sdm calculator */ |
| 666 | while (vco_fra > 1) { |
| 667 | if (vco_fra > (2 * pll_ref / n_sdm)) { |
| 668 | sdm = sdm + 32768 / (n_sdm / 2); |
| 669 | vco_fra = vco_fra - 2 * pll_ref / n_sdm; |
| 670 | if (n_sdm >= 0x8000) |
| 671 | break; |
| 672 | } |
| 673 | n_sdm = n_sdm << 1; |
| 674 | } |
| 675 | |
| 676 | rc = r820t_write_reg_mask(priv, 0x16, sdm >> 8, 0x08); |
| 677 | if (rc < 0) |
| 678 | return rc; |
| 679 | rc = r820t_write_reg_mask(priv, 0x15, sdm & 0xff, 0x08); |
| 680 | if (rc < 0) |
| 681 | return rc; |
| 682 | |
| 683 | for (i = 0; i < 2; i++) { |
Mauro Carvalho Chehab | d75d538 | 2013-04-10 15:54:46 -0300 | [diff] [blame] | 684 | usleep_range(sleep_time, sleep_time + 1000); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 685 | |
| 686 | /* Check if PLL has locked */ |
Mauro Carvalho Chehab | 226471a | 2013-04-10 10:53:35 -0300 | [diff] [blame] | 687 | rc = r820t_read(priv, 0x00, data, 3); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 688 | if (rc < 0) |
| 689 | return rc; |
| 690 | if (data[2] & 0x40) |
| 691 | break; |
| 692 | |
| 693 | if (!i) { |
| 694 | /* Didn't lock. Increase VCO current */ |
| 695 | rc = r820t_write_reg_mask(priv, 0x12, 0x60, 0xe0); |
| 696 | if (rc < 0) |
| 697 | return rc; |
| 698 | } |
| 699 | } |
| 700 | |
| 701 | if (!(data[2] & 0x40)) { |
| 702 | priv->has_lock = false; |
| 703 | return 0; |
| 704 | } |
| 705 | |
| 706 | priv->has_lock = true; |
| 707 | tuner_dbg("tuner has lock at frequency %d kHz\n", freq); |
| 708 | |
| 709 | /* set pll autotune = 8kHz */ |
| 710 | rc = r820t_write_reg_mask(priv, 0x1a, 0x08, 0x08); |
| 711 | |
| 712 | return rc; |
| 713 | } |
| 714 | |
| 715 | static int r820t_sysfreq_sel(struct r820t_priv *priv, u32 freq, |
| 716 | enum v4l2_tuner_type type, |
| 717 | v4l2_std_id std, |
| 718 | u32 delsys) |
| 719 | { |
| 720 | int rc; |
| 721 | u8 mixer_top, lna_top, cp_cur, div_buf_cur, lna_vth_l, mixer_vth_l; |
| 722 | u8 air_cable1_in, cable2_in, pre_dect, lna_discharge, filter_cur; |
| 723 | |
| 724 | tuner_dbg("adjusting tuner parameters for the standard\n"); |
| 725 | |
| 726 | switch (delsys) { |
| 727 | case SYS_DVBT: |
| 728 | if ((freq == 506000000) || (freq == 666000000) || |
| 729 | (freq == 818000000)) { |
| 730 | mixer_top = 0x14; /* mixer top:14 , top-1, low-discharge */ |
| 731 | lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */ |
| 732 | cp_cur = 0x28; /* 101, 0.2 */ |
| 733 | div_buf_cur = 0x20; /* 10, 200u */ |
| 734 | } else { |
| 735 | mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */ |
| 736 | lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */ |
| 737 | cp_cur = 0x38; /* 111, auto */ |
| 738 | div_buf_cur = 0x30; /* 11, 150u */ |
| 739 | } |
| 740 | lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */ |
| 741 | mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */ |
| 742 | air_cable1_in = 0x00; |
| 743 | cable2_in = 0x00; |
| 744 | pre_dect = 0x40; |
| 745 | lna_discharge = 14; |
| 746 | filter_cur = 0x40; /* 10, low */ |
| 747 | break; |
| 748 | case SYS_DVBT2: |
| 749 | mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */ |
| 750 | lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */ |
| 751 | lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */ |
| 752 | mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */ |
| 753 | air_cable1_in = 0x00; |
| 754 | cable2_in = 0x00; |
| 755 | pre_dect = 0x40; |
| 756 | lna_discharge = 14; |
| 757 | cp_cur = 0x38; /* 111, auto */ |
| 758 | div_buf_cur = 0x30; /* 11, 150u */ |
| 759 | filter_cur = 0x40; /* 10, low */ |
| 760 | break; |
| 761 | case SYS_ISDBT: |
| 762 | mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */ |
| 763 | lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */ |
| 764 | lna_vth_l = 0x75; /* lna vth 1.04 , vtl 0.84 */ |
| 765 | mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */ |
| 766 | air_cable1_in = 0x00; |
| 767 | cable2_in = 0x00; |
| 768 | pre_dect = 0x40; |
| 769 | lna_discharge = 14; |
| 770 | cp_cur = 0x38; /* 111, auto */ |
| 771 | div_buf_cur = 0x30; /* 11, 150u */ |
| 772 | filter_cur = 0x40; /* 10, low */ |
| 773 | break; |
| 774 | default: /* DVB-T 8M */ |
| 775 | mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */ |
| 776 | lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */ |
| 777 | lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */ |
| 778 | mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */ |
| 779 | air_cable1_in = 0x00; |
| 780 | cable2_in = 0x00; |
| 781 | pre_dect = 0x40; |
| 782 | lna_discharge = 14; |
| 783 | cp_cur = 0x38; /* 111, auto */ |
| 784 | div_buf_cur = 0x30; /* 11, 150u */ |
| 785 | filter_cur = 0x40; /* 10, low */ |
| 786 | break; |
| 787 | } |
| 788 | |
Mauro Carvalho Chehab | 84ddc33 | 2013-04-10 08:51:45 -0300 | [diff] [blame] | 789 | if (priv->cfg->use_diplexer && |
| 790 | ((priv->cfg->rafael_chip == CHIP_R820T) || |
| 791 | (priv->cfg->rafael_chip == CHIP_R828S) || |
| 792 | (priv->cfg->rafael_chip == CHIP_R820C))) { |
| 793 | if (freq > DIP_FREQ) |
| 794 | air_cable1_in = 0x00; |
| 795 | else |
| 796 | air_cable1_in = 0x60; |
| 797 | cable2_in = 0x00; |
| 798 | } |
| 799 | |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 800 | rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0xc7); |
| 801 | if (rc < 0) |
| 802 | return rc; |
| 803 | rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0xf8); |
| 804 | if (rc < 0) |
| 805 | return rc; |
| 806 | rc = r820t_write_reg(priv, 0x0d, lna_vth_l); |
| 807 | if (rc < 0) |
| 808 | return rc; |
| 809 | rc = r820t_write_reg(priv, 0x0e, mixer_vth_l); |
| 810 | if (rc < 0) |
| 811 | return rc; |
| 812 | |
| 813 | /* Air-IN only for Astrometa */ |
| 814 | rc = r820t_write_reg_mask(priv, 0x05, air_cable1_in, 0x60); |
| 815 | if (rc < 0) |
| 816 | return rc; |
| 817 | rc = r820t_write_reg_mask(priv, 0x06, cable2_in, 0x08); |
| 818 | if (rc < 0) |
| 819 | return rc; |
| 820 | |
| 821 | rc = r820t_write_reg_mask(priv, 0x11, cp_cur, 0x38); |
| 822 | if (rc < 0) |
| 823 | return rc; |
| 824 | rc = r820t_write_reg_mask(priv, 0x17, div_buf_cur, 0x30); |
| 825 | if (rc < 0) |
| 826 | return rc; |
| 827 | rc = r820t_write_reg_mask(priv, 0x0a, filter_cur, 0x60); |
| 828 | if (rc < 0) |
| 829 | return rc; |
| 830 | /* |
| 831 | * Original driver initializes regs 0x05 and 0x06 with the |
| 832 | * same value again on this point. Probably, it is just an |
| 833 | * error there |
| 834 | */ |
| 835 | |
| 836 | /* |
| 837 | * Set LNA |
| 838 | */ |
| 839 | |
| 840 | tuner_dbg("adjusting LNA parameters\n"); |
| 841 | if (type != V4L2_TUNER_ANALOG_TV) { |
| 842 | /* LNA TOP: lowest */ |
| 843 | rc = r820t_write_reg_mask(priv, 0x1d, 0, 0x38); |
| 844 | if (rc < 0) |
| 845 | return rc; |
| 846 | |
| 847 | /* 0: normal mode */ |
| 848 | rc = r820t_write_reg_mask(priv, 0x1c, 0, 0x04); |
| 849 | if (rc < 0) |
| 850 | return rc; |
| 851 | |
| 852 | /* 0: PRE_DECT off */ |
| 853 | rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40); |
| 854 | if (rc < 0) |
| 855 | return rc; |
| 856 | |
| 857 | /* agc clk 250hz */ |
| 858 | rc = r820t_write_reg_mask(priv, 0x1a, 0x30, 0x30); |
| 859 | if (rc < 0) |
| 860 | return rc; |
| 861 | |
| 862 | msleep(250); |
| 863 | |
| 864 | /* write LNA TOP = 3 */ |
| 865 | rc = r820t_write_reg_mask(priv, 0x1d, 0x18, 0x38); |
| 866 | if (rc < 0) |
| 867 | return rc; |
| 868 | |
| 869 | /* |
| 870 | * write discharge mode |
| 871 | * FIXME: IMHO, the mask here is wrong, but it matches |
| 872 | * what's there at the original driver |
| 873 | */ |
| 874 | rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04); |
| 875 | if (rc < 0) |
| 876 | return rc; |
| 877 | |
| 878 | /* LNA discharge current */ |
| 879 | rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f); |
| 880 | if (rc < 0) |
| 881 | return rc; |
| 882 | |
| 883 | /* agc clk 60hz */ |
| 884 | rc = r820t_write_reg_mask(priv, 0x1a, 0x20, 0x30); |
| 885 | if (rc < 0) |
| 886 | return rc; |
| 887 | } else { |
| 888 | /* PRE_DECT off */ |
| 889 | rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40); |
| 890 | if (rc < 0) |
| 891 | return rc; |
| 892 | |
| 893 | /* write LNA TOP */ |
| 894 | rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0x38); |
| 895 | if (rc < 0) |
| 896 | return rc; |
| 897 | |
| 898 | /* |
| 899 | * write discharge mode |
| 900 | * FIXME: IMHO, the mask here is wrong, but it matches |
| 901 | * what's there at the original driver |
| 902 | */ |
| 903 | rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04); |
| 904 | if (rc < 0) |
| 905 | return rc; |
| 906 | |
| 907 | /* LNA discharge current */ |
| 908 | rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f); |
| 909 | if (rc < 0) |
| 910 | return rc; |
| 911 | |
| 912 | /* agc clk 1Khz, external det1 cap 1u */ |
| 913 | rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x30); |
| 914 | if (rc < 0) |
| 915 | return rc; |
| 916 | |
| 917 | rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x04); |
| 918 | if (rc < 0) |
| 919 | return rc; |
| 920 | } |
| 921 | return 0; |
| 922 | } |
| 923 | |
| 924 | static int r820t_set_tv_standard(struct r820t_priv *priv, |
| 925 | unsigned bw, |
| 926 | enum v4l2_tuner_type type, |
| 927 | v4l2_std_id std, u32 delsys) |
| 928 | |
| 929 | { |
| 930 | int rc, i; |
| 931 | u32 if_khz, filt_cal_lo; |
| 932 | u8 data[5], val; |
| 933 | u8 filt_gain, img_r, filt_q, hp_cor, ext_enable, loop_through; |
| 934 | u8 lt_att, flt_ext_widest, polyfil_cur; |
| 935 | bool need_calibration; |
| 936 | |
| 937 | tuner_dbg("selecting the delivery system\n"); |
| 938 | |
| 939 | if (delsys == SYS_ISDBT) { |
| 940 | if_khz = 4063; |
| 941 | filt_cal_lo = 59000; |
| 942 | filt_gain = 0x10; /* +3db, 6mhz on */ |
| 943 | img_r = 0x00; /* image negative */ |
| 944 | filt_q = 0x10; /* r10[4]:low q(1'b1) */ |
| 945 | hp_cor = 0x6a; /* 1.7m disable, +2cap, 1.25mhz */ |
| 946 | ext_enable = 0x40; /* r30[6], ext enable; r30[5]:0 ext at lna max */ |
| 947 | loop_through = 0x00; /* r5[7], lt on */ |
| 948 | lt_att = 0x00; /* r31[7], lt att enable */ |
| 949 | flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */ |
| 950 | polyfil_cur = 0x60; /* r25[6:5]:min */ |
| 951 | } else { |
| 952 | if (bw <= 6) { |
| 953 | if_khz = 3570; |
| 954 | filt_cal_lo = 56000; /* 52000->56000 */ |
| 955 | filt_gain = 0x10; /* +3db, 6mhz on */ |
| 956 | img_r = 0x00; /* image negative */ |
| 957 | filt_q = 0x10; /* r10[4]:low q(1'b1) */ |
| 958 | hp_cor = 0x6b; /* 1.7m disable, +2cap, 1.0mhz */ |
| 959 | ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */ |
| 960 | loop_through = 0x00; /* r5[7], lt on */ |
| 961 | lt_att = 0x00; /* r31[7], lt att enable */ |
| 962 | flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */ |
| 963 | polyfil_cur = 0x60; /* r25[6:5]:min */ |
| 964 | } else if (bw == 7) { |
Mauro Carvalho Chehab | 6189f80 | 2013-04-10 07:33:23 -0300 | [diff] [blame] | 965 | #if 0 |
| 966 | /* |
| 967 | * There are two 7 MHz tables defined on the original |
| 968 | * driver, but just the second one seems to be visible |
| 969 | * by rtl2832. Keep this one here commented, as it |
| 970 | * might be needed in the future |
| 971 | */ |
| 972 | |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 973 | if_khz = 4070; |
| 974 | filt_cal_lo = 60000; |
| 975 | filt_gain = 0x10; /* +3db, 6mhz on */ |
| 976 | img_r = 0x00; /* image negative */ |
| 977 | filt_q = 0x10; /* r10[4]:low q(1'b1) */ |
| 978 | hp_cor = 0x2b; /* 1.7m disable, +1cap, 1.0mhz */ |
| 979 | ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */ |
| 980 | loop_through = 0x00; /* r5[7], lt on */ |
| 981 | lt_att = 0x00; /* r31[7], lt att enable */ |
| 982 | flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */ |
| 983 | polyfil_cur = 0x60; /* r25[6:5]:min */ |
Mauro Carvalho Chehab | 6189f80 | 2013-04-10 07:33:23 -0300 | [diff] [blame] | 984 | #endif |
| 985 | /* 7 MHz, second table */ |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 986 | if_khz = 4570; |
| 987 | filt_cal_lo = 63000; |
| 988 | filt_gain = 0x10; /* +3db, 6mhz on */ |
| 989 | img_r = 0x00; /* image negative */ |
| 990 | filt_q = 0x10; /* r10[4]:low q(1'b1) */ |
| 991 | hp_cor = 0x2a; /* 1.7m disable, +1cap, 1.25mhz */ |
| 992 | ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */ |
| 993 | loop_through = 0x00; /* r5[7], lt on */ |
| 994 | lt_att = 0x00; /* r31[7], lt att enable */ |
| 995 | flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */ |
| 996 | polyfil_cur = 0x60; /* r25[6:5]:min */ |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 997 | } else { |
| 998 | if_khz = 4570; |
| 999 | filt_cal_lo = 68500; |
| 1000 | filt_gain = 0x10; /* +3db, 6mhz on */ |
| 1001 | img_r = 0x00; /* image negative */ |
| 1002 | filt_q = 0x10; /* r10[4]:low q(1'b1) */ |
| 1003 | hp_cor = 0x0b; /* 1.7m disable, +0cap, 1.0mhz */ |
| 1004 | ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */ |
| 1005 | loop_through = 0x00; /* r5[7], lt on */ |
| 1006 | lt_att = 0x00; /* r31[7], lt att enable */ |
| 1007 | flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */ |
| 1008 | polyfil_cur = 0x60; /* r25[6:5]:min */ |
| 1009 | } |
| 1010 | } |
| 1011 | |
| 1012 | /* Initialize the shadow registers */ |
| 1013 | memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array)); |
| 1014 | |
| 1015 | /* Init Flag & Xtal_check Result */ |
| 1016 | if (priv->imr_done) |
| 1017 | val = 1 | priv->xtal_cap_sel << 1; |
| 1018 | else |
| 1019 | val = 0; |
| 1020 | rc = r820t_write_reg_mask(priv, 0x0c, val, 0x0f); |
| 1021 | if (rc < 0) |
| 1022 | return rc; |
| 1023 | |
| 1024 | /* version */ |
| 1025 | rc = r820t_write_reg_mask(priv, 0x13, VER_NUM, 0x3f); |
| 1026 | if (rc < 0) |
| 1027 | return rc; |
| 1028 | |
| 1029 | /* for LT Gain test */ |
| 1030 | if (type != V4L2_TUNER_ANALOG_TV) { |
| 1031 | rc = r820t_write_reg_mask(priv, 0x1d, 0x00, 0x38); |
| 1032 | if (rc < 0) |
| 1033 | return rc; |
Mauro Carvalho Chehab | 9cc2570 | 2013-04-10 15:48:02 -0300 | [diff] [blame] | 1034 | usleep_range(1000, 2000); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 1035 | } |
Mauro Carvalho Chehab | f60f5bc | 2013-04-09 18:46:10 -0300 | [diff] [blame] | 1036 | priv->int_freq = if_khz * 1000; |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 1037 | |
| 1038 | /* Check if standard changed. If so, filter calibration is needed */ |
| 1039 | if (type != priv->type) |
| 1040 | need_calibration = true; |
| 1041 | else if ((type == V4L2_TUNER_ANALOG_TV) && (std != priv->std)) |
| 1042 | need_calibration = true; |
| 1043 | else if ((type == V4L2_TUNER_DIGITAL_TV) && |
| 1044 | ((delsys != priv->delsys) || bw != priv->bw)) |
| 1045 | need_calibration = true; |
| 1046 | else |
| 1047 | need_calibration = false; |
| 1048 | |
| 1049 | if (need_calibration) { |
| 1050 | tuner_dbg("calibrating the tuner\n"); |
| 1051 | for (i = 0; i < 2; i++) { |
| 1052 | /* Set filt_cap */ |
| 1053 | rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0x60); |
| 1054 | if (rc < 0) |
| 1055 | return rc; |
| 1056 | |
| 1057 | /* set cali clk =on */ |
| 1058 | rc = r820t_write_reg_mask(priv, 0x0f, 0x04, 0x04); |
| 1059 | if (rc < 0) |
| 1060 | return rc; |
| 1061 | |
| 1062 | /* X'tal cap 0pF for PLL */ |
| 1063 | rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x03); |
| 1064 | if (rc < 0) |
| 1065 | return rc; |
| 1066 | |
Mauro Carvalho Chehab | d75d538 | 2013-04-10 15:54:46 -0300 | [diff] [blame] | 1067 | rc = r820t_set_pll(priv, type, filt_cal_lo); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 1068 | if (rc < 0 || !priv->has_lock) |
| 1069 | return rc; |
| 1070 | |
| 1071 | /* Start Trigger */ |
| 1072 | rc = r820t_write_reg_mask(priv, 0x0b, 0x10, 0x10); |
| 1073 | if (rc < 0) |
| 1074 | return rc; |
| 1075 | |
Mauro Carvalho Chehab | 9cc2570 | 2013-04-10 15:48:02 -0300 | [diff] [blame] | 1076 | usleep_range(1000, 2000); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 1077 | |
| 1078 | /* Stop Trigger */ |
| 1079 | rc = r820t_write_reg_mask(priv, 0x0b, 0x00, 0x10); |
| 1080 | if (rc < 0) |
| 1081 | return rc; |
| 1082 | |
| 1083 | /* set cali clk =off */ |
| 1084 | rc = r820t_write_reg_mask(priv, 0x0f, 0x00, 0x04); |
| 1085 | if (rc < 0) |
| 1086 | return rc; |
| 1087 | |
| 1088 | /* Check if calibration worked */ |
Mauro Carvalho Chehab | 226471a | 2013-04-10 10:53:35 -0300 | [diff] [blame] | 1089 | rc = r820t_read(priv, 0x00, data, sizeof(data)); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 1090 | if (rc < 0) |
| 1091 | return rc; |
| 1092 | |
| 1093 | priv->fil_cal_code = data[4] & 0x0f; |
| 1094 | if (priv->fil_cal_code && priv->fil_cal_code != 0x0f) |
| 1095 | break; |
| 1096 | } |
| 1097 | /* narrowest */ |
| 1098 | if (priv->fil_cal_code == 0x0f) |
| 1099 | priv->fil_cal_code = 0; |
| 1100 | } |
| 1101 | |
| 1102 | rc = r820t_write_reg_mask(priv, 0x0a, |
| 1103 | filt_q | priv->fil_cal_code, 0x1f); |
| 1104 | if (rc < 0) |
| 1105 | return rc; |
| 1106 | |
| 1107 | /* Set BW, Filter_gain, & HP corner */ |
| 1108 | rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0x10); |
| 1109 | if (rc < 0) |
| 1110 | return rc; |
| 1111 | |
| 1112 | |
| 1113 | /* Set Img_R */ |
| 1114 | rc = r820t_write_reg_mask(priv, 0x07, img_r, 0x80); |
| 1115 | if (rc < 0) |
| 1116 | return rc; |
| 1117 | |
| 1118 | /* Set filt_3dB, V6MHz */ |
| 1119 | rc = r820t_write_reg_mask(priv, 0x06, filt_gain, 0x30); |
| 1120 | if (rc < 0) |
| 1121 | return rc; |
| 1122 | |
| 1123 | /* channel filter extension */ |
| 1124 | rc = r820t_write_reg_mask(priv, 0x1e, ext_enable, 0x60); |
| 1125 | if (rc < 0) |
| 1126 | return rc; |
| 1127 | |
| 1128 | /* Loop through */ |
| 1129 | rc = r820t_write_reg_mask(priv, 0x05, loop_through, 0x80); |
| 1130 | if (rc < 0) |
| 1131 | return rc; |
| 1132 | |
| 1133 | /* Loop through attenuation */ |
| 1134 | rc = r820t_write_reg_mask(priv, 0x1f, lt_att, 0x80); |
| 1135 | if (rc < 0) |
| 1136 | return rc; |
| 1137 | |
| 1138 | /* filter extension widest */ |
| 1139 | rc = r820t_write_reg_mask(priv, 0x0f, flt_ext_widest, 0x80); |
| 1140 | if (rc < 0) |
| 1141 | return rc; |
| 1142 | |
| 1143 | /* RF poly filter current */ |
| 1144 | rc = r820t_write_reg_mask(priv, 0x19, polyfil_cur, 0x60); |
| 1145 | if (rc < 0) |
| 1146 | return rc; |
| 1147 | |
| 1148 | /* Store current standard. If it changes, re-calibrate the tuner */ |
| 1149 | priv->delsys = delsys; |
| 1150 | priv->type = type; |
| 1151 | priv->std = std; |
| 1152 | priv->bw = bw; |
| 1153 | |
| 1154 | return 0; |
| 1155 | } |
| 1156 | |
Mauro Carvalho Chehab | f8fde0e | 2013-04-07 18:12:56 -0300 | [diff] [blame] | 1157 | static int r820t_read_gain(struct r820t_priv *priv) |
| 1158 | { |
| 1159 | u8 data[4]; |
| 1160 | int rc; |
| 1161 | |
Mauro Carvalho Chehab | 226471a | 2013-04-10 10:53:35 -0300 | [diff] [blame] | 1162 | rc = r820t_read(priv, 0x00, data, sizeof(data)); |
Mauro Carvalho Chehab | f8fde0e | 2013-04-07 18:12:56 -0300 | [diff] [blame] | 1163 | if (rc < 0) |
| 1164 | return rc; |
| 1165 | |
| 1166 | return ((data[3] & 0x0f) << 1) + ((data[3] & 0xf0) >> 4); |
| 1167 | } |
| 1168 | |
Mauro Carvalho Chehab | 50786dd | 2013-04-07 18:33:13 -0300 | [diff] [blame] | 1169 | static int r820t_set_gain_mode(struct r820t_priv *priv, |
| 1170 | bool set_manual_gain, |
| 1171 | int gain) |
| 1172 | { |
| 1173 | int rc; |
| 1174 | |
| 1175 | if (set_manual_gain) { |
| 1176 | int i, total_gain = 0; |
| 1177 | uint8_t mix_index = 0, lna_index = 0; |
| 1178 | u8 data[4]; |
| 1179 | |
| 1180 | /* LNA auto off */ |
| 1181 | rc = r820t_write_reg_mask(priv, 0x05, 0x10, 0x10); |
| 1182 | if (rc < 0) |
| 1183 | return rc; |
| 1184 | |
| 1185 | /* Mixer auto off */ |
| 1186 | rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10); |
| 1187 | if (rc < 0) |
| 1188 | return rc; |
| 1189 | |
Mauro Carvalho Chehab | 226471a | 2013-04-10 10:53:35 -0300 | [diff] [blame] | 1190 | rc = r820t_read(priv, 0x00, data, sizeof(data)); |
Mauro Carvalho Chehab | 50786dd | 2013-04-07 18:33:13 -0300 | [diff] [blame] | 1191 | if (rc < 0) |
| 1192 | return rc; |
| 1193 | |
| 1194 | /* set fixed VGA gain for now (16.3 dB) */ |
| 1195 | rc = r820t_write_reg_mask(priv, 0x0c, 0x08, 0x9f); |
| 1196 | if (rc < 0) |
| 1197 | return rc; |
| 1198 | |
| 1199 | for (i = 0; i < 15; i++) { |
| 1200 | if (total_gain >= gain) |
| 1201 | break; |
| 1202 | |
| 1203 | total_gain += r820t_lna_gain_steps[++lna_index]; |
| 1204 | |
| 1205 | if (total_gain >= gain) |
| 1206 | break; |
| 1207 | |
| 1208 | total_gain += r820t_mixer_gain_steps[++mix_index]; |
| 1209 | } |
| 1210 | |
| 1211 | /* set LNA gain */ |
| 1212 | rc = r820t_write_reg_mask(priv, 0x05, lna_index, 0x0f); |
| 1213 | if (rc < 0) |
| 1214 | return rc; |
| 1215 | |
| 1216 | /* set Mixer gain */ |
| 1217 | rc = r820t_write_reg_mask(priv, 0x07, mix_index, 0x0f); |
| 1218 | if (rc < 0) |
| 1219 | return rc; |
| 1220 | } else { |
| 1221 | /* LNA */ |
| 1222 | rc = r820t_write_reg_mask(priv, 0x05, 0, 0xef); |
| 1223 | if (rc < 0) |
| 1224 | return rc; |
| 1225 | |
| 1226 | /* Mixer */ |
| 1227 | rc = r820t_write_reg_mask(priv, 0x07, 0x10, 0xef); |
| 1228 | if (rc < 0) |
| 1229 | return rc; |
| 1230 | |
| 1231 | /* set fixed VGA gain for now (26.5 dB) */ |
| 1232 | rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f); |
| 1233 | if (rc < 0) |
| 1234 | return rc; |
| 1235 | } |
| 1236 | |
| 1237 | return 0; |
| 1238 | } |
| 1239 | |
| 1240 | |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 1241 | static int generic_set_freq(struct dvb_frontend *fe, |
| 1242 | u32 freq /* in HZ */, |
| 1243 | unsigned bw, |
| 1244 | enum v4l2_tuner_type type, |
| 1245 | v4l2_std_id std, u32 delsys) |
| 1246 | { |
| 1247 | struct r820t_priv *priv = fe->tuner_priv; |
| 1248 | int rc = -EINVAL; |
| 1249 | u32 lo_freq; |
| 1250 | |
| 1251 | tuner_dbg("should set frequency to %d kHz, bw %d MHz\n", |
| 1252 | freq / 1000, bw); |
| 1253 | |
Mauro Carvalho Chehab | a7dd065 | 2013-04-09 21:29:40 -0300 | [diff] [blame] | 1254 | rc = r820t_set_tv_standard(priv, bw, type, std, delsys); |
| 1255 | if (rc < 0) |
| 1256 | goto err; |
| 1257 | |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 1258 | if ((type == V4L2_TUNER_ANALOG_TV) && (std == V4L2_STD_SECAM_LC)) |
| 1259 | lo_freq = freq - priv->int_freq; |
| 1260 | else |
| 1261 | lo_freq = freq + priv->int_freq; |
| 1262 | |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 1263 | rc = r820t_set_mux(priv, lo_freq); |
| 1264 | if (rc < 0) |
| 1265 | goto err; |
Mauro Carvalho Chehab | 50786dd | 2013-04-07 18:33:13 -0300 | [diff] [blame] | 1266 | |
| 1267 | rc = r820t_set_gain_mode(priv, true, 0); |
| 1268 | if (rc < 0) |
| 1269 | goto err; |
| 1270 | |
Mauro Carvalho Chehab | d75d538 | 2013-04-10 15:54:46 -0300 | [diff] [blame] | 1271 | rc = r820t_set_pll(priv, type, lo_freq); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 1272 | if (rc < 0 || !priv->has_lock) |
| 1273 | goto err; |
| 1274 | |
| 1275 | rc = r820t_sysfreq_sel(priv, freq, type, std, delsys); |
Mauro Carvalho Chehab | da31934 | 2013-04-07 19:47:49 -0300 | [diff] [blame] | 1276 | if (rc < 0) |
| 1277 | goto err; |
| 1278 | |
| 1279 | tuner_dbg("%s: PLL locked on frequency %d Hz, gain=%d\n", |
| 1280 | __func__, freq, r820t_read_gain(priv)); |
| 1281 | |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 1282 | err: |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 1283 | |
| 1284 | if (rc < 0) |
| 1285 | tuner_dbg("%s: failed=%d\n", __func__, rc); |
| 1286 | return rc; |
| 1287 | } |
| 1288 | |
| 1289 | /* |
| 1290 | * r820t standby logic |
| 1291 | */ |
| 1292 | |
| 1293 | static int r820t_standby(struct r820t_priv *priv) |
| 1294 | { |
| 1295 | int rc; |
| 1296 | |
| 1297 | rc = r820t_write_reg(priv, 0x06, 0xb1); |
| 1298 | if (rc < 0) |
| 1299 | return rc; |
| 1300 | rc = r820t_write_reg(priv, 0x05, 0x03); |
| 1301 | if (rc < 0) |
| 1302 | return rc; |
| 1303 | rc = r820t_write_reg(priv, 0x07, 0x3a); |
| 1304 | if (rc < 0) |
| 1305 | return rc; |
| 1306 | rc = r820t_write_reg(priv, 0x08, 0x40); |
| 1307 | if (rc < 0) |
| 1308 | return rc; |
| 1309 | rc = r820t_write_reg(priv, 0x09, 0xc0); |
| 1310 | if (rc < 0) |
| 1311 | return rc; |
| 1312 | rc = r820t_write_reg(priv, 0x0a, 0x36); |
| 1313 | if (rc < 0) |
| 1314 | return rc; |
| 1315 | rc = r820t_write_reg(priv, 0x0c, 0x35); |
| 1316 | if (rc < 0) |
| 1317 | return rc; |
| 1318 | rc = r820t_write_reg(priv, 0x0f, 0x68); |
| 1319 | if (rc < 0) |
| 1320 | return rc; |
| 1321 | rc = r820t_write_reg(priv, 0x11, 0x03); |
| 1322 | if (rc < 0) |
| 1323 | return rc; |
| 1324 | rc = r820t_write_reg(priv, 0x17, 0xf4); |
| 1325 | if (rc < 0) |
| 1326 | return rc; |
| 1327 | rc = r820t_write_reg(priv, 0x19, 0x0c); |
| 1328 | |
| 1329 | /* Force initial calibration */ |
| 1330 | priv->type = -1; |
| 1331 | |
| 1332 | return rc; |
| 1333 | } |
| 1334 | |
| 1335 | /* |
| 1336 | * r820t device init logic |
| 1337 | */ |
| 1338 | |
| 1339 | static int r820t_xtal_check(struct r820t_priv *priv) |
| 1340 | { |
| 1341 | int rc, i; |
| 1342 | u8 data[3], val; |
| 1343 | |
| 1344 | /* Initialize the shadow registers */ |
| 1345 | memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array)); |
| 1346 | |
| 1347 | /* cap 30pF & Drive Low */ |
| 1348 | rc = r820t_write_reg_mask(priv, 0x10, 0x0b, 0x0b); |
| 1349 | if (rc < 0) |
| 1350 | return rc; |
| 1351 | |
| 1352 | /* set pll autotune = 128kHz */ |
| 1353 | rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c); |
| 1354 | if (rc < 0) |
| 1355 | return rc; |
| 1356 | |
| 1357 | /* set manual initial reg = 111111; */ |
| 1358 | rc = r820t_write_reg_mask(priv, 0x13, 0x7f, 0x7f); |
| 1359 | if (rc < 0) |
| 1360 | return rc; |
| 1361 | |
| 1362 | /* set auto */ |
| 1363 | rc = r820t_write_reg_mask(priv, 0x13, 0x00, 0x40); |
| 1364 | if (rc < 0) |
| 1365 | return rc; |
| 1366 | |
| 1367 | /* Try several xtal capacitor alternatives */ |
| 1368 | for (i = 0; i < ARRAY_SIZE(r820t_xtal_capacitor); i++) { |
| 1369 | rc = r820t_write_reg_mask(priv, 0x10, |
| 1370 | r820t_xtal_capacitor[i][0], 0x1b); |
| 1371 | if (rc < 0) |
| 1372 | return rc; |
| 1373 | |
Mauro Carvalho Chehab | 9cc2570 | 2013-04-10 15:48:02 -0300 | [diff] [blame] | 1374 | usleep_range(5000, 6000); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 1375 | |
Mauro Carvalho Chehab | 226471a | 2013-04-10 10:53:35 -0300 | [diff] [blame] | 1376 | rc = r820t_read(priv, 0x00, data, sizeof(data)); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 1377 | if (rc < 0) |
| 1378 | return rc; |
| 1379 | if ((!data[2]) & 0x40) |
| 1380 | continue; |
| 1381 | |
| 1382 | val = data[2] & 0x3f; |
| 1383 | |
| 1384 | if (priv->cfg->xtal == 16000000 && (val > 29 || val < 23)) |
| 1385 | break; |
| 1386 | |
| 1387 | if (val != 0x3f) |
| 1388 | break; |
| 1389 | } |
| 1390 | |
| 1391 | if (i == ARRAY_SIZE(r820t_xtal_capacitor)) |
| 1392 | return -EINVAL; |
| 1393 | |
| 1394 | return r820t_xtal_capacitor[i][1]; |
| 1395 | } |
| 1396 | |
Mauro Carvalho Chehab | 25cf4d4 | 2013-04-10 15:55:48 -0300 | [diff] [blame^] | 1397 | static int r820t_imr_prepare(struct r820t_priv *priv) |
| 1398 | { |
| 1399 | int rc; |
| 1400 | |
| 1401 | /* Initialize the shadow registers */ |
| 1402 | memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array)); |
| 1403 | |
| 1404 | /* lna off (air-in off) */ |
| 1405 | rc = r820t_write_reg_mask(priv, 0x05, 0x20, 0x20); |
| 1406 | if (rc < 0) |
| 1407 | return rc; |
| 1408 | |
| 1409 | /* mixer gain mode = manual */ |
| 1410 | rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10); |
| 1411 | if (rc < 0) |
| 1412 | return rc; |
| 1413 | |
| 1414 | /* filter corner = lowest */ |
| 1415 | rc = r820t_write_reg_mask(priv, 0x0a, 0x0f, 0x0f); |
| 1416 | if (rc < 0) |
| 1417 | return rc; |
| 1418 | |
| 1419 | /* filter bw=+2cap, hp=5M */ |
| 1420 | rc = r820t_write_reg_mask(priv, 0x0b, 0x60, 0x6f); |
| 1421 | if (rc < 0) |
| 1422 | return rc; |
| 1423 | |
| 1424 | /* adc=on, vga code mode, gain = 26.5dB */ |
| 1425 | rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f); |
| 1426 | if (rc < 0) |
| 1427 | return rc; |
| 1428 | |
| 1429 | /* ring clk = on */ |
| 1430 | rc = r820t_write_reg_mask(priv, 0x0f, 0, 0x08); |
| 1431 | if (rc < 0) |
| 1432 | return rc; |
| 1433 | |
| 1434 | /* ring power = on */ |
| 1435 | rc = r820t_write_reg_mask(priv, 0x18, 0x10, 0x10); |
| 1436 | if (rc < 0) |
| 1437 | return rc; |
| 1438 | |
| 1439 | /* from ring = ring pll in */ |
| 1440 | rc = r820t_write_reg_mask(priv, 0x1c, 0x02, 0x02); |
| 1441 | if (rc < 0) |
| 1442 | return rc; |
| 1443 | |
| 1444 | /* sw_pdect = det3 */ |
| 1445 | rc = r820t_write_reg_mask(priv, 0x1e, 0x80, 0x80); |
| 1446 | if (rc < 0) |
| 1447 | return rc; |
| 1448 | |
| 1449 | /* Set filt_3dB */ |
| 1450 | rc = r820t_write_reg_mask(priv, 0x06, 0x20, 0x20); |
| 1451 | |
| 1452 | return rc; |
| 1453 | } |
| 1454 | |
| 1455 | static int r820t_multi_read(struct r820t_priv *priv) |
| 1456 | { |
| 1457 | int rc, i; |
| 1458 | u8 data[2], min = 0, max = 255, sum = 0; |
| 1459 | |
| 1460 | usleep_range(5000, 6000); |
| 1461 | |
| 1462 | for (i = 0; i < 6; i++) { |
| 1463 | rc = r820t_read(priv, 0x00, data, sizeof(data)); |
| 1464 | if (rc < 0) |
| 1465 | return rc; |
| 1466 | |
| 1467 | sum += data[1]; |
| 1468 | |
| 1469 | if (data[1] < min) |
| 1470 | min = data[1]; |
| 1471 | |
| 1472 | if (data[1] > max) |
| 1473 | max = data[1]; |
| 1474 | } |
| 1475 | rc = sum - max - min; |
| 1476 | |
| 1477 | return rc; |
| 1478 | } |
| 1479 | |
| 1480 | static int r820t_imr_cross(struct r820t_priv *priv, |
| 1481 | struct r820t_sect_type iq_point[3], |
| 1482 | u8 *x_direct) |
| 1483 | { |
| 1484 | struct r820t_sect_type cross[5]; /* (0,0)(0,Q-1)(0,I-1)(Q-1,0)(I-1,0) */ |
| 1485 | struct r820t_sect_type tmp; |
| 1486 | int i, rc; |
| 1487 | u8 reg08, reg09; |
| 1488 | |
| 1489 | reg08 = r820t_read_cache_reg(priv, 8) & 0xc0; |
| 1490 | reg09 = r820t_read_cache_reg(priv, 9) & 0xc0; |
| 1491 | |
| 1492 | tmp.gain_x = 0; |
| 1493 | tmp.phase_y = 0; |
| 1494 | tmp.value = 255; |
| 1495 | |
| 1496 | for (i = 0; i < 5; i++) { |
| 1497 | switch (i) { |
| 1498 | case 0: |
| 1499 | cross[i].gain_x = reg08; |
| 1500 | cross[i].phase_y = reg09; |
| 1501 | break; |
| 1502 | case 1: |
| 1503 | cross[i].gain_x = reg08; /* 0 */ |
| 1504 | cross[i].phase_y = reg09 + 1; /* Q-1 */ |
| 1505 | break; |
| 1506 | case 2: |
| 1507 | cross[i].gain_x = reg08; /* 0 */ |
| 1508 | cross[i].phase_y = (reg09 | 0x20) + 1; /* I-1 */ |
| 1509 | break; |
| 1510 | case 3: |
| 1511 | cross[i].gain_x = reg08 + 1; /* Q-1 */ |
| 1512 | cross[i].phase_y = reg09; |
| 1513 | break; |
| 1514 | default: |
| 1515 | cross[i].gain_x = (reg08 | 0x20) + 1; /* I-1 */ |
| 1516 | cross[i].phase_y = reg09; |
| 1517 | } |
| 1518 | |
| 1519 | rc = r820t_write_reg(priv, 0x08, cross[i].gain_x); |
| 1520 | if (rc < 0) |
| 1521 | return rc; |
| 1522 | |
| 1523 | rc = r820t_write_reg(priv, 0x09, cross[i].phase_y); |
| 1524 | if (rc < 0) |
| 1525 | return rc; |
| 1526 | |
| 1527 | rc = r820t_multi_read(priv); |
| 1528 | if (rc < 0) |
| 1529 | return rc; |
| 1530 | |
| 1531 | cross[i].value = rc; |
| 1532 | |
| 1533 | if (cross[i].value < tmp.value) |
| 1534 | memcpy(&tmp, &cross[i], sizeof(tmp)); |
| 1535 | } |
| 1536 | |
| 1537 | if ((tmp.phase_y & 0x1f) == 1) { /* y-direction */ |
| 1538 | *x_direct = 0; |
| 1539 | |
| 1540 | iq_point[0] = cross[0]; |
| 1541 | iq_point[1] = cross[1]; |
| 1542 | iq_point[2] = cross[2]; |
| 1543 | } else { /* (0,0) or x-direction */ |
| 1544 | *x_direct = 1; |
| 1545 | |
| 1546 | iq_point[0] = cross[0]; |
| 1547 | iq_point[1] = cross[3]; |
| 1548 | iq_point[2] = cross[4]; |
| 1549 | } |
| 1550 | return 0; |
| 1551 | } |
| 1552 | |
| 1553 | static void r820t_compre_cor(struct r820t_sect_type iq[3]) |
| 1554 | { |
| 1555 | int i; |
| 1556 | |
| 1557 | for (i = 3; i > 0; i--) { |
| 1558 | if (iq[0].value > iq[i - 1].value) |
| 1559 | swap(iq[0], iq[i - 1]); |
| 1560 | } |
| 1561 | } |
| 1562 | |
| 1563 | static int r820t_compre_step(struct r820t_priv *priv, |
| 1564 | struct r820t_sect_type iq[3], u8 reg) |
| 1565 | { |
| 1566 | int rc; |
| 1567 | struct r820t_sect_type tmp; |
| 1568 | |
| 1569 | /* |
| 1570 | * Purpose: if (Gain<9 or Phase<9), Gain+1 or Phase+1 and compare |
| 1571 | * with min value: |
| 1572 | * new < min => update to min and continue |
| 1573 | * new > min => Exit |
| 1574 | */ |
| 1575 | |
| 1576 | /* min value already saved in iq[0] */ |
| 1577 | tmp.phase_y = iq[0].phase_y; |
| 1578 | tmp.gain_x = iq[0].gain_x; |
| 1579 | |
| 1580 | while (((tmp.gain_x & 0x1f) < IMR_TRIAL) && |
| 1581 | ((tmp.phase_y & 0x1f) < IMR_TRIAL)) { |
| 1582 | if (reg == 0x08) |
| 1583 | tmp.gain_x++; |
| 1584 | else |
| 1585 | tmp.phase_y++; |
| 1586 | |
| 1587 | rc = r820t_write_reg(priv, 0x08, tmp.gain_x); |
| 1588 | if (rc < 0) |
| 1589 | return rc; |
| 1590 | |
| 1591 | rc = r820t_write_reg(priv, 0x09, tmp.phase_y); |
| 1592 | if (rc < 0) |
| 1593 | return rc; |
| 1594 | |
| 1595 | rc = r820t_multi_read(priv); |
| 1596 | if (rc < 0) |
| 1597 | return rc; |
| 1598 | tmp.value = rc; |
| 1599 | |
| 1600 | if (tmp.value <= iq[0].value) { |
| 1601 | iq[0].gain_x = tmp.gain_x; |
| 1602 | iq[0].phase_y = tmp.phase_y; |
| 1603 | iq[0].value = tmp.value; |
| 1604 | } else { |
| 1605 | return 0; |
| 1606 | } |
| 1607 | |
| 1608 | } |
| 1609 | |
| 1610 | return 0; |
| 1611 | } |
| 1612 | |
| 1613 | static int r820t_iq_tree(struct r820t_priv *priv, |
| 1614 | struct r820t_sect_type iq[3], |
| 1615 | u8 fix_val, u8 var_val, u8 fix_reg) |
| 1616 | { |
| 1617 | int rc, i; |
| 1618 | u8 tmp, var_reg; |
| 1619 | |
| 1620 | /* |
| 1621 | * record IMC results by input gain/phase location then adjust |
| 1622 | * gain or phase positive 1 step and negtive 1 step, |
| 1623 | * both record results |
| 1624 | */ |
| 1625 | |
| 1626 | if (fix_reg == 0x08) |
| 1627 | var_reg = 0x09; |
| 1628 | else |
| 1629 | var_reg = 0x08; |
| 1630 | |
| 1631 | for (i = 0; i < 3; i++) { |
| 1632 | rc = r820t_write_reg(priv, fix_reg, fix_val); |
| 1633 | if (rc < 0) |
| 1634 | return rc; |
| 1635 | |
| 1636 | rc = r820t_write_reg(priv, var_reg, var_val); |
| 1637 | if (rc < 0) |
| 1638 | return rc; |
| 1639 | |
| 1640 | rc = r820t_multi_read(priv); |
| 1641 | if (rc < 0) |
| 1642 | return rc; |
| 1643 | iq[i].value = rc; |
| 1644 | |
| 1645 | if (fix_reg == 0x08) { |
| 1646 | iq[i].gain_x = fix_val; |
| 1647 | iq[i].phase_y = var_val; |
| 1648 | } else { |
| 1649 | iq[i].phase_y = fix_val; |
| 1650 | iq[i].gain_x = var_val; |
| 1651 | } |
| 1652 | |
| 1653 | if (i == 0) { /* try right-side point */ |
| 1654 | var_val++; |
| 1655 | } else if (i == 1) { /* try left-side point */ |
| 1656 | /* if absolute location is 1, change I/Q direction */ |
| 1657 | if ((var_val & 0x1f) < 0x02) { |
| 1658 | tmp = 2 - (var_val & 0x1f); |
| 1659 | |
| 1660 | /* b[5]:I/Q selection. 0:Q-path, 1:I-path */ |
| 1661 | if (var_val & 0x20) { |
| 1662 | var_val &= 0xc0; |
| 1663 | var_val |= tmp; |
| 1664 | } else { |
| 1665 | var_val |= 0x20 | tmp; |
| 1666 | } |
| 1667 | } else { |
| 1668 | var_val -= 2; |
| 1669 | } |
| 1670 | } |
| 1671 | } |
| 1672 | |
| 1673 | return 0; |
| 1674 | } |
| 1675 | |
| 1676 | static int r820t_section(struct r820t_priv *priv, |
| 1677 | struct r820t_sect_type *iq_point) |
| 1678 | { |
| 1679 | int rc; |
| 1680 | struct r820t_sect_type compare_iq[3], compare_bet[3]; |
| 1681 | |
| 1682 | /* Try X-1 column and save min result to compare_bet[0] */ |
| 1683 | if (!(iq_point->gain_x & 0x1f)) |
| 1684 | compare_iq[0].gain_x = ((iq_point->gain_x) & 0xdf) + 1; /* Q-path, Gain=1 */ |
| 1685 | else |
| 1686 | compare_iq[0].gain_x = iq_point->gain_x - 1; /* left point */ |
| 1687 | compare_iq[0].phase_y = iq_point->phase_y; |
| 1688 | |
| 1689 | /* y-direction */ |
| 1690 | rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x, |
| 1691 | compare_iq[0].phase_y, 0x08); |
| 1692 | if (rc < 0) |
| 1693 | return rc; |
| 1694 | |
| 1695 | r820t_compre_cor(compare_iq); |
| 1696 | |
| 1697 | compare_bet[0] = compare_iq[0]; |
| 1698 | |
| 1699 | /* Try X column and save min result to compare_bet[1] */ |
| 1700 | compare_iq[0].gain_x = iq_point->gain_x; |
| 1701 | compare_iq[0].phase_y = iq_point->phase_y; |
| 1702 | |
| 1703 | rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x, |
| 1704 | compare_iq[0].phase_y, 0x08); |
| 1705 | if (rc < 0) |
| 1706 | return rc; |
| 1707 | |
| 1708 | r820t_compre_cor(compare_iq); |
| 1709 | |
| 1710 | compare_bet[1] = compare_iq[0]; |
| 1711 | |
| 1712 | /* Try X+1 column and save min result to compare_bet[2] */ |
| 1713 | if ((iq_point->gain_x & 0x1f) == 0x00) |
| 1714 | compare_iq[0].gain_x = ((iq_point->gain_x) | 0x20) + 1; /* I-path, Gain=1 */ |
| 1715 | else |
| 1716 | compare_iq[0].gain_x = iq_point->gain_x + 1; |
| 1717 | compare_iq[0].phase_y = iq_point->phase_y; |
| 1718 | |
| 1719 | rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x, |
| 1720 | compare_iq[0].phase_y, 0x08); |
| 1721 | if (rc < 0) |
| 1722 | return rc; |
| 1723 | |
| 1724 | r820t_compre_cor(compare_iq); |
| 1725 | |
| 1726 | compare_bet[2] = compare_iq[0]; |
| 1727 | |
| 1728 | r820t_compre_cor(compare_bet); |
| 1729 | |
| 1730 | *iq_point = compare_bet[0]; |
| 1731 | |
| 1732 | return 0; |
| 1733 | } |
| 1734 | |
| 1735 | static int r820t_vga_adjust(struct r820t_priv *priv) |
| 1736 | { |
| 1737 | int rc; |
| 1738 | u8 vga_count; |
| 1739 | |
| 1740 | /* increase vga power to let image significant */ |
| 1741 | for (vga_count = 12; vga_count < 16; vga_count++) { |
| 1742 | rc = r820t_write_reg_mask(priv, 0x0c, vga_count, 0x0f); |
| 1743 | if (rc < 0) |
| 1744 | return rc; |
| 1745 | |
| 1746 | usleep_range(10000, 11000); |
| 1747 | |
| 1748 | rc = r820t_multi_read(priv); |
| 1749 | if (rc < 0) |
| 1750 | return rc; |
| 1751 | |
| 1752 | if (rc > 40 * 4) |
| 1753 | break; |
| 1754 | } |
| 1755 | |
| 1756 | return 0; |
| 1757 | } |
| 1758 | |
| 1759 | static int r820t_iq(struct r820t_priv *priv, struct r820t_sect_type *iq_pont) |
| 1760 | { |
| 1761 | struct r820t_sect_type compare_iq[3]; |
| 1762 | int rc; |
| 1763 | u8 x_direction = 0; /* 1:x, 0:y */ |
| 1764 | u8 dir_reg, other_reg; |
| 1765 | |
| 1766 | r820t_vga_adjust(priv); |
| 1767 | |
| 1768 | rc = r820t_imr_cross(priv, compare_iq, &x_direction); |
| 1769 | if (rc < 0) |
| 1770 | return rc; |
| 1771 | |
| 1772 | if (x_direction == 1) { |
| 1773 | dir_reg = 0x08; |
| 1774 | other_reg = 0x09; |
| 1775 | } else { |
| 1776 | dir_reg = 0x09; |
| 1777 | other_reg = 0x08; |
| 1778 | } |
| 1779 | |
| 1780 | /* compare and find min of 3 points. determine i/q direction */ |
| 1781 | r820t_compre_cor(compare_iq); |
| 1782 | |
| 1783 | /* increase step to find min value of this direction */ |
| 1784 | rc = r820t_compre_step(priv, compare_iq, dir_reg); |
| 1785 | if (rc < 0) |
| 1786 | return rc; |
| 1787 | |
| 1788 | /* the other direction */ |
| 1789 | rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x, |
| 1790 | compare_iq[0].phase_y, dir_reg); |
| 1791 | if (rc < 0) |
| 1792 | return rc; |
| 1793 | |
| 1794 | /* compare and find min of 3 points. determine i/q direction */ |
| 1795 | r820t_compre_cor(compare_iq); |
| 1796 | |
| 1797 | /* increase step to find min value on this direction */ |
| 1798 | rc = r820t_compre_step(priv, compare_iq, other_reg); |
| 1799 | if (rc < 0) |
| 1800 | return rc; |
| 1801 | |
| 1802 | /* check 3 points again */ |
| 1803 | rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x, |
| 1804 | compare_iq[0].phase_y, other_reg); |
| 1805 | if (rc < 0) |
| 1806 | return rc; |
| 1807 | |
| 1808 | r820t_compre_cor(compare_iq); |
| 1809 | |
| 1810 | /* section-9 check */ |
| 1811 | rc = r820t_section(priv, compare_iq); |
| 1812 | |
| 1813 | *iq_pont = compare_iq[0]; |
| 1814 | |
| 1815 | /* reset gain/phase control setting */ |
| 1816 | rc = r820t_write_reg_mask(priv, 0x08, 0, 0x3f); |
| 1817 | if (rc < 0) |
| 1818 | return rc; |
| 1819 | |
| 1820 | rc = r820t_write_reg_mask(priv, 0x09, 0, 0x3f); |
| 1821 | |
| 1822 | return rc; |
| 1823 | } |
| 1824 | |
| 1825 | static int r820t_f_imr(struct r820t_priv *priv, struct r820t_sect_type *iq_pont) |
| 1826 | { |
| 1827 | int rc; |
| 1828 | |
| 1829 | r820t_vga_adjust(priv); |
| 1830 | |
| 1831 | /* |
| 1832 | * search surrounding points from previous point |
| 1833 | * try (x-1), (x), (x+1) columns, and find min IMR result point |
| 1834 | */ |
| 1835 | rc = r820t_section(priv, iq_pont); |
| 1836 | if (rc < 0) |
| 1837 | return rc; |
| 1838 | |
| 1839 | return 0; |
| 1840 | } |
| 1841 | |
| 1842 | static int r820t_imr(struct r820t_priv *priv, unsigned imr_mem, bool im_flag) |
| 1843 | { |
| 1844 | struct r820t_sect_type imr_point; |
| 1845 | int rc; |
| 1846 | u32 ring_vco, ring_freq, ring_ref; |
| 1847 | u8 n_ring, n; |
| 1848 | int reg18, reg19, reg1f; |
| 1849 | |
| 1850 | if (priv->cfg->xtal > 24000000) |
| 1851 | ring_ref = priv->cfg->xtal / 2; |
| 1852 | else |
| 1853 | ring_ref = priv->cfg->xtal; |
| 1854 | |
| 1855 | for (n = 0; n < 16; n++) { |
| 1856 | if ((16 + n) * 8 * ring_ref >= 3100000) { |
| 1857 | n_ring = n; |
| 1858 | break; |
| 1859 | } |
| 1860 | |
| 1861 | /* n_ring not found */ |
| 1862 | if (n == 15) |
| 1863 | n_ring = n; |
| 1864 | } |
| 1865 | |
| 1866 | reg18 = r820t_read_cache_reg(priv, 0x18); |
| 1867 | reg19 = r820t_read_cache_reg(priv, 0x19); |
| 1868 | reg1f = r820t_read_cache_reg(priv, 0x1f); |
| 1869 | |
| 1870 | reg18 &= 0xf0; /* set ring[3:0] */ |
| 1871 | reg18 |= n_ring; |
| 1872 | |
| 1873 | ring_vco = (16 + n_ring) * 8 * ring_ref; |
| 1874 | |
| 1875 | reg18 &= 0xdf; /* clear ring_se23 */ |
| 1876 | reg19 &= 0xfc; /* clear ring_seldiv */ |
| 1877 | reg1f &= 0xfc; /* clear ring_att */ |
| 1878 | |
| 1879 | switch (imr_mem) { |
| 1880 | case 0: |
| 1881 | ring_freq = ring_vco / 48; |
| 1882 | reg18 |= 0x20; /* ring_se23 = 1 */ |
| 1883 | reg19 |= 0x03; /* ring_seldiv = 3 */ |
| 1884 | reg1f |= 0x02; /* ring_att 10 */ |
| 1885 | break; |
| 1886 | case 1: |
| 1887 | ring_freq = ring_vco / 16; |
| 1888 | reg18 |= 0x00; /* ring_se23 = 0 */ |
| 1889 | reg19 |= 0x02; /* ring_seldiv = 2 */ |
| 1890 | reg1f |= 0x00; /* pw_ring 00 */ |
| 1891 | break; |
| 1892 | case 2: |
| 1893 | ring_freq = ring_vco / 8; |
| 1894 | reg18 |= 0x00; /* ring_se23 = 0 */ |
| 1895 | reg19 |= 0x01; /* ring_seldiv = 1 */ |
| 1896 | reg1f |= 0x03; /* pw_ring 11 */ |
| 1897 | break; |
| 1898 | case 3: |
| 1899 | ring_freq = ring_vco / 6; |
| 1900 | reg18 |= 0x20; /* ring_se23 = 1 */ |
| 1901 | reg19 |= 0x00; /* ring_seldiv = 0 */ |
| 1902 | reg1f |= 0x03; /* pw_ring 11 */ |
| 1903 | break; |
| 1904 | case 4: |
| 1905 | ring_freq = ring_vco / 4; |
| 1906 | reg18 |= 0x00; /* ring_se23 = 0 */ |
| 1907 | reg19 |= 0x00; /* ring_seldiv = 0 */ |
| 1908 | reg1f |= 0x01; /* pw_ring 01 */ |
| 1909 | break; |
| 1910 | default: |
| 1911 | ring_freq = ring_vco / 4; |
| 1912 | reg18 |= 0x00; /* ring_se23 = 0 */ |
| 1913 | reg19 |= 0x00; /* ring_seldiv = 0 */ |
| 1914 | reg1f |= 0x01; /* pw_ring 01 */ |
| 1915 | break; |
| 1916 | } |
| 1917 | |
| 1918 | |
| 1919 | /* write pw_ring, n_ring, ringdiv2 registers */ |
| 1920 | |
| 1921 | /* n_ring, ring_se23 */ |
| 1922 | rc = r820t_write_reg(priv, 0x18, reg18); |
| 1923 | if (rc < 0) |
| 1924 | return rc; |
| 1925 | |
| 1926 | /* ring_sediv */ |
| 1927 | rc = r820t_write_reg(priv, 0x19, reg19); |
| 1928 | if (rc < 0) |
| 1929 | return rc; |
| 1930 | |
| 1931 | /* pw_ring */ |
| 1932 | rc = r820t_write_reg(priv, 0x1f, reg1f); |
| 1933 | if (rc < 0) |
| 1934 | return rc; |
| 1935 | |
| 1936 | /* mux input freq ~ rf_in freq */ |
| 1937 | rc = r820t_set_mux(priv, (ring_freq - 5300) * 1000); |
| 1938 | if (rc < 0) |
| 1939 | return rc; |
| 1940 | |
| 1941 | rc = r820t_set_pll(priv, V4L2_TUNER_DIGITAL_TV, |
| 1942 | (ring_freq - 5300) * 1000); |
| 1943 | if (!priv->has_lock) |
| 1944 | rc = -EINVAL; |
| 1945 | if (rc < 0) |
| 1946 | return rc; |
| 1947 | |
| 1948 | if (im_flag) { |
| 1949 | rc = r820t_iq(priv, &imr_point); |
| 1950 | } else { |
| 1951 | imr_point.gain_x = priv->imr_data[3].gain_x; |
| 1952 | imr_point.phase_y = priv->imr_data[3].phase_y; |
| 1953 | imr_point.value = priv->imr_data[3].value; |
| 1954 | |
| 1955 | rc = r820t_f_imr(priv, &imr_point); |
| 1956 | } |
| 1957 | if (rc < 0) |
| 1958 | return rc; |
| 1959 | |
| 1960 | /* save IMR value */ |
| 1961 | switch (imr_mem) { |
| 1962 | case 0: |
| 1963 | priv->imr_data[0].gain_x = imr_point.gain_x; |
| 1964 | priv->imr_data[0].phase_y = imr_point.phase_y; |
| 1965 | priv->imr_data[0].value = imr_point.value; |
| 1966 | break; |
| 1967 | case 1: |
| 1968 | priv->imr_data[1].gain_x = imr_point.gain_x; |
| 1969 | priv->imr_data[1].phase_y = imr_point.phase_y; |
| 1970 | priv->imr_data[1].value = imr_point.value; |
| 1971 | break; |
| 1972 | case 2: |
| 1973 | priv->imr_data[2].gain_x = imr_point.gain_x; |
| 1974 | priv->imr_data[2].phase_y = imr_point.phase_y; |
| 1975 | priv->imr_data[2].value = imr_point.value; |
| 1976 | break; |
| 1977 | case 3: |
| 1978 | priv->imr_data[3].gain_x = imr_point.gain_x; |
| 1979 | priv->imr_data[3].phase_y = imr_point.phase_y; |
| 1980 | priv->imr_data[3].value = imr_point.value; |
| 1981 | break; |
| 1982 | case 4: |
| 1983 | priv->imr_data[4].gain_x = imr_point.gain_x; |
| 1984 | priv->imr_data[4].phase_y = imr_point.phase_y; |
| 1985 | priv->imr_data[4].value = imr_point.value; |
| 1986 | break; |
| 1987 | default: |
| 1988 | priv->imr_data[4].gain_x = imr_point.gain_x; |
| 1989 | priv->imr_data[4].phase_y = imr_point.phase_y; |
| 1990 | priv->imr_data[4].value = imr_point.value; |
| 1991 | break; |
| 1992 | } |
| 1993 | |
| 1994 | return 0; |
| 1995 | } |
| 1996 | |
| 1997 | static int r820t_imr_callibrate(struct r820t_priv *priv) |
| 1998 | { |
| 1999 | int rc, i; |
| 2000 | int xtal_cap = 0; |
| 2001 | |
| 2002 | if (priv->imr_done) |
| 2003 | return 0; |
| 2004 | |
| 2005 | /* Initialize registers */ |
| 2006 | rc = r820t_write(priv, 0x05, |
| 2007 | r820t_init_array, sizeof(r820t_init_array)); |
| 2008 | if (rc < 0) |
| 2009 | return rc; |
| 2010 | |
| 2011 | /* Detect Xtal capacitance */ |
| 2012 | if ((priv->cfg->rafael_chip == CHIP_R820T) || |
| 2013 | (priv->cfg->rafael_chip == CHIP_R828S) || |
| 2014 | (priv->cfg->rafael_chip == CHIP_R820C)) { |
| 2015 | priv->xtal_cap_sel = XTAL_HIGH_CAP_0P; |
| 2016 | } else { |
| 2017 | for (i = 0; i < 3; i++) { |
| 2018 | rc = r820t_xtal_check(priv); |
| 2019 | if (rc < 0) |
| 2020 | return rc; |
| 2021 | if (!i || rc > xtal_cap) |
| 2022 | xtal_cap = rc; |
| 2023 | } |
| 2024 | priv->xtal_cap_sel = xtal_cap; |
| 2025 | } |
| 2026 | |
| 2027 | /* Initialize registers */ |
| 2028 | rc = r820t_write(priv, 0x05, |
| 2029 | r820t_init_array, sizeof(r820t_init_array)); |
| 2030 | if (rc < 0) |
| 2031 | return rc; |
| 2032 | |
| 2033 | rc = r820t_imr_prepare(priv); |
| 2034 | if (rc < 0) |
| 2035 | return rc; |
| 2036 | |
| 2037 | rc = r820t_imr(priv, 3, true); |
| 2038 | if (rc < 0) |
| 2039 | return rc; |
| 2040 | rc = r820t_imr(priv, 1, false); |
| 2041 | if (rc < 0) |
| 2042 | return rc; |
| 2043 | rc = r820t_imr(priv, 0, false); |
| 2044 | if (rc < 0) |
| 2045 | return rc; |
| 2046 | rc = r820t_imr(priv, 2, false); |
| 2047 | if (rc < 0) |
| 2048 | return rc; |
| 2049 | rc = r820t_imr(priv, 4, false); |
| 2050 | if (rc < 0) |
| 2051 | return rc; |
| 2052 | |
| 2053 | priv->imr_done = true; |
| 2054 | |
| 2055 | return 0; |
| 2056 | } |
| 2057 | |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 2058 | /* |
| 2059 | * r820t frontend operations and tuner attach code |
Mauro Carvalho Chehab | 7a5ef30 | 2013-04-07 19:32:55 -0300 | [diff] [blame] | 2060 | * |
| 2061 | * All driver locks and i2c control are only in this part of the code |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 2062 | */ |
| 2063 | |
| 2064 | static int r820t_init(struct dvb_frontend *fe) |
| 2065 | { |
| 2066 | struct r820t_priv *priv = fe->tuner_priv; |
Mauro Carvalho Chehab | 25cf4d4 | 2013-04-10 15:55:48 -0300 | [diff] [blame^] | 2067 | int rc; |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 2068 | |
| 2069 | tuner_dbg("%s:\n", __func__); |
| 2070 | |
Mauro Carvalho Chehab | 7a5ef30 | 2013-04-07 19:32:55 -0300 | [diff] [blame] | 2071 | mutex_lock(&priv->lock); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 2072 | if (fe->ops.i2c_gate_ctrl) |
| 2073 | fe->ops.i2c_gate_ctrl(fe, 1); |
| 2074 | |
Mauro Carvalho Chehab | 25cf4d4 | 2013-04-10 15:55:48 -0300 | [diff] [blame^] | 2075 | rc = r820t_imr_callibrate(priv); |
| 2076 | if (rc < 0) |
| 2077 | goto err; |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 2078 | |
| 2079 | /* Initialize registers */ |
| 2080 | rc = r820t_write(priv, 0x05, |
| 2081 | r820t_init_array, sizeof(r820t_init_array)); |
| 2082 | |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 2083 | err: |
| 2084 | if (fe->ops.i2c_gate_ctrl) |
| 2085 | fe->ops.i2c_gate_ctrl(fe, 0); |
Mauro Carvalho Chehab | 7a5ef30 | 2013-04-07 19:32:55 -0300 | [diff] [blame] | 2086 | mutex_unlock(&priv->lock); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 2087 | |
Mauro Carvalho Chehab | 7a5ef30 | 2013-04-07 19:32:55 -0300 | [diff] [blame] | 2088 | if (rc < 0) |
| 2089 | tuner_dbg("%s: failed=%d\n", __func__, rc); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 2090 | return rc; |
| 2091 | } |
| 2092 | |
| 2093 | static int r820t_sleep(struct dvb_frontend *fe) |
| 2094 | { |
| 2095 | struct r820t_priv *priv = fe->tuner_priv; |
| 2096 | int rc; |
| 2097 | |
| 2098 | tuner_dbg("%s:\n", __func__); |
| 2099 | |
Mauro Carvalho Chehab | 7a5ef30 | 2013-04-07 19:32:55 -0300 | [diff] [blame] | 2100 | mutex_lock(&priv->lock); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 2101 | if (fe->ops.i2c_gate_ctrl) |
| 2102 | fe->ops.i2c_gate_ctrl(fe, 1); |
| 2103 | |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 2104 | rc = r820t_standby(priv); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 2105 | |
| 2106 | if (fe->ops.i2c_gate_ctrl) |
| 2107 | fe->ops.i2c_gate_ctrl(fe, 0); |
Mauro Carvalho Chehab | 7a5ef30 | 2013-04-07 19:32:55 -0300 | [diff] [blame] | 2108 | mutex_unlock(&priv->lock); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 2109 | |
| 2110 | tuner_dbg("%s: failed=%d\n", __func__, rc); |
| 2111 | return rc; |
| 2112 | } |
| 2113 | |
| 2114 | static int r820t_set_analog_freq(struct dvb_frontend *fe, |
| 2115 | struct analog_parameters *p) |
| 2116 | { |
| 2117 | struct r820t_priv *priv = fe->tuner_priv; |
| 2118 | unsigned bw; |
Mauro Carvalho Chehab | 7a5ef30 | 2013-04-07 19:32:55 -0300 | [diff] [blame] | 2119 | int rc; |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 2120 | |
| 2121 | tuner_dbg("%s called\n", __func__); |
| 2122 | |
| 2123 | /* if std is not defined, choose one */ |
| 2124 | if (!p->std) |
| 2125 | p->std = V4L2_STD_MN; |
| 2126 | |
| 2127 | if ((p->std == V4L2_STD_PAL_M) || (p->std == V4L2_STD_NTSC)) |
| 2128 | bw = 6; |
| 2129 | else |
| 2130 | bw = 8; |
| 2131 | |
Mauro Carvalho Chehab | 7a5ef30 | 2013-04-07 19:32:55 -0300 | [diff] [blame] | 2132 | mutex_lock(&priv->lock); |
| 2133 | if (fe->ops.i2c_gate_ctrl) |
| 2134 | fe->ops.i2c_gate_ctrl(fe, 1); |
| 2135 | |
| 2136 | rc = generic_set_freq(fe, 62500l * p->frequency, bw, |
| 2137 | V4L2_TUNER_ANALOG_TV, p->std, SYS_UNDEFINED); |
| 2138 | |
| 2139 | if (fe->ops.i2c_gate_ctrl) |
| 2140 | fe->ops.i2c_gate_ctrl(fe, 0); |
| 2141 | mutex_unlock(&priv->lock); |
| 2142 | |
| 2143 | return rc; |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 2144 | } |
| 2145 | |
| 2146 | static int r820t_set_params(struct dvb_frontend *fe) |
| 2147 | { |
| 2148 | struct r820t_priv *priv = fe->tuner_priv; |
| 2149 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
| 2150 | int rc; |
| 2151 | unsigned bw; |
| 2152 | |
| 2153 | tuner_dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n", |
| 2154 | __func__, c->delivery_system, c->frequency, c->bandwidth_hz); |
| 2155 | |
Mauro Carvalho Chehab | 7a5ef30 | 2013-04-07 19:32:55 -0300 | [diff] [blame] | 2156 | mutex_lock(&priv->lock); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 2157 | if (fe->ops.i2c_gate_ctrl) |
| 2158 | fe->ops.i2c_gate_ctrl(fe, 1); |
| 2159 | |
| 2160 | bw = (c->bandwidth_hz + 500000) / 1000000; |
| 2161 | if (!bw) |
| 2162 | bw = 8; |
| 2163 | |
| 2164 | rc = generic_set_freq(fe, c->frequency, bw, |
| 2165 | V4L2_TUNER_DIGITAL_TV, 0, c->delivery_system); |
| 2166 | |
| 2167 | if (fe->ops.i2c_gate_ctrl) |
| 2168 | fe->ops.i2c_gate_ctrl(fe, 0); |
Mauro Carvalho Chehab | 7a5ef30 | 2013-04-07 19:32:55 -0300 | [diff] [blame] | 2169 | mutex_unlock(&priv->lock); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 2170 | |
| 2171 | if (rc) |
| 2172 | tuner_dbg("%s: failed=%d\n", __func__, rc); |
| 2173 | return rc; |
| 2174 | } |
| 2175 | |
| 2176 | static int r820t_signal(struct dvb_frontend *fe, u16 *strength) |
| 2177 | { |
| 2178 | struct r820t_priv *priv = fe->tuner_priv; |
Mauro Carvalho Chehab | f8fde0e | 2013-04-07 18:12:56 -0300 | [diff] [blame] | 2179 | int rc = 0; |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 2180 | |
Mauro Carvalho Chehab | 7a5ef30 | 2013-04-07 19:32:55 -0300 | [diff] [blame] | 2181 | mutex_lock(&priv->lock); |
| 2182 | if (fe->ops.i2c_gate_ctrl) |
| 2183 | fe->ops.i2c_gate_ctrl(fe, 1); |
| 2184 | |
Mauro Carvalho Chehab | f8fde0e | 2013-04-07 18:12:56 -0300 | [diff] [blame] | 2185 | if (priv->has_lock) { |
| 2186 | rc = r820t_read_gain(priv); |
| 2187 | if (rc < 0) |
Mauro Carvalho Chehab | 7a5ef30 | 2013-04-07 19:32:55 -0300 | [diff] [blame] | 2188 | goto err; |
Mauro Carvalho Chehab | f8fde0e | 2013-04-07 18:12:56 -0300 | [diff] [blame] | 2189 | |
| 2190 | /* A higher gain at LNA means a lower signal strength */ |
| 2191 | *strength = (45 - rc) << 4 | 0xff; |
Mauro Carvalho Chehab | 75c1819 | 2013-04-10 09:04:03 -0300 | [diff] [blame] | 2192 | if (*strength == 0xff) |
| 2193 | *strength = 0; |
Mauro Carvalho Chehab | f8fde0e | 2013-04-07 18:12:56 -0300 | [diff] [blame] | 2194 | } else { |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 2195 | *strength = 0; |
Mauro Carvalho Chehab | f8fde0e | 2013-04-07 18:12:56 -0300 | [diff] [blame] | 2196 | } |
| 2197 | |
Mauro Carvalho Chehab | 7a5ef30 | 2013-04-07 19:32:55 -0300 | [diff] [blame] | 2198 | err: |
| 2199 | if (fe->ops.i2c_gate_ctrl) |
| 2200 | fe->ops.i2c_gate_ctrl(fe, 0); |
| 2201 | mutex_unlock(&priv->lock); |
| 2202 | |
Mauro Carvalho Chehab | f8fde0e | 2013-04-07 18:12:56 -0300 | [diff] [blame] | 2203 | tuner_dbg("%s: %s, gain=%d strength=%d\n", |
| 2204 | __func__, |
| 2205 | priv->has_lock ? "PLL locked" : "no signal", |
| 2206 | rc, *strength); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 2207 | |
| 2208 | return 0; |
| 2209 | } |
| 2210 | |
| 2211 | static int r820t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) |
| 2212 | { |
| 2213 | struct r820t_priv *priv = fe->tuner_priv; |
| 2214 | |
| 2215 | tuner_dbg("%s:\n", __func__); |
| 2216 | |
| 2217 | *frequency = priv->int_freq; |
| 2218 | |
| 2219 | return 0; |
| 2220 | } |
| 2221 | |
| 2222 | static int r820t_release(struct dvb_frontend *fe) |
| 2223 | { |
| 2224 | struct r820t_priv *priv = fe->tuner_priv; |
| 2225 | |
| 2226 | tuner_dbg("%s:\n", __func__); |
| 2227 | |
| 2228 | mutex_lock(&r820t_list_mutex); |
| 2229 | |
| 2230 | if (priv) |
| 2231 | hybrid_tuner_release_state(priv); |
| 2232 | |
| 2233 | mutex_unlock(&r820t_list_mutex); |
| 2234 | |
| 2235 | fe->tuner_priv = NULL; |
| 2236 | |
| 2237 | kfree(fe->tuner_priv); |
| 2238 | |
| 2239 | return 0; |
| 2240 | } |
| 2241 | |
| 2242 | static const struct dvb_tuner_ops r820t_tuner_ops = { |
| 2243 | .info = { |
| 2244 | .name = "Rafael Micro R820T", |
| 2245 | .frequency_min = 42000000, |
| 2246 | .frequency_max = 1002000000, |
| 2247 | }, |
| 2248 | .init = r820t_init, |
| 2249 | .release = r820t_release, |
| 2250 | .sleep = r820t_sleep, |
| 2251 | .set_params = r820t_set_params, |
| 2252 | .set_analog_params = r820t_set_analog_freq, |
| 2253 | .get_if_frequency = r820t_get_if_frequency, |
| 2254 | .get_rf_strength = r820t_signal, |
| 2255 | }; |
| 2256 | |
| 2257 | struct dvb_frontend *r820t_attach(struct dvb_frontend *fe, |
| 2258 | struct i2c_adapter *i2c, |
| 2259 | const struct r820t_config *cfg) |
| 2260 | { |
| 2261 | struct r820t_priv *priv; |
| 2262 | int rc = -ENODEV; |
| 2263 | u8 data[5]; |
| 2264 | int instance; |
| 2265 | |
| 2266 | mutex_lock(&r820t_list_mutex); |
| 2267 | |
| 2268 | instance = hybrid_tuner_request_state(struct r820t_priv, priv, |
| 2269 | hybrid_tuner_instance_list, |
| 2270 | i2c, cfg->i2c_addr, |
| 2271 | "r820t"); |
| 2272 | switch (instance) { |
| 2273 | case 0: |
| 2274 | /* memory allocation failure */ |
| 2275 | goto err_no_gate; |
| 2276 | break; |
| 2277 | case 1: |
| 2278 | /* new tuner instance */ |
| 2279 | priv->cfg = cfg; |
| 2280 | |
| 2281 | mutex_init(&priv->lock); |
| 2282 | |
| 2283 | fe->tuner_priv = priv; |
| 2284 | break; |
| 2285 | case 2: |
| 2286 | /* existing tuner instance */ |
| 2287 | fe->tuner_priv = priv; |
| 2288 | break; |
| 2289 | } |
| 2290 | |
| 2291 | memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops, sizeof(r820t_tuner_ops)); |
| 2292 | |
| 2293 | if (fe->ops.i2c_gate_ctrl) |
| 2294 | fe->ops.i2c_gate_ctrl(fe, 1); |
| 2295 | |
| 2296 | /* check if the tuner is there */ |
Mauro Carvalho Chehab | 226471a | 2013-04-10 10:53:35 -0300 | [diff] [blame] | 2297 | rc = r820t_read(priv, 0x00, data, sizeof(data)); |
Mauro Carvalho Chehab | a80abc5 | 2013-04-05 14:35:18 -0300 | [diff] [blame] | 2298 | if (rc < 0) |
| 2299 | goto err; |
| 2300 | |
| 2301 | rc = r820t_sleep(fe); |
| 2302 | if (rc < 0) |
| 2303 | goto err; |
| 2304 | |
| 2305 | tuner_info("Rafael Micro r820t successfully identified\n"); |
| 2306 | |
| 2307 | fe->tuner_priv = priv; |
| 2308 | memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops, |
| 2309 | sizeof(struct dvb_tuner_ops)); |
| 2310 | |
| 2311 | if (fe->ops.i2c_gate_ctrl) |
| 2312 | fe->ops.i2c_gate_ctrl(fe, 0); |
| 2313 | |
| 2314 | mutex_unlock(&r820t_list_mutex); |
| 2315 | |
| 2316 | return fe; |
| 2317 | err: |
| 2318 | if (fe->ops.i2c_gate_ctrl) |
| 2319 | fe->ops.i2c_gate_ctrl(fe, 0); |
| 2320 | |
| 2321 | err_no_gate: |
| 2322 | mutex_unlock(&r820t_list_mutex); |
| 2323 | |
| 2324 | tuner_info("%s: failed=%d\n", __func__, rc); |
| 2325 | r820t_release(fe); |
| 2326 | return NULL; |
| 2327 | } |
| 2328 | EXPORT_SYMBOL_GPL(r820t_attach); |
| 2329 | |
| 2330 | MODULE_DESCRIPTION("Rafael Micro r820t silicon tuner driver"); |
| 2331 | MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); |
| 2332 | MODULE_LICENSE("GPL"); |